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- From c7b89dd10cf3e18c695533e214a51b3efe7dd992 Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Thu, 7 Jan 2021 21:05:48 +0800
- Subject: [PATCH 47/48] RISC-V: Freeze ZBA/ZBB/ZBC to 0.93.
- Only enable the frozen ZBA/ZBB/ZBC, other ZB* can not be used but
- still keep their opcodes. Rename ZBS from sb* to b* will cause
- encoding conflicts for bext/bextw (ZBE), so rename the conflict
- sbext/sbextw to bfext/bfextw.
- Besides, cleanup and make them the same as the upstream code.
- ---
- bfd/elfxx-riscv.c | 3 +-
- gas/config/tc-riscv.c | 86 +------
- .../gas/riscv/attribute-15-unratified.d | 4 +-
- gas/testsuite/gas/riscv/bitmanip-insns-32.d | 26 ++-
- gas/testsuite/gas/riscv/bitmanip-insns-64.d | 53 ++---
- .../gas/riscv/bitmanip-insns-pseudo-32.d | 61 -----
- .../gas/riscv/bitmanip-insns-pseudo-64.d | 84 -------
- .../riscv/bitmanip-insns-pseudo-noalias-32.d | 61 -----
- .../riscv/bitmanip-insns-pseudo-noalias-64.d | 84 -------
- gas/testsuite/gas/riscv/bitmanip-insns.s | 57 ++---
- include/opcode/riscv-opc.h | 138 +++++------
- include/opcode/riscv.h | 21 +-
- opcodes/riscv-opc.c | 220 ++++++++----------
- 13 files changed, 256 insertions(+), 642 deletions(-)
- delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
- delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
- delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
- delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
- diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
- index 75add5be1c..af014b29cb 100644
- --- a/bfd/elfxx-riscv.c
- +++ b/bfd/elfxx-riscv.c
- @@ -1566,8 +1566,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
-
- static const char * const riscv_std_z_ext_strtab[] =
- {
- - "zicsr", "zifencei", "zfh",
- - "zba", "zbb", "zbc", "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt",
- + "zicsr", "zifencei", "zfh", "zba", "zbb", "zbc",
- "zvamo", "zvediv", "zvlsseg", "zvqmac",
- NULL
- };
- diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
- index 60b9a92d77..25405ca30d 100644
- --- a/gas/config/tc-riscv.c
- +++ b/gas/config/tc-riscv.c
- @@ -260,35 +260,14 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
- case INSN_CLASS_V_AND_ZVQMAC:
- return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
-
- - /* Sure. */
- - case INSN_CLASS_B_OR_ZBA:
- - return riscv_subset_supports ("b") || riscv_subset_supports ("zba");
- - case INSN_CLASS_B_OR_ZBB:
- - return riscv_subset_supports ("b") || riscv_subset_supports ("zbb");
- - case INSN_CLASS_B_OR_ZBC:
- - return riscv_subset_supports ("b") || riscv_subset_supports ("zbc");
- - case INSN_CLASS_B_OR_ZBS:
- - return riscv_subset_supports ("b") || riscv_subset_supports ("zbs");
- - case INSN_CLASS_B_OR_ZBA_OR_ZBB:
- - return (riscv_subset_supports ("b")
- - || riscv_subset_supports ("zba")
- - || riscv_subset_supports ("zbb"));
- -
- - /* Not sure. */
- - case INSN_CLASS_B:
- - return riscv_subset_supports ("b");
- - case INSN_CLASS_B_OR_ZBE:
- - return riscv_subset_supports ("b") || riscv_subset_supports ("zbe");
- - case INSN_CLASS_B_OR_ZBF:
- - return riscv_subset_supports ("b") || riscv_subset_supports ("zbf");
- - case INSN_CLASS_B_OR_ZBM:
- - return riscv_subset_supports ("b") || riscv_subset_supports ("zbm");
- - case INSN_CLASS_B_OR_ZBP:
- - return riscv_subset_supports ("b") || riscv_subset_supports ("zbp");
- - case INSN_CLASS_ZBR:
- - return riscv_subset_supports ("zbr");
- - case INSN_CLASS_ZBT:
- - return riscv_subset_supports ("zbt");
- + case INSN_CLASS_ZBA:
- + return riscv_subset_supports ("zba");
- + case INSN_CLASS_ZBB:
- + return riscv_subset_supports ("zbb");
- + case INSN_CLASS_ZBC:
- + return riscv_subset_supports ("zbc");
- + case INSN_CLASS_ZBA_OR_ZBB:
- + return riscv_subset_supports ("zba") || riscv_subset_supports ("zbb");
-
- default:
- as_fatal ("Unreachable");
- @@ -335,7 +314,7 @@ riscv_get_default_ext_version (const char *name,
- && ext->name
- && strcmp (ext->name, name) == 0)
- {
- - if (ext->isa_spec_class == ISA_SPEC_CLASS_NONE
- + if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT
- || ext->isa_spec_class == default_isa_spec)
- {
- *major_version = ext->major_version;
- @@ -1282,15 +1261,6 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
- INSERT_OPERAND (RS2, insn, va_arg (args, int));
- continue;
-
- - case 'r':
- - INSERT_OPERAND (RS3, insn, va_arg (args, int));
- - continue;
- -
- - case '<':
- - case '|':
- - INSERT_OPERAND (SHAMTW, insn, va_arg (args, int));
- - continue;
- -
- case '>':
- INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
- continue;
- @@ -1506,34 +1476,6 @@ load_const (int reg, expressionS *ep)
- }
- }
-
- -/* Immediate rotate left shift via right shift. */
- -
- -static void
- -rotate_left (int rd, int rs, unsigned shamt, unsigned this_xlen)
- -{
- - shamt = (this_xlen-1) & -shamt;
- -
- - if (this_xlen == xlen)
- - macro_build (NULL, "rori", "d,s,>", rd, rs, shamt);
- - else if (this_xlen == 32)
- - macro_build (NULL, "roriw", "d,s,<", rd, rs, shamt);
- - else
- - as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
- -}
- -
- -static void
- -funnel_left (int rd, int rs1, int rs3, unsigned shamt, unsigned this_xlen)
- -{
- - shamt = (this_xlen-1) & -shamt;
- -
- - if (this_xlen == xlen)
- - macro_build (NULL, "fsri", "d,s,r,>", rd, rs3, rs1, shamt);
- - else if (this_xlen == 32)
- - macro_build (NULL, "fsriw", "d,s,r,<", rd, rs3, rs1, shamt);
- - else
- - as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
- -}
- -
- /* Expand RISC-V Vector macros into one of more instructions. */
-
- static void
- @@ -1649,8 +1591,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
- int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
- int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
- int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
- - int rs3 = (ip->insn_opcode >> OP_SH_RS3) & OP_MASK_RS3;
- - int shamt = (ip->insn_opcode >> OP_SH_SHAMT) & OP_MASK_SHAMT;
- int mask = ip->insn_mo->mask;
-
- switch (mask)
- @@ -1659,14 +1599,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
- load_const (rd, imm_expr);
- break;
-
- - case M_RL:
- - rotate_left (rd, rs1, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
- - break;
- -
- - case M_FL:
- - funnel_left (rd, rs1, rs3, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
- - break;
- -
- case M_LA:
- case M_LLA:
- /* Load the address of a symbol into a register. */
- diff --git a/gas/testsuite/gas/riscv/attribute-15-unratified.d b/gas/testsuite/gas/riscv/attribute-15-unratified.d
- index 4645762bd6..3d6c68ec2c 100644
- --- a/gas/testsuite/gas/riscv/attribute-15-unratified.d
- +++ b/gas/testsuite/gas/riscv/attribute-15-unratified.d
- @@ -1,6 +1,6 @@
- -#as: -march-attr -march=rv32ibv_zfh_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt_zvamo_zvediv_zvlsseg_zvqmac
- +#as: -march-attr -march=rv32iv_zfh_zba_zbb_zbc_zvamo_zvediv_zvlsseg_zvqmac
- #readelf: -A
- #source: empty.s
- Attribute Section: riscv
- File Attributes
- - Tag_RISCV_arch: ".*_b0p92_v1p0_zfh0p1_zba0p92_zbb0p92_zbc0p92_zbe0p92_zbf0p92_zbm0p92_zbp0p92_zbr0p92_zbs0p92_zbt0p92_zvamo1p0_zvediv1p0_zvlsseg1p0_zvqmac1p0"
- + Tag_RISCV_arch: ".*_v1p0_zfh0p1_zba0p93_zbb0p93_zbc0p93_zvamo1p0_zvediv1p0_zvlsseg1p0_zvqmac1p0"
- diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
- index bda9d603af..b218f96e94 100644
- --- a/gas/testsuite/gas/riscv/bitmanip-insns-32.d
- +++ b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
- @@ -1,6 +1,6 @@
- -#as: -march=rv32i_zba_zbb
- +#as: -march=rv32i_zba_zbb_zbc
- #source: bitmanip-insns.s
- -#objdump: -dr
- +#objdump: -dr -Mno-aliases
-
- .*:[ ]+file format .*
-
- @@ -8,28 +8,30 @@
- Disassembly of section .text:
-
- 0+000 <.text>:
- +[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext.h[ ]+a0,a1
- +[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
- +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1
- [ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
- [ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
- -[ ]+[0-9a-f]+:[ ]+60259513[ ]+pcnt[ ]+a0,a1
- +[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
- [ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1
- +[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1
- [ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+00c5c533[ ]+xor[ ]+a0,a1,a2
- -[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
- -[ ]+[0-9a-f]+:[ ]+6015d513[ ]+rori[ ]+a0,a1,0x1
- -[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
- -[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
- -[ ]+[0-9a-f]+:[ ]+6015d513[ ]+rori[ ]+a0,a1,0x1
- -[ ]+[0-9a-f]+:[ ]+6015d513[ ]+rori[ ]+a0,a1,0x1
- +[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
- [ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
- [ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
- -[ ]+[0-9a-f]+:[ ]+6015d513[ ]+rori[ ]+a0,a1,0x1
- +[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
- [ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
- -[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1
- -[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1
- +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
- diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
- index 843bb319be..9914f3e557 100644
- --- a/gas/testsuite/gas/riscv/bitmanip-insns-64.d
- +++ b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
- @@ -1,6 +1,6 @@
- -#as: -march=rv64i_zba_zbb -defsym __64_bit__=1
- +#as: -march=rv64i_zba_zbb_zbc -defsym __64_bit__=1
- #source: bitmanip-insns.s
- -#objdump: -dr
- +#objdump: -dr -Mno-aliases
-
- .*:[ ]+file format .*
-
- @@ -8,51 +8,48 @@
- Disassembly of section .text:
-
- 0+000 <.text>:
- +[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext.h[ ]+a0,a1
- +[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
- +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1
- +[ ]+[0-9a-f]+:[ ]+0805853b[ ]+add.uw[ ]+a0,a1,zero
- [ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
- [ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
- -[ ]+[0-9a-f]+:[ ]+0815951b[ ]+slliu.w[ ]+a0,a1,0x1
- -[ ]+[0-9a-f]+:[ ]+0bf5951b[ ]+slliu.w[ ]+a0,a1,0x3f
- -[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+addu.w[ ]+a0,a1,a2
- -[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1addu.w[ ]+a0,a1,a2
- -[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2addu.w[ ]+a0,a1,a2
- -[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3addu.w[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add.uw[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add.uw[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add.uw[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+0805951b[ ]+slli.uw[ ]+a0,a1,0x0
- +[ ]+[0-9a-f]+:[ ]+0bf5951b[ ]+slli.uw[ ]+a0,a1,0x3f
- [ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
- [ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
- -[ ]+[0-9a-f]+:[ ]+60259513[ ]+pcnt[ ]+a0,a1
- +[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
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- diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
- deleted file mode 100644
- index b0cdb16efc..0000000000
- --- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
- +++ /dev/null
- @@ -1,61 +0,0 @@
- -#as: -march=rv32ib
- -#source: bitmanip-insns-pseudo.s
- -#objdump: -dr
- -
- -.*:[ ]+file format .*
- -
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- diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
- deleted file mode 100644
- index 23b8b7b5a6..0000000000
- --- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
- +++ /dev/null
- @@ -1,84 +0,0 @@
- -#as: -march=rv64ib -defsym __64_bit__=1
- -#source: bitmanip-insns-pseudo.s
- -#objdump: -dr
- -
- -.*:[ ]+file format .*
- -
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- -Disassembly of section .text:
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- diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
- deleted file mode 100644
- index 91190c8b6a..0000000000
- --- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
- +++ /dev/null
- @@ -1,61 +0,0 @@
- -#as: -march=rv32ib
- -#source: bitmanip-insns-pseudo.s
- -#objdump: -dr -Mno-aliases
- -
- -.*:[ ]+file format .*
- -
- -
- -Disassembly of section .text:
- -
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- -[ ]+[0-9a-f]+:[ ]+28f5d513[ ]+gorci[ ]+a0,a1,0xf
- -[ ]+[0-9a-f]+:[ ]+2905d513[ ]+gorci[ ]+a0,a1,0x10
- -[ ]+[0-9a-f]+:[ ]+2985d513[ ]+gorci[ ]+a0,a1,0x18
- -[ ]+[0-9a-f]+:[ ]+29c5d513[ ]+gorci[ ]+a0,a1,0x1c
- -[ ]+[0-9a-f]+:[ ]+29e5d513[ ]+gorci[ ]+a0,a1,0x1e
- -[ ]+[0-9a-f]+:[ ]+29f5d513[ ]+gorci[ ]+a0,a1,0x1f
- -[ ]+[0-9a-f]+:[ ]+08159513[ ]+shfli[ ]+a0,a1,0x1
- -[ ]+[0-9a-f]+:[ ]+08259513[ ]+shfli[ ]+a0,a1,0x2
- -[ ]+[0-9a-f]+:[ ]+08359513[ ]+shfli[ ]+a0,a1,0x3
- -[ ]+[0-9a-f]+:[ ]+08459513[ ]+shfli[ ]+a0,a1,0x4
- -[ ]+[0-9a-f]+:[ ]+08659513[ ]+shfli[ ]+a0,a1,0x6
- -[ ]+[0-9a-f]+:[ ]+08759513[ ]+shfli[ ]+a0,a1,0x7
- -[ ]+[0-9a-f]+:[ ]+08859513[ ]+shfli[ ]+a0,a1,0x8
- -[ ]+[0-9a-f]+:[ ]+08c59513[ ]+shfli[ ]+a0,a1,0xc
- -[ ]+[0-9a-f]+:[ ]+08e59513[ ]+shfli[ ]+a0,a1,0xe
- -[ ]+[0-9a-f]+:[ ]+08f59513[ ]+shfli[ ]+a0,a1,0xf
- -[ ]+[0-9a-f]+:[ ]+0815d513[ ]+unshfli[ ]+a0,a1,0x1
- -[ ]+[0-9a-f]+:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
- -[ ]+[0-9a-f]+:[ ]+0835d513[ ]+unshfli[ ]+a0,a1,0x3
- -[ ]+[0-9a-f]+:[ ]+0845d513[ ]+unshfli[ ]+a0,a1,0x4
- -[ ]+[0-9a-f]+:[ ]+0865d513[ ]+unshfli[ ]+a0,a1,0x6
- -[ ]+[0-9a-f]+:[ ]+0875d513[ ]+unshfli[ ]+a0,a1,0x7
- -[ ]+[0-9a-f]+:[ ]+0885d513[ ]+unshfli[ ]+a0,a1,0x8
- -[ ]+[0-9a-f]+:[ ]+08c5d513[ ]+unshfli[ ]+a0,a1,0xc
- -[ ]+[0-9a-f]+:[ ]+08e5d513[ ]+unshfli[ ]+a0,a1,0xe
- -[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unshfli[ ]+a0,a1,0xf
- diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
- deleted file mode 100644
- index 187c487e7c..0000000000
- --- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
- +++ /dev/null
- @@ -1,84 +0,0 @@
- -#as: -march=rv64ib -defsym __64_bit__=1
- -#source: bitmanip-insns-pseudo.s
- -#objdump: -dr -Mno-aliases
- -
- -.*:[ ]+file format .*
- -
- -
- -Disassembly of section .text:
- -
- -0+000 <.text>:
- -[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+packw[ ]+a0,a1,zero
- -[ ]+[0-9a-f]+:[ ]+6815d513[ ]+grevi[ ]+a0,a1,0x1
- -[ ]+[0-9a-f]+:[ ]+6825d513[ ]+grevi[ ]+a0,a1,0x2
- -[ ]+[0-9a-f]+:[ ]+6835d513[ ]+grevi[ ]+a0,a1,0x3
- -[ ]+[0-9a-f]+:[ ]+6845d513[ ]+grevi[ ]+a0,a1,0x4
- -[ ]+[0-9a-f]+:[ ]+6865d513[ ]+grevi[ ]+a0,a1,0x6
- -[ ]+[0-9a-f]+:[ ]+6875d513[ ]+grevi[ ]+a0,a1,0x7
- -[ ]+[0-9a-f]+:[ ]+6885d513[ ]+grevi[ ]+a0,a1,0x8
- -[ ]+[0-9a-f]+:[ ]+68c5d513[ ]+grevi[ ]+a0,a1,0xc
- -[ ]+[0-9a-f]+:[ ]+68e5d513[ ]+grevi[ ]+a0,a1,0xe
- -[ ]+[0-9a-f]+:[ ]+68f5d513[ ]+grevi[ ]+a0,a1,0xf
- -[ ]+[0-9a-f]+:[ ]+6b05d513[ ]+grevi[ ]+a0,a1,0x30
- -[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+grevi[ ]+a0,a1,0x38
- -[ ]+[0-9a-f]+:[ ]+6bc5d513[ ]+grevi[ ]+a0,a1,0x3c
- -[ ]+[0-9a-f]+:[ ]+6be5d513[ ]+grevi[ ]+a0,a1,0x3e
- -[ ]+[0-9a-f]+:[ ]+6bf5d513[ ]+grevi[ ]+a0,a1,0x3f
- -[ ]+[0-9a-f]+:[ ]+2815d513[ ]+gorci[ ]+a0,a1,0x1
- -[ ]+[0-9a-f]+:[ ]+2825d513[ ]+gorci[ ]+a0,a1,0x2
- -[ ]+[0-9a-f]+:[ ]+2835d513[ ]+gorci[ ]+a0,a1,0x3
- -[ ]+[0-9a-f]+:[ ]+2845d513[ ]+gorci[ ]+a0,a1,0x4
- -[ ]+[0-9a-f]+:[ ]+2865d513[ ]+gorci[ ]+a0,a1,0x6
- -[ ]+[0-9a-f]+:[ ]+2875d513[ ]+gorci[ ]+a0,a1,0x7
- -[ ]+[0-9a-f]+:[ ]+2885d513[ ]+gorci[ ]+a0,a1,0x8
- -[ ]+[0-9a-f]+:[ ]+28c5d513[ ]+gorci[ ]+a0,a1,0xc
- -[ ]+[0-9a-f]+:[ ]+28e5d513[ ]+gorci[ ]+a0,a1,0xe
- -[ ]+[0-9a-f]+:[ ]+28f5d513[ ]+gorci[ ]+a0,a1,0xf
- -[ ]+[0-9a-f]+:[ ]+2b05d513[ ]+gorci[ ]+a0,a1,0x30
- -[ ]+[0-9a-f]+:[ ]+2b85d513[ ]+gorci[ ]+a0,a1,0x38
- -[ ]+[0-9a-f]+:[ ]+2bc5d513[ ]+gorci[ ]+a0,a1,0x3c
- -[ ]+[0-9a-f]+:[ ]+2be5d513[ ]+gorci[ ]+a0,a1,0x3e
- -[ ]+[0-9a-f]+:[ ]+2bf5d513[ ]+gorci[ ]+a0,a1,0x3f
- -[ ]+[0-9a-f]+:[ ]+08159513[ ]+shfli[ ]+a0,a1,0x1
- -[ ]+[0-9a-f]+:[ ]+08259513[ ]+shfli[ ]+a0,a1,0x2
- -[ ]+[0-9a-f]+:[ ]+08359513[ ]+shfli[ ]+a0,a1,0x3
- -[ ]+[0-9a-f]+:[ ]+08459513[ ]+shfli[ ]+a0,a1,0x4
- -[ ]+[0-9a-f]+:[ ]+08659513[ ]+shfli[ ]+a0,a1,0x6
- -[ ]+[0-9a-f]+:[ ]+08759513[ ]+shfli[ ]+a0,a1,0x7
- -[ ]+[0-9a-f]+:[ ]+09859513[ ]+shfli[ ]+a0,a1,0x18
- -[ ]+[0-9a-f]+:[ ]+09c59513[ ]+shfli[ ]+a0,a1,0x1c
- -[ ]+[0-9a-f]+:[ ]+09e59513[ ]+shfli[ ]+a0,a1,0x1e
- -[ ]+[0-9a-f]+:[ ]+09f59513[ ]+shfli[ ]+a0,a1,0x1f
- -[ ]+[0-9a-f]+:[ ]+0815d513[ ]+unshfli[ ]+a0,a1,0x1
- -[ ]+[0-9a-f]+:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
- -[ ]+[0-9a-f]+:[ ]+0835d513[ ]+unshfli[ ]+a0,a1,0x3
- -[ ]+[0-9a-f]+:[ ]+0845d513[ ]+unshfli[ ]+a0,a1,0x4
- -[ ]+[0-9a-f]+:[ ]+0865d513[ ]+unshfli[ ]+a0,a1,0x6
- -[ ]+[0-9a-f]+:[ ]+0875d513[ ]+unshfli[ ]+a0,a1,0x7
- -[ ]+[0-9a-f]+:[ ]+0985d513[ ]+unshfli[ ]+a0,a1,0x18
- -[ ]+[0-9a-f]+:[ ]+09c5d513[ ]+unshfli[ ]+a0,a1,0x1c
- -[ ]+[0-9a-f]+:[ ]+09e5d513[ ]+unshfli[ ]+a0,a1,0x1e
- -[ ]+[0-9a-f]+:[ ]+09f5d513[ ]+unshfli[ ]+a0,a1,0x1f
- -[ ]+[0-9a-f]+:[ ]+0805853b[ ]+addu.w[ ]+a0,a1,zero
- -[ ]+[0-9a-f]+:[ ]+6905d513[ ]+grevi[ ]+a0,a1,0x10
- -[ ]+[0-9a-f]+:[ ]+6985d513[ ]+grevi[ ]+a0,a1,0x18
- -[ ]+[0-9a-f]+:[ ]+69c5d513[ ]+grevi[ ]+a0,a1,0x1c
- -[ ]+[0-9a-f]+:[ ]+69e5d513[ ]+grevi[ ]+a0,a1,0x1e
- -[ ]+[0-9a-f]+:[ ]+69f5d513[ ]+grevi[ ]+a0,a1,0x1f
- -[ ]+[0-9a-f]+:[ ]+6a05d513[ ]+grevi[ ]+a0,a1,0x20
- -[ ]+[0-9a-f]+:[ ]+2905d513[ ]+gorci[ ]+a0,a1,0x10
- -[ ]+[0-9a-f]+:[ ]+2985d513[ ]+gorci[ ]+a0,a1,0x18
- -[ ]+[0-9a-f]+:[ ]+29c5d513[ ]+gorci[ ]+a0,a1,0x1c
- -[ ]+[0-9a-f]+:[ ]+29e5d513[ ]+gorci[ ]+a0,a1,0x1e
- -[ ]+[0-9a-f]+:[ ]+29f5d513[ ]+gorci[ ]+a0,a1,0x1f
- -[ ]+[0-9a-f]+:[ ]+2a05d513[ ]+gorci[ ]+a0,a1,0x20
- -[ ]+[0-9a-f]+:[ ]+08859513[ ]+shfli[ ]+a0,a1,0x8
- -[ ]+[0-9a-f]+:[ ]+08c59513[ ]+shfli[ ]+a0,a1,0xc
- -[ ]+[0-9a-f]+:[ ]+08e59513[ ]+shfli[ ]+a0,a1,0xe
- -[ ]+[0-9a-f]+:[ ]+08f59513[ ]+shfli[ ]+a0,a1,0xf
- -[ ]+[0-9a-f]+:[ ]+09059513[ ]+shfli[ ]+a0,a1,0x10
- -[ ]+[0-9a-f]+:[ ]+0885d513[ ]+unshfli[ ]+a0,a1,0x8
- -[ ]+[0-9a-f]+:[ ]+08c5d513[ ]+unshfli[ ]+a0,a1,0xc
- -[ ]+[0-9a-f]+:[ ]+08e5d513[ ]+unshfli[ ]+a0,a1,0xe
- -[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unshfli[ ]+a0,a1,0xf
- -[ ]+[0-9a-f]+:[ ]+0905d513[ ]+unshfli[ ]+a0,a1,0x10
- diff --git a/gas/testsuite/gas/riscv/bitmanip-insns.s b/gas/testsuite/gas/riscv/bitmanip-insns.s
- index 52e4b3afff..b14e89c1d4 100644
- --- a/gas/testsuite/gas/riscv/bitmanip-insns.s
- +++ b/gas/testsuite/gas/riscv/bitmanip-insns.s
- @@ -1,57 +1,58 @@
- + # pseudo/aliaese
- + zext.h a0, a1
- + rev8 a0, a1
- + orc.b a0, a1
- +.ifdef __64_bit__
- + zext.w a0, a1
- +.endif
- +
- # ZBA
- sh1add a0, a1, a2
- sh2add a0, a1, a2
- sh3add a0, a1, a2
- -
- .ifdef __64_bit__
- - slliu.w a0, a1, 1
- - slliu.w a0, a1, 63
- - addu.w a0, a1, a2
- - sh1addu.w a0, a1, a2
- - sh2addu.w a0, a1, a2
- - sh3addu.w a0, a1, a2
- + sh1add.uw a0, a1, a2
- + sh2add.uw a0, a1, a2
- + sh3add.uw a0, a1, a2
- + add.uw a0, a1, a2
- + slli.uw a0, a1, 0
- + slli.uw a0, a1, 63
- .endif
-
- # ZBB
- clz a0, a1
- ctz a0, a1
- - pcnt a0, a1
- + cpop a0, a1
- min a0, a1, a2
- max a0, a1, a2
- minu a0, a1, a2
- maxu a0, a1, a2
- + sext.b a0, a1
- + sext.h a0, a1
- andn a0, a1, a2
- orn a0, a1, a2
- xor a0, a1, a2
- - roli a0, a1, 1
- - roli a0, a1, 31
- - rol a0, a1, a2
- - rol a0, a1, 1
- - rol a0, a1, 31
- - rori a0, a1, 1
- + rori a0, a1, 0
- rori a0, a1, 31
- ror a0, a1, a2
- - ror a0, a1, 1
- + ror a0, a1, 0
- ror a0, a1, 31
- - sext.b a0, a1
- - sext.h a0, a1
- -
- + rol a0, a1, a2
- .ifdef __64_bit__
- clzw a0, a1
- ctzw a0, a1
- - pcntw a0, a1
- - roli a0, a1, 63
- - rol a0, a1, 63
- + cpopw a0, a1
- rori a0, a1, 63
- ror a0, a1, 63
- - roliw a0, a1, 1
- - roliw a0, a1, 31
- - roriw a0, a1, 1
- + roriw a0, a1, 0
- roriw a0, a1, 31
- - rolw a0, a1, a2
- - rolw a0, a1, 1
- - rolw a0, a1, 31
- rorw a0, a1, a2
- - rorw a0, a1, 1
- + rorw a0, a1, 0
- rorw a0, a1, 31
- + rolw a0, a1, a2
- .endif
- +
- + # ZBC
- + clmul a0, a1, a2
- + clmulh a0, a1, a2
- + clmulr a0, a1, a2
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index 1faa2a8a8a..d481d5e2e6 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -203,14 +203,14 @@
- #define MASK_ROL 0xfe00707f
- #define MATCH_ROR 0x60005033
- #define MASK_ROR 0xfe00707f
- -#define MATCH_SBCLR 0x48001033
- -#define MASK_SBCLR 0xfe00707f
- -#define MATCH_SBSET 0x28001033
- -#define MASK_SBSET 0xfe00707f
- -#define MATCH_SBINV 0x68001033
- -#define MASK_SBINV 0xfe00707f
- -#define MATCH_SBEXT 0x48005033
- -#define MASK_SBEXT 0xfe00707f
- +#define MATCH_BCLR 0x48001033
- +#define MASK_BCLR 0xfe00707f
- +#define MATCH_BSET 0x28001033
- +#define MASK_BSET 0xfe00707f
- +#define MATCH_BINV 0x68001033
- +#define MASK_BINV 0xfe00707f
- +#define MATCH_BFEXT 0x48005033
- +#define MASK_BFEXT 0xfe00707f
- #define MATCH_GORC 0x28005033
- #define MASK_GORC 0xfe00707f
- #define MATCH_GREV 0x68005033
- @@ -221,14 +221,14 @@
- #define MASK_SROI 0xfc00707f
- #define MATCH_RORI 0x60005013
- #define MASK_RORI 0xfc00707f
- -#define MATCH_SBCLRI 0x48001013
- -#define MASK_SBCLRI 0xfc00707f
- -#define MATCH_SBSETI 0x28001013
- -#define MASK_SBSETI 0xfc00707f
- -#define MATCH_SBINVI 0x68001013
- -#define MASK_SBINVI 0xfc00707f
- -#define MATCH_SBEXTI 0x48005013
- -#define MASK_SBEXTI 0xfc00707f
- +#define MATCH_BCLRI 0x48001013
- +#define MASK_BCLRI 0xfc00707f
- +#define MATCH_BSETI 0x28001013
- +#define MASK_BSETI 0xfc00707f
- +#define MATCH_BINVI 0x68001013
- +#define MASK_BINVI 0xfc00707f
- +#define MATCH_BEXTI 0x48005013
- +#define MASK_BEXTI 0xfc00707f
- #define MATCH_GORCI 0x28005013
- #define MASK_GORCI 0xfc00707f
- #define MATCH_GREVI 0x68005013
- @@ -247,8 +247,8 @@
- #define MASK_CLZ 0xfff0707f
- #define MATCH_CTZ 0x60101013
- #define MASK_CTZ 0xfff0707f
- -#define MATCH_PCNT 0x60201013
- -#define MASK_PCNT 0xfff0707f
- +#define MATCH_CPOP 0x60201013
- +#define MASK_CPOP 0xfff0707f
- #define MATCH_SEXT_B 0x60401013
- #define MASK_SEXT_B 0xfff0707f
- #define MATCH_SEXT_H 0x60501013
- @@ -321,12 +321,12 @@
- #define MASK_BMATOR 0xfe00707f
- #define MATCH_BMATXOR 0x48003033
- #define MASK_BMATXOR 0xfe00707f
- -#define MATCH_SLLIU_W 0x800101b
- -#define MASK_SLLIU_W 0xfc00707f
- -#define MATCH_ADDU_W 0x800003b
- -#define MASK_ADDU_W 0xfe00707f
- -#define MATCH_SUBU_W 0x4800003b
- -#define MASK_SUBU_W 0xfe00707f
- +#define MATCH_SLLI_UW 0x800101b
- +#define MASK_SLLI_UW 0xfc00707f
- +#define MATCH_ADD_UW 0x800003b
- +#define MASK_ADD_UW 0xfe00707f
- +#define MATCH_SUB_UW 0x4800003b
- +#define MASK_SUB_UW 0xfe00707f
- #define MATCH_SLOW 0x2000103b
- #define MASK_SLOW 0xfe00707f
- #define MATCH_SROW 0x2000503b
- @@ -335,14 +335,14 @@
- #define MASK_ROLW 0xfe00707f
- #define MATCH_RORW 0x6000503b
- #define MASK_RORW 0xfe00707f
- -#define MATCH_SBCLRW 0x4800103b
- -#define MASK_SBCLRW 0xfe00707f
- -#define MATCH_SBSETW 0x2800103b
- -#define MASK_SBSETW 0xfe00707f
- -#define MATCH_SBINVW 0x6800103b
- -#define MASK_SBINVW 0xfe00707f
- -#define MATCH_SBEXTW 0x4800503b
- -#define MASK_SBEXTW 0xfe00707f
- +#define MATCH_BCLRW 0x4800103b
- +#define MASK_BCLRW 0xfe00707f
- +#define MATCH_BSETW 0x2800103b
- +#define MASK_BSETW 0xfe00707f
- +#define MATCH_BINVW 0x6800103b
- +#define MASK_BINVW 0xfe00707f
- +#define MATCH_BFEXTW 0x4800503b
- +#define MASK_BFEXTW 0xfe00707f
- #define MATCH_GORCW 0x2800503b
- #define MASK_GORCW 0xfe00707f
- #define MATCH_GREVW 0x6800503b
- @@ -353,12 +353,12 @@
- #define MASK_SROIW 0xfe00707f
- #define MATCH_RORIW 0x6000501b
- #define MASK_RORIW 0xfe00707f
- -#define MATCH_SBCLRIW 0x4800101b
- -#define MASK_SBCLRIW 0xfe00707f
- -#define MATCH_SBSETIW 0x2800101b
- -#define MASK_SBSETIW 0xfe00707f
- -#define MATCH_SBINVIW 0x6800101b
- -#define MASK_SBINVIW 0xfe00707f
- +#define MATCH_BCLRIW 0x4800101b
- +#define MASK_BCLRIW 0xfe00707f
- +#define MATCH_BSETIW 0x2800101b
- +#define MASK_BSETIW 0xfe00707f
- +#define MATCH_BINVIW 0x6800101b
- +#define MASK_BINVIW 0xfe00707f
- #define MATCH_GORCIW 0x2800501b
- #define MASK_GORCIW 0xfe00707f
- #define MATCH_GREVIW 0x6800501b
- @@ -373,14 +373,14 @@
- #define MASK_CLZW 0xfff0707f
- #define MATCH_CTZW 0x6010101b
- #define MASK_CTZW 0xfff0707f
- -#define MATCH_PCNTW 0x6020101b
- -#define MASK_PCNTW 0xfff0707f
- -#define MATCH_SH1ADDU_W 0x2000203b
- -#define MASK_SH1ADDU_W 0xfe00707f
- -#define MATCH_SH2ADDU_W 0x2000403b
- -#define MASK_SH2ADDU_W 0xfe00707f
- -#define MATCH_SH3ADDU_W 0x2000603b
- -#define MASK_SH3ADDU_W 0xfe00707f
- +#define MATCH_CPOPW 0x6020101b
- +#define MASK_CPOPW 0xfff0707f
- +#define MATCH_SH1ADD_UW 0x2000203b
- +#define MASK_SH1ADD_UW 0xfe00707f
- +#define MATCH_SH2ADD_UW 0x2000403b
- +#define MASK_SH2ADD_UW 0xfe00707f
- +#define MATCH_SH3ADD_UW 0x2000603b
- +#define MASK_SH3ADD_UW 0xfe00707f
- #define MATCH_SHFLW 0x800103b
- #define MASK_SHFLW 0xfe00707f
- #define MATCH_UNSHFLW 0x800503b
- @@ -3665,19 +3665,19 @@ DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
- DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
- DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
- DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
- -DECLARE_INSN(sbclr, MATCH_SBCLR, MASK_SBCLR)
- -DECLARE_INSN(sbset, MATCH_SBSET, MASK_SBSET)
- -DECLARE_INSN(sbinv, MATCH_SBINV, MASK_SBINV)
- -DECLARE_INSN(sbext, MATCH_SBEXT, MASK_SBEXT)
- +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
- +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
- +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
- +DECLARE_INSN(bfext, MATCH_BFEXT, MASK_BFEXT)
- DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
- DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
- DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
- DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
- DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
- -DECLARE_INSN(sbclri, MATCH_SBCLRI, MASK_SBCLRI)
- -DECLARE_INSN(sbseti, MATCH_SBSETI, MASK_SBSETI)
- -DECLARE_INSN(sbinvi, MATCH_SBINVI, MASK_SBINVI)
- -DECLARE_INSN(sbexti, MATCH_SBEXTI, MASK_SBEXTI)
- +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
- +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
- +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
- +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
- DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
- DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
- DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
- @@ -3687,7 +3687,7 @@ DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
- DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
- DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
- DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
- -DECLARE_INSN(pcnt, MATCH_PCNT, MASK_PCNT)
- +DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
- DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
- DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
- DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
- @@ -3724,25 +3724,25 @@ DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
- DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
- DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
- DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
- -DECLARE_INSN(slliu_w, MATCH_SLLIU_W, MASK_SLLIU_W)
- -DECLARE_INSN(addu_w, MATCH_ADDU_W, MASK_ADDU_W)
- -DECLARE_INSN(subu_w, MATCH_SUBU_W, MASK_SUBU_W)
- +DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
- +DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
- +DECLARE_INSN(sub_uw, MATCH_SUB_UW, MASK_SUB_UW)
- DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
- DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
- DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
- DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
- -DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
- -DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
- -DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
- -DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
- +DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
- +DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
- +DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
- +DECLARE_INSN(bfextw, MATCH_BFEXTW, MASK_BFEXTW)
- DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
- DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
- DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
- DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
- DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
- -DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
- -DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
- -DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
- +DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
- +DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
- +DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
- DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
- DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
- DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
- @@ -3750,10 +3750,10 @@ DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
- DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
- DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
- DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
- -DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW)
- -DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W)
- -DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W)
- -DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W)
- +DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
- +DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
- +DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
- +DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
- DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
- DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
- DECLARE_INSN(xperm_w, MATCH_XPERMW, MASK_XPERMW)
- diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
- index 02800fda64..6ff292d794 100644
- --- a/include/opcode/riscv.h
- +++ b/include/opcode/riscv.h
- @@ -391,18 +391,10 @@ enum riscv_insn_class
- INSN_CLASS_V_AND_ZVEDIV,
- INSN_CLASS_V_OR_ZVLSSEG,
- INSN_CLASS_V_AND_ZVQMAC,
- - INSN_CLASS_B_OR_ZBA,
- - INSN_CLASS_B_OR_ZBB,
- - INSN_CLASS_B_OR_ZBC,
- - INSN_CLASS_B_OR_ZBS,
- - INSN_CLASS_B_OR_ZBA_OR_ZBB,
- -
- - INSN_CLASS_B_OR_ZBE,
- - INSN_CLASS_B_OR_ZBF,
- - INSN_CLASS_B_OR_ZBM,
- - INSN_CLASS_B_OR_ZBP,
- - INSN_CLASS_ZBR,
- - INSN_CLASS_ZBT,
- + INSN_CLASS_ZBA,
- + INSN_CLASS_ZBB,
- + INSN_CLASS_ZBC,
- + INSN_CLASS_ZBA_OR_ZBB,
- };
-
- /* This structure holds information for a particular instruction. */
- @@ -448,7 +440,8 @@ enum riscv_isa_spec_class
-
- ISA_SPEC_CLASS_2P2,
- ISA_SPEC_CLASS_20190608,
- - ISA_SPEC_CLASS_20191213
- + ISA_SPEC_CLASS_20191213,
- + ISA_SPEC_CLASS_DRAFT
- };
-
- #define RISCV_UNKNOWN_VERSION -1
- @@ -582,8 +575,6 @@ enum
- M_LI,
- M_VMSGE,
- M_VMSGEU,
- - M_RL,
- - M_FL,
- M_ZEXTH,
- M_ZEXTW,
- M_SEXTB,
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index 5c07c0a2db..af408b041c 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -1053,8 +1053,6 @@ const struct riscv_opcode riscv_opcodes[] =
- {"rev.h", 64, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERMH_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"rev16", 32, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM16_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"rev16", 64, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM16_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- -{"rev8", 32, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_GREVI | MATCH_PERM8_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- -{"rev8", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_GREVI | MATCH_PERM8_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"rev4", 32, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM4_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"rev4", 64, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM4_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"rev2", 32, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM2_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- @@ -1078,8 +1076,6 @@ const struct riscv_opcode riscv_opcodes[] =
- {"orc4.b", 64, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM4B_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"orc2.b", 32, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM2B_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"orc2.b", 64, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM2B_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- -{"orc.b", 32, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_GORCI | MATCH_PERMB_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- -{"orc.b", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_GORCI | MATCH_PERMB_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"orc8.h", 32, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM8H_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"orc8.h", 64, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM8H_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"orc4.h", 32, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM4H_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- @@ -1157,77 +1153,53 @@ const struct riscv_opcode riscv_opcodes[] =
- {"unzip.w", 64, INSN_CLASS_B, "d,s", MATCH_UNSHFLI | MATCH_PERMW_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
- {"unzip16", 64, INSN_CLASS_B, "d,s", MATCH_UNSHFLI | MATCH_PERM16_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
-
- -/* Bitmanip instruction subset - for sure */
- -{"sh1add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
- -{"sh2add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
- -{"sh3add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
- -{"slliu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,>", MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
- -{"zext.w", 64, INSN_CLASS_B_OR_ZBA_OR_ZBB, "d,s", MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
- -{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
- -{"addu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
- -{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
- -{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
- -{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
- -
- -{"clz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
- -{"ctz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
- -{"pcnt", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNT, MASK_PCNT, match_opcode, 0 },
- -{"min", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
- -{"max", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
- -{"minu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
- -{"maxu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
- -{"andn", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
- -{"orn", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
- -{"xnor", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
- -{"roli", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO }, /* rori */
- -{"rol", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
- -{"rol", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO }, /* rori */
- -{"rori", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
- -{"ror", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
- -{"ror", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
- -{"sext.b", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
- -{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
- -{"sext.h", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
- -{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
- -{"zext.h", 32, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS }, /* pack with rs2=x0 */
- -{"zext.h", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS }, /* packw with rs2=x0 */
- -{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
- -{"clzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
- -{"ctzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
- -{"pcntw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
- -{"roliw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO }, /* roriw */
- -{"rolw", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
- -{"rolw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO }, /* roriw */
- -{"roriw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
- -{"rorw", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
- -{"rorw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
- -
- -{"clmul", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
- -{"clmulh", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
- -{"clmulr", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
- -
- -{"sbseti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
- -{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
- -{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
- -{"sbclri", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
- -{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
- -{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
- -{"sbinvi", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
- -{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
- -{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
- -{"sbexti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
- -{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
- -{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
- -{"sbsetiw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, 0 },
- -{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSETW, MASK_SBSETW, match_opcode, 0 },
- -{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, INSN_ALIAS },
- -{"sbclriw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
- -{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
- -{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
- -{"sbinviw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
- -{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINVW, MASK_SBINVW, match_opcode, 0 },
- -{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, INSN_ALIAS },
- -{"sbextw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 }, /* No sbextiw */
- +/* Bitmanip instruction subset - ZBA/ZBB/ZBC */
- +{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
- +{"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
- +{"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
- +{"sh1add.uw",64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
- +{"sh2add.uw",64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
- +{"sh3add.uw",64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
- +{"zext.w", 64, INSN_CLASS_ZBA_OR_ZBB, "d,s", MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS },
- +{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
- +{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
- +{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
- +
- +{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
- +{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
- +{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
- +{"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
- +{"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
- +{"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
- +{"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
- +{"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
- +{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
- +{"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
- +{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
- +{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
- +{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
- +{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
- +{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
- +{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
- +{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
- +{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
- +{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
- +{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
- +{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
- +{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
- +{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
- +{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
- +{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
- +{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
- +{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
- +{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
- +{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | ENCODE_ITYPE_IMM (0x18), MASK_GREVI | MASK_RVB_IMM, match_opcode, 0 },
- +{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | ENCODE_ITYPE_IMM (0x38), MASK_GREVI | MASK_RVB_IMM, match_opcode, 0 },
- +{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | ENCODE_ITYPE_IMM (0x7), MASK_GORCI | MASK_RVB_IMM, match_opcode, 0 },
- +
- +{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
- +{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
- +{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
-
- /* Bitmanip instruction subset - unsure */
- {"sloi", 0, INSN_CLASS_B, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
- @@ -1260,7 +1232,7 @@ const struct riscv_opcode riscv_opcodes[] =
- {"bmator", 64, INSN_CLASS_B, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
- {"bmatxor", 64, INSN_CLASS_B, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
- {"bfp", 0, INSN_CLASS_B, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
- -{"subu.w", 64, INSN_CLASS_B, "d,s,t", MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
- +{"sub.uw", 64, INSN_CLASS_B, "d,s,t", MATCH_SUB_UW, MASK_SUB_UW, match_opcode, 0 },
- {"sloiw", 64, INSN_CLASS_B, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
- {"sroiw", 64, INSN_CLASS_B, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
- {"slow", 64, INSN_CLASS_B, "d,s,t", MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
- @@ -1282,29 +1254,48 @@ const struct riscv_opcode riscv_opcodes[] =
- {"packuw", 64, INSN_CLASS_B, "d,s,t", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
- {"bfpw", 64, INSN_CLASS_B, "d,s,t", MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
-
- -{"cmix", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
- -{"cmov", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
- -{"fsli", 0, INSN_CLASS_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsri */
- -{"fsl", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 },
- -{"fsl", 0, INSN_CLASS_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsri */
- -{"fsri", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
- -{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
- -{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
- -{"fsliw", 64, INSN_CLASS_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsriw */
- -{"fslw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
- -{"fslw", 64, INSN_CLASS_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsriw */
- -{"fsriw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
- -{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
- -{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
- -
- -{"crc32.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
- -{"crc32.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
- -{"crc32.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
- -{"crc32c.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
- -{"crc32c.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
- -{"crc32c.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
- -{"crc32.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
- -{"crc32c.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
- +{"cmix", 0, INSN_CLASS_B, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
- +{"cmov", 0, INSN_CLASS_B, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
- +{"fsl", 0, INSN_CLASS_B, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 },
- +{"fsri", 0, INSN_CLASS_B, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
- +{"fsr", 0, INSN_CLASS_B, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
- +{"fsr", 0, INSN_CLASS_B, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
- +{"fslw", 64, INSN_CLASS_B, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
- +{"fsriw", 64, INSN_CLASS_B, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
- +{"fsrw", 64, INSN_CLASS_B, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
- +{"fsrw", 64, INSN_CLASS_B, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
- +
- +{"bseti", 0, INSN_CLASS_B, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
- +{"bset", 0, INSN_CLASS_B, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
- +{"bset", 0, INSN_CLASS_B, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
- +{"bclri", 0, INSN_CLASS_B, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
- +{"bclr", 0, INSN_CLASS_B, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
- +{"bclr", 0, INSN_CLASS_B, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
- +{"binvi", 0, INSN_CLASS_B, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
- +{"binv", 0, INSN_CLASS_B, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
- +{"binv", 0, INSN_CLASS_B, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
- +{"bexti", 0, INSN_CLASS_B, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
- +{"bfext", 0, INSN_CLASS_B, "d,s,t", MATCH_BFEXT, MASK_BFEXT, match_opcode, 0 },
- +{"bfext", 0, INSN_CLASS_B, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
- +{"bsetiw", 64, INSN_CLASS_B, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
- +{"bsetw", 64, INSN_CLASS_B, "d,s,t", MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
- +{"bsetw", 64, INSN_CLASS_B, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, INSN_ALIAS },
- +{"bclriw", 64, INSN_CLASS_B, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
- +{"bclrw", 64, INSN_CLASS_B, "d,s,t", MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
- +{"bclrw", 64, INSN_CLASS_B, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, INSN_ALIAS },
- +{"binviw", 64, INSN_CLASS_B, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
- +{"binvw", 64, INSN_CLASS_B, "d,s,t", MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
- +{"binvw", 64, INSN_CLASS_B, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, INSN_ALIAS },
- +{"bfextw", 64, INSN_CLASS_B, "d,s,t", MATCH_BFEXTW, MASK_BFEXTW, match_opcode, 0 }, /* No sbextiw */
- +
- +{"crc32.b", 0, INSN_CLASS_B, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
- +{"crc32.h", 0, INSN_CLASS_B, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
- +{"crc32.w", 0, INSN_CLASS_B, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
- +{"crc32c.b", 0, INSN_CLASS_B, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
- +{"crc32c.h", 0, INSN_CLASS_B, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
- +{"crc32c.w", 0, INSN_CLASS_B, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
- +{"crc32.d", 64, INSN_CLASS_B, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
- +{"crc32c.d", 64, INSN_CLASS_B, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
-
- /* Single-precision floating-point instruction subset */
- {"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
- @@ -2867,9 +2858,7 @@ const struct riscv_ext_version riscv_ext_version_table[] =
- {"c", ISA_SPEC_CLASS_20190608, 2, 0},
- {"c", ISA_SPEC_CLASS_2P2, 2, 0},
-
- -{"b", ISA_SPEC_CLASS_NONE, 0, 92},
- -
- -{"v", ISA_SPEC_CLASS_NONE, 1, 0},
- +{"v", ISA_SPEC_CLASS_DRAFT, 1, 0},
-
- {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
- {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
- @@ -2877,23 +2866,16 @@ const struct riscv_ext_version riscv_ext_version_table[] =
- {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
- {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
-
- -{"zfh", ISA_SPEC_CLASS_NONE, 0, 1},
- -
- -{"zba", ISA_SPEC_CLASS_NONE, 0, 92},
- -{"zbb", ISA_SPEC_CLASS_NONE, 0, 92},
- -{"zbc", ISA_SPEC_CLASS_NONE, 0, 92},
- -{"zbe", ISA_SPEC_CLASS_NONE, 0, 92},
- -{"zbf", ISA_SPEC_CLASS_NONE, 0, 92},
- -{"zbm", ISA_SPEC_CLASS_NONE, 0, 92},
- -{"zbp", ISA_SPEC_CLASS_NONE, 0, 92},
- -{"zbr", ISA_SPEC_CLASS_NONE, 0, 92},
- -{"zbs", ISA_SPEC_CLASS_NONE, 0, 92},
- -{"zbt", ISA_SPEC_CLASS_NONE, 0, 92},
- -
- -{"zvamo", ISA_SPEC_CLASS_NONE, 1, 0},
- -{"zvediv", ISA_SPEC_CLASS_NONE, 1, 0},
- -{"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
- -{"zvqmac", ISA_SPEC_CLASS_NONE, 1, 0},
- +{"zfh", ISA_SPEC_CLASS_DRAFT, 0, 1},
- +
- +{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +
- +{"zvamo", ISA_SPEC_CLASS_DRAFT, 1, 0},
- +{"zvediv", ISA_SPEC_CLASS_DRAFT, 1, 0},
- +{"zvlsseg", ISA_SPEC_CLASS_DRAFT, 1, 0},
- +{"zvqmac", ISA_SPEC_CLASS_DRAFT, 1, 0},
-
- /* Terminate the list. */
- {NULL, 0, 0, 0}
- --
- 2.33.0
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