0047-RISC-V-Freeze-ZBA-ZBB-ZBC-to-0.93.patch 62 KB

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  1. From c7b89dd10cf3e18c695533e214a51b3efe7dd992 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Thu, 7 Jan 2021 21:05:48 +0800
  4. Subject: [PATCH 47/48] RISC-V: Freeze ZBA/ZBB/ZBC to 0.93.
  5. Only enable the frozen ZBA/ZBB/ZBC, other ZB* can not be used but
  6. still keep their opcodes. Rename ZBS from sb* to b* will cause
  7. encoding conflicts for bext/bextw (ZBE), so rename the conflict
  8. sbext/sbextw to bfext/bfextw.
  9. Besides, cleanup and make them the same as the upstream code.
  10. ---
  11. bfd/elfxx-riscv.c | 3 +-
  12. gas/config/tc-riscv.c | 86 +------
  13. .../gas/riscv/attribute-15-unratified.d | 4 +-
  14. gas/testsuite/gas/riscv/bitmanip-insns-32.d | 26 ++-
  15. gas/testsuite/gas/riscv/bitmanip-insns-64.d | 53 ++---
  16. .../gas/riscv/bitmanip-insns-pseudo-32.d | 61 -----
  17. .../gas/riscv/bitmanip-insns-pseudo-64.d | 84 -------
  18. .../riscv/bitmanip-insns-pseudo-noalias-32.d | 61 -----
  19. .../riscv/bitmanip-insns-pseudo-noalias-64.d | 84 -------
  20. gas/testsuite/gas/riscv/bitmanip-insns.s | 57 ++---
  21. include/opcode/riscv-opc.h | 138 +++++------
  22. include/opcode/riscv.h | 21 +-
  23. opcodes/riscv-opc.c | 220 ++++++++----------
  24. 13 files changed, 256 insertions(+), 642 deletions(-)
  25. delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
  26. delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
  27. delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
  28. delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
  29. diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
  30. index 75add5be1c..af014b29cb 100644
  31. --- a/bfd/elfxx-riscv.c
  32. +++ b/bfd/elfxx-riscv.c
  33. @@ -1566,8 +1566,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
  34. static const char * const riscv_std_z_ext_strtab[] =
  35. {
  36. - "zicsr", "zifencei", "zfh",
  37. - "zba", "zbb", "zbc", "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt",
  38. + "zicsr", "zifencei", "zfh", "zba", "zbb", "zbc",
  39. "zvamo", "zvediv", "zvlsseg", "zvqmac",
  40. NULL
  41. };
  42. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  43. index 60b9a92d77..25405ca30d 100644
  44. --- a/gas/config/tc-riscv.c
  45. +++ b/gas/config/tc-riscv.c
  46. @@ -260,35 +260,14 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
  47. case INSN_CLASS_V_AND_ZVQMAC:
  48. return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
  49. - /* Sure. */
  50. - case INSN_CLASS_B_OR_ZBA:
  51. - return riscv_subset_supports ("b") || riscv_subset_supports ("zba");
  52. - case INSN_CLASS_B_OR_ZBB:
  53. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbb");
  54. - case INSN_CLASS_B_OR_ZBC:
  55. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbc");
  56. - case INSN_CLASS_B_OR_ZBS:
  57. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbs");
  58. - case INSN_CLASS_B_OR_ZBA_OR_ZBB:
  59. - return (riscv_subset_supports ("b")
  60. - || riscv_subset_supports ("zba")
  61. - || riscv_subset_supports ("zbb"));
  62. -
  63. - /* Not sure. */
  64. - case INSN_CLASS_B:
  65. - return riscv_subset_supports ("b");
  66. - case INSN_CLASS_B_OR_ZBE:
  67. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbe");
  68. - case INSN_CLASS_B_OR_ZBF:
  69. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbf");
  70. - case INSN_CLASS_B_OR_ZBM:
  71. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbm");
  72. - case INSN_CLASS_B_OR_ZBP:
  73. - return riscv_subset_supports ("b") || riscv_subset_supports ("zbp");
  74. - case INSN_CLASS_ZBR:
  75. - return riscv_subset_supports ("zbr");
  76. - case INSN_CLASS_ZBT:
  77. - return riscv_subset_supports ("zbt");
  78. + case INSN_CLASS_ZBA:
  79. + return riscv_subset_supports ("zba");
  80. + case INSN_CLASS_ZBB:
  81. + return riscv_subset_supports ("zbb");
  82. + case INSN_CLASS_ZBC:
  83. + return riscv_subset_supports ("zbc");
  84. + case INSN_CLASS_ZBA_OR_ZBB:
  85. + return riscv_subset_supports ("zba") || riscv_subset_supports ("zbb");
  86. default:
  87. as_fatal ("Unreachable");
  88. @@ -335,7 +314,7 @@ riscv_get_default_ext_version (const char *name,
  89. && ext->name
  90. && strcmp (ext->name, name) == 0)
  91. {
  92. - if (ext->isa_spec_class == ISA_SPEC_CLASS_NONE
  93. + if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT
  94. || ext->isa_spec_class == default_isa_spec)
  95. {
  96. *major_version = ext->major_version;
  97. @@ -1282,15 +1261,6 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
  98. INSERT_OPERAND (RS2, insn, va_arg (args, int));
  99. continue;
  100. - case 'r':
  101. - INSERT_OPERAND (RS3, insn, va_arg (args, int));
  102. - continue;
  103. -
  104. - case '<':
  105. - case '|':
  106. - INSERT_OPERAND (SHAMTW, insn, va_arg (args, int));
  107. - continue;
  108. -
  109. case '>':
  110. INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
  111. continue;
  112. @@ -1506,34 +1476,6 @@ load_const (int reg, expressionS *ep)
  113. }
  114. }
  115. -/* Immediate rotate left shift via right shift. */
  116. -
  117. -static void
  118. -rotate_left (int rd, int rs, unsigned shamt, unsigned this_xlen)
  119. -{
  120. - shamt = (this_xlen-1) & -shamt;
  121. -
  122. - if (this_xlen == xlen)
  123. - macro_build (NULL, "rori", "d,s,>", rd, rs, shamt);
  124. - else if (this_xlen == 32)
  125. - macro_build (NULL, "roriw", "d,s,<", rd, rs, shamt);
  126. - else
  127. - as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
  128. -}
  129. -
  130. -static void
  131. -funnel_left (int rd, int rs1, int rs3, unsigned shamt, unsigned this_xlen)
  132. -{
  133. - shamt = (this_xlen-1) & -shamt;
  134. -
  135. - if (this_xlen == xlen)
  136. - macro_build (NULL, "fsri", "d,s,r,>", rd, rs3, rs1, shamt);
  137. - else if (this_xlen == 32)
  138. - macro_build (NULL, "fsriw", "d,s,r,<", rd, rs3, rs1, shamt);
  139. - else
  140. - as_fatal (_("internal error: bad left shift xlen %d"), this_xlen);
  141. -}
  142. -
  143. /* Expand RISC-V Vector macros into one of more instructions. */
  144. static void
  145. @@ -1649,8 +1591,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
  146. int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
  147. int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
  148. int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
  149. - int rs3 = (ip->insn_opcode >> OP_SH_RS3) & OP_MASK_RS3;
  150. - int shamt = (ip->insn_opcode >> OP_SH_SHAMT) & OP_MASK_SHAMT;
  151. int mask = ip->insn_mo->mask;
  152. switch (mask)
  153. @@ -1659,14 +1599,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
  154. load_const (rd, imm_expr);
  155. break;
  156. - case M_RL:
  157. - rotate_left (rd, rs1, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
  158. - break;
  159. -
  160. - case M_FL:
  161. - funnel_left (rd, rs1, rs3, shamt, ip->insn_mo->xlen_requirement ? ip->insn_mo->xlen_requirement/2 : xlen);
  162. - break;
  163. -
  164. case M_LA:
  165. case M_LLA:
  166. /* Load the address of a symbol into a register. */
  167. diff --git a/gas/testsuite/gas/riscv/attribute-15-unratified.d b/gas/testsuite/gas/riscv/attribute-15-unratified.d
  168. index 4645762bd6..3d6c68ec2c 100644
  169. --- a/gas/testsuite/gas/riscv/attribute-15-unratified.d
  170. +++ b/gas/testsuite/gas/riscv/attribute-15-unratified.d
  171. @@ -1,6 +1,6 @@
  172. -#as: -march-attr -march=rv32ibv_zfh_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt_zvamo_zvediv_zvlsseg_zvqmac
  173. +#as: -march-attr -march=rv32iv_zfh_zba_zbb_zbc_zvamo_zvediv_zvlsseg_zvqmac
  174. #readelf: -A
  175. #source: empty.s
  176. Attribute Section: riscv
  177. File Attributes
  178. - Tag_RISCV_arch: ".*_b0p92_v1p0_zfh0p1_zba0p92_zbb0p92_zbc0p92_zbe0p92_zbf0p92_zbm0p92_zbp0p92_zbr0p92_zbs0p92_zbt0p92_zvamo1p0_zvediv1p0_zvlsseg1p0_zvqmac1p0"
  179. + Tag_RISCV_arch: ".*_v1p0_zfh0p1_zba0p93_zbb0p93_zbc0p93_zvamo1p0_zvediv1p0_zvlsseg1p0_zvqmac1p0"
  180. diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
  181. index bda9d603af..b218f96e94 100644
  182. --- a/gas/testsuite/gas/riscv/bitmanip-insns-32.d
  183. +++ b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
  184. @@ -1,6 +1,6 @@
  185. -#as: -march=rv32i_zba_zbb
  186. +#as: -march=rv32i_zba_zbb_zbc
  187. #source: bitmanip-insns.s
  188. -#objdump: -dr
  189. +#objdump: -dr -Mno-aliases
  190. .*:[ ]+file format .*
  191. @@ -8,28 +8,30 @@
  192. Disassembly of section .text:
  193. 0+000 <.text>:
  194. +[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext.h[ ]+a0,a1
  195. +[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
  196. +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1
  197. [ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
  198. [ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
  199. [ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
  200. [ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
  201. [ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
  202. -[ ]+[0-9a-f]+:[ ]+60259513[ ]+pcnt[ ]+a0,a1
  203. +[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
  204. [ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
  205. [ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
  206. [ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
  207. [ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
  208. +[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1
  209. +[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1
  210. [ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
  211. [ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
  212. [ ]+[0-9a-f]+:[ ]+00c5c533[ ]+xor[ ]+a0,a1,a2
  213. -[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
  214. -[ ]+[0-9a-f]+:[ ]+6015d513[ ]+rori[ ]+a0,a1,0x1
  215. -[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
  216. -[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
  217. -[ ]+[0-9a-f]+:[ ]+6015d513[ ]+rori[ ]+a0,a1,0x1
  218. -[ ]+[0-9a-f]+:[ ]+6015d513[ ]+rori[ ]+a0,a1,0x1
  219. +[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
  220. [ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
  221. [ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
  222. -[ ]+[0-9a-f]+:[ ]+6015d513[ ]+rori[ ]+a0,a1,0x1
  223. +[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
  224. [ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
  225. -[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1
  226. -[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1
  227. +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
  228. +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
  229. +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
  230. +[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
  231. diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
  232. index 843bb319be..9914f3e557 100644
  233. --- a/gas/testsuite/gas/riscv/bitmanip-insns-64.d
  234. +++ b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
  235. @@ -1,6 +1,6 @@
  236. -#as: -march=rv64i_zba_zbb -defsym __64_bit__=1
  237. +#as: -march=rv64i_zba_zbb_zbc -defsym __64_bit__=1
  238. #source: bitmanip-insns.s
  239. -#objdump: -dr
  240. +#objdump: -dr -Mno-aliases
  241. .*:[ ]+file format .*
  242. @@ -8,51 +8,48 @@
  243. Disassembly of section .text:
  244. 0+000 <.text>:
  245. +[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext.h[ ]+a0,a1
  246. +[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
  247. +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1
  248. +[ ]+[0-9a-f]+:[ ]+0805853b[ ]+add.uw[ ]+a0,a1,zero
  249. [ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
  250. [ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
  251. [ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
  252. -[ ]+[0-9a-f]+:[ ]+0815951b[ ]+slliu.w[ ]+a0,a1,0x1
  253. -[ ]+[0-9a-f]+:[ ]+0bf5951b[ ]+slliu.w[ ]+a0,a1,0x3f
  254. -[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+addu.w[ ]+a0,a1,a2
  255. -[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1addu.w[ ]+a0,a1,a2
  256. -[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2addu.w[ ]+a0,a1,a2
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  316. diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
  317. deleted file mode 100644
  318. index b0cdb16efc..0000000000
  319. --- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
  320. +++ /dev/null
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  383. diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
  384. deleted file mode 100644
  385. index 23b8b7b5a6..0000000000
  386. --- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
  387. +++ /dev/null
  388. @@ -1,84 +0,0 @@
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  473. diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
  474. deleted file mode 100644
  475. index 91190c8b6a..0000000000
  476. --- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-32.d
  477. +++ /dev/null
  478. @@ -1,61 +0,0 @@
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  488. -0+000 <.text>:
  489. -[ ]+[0-9a-f]+:[ ]+0805c533[ ]+pack[ ]+a0,a1,zero
  490. -[ ]+[0-9a-f]+:[ ]+6815d513[ ]+grevi[ ]+a0,a1,0x1
  491. -[ ]+[0-9a-f]+:[ ]+6825d513[ ]+grevi[ ]+a0,a1,0x2
  492. -[ ]+[0-9a-f]+:[ ]+6835d513[ ]+grevi[ ]+a0,a1,0x3
  493. -[ ]+[0-9a-f]+:[ ]+6845d513[ ]+grevi[ ]+a0,a1,0x4
  494. -[ ]+[0-9a-f]+:[ ]+6865d513[ ]+grevi[ ]+a0,a1,0x6
  495. -[ ]+[0-9a-f]+:[ ]+6875d513[ ]+grevi[ ]+a0,a1,0x7
  496. -[ ]+[0-9a-f]+:[ ]+6885d513[ ]+grevi[ ]+a0,a1,0x8
  497. -[ ]+[0-9a-f]+:[ ]+68c5d513[ ]+grevi[ ]+a0,a1,0xc
  498. -[ ]+[0-9a-f]+:[ ]+68e5d513[ ]+grevi[ ]+a0,a1,0xe
  499. -[ ]+[0-9a-f]+:[ ]+68f5d513[ ]+grevi[ ]+a0,a1,0xf
  500. -[ ]+[0-9a-f]+:[ ]+6905d513[ ]+grevi[ ]+a0,a1,0x10
  501. -[ ]+[0-9a-f]+:[ ]+6985d513[ ]+grevi[ ]+a0,a1,0x18
  502. -[ ]+[0-9a-f]+:[ ]+69c5d513[ ]+grevi[ ]+a0,a1,0x1c
  503. -[ ]+[0-9a-f]+:[ ]+69e5d513[ ]+grevi[ ]+a0,a1,0x1e
  504. -[ ]+[0-9a-f]+:[ ]+69f5d513[ ]+grevi[ ]+a0,a1,0x1f
  505. -[ ]+[0-9a-f]+:[ ]+2815d513[ ]+gorci[ ]+a0,a1,0x1
  506. -[ ]+[0-9a-f]+:[ ]+2825d513[ ]+gorci[ ]+a0,a1,0x2
  507. -[ ]+[0-9a-f]+:[ ]+2835d513[ ]+gorci[ ]+a0,a1,0x3
  508. -[ ]+[0-9a-f]+:[ ]+2845d513[ ]+gorci[ ]+a0,a1,0x4
  509. -[ ]+[0-9a-f]+:[ ]+2865d513[ ]+gorci[ ]+a0,a1,0x6
  510. -[ ]+[0-9a-f]+:[ ]+2875d513[ ]+gorci[ ]+a0,a1,0x7
  511. -[ ]+[0-9a-f]+:[ ]+2885d513[ ]+gorci[ ]+a0,a1,0x8
  512. -[ ]+[0-9a-f]+:[ ]+28c5d513[ ]+gorci[ ]+a0,a1,0xc
  513. -[ ]+[0-9a-f]+:[ ]+28e5d513[ ]+gorci[ ]+a0,a1,0xe
  514. -[ ]+[0-9a-f]+:[ ]+28f5d513[ ]+gorci[ ]+a0,a1,0xf
  515. -[ ]+[0-9a-f]+:[ ]+2905d513[ ]+gorci[ ]+a0,a1,0x10
  516. -[ ]+[0-9a-f]+:[ ]+2985d513[ ]+gorci[ ]+a0,a1,0x18
  517. -[ ]+[0-9a-f]+:[ ]+29c5d513[ ]+gorci[ ]+a0,a1,0x1c
  518. -[ ]+[0-9a-f]+:[ ]+29e5d513[ ]+gorci[ ]+a0,a1,0x1e
  519. -[ ]+[0-9a-f]+:[ ]+29f5d513[ ]+gorci[ ]+a0,a1,0x1f
  520. -[ ]+[0-9a-f]+:[ ]+08159513[ ]+shfli[ ]+a0,a1,0x1
  521. -[ ]+[0-9a-f]+:[ ]+08259513[ ]+shfli[ ]+a0,a1,0x2
  522. -[ ]+[0-9a-f]+:[ ]+08359513[ ]+shfli[ ]+a0,a1,0x3
  523. -[ ]+[0-9a-f]+:[ ]+08459513[ ]+shfli[ ]+a0,a1,0x4
  524. -[ ]+[0-9a-f]+:[ ]+08659513[ ]+shfli[ ]+a0,a1,0x6
  525. -[ ]+[0-9a-f]+:[ ]+08759513[ ]+shfli[ ]+a0,a1,0x7
  526. -[ ]+[0-9a-f]+:[ ]+08859513[ ]+shfli[ ]+a0,a1,0x8
  527. -[ ]+[0-9a-f]+:[ ]+08c59513[ ]+shfli[ ]+a0,a1,0xc
  528. -[ ]+[0-9a-f]+:[ ]+08e59513[ ]+shfli[ ]+a0,a1,0xe
  529. -[ ]+[0-9a-f]+:[ ]+08f59513[ ]+shfli[ ]+a0,a1,0xf
  530. -[ ]+[0-9a-f]+:[ ]+0815d513[ ]+unshfli[ ]+a0,a1,0x1
  531. -[ ]+[0-9a-f]+:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
  532. -[ ]+[0-9a-f]+:[ ]+0835d513[ ]+unshfli[ ]+a0,a1,0x3
  533. -[ ]+[0-9a-f]+:[ ]+0845d513[ ]+unshfli[ ]+a0,a1,0x4
  534. -[ ]+[0-9a-f]+:[ ]+0865d513[ ]+unshfli[ ]+a0,a1,0x6
  535. -[ ]+[0-9a-f]+:[ ]+0875d513[ ]+unshfli[ ]+a0,a1,0x7
  536. -[ ]+[0-9a-f]+:[ ]+0885d513[ ]+unshfli[ ]+a0,a1,0x8
  537. -[ ]+[0-9a-f]+:[ ]+08c5d513[ ]+unshfli[ ]+a0,a1,0xc
  538. -[ ]+[0-9a-f]+:[ ]+08e5d513[ ]+unshfli[ ]+a0,a1,0xe
  539. -[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unshfli[ ]+a0,a1,0xf
  540. diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
  541. deleted file mode 100644
  542. index 187c487e7c..0000000000
  543. --- a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-noalias-64.d
  544. +++ /dev/null
  545. @@ -1,84 +0,0 @@
  546. -#as: -march=rv64ib -defsym __64_bit__=1
  547. -#source: bitmanip-insns-pseudo.s
  548. -#objdump: -dr -Mno-aliases
  549. -
  550. -.*:[ ]+file format .*
  551. -
  552. -
  553. -Disassembly of section .text:
  554. -
  555. -0+000 <.text>:
  556. -[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+packw[ ]+a0,a1,zero
  557. -[ ]+[0-9a-f]+:[ ]+6815d513[ ]+grevi[ ]+a0,a1,0x1
  558. -[ ]+[0-9a-f]+:[ ]+6825d513[ ]+grevi[ ]+a0,a1,0x2
  559. -[ ]+[0-9a-f]+:[ ]+6835d513[ ]+grevi[ ]+a0,a1,0x3
  560. -[ ]+[0-9a-f]+:[ ]+6845d513[ ]+grevi[ ]+a0,a1,0x4
  561. -[ ]+[0-9a-f]+:[ ]+6865d513[ ]+grevi[ ]+a0,a1,0x6
  562. -[ ]+[0-9a-f]+:[ ]+6875d513[ ]+grevi[ ]+a0,a1,0x7
  563. -[ ]+[0-9a-f]+:[ ]+6885d513[ ]+grevi[ ]+a0,a1,0x8
  564. -[ ]+[0-9a-f]+:[ ]+68c5d513[ ]+grevi[ ]+a0,a1,0xc
  565. -[ ]+[0-9a-f]+:[ ]+68e5d513[ ]+grevi[ ]+a0,a1,0xe
  566. -[ ]+[0-9a-f]+:[ ]+68f5d513[ ]+grevi[ ]+a0,a1,0xf
  567. -[ ]+[0-9a-f]+:[ ]+6b05d513[ ]+grevi[ ]+a0,a1,0x30
  568. -[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+grevi[ ]+a0,a1,0x38
  569. -[ ]+[0-9a-f]+:[ ]+6bc5d513[ ]+grevi[ ]+a0,a1,0x3c
  570. -[ ]+[0-9a-f]+:[ ]+6be5d513[ ]+grevi[ ]+a0,a1,0x3e
  571. -[ ]+[0-9a-f]+:[ ]+6bf5d513[ ]+grevi[ ]+a0,a1,0x3f
  572. -[ ]+[0-9a-f]+:[ ]+2815d513[ ]+gorci[ ]+a0,a1,0x1
  573. -[ ]+[0-9a-f]+:[ ]+2825d513[ ]+gorci[ ]+a0,a1,0x2
  574. -[ ]+[0-9a-f]+:[ ]+2835d513[ ]+gorci[ ]+a0,a1,0x3
  575. -[ ]+[0-9a-f]+:[ ]+2845d513[ ]+gorci[ ]+a0,a1,0x4
  576. -[ ]+[0-9a-f]+:[ ]+2865d513[ ]+gorci[ ]+a0,a1,0x6
  577. -[ ]+[0-9a-f]+:[ ]+2875d513[ ]+gorci[ ]+a0,a1,0x7
  578. -[ ]+[0-9a-f]+:[ ]+2885d513[ ]+gorci[ ]+a0,a1,0x8
  579. -[ ]+[0-9a-f]+:[ ]+28c5d513[ ]+gorci[ ]+a0,a1,0xc
  580. -[ ]+[0-9a-f]+:[ ]+28e5d513[ ]+gorci[ ]+a0,a1,0xe
  581. -[ ]+[0-9a-f]+:[ ]+28f5d513[ ]+gorci[ ]+a0,a1,0xf
  582. -[ ]+[0-9a-f]+:[ ]+2b05d513[ ]+gorci[ ]+a0,a1,0x30
  583. -[ ]+[0-9a-f]+:[ ]+2b85d513[ ]+gorci[ ]+a0,a1,0x38
  584. -[ ]+[0-9a-f]+:[ ]+2bc5d513[ ]+gorci[ ]+a0,a1,0x3c
  585. -[ ]+[0-9a-f]+:[ ]+2be5d513[ ]+gorci[ ]+a0,a1,0x3e
  586. -[ ]+[0-9a-f]+:[ ]+2bf5d513[ ]+gorci[ ]+a0,a1,0x3f
  587. -[ ]+[0-9a-f]+:[ ]+08159513[ ]+shfli[ ]+a0,a1,0x1
  588. -[ ]+[0-9a-f]+:[ ]+08259513[ ]+shfli[ ]+a0,a1,0x2
  589. -[ ]+[0-9a-f]+:[ ]+08359513[ ]+shfli[ ]+a0,a1,0x3
  590. -[ ]+[0-9a-f]+:[ ]+08459513[ ]+shfli[ ]+a0,a1,0x4
  591. -[ ]+[0-9a-f]+:[ ]+08659513[ ]+shfli[ ]+a0,a1,0x6
  592. -[ ]+[0-9a-f]+:[ ]+08759513[ ]+shfli[ ]+a0,a1,0x7
  593. -[ ]+[0-9a-f]+:[ ]+09859513[ ]+shfli[ ]+a0,a1,0x18
  594. -[ ]+[0-9a-f]+:[ ]+09c59513[ ]+shfli[ ]+a0,a1,0x1c
  595. -[ ]+[0-9a-f]+:[ ]+09e59513[ ]+shfli[ ]+a0,a1,0x1e
  596. -[ ]+[0-9a-f]+:[ ]+09f59513[ ]+shfli[ ]+a0,a1,0x1f
  597. -[ ]+[0-9a-f]+:[ ]+0815d513[ ]+unshfli[ ]+a0,a1,0x1
  598. -[ ]+[0-9a-f]+:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
  599. -[ ]+[0-9a-f]+:[ ]+0835d513[ ]+unshfli[ ]+a0,a1,0x3
  600. -[ ]+[0-9a-f]+:[ ]+0845d513[ ]+unshfli[ ]+a0,a1,0x4
  601. -[ ]+[0-9a-f]+:[ ]+0865d513[ ]+unshfli[ ]+a0,a1,0x6
  602. -[ ]+[0-9a-f]+:[ ]+0875d513[ ]+unshfli[ ]+a0,a1,0x7
  603. -[ ]+[0-9a-f]+:[ ]+0985d513[ ]+unshfli[ ]+a0,a1,0x18
  604. -[ ]+[0-9a-f]+:[ ]+09c5d513[ ]+unshfli[ ]+a0,a1,0x1c
  605. -[ ]+[0-9a-f]+:[ ]+09e5d513[ ]+unshfli[ ]+a0,a1,0x1e
  606. -[ ]+[0-9a-f]+:[ ]+09f5d513[ ]+unshfli[ ]+a0,a1,0x1f
  607. -[ ]+[0-9a-f]+:[ ]+0805853b[ ]+addu.w[ ]+a0,a1,zero
  608. -[ ]+[0-9a-f]+:[ ]+6905d513[ ]+grevi[ ]+a0,a1,0x10
  609. -[ ]+[0-9a-f]+:[ ]+6985d513[ ]+grevi[ ]+a0,a1,0x18
  610. -[ ]+[0-9a-f]+:[ ]+69c5d513[ ]+grevi[ ]+a0,a1,0x1c
  611. -[ ]+[0-9a-f]+:[ ]+69e5d513[ ]+grevi[ ]+a0,a1,0x1e
  612. -[ ]+[0-9a-f]+:[ ]+69f5d513[ ]+grevi[ ]+a0,a1,0x1f
  613. -[ ]+[0-9a-f]+:[ ]+6a05d513[ ]+grevi[ ]+a0,a1,0x20
  614. -[ ]+[0-9a-f]+:[ ]+2905d513[ ]+gorci[ ]+a0,a1,0x10
  615. -[ ]+[0-9a-f]+:[ ]+2985d513[ ]+gorci[ ]+a0,a1,0x18
  616. -[ ]+[0-9a-f]+:[ ]+29c5d513[ ]+gorci[ ]+a0,a1,0x1c
  617. -[ ]+[0-9a-f]+:[ ]+29e5d513[ ]+gorci[ ]+a0,a1,0x1e
  618. -[ ]+[0-9a-f]+:[ ]+29f5d513[ ]+gorci[ ]+a0,a1,0x1f
  619. -[ ]+[0-9a-f]+:[ ]+2a05d513[ ]+gorci[ ]+a0,a1,0x20
  620. -[ ]+[0-9a-f]+:[ ]+08859513[ ]+shfli[ ]+a0,a1,0x8
  621. -[ ]+[0-9a-f]+:[ ]+08c59513[ ]+shfli[ ]+a0,a1,0xc
  622. -[ ]+[0-9a-f]+:[ ]+08e59513[ ]+shfli[ ]+a0,a1,0xe
  623. -[ ]+[0-9a-f]+:[ ]+08f59513[ ]+shfli[ ]+a0,a1,0xf
  624. -[ ]+[0-9a-f]+:[ ]+09059513[ ]+shfli[ ]+a0,a1,0x10
  625. -[ ]+[0-9a-f]+:[ ]+0885d513[ ]+unshfli[ ]+a0,a1,0x8
  626. -[ ]+[0-9a-f]+:[ ]+08c5d513[ ]+unshfli[ ]+a0,a1,0xc
  627. -[ ]+[0-9a-f]+:[ ]+08e5d513[ ]+unshfli[ ]+a0,a1,0xe
  628. -[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unshfli[ ]+a0,a1,0xf
  629. -[ ]+[0-9a-f]+:[ ]+0905d513[ ]+unshfli[ ]+a0,a1,0x10
  630. diff --git a/gas/testsuite/gas/riscv/bitmanip-insns.s b/gas/testsuite/gas/riscv/bitmanip-insns.s
  631. index 52e4b3afff..b14e89c1d4 100644
  632. --- a/gas/testsuite/gas/riscv/bitmanip-insns.s
  633. +++ b/gas/testsuite/gas/riscv/bitmanip-insns.s
  634. @@ -1,57 +1,58 @@
  635. + # pseudo/aliaese
  636. + zext.h a0, a1
  637. + rev8 a0, a1
  638. + orc.b a0, a1
  639. +.ifdef __64_bit__
  640. + zext.w a0, a1
  641. +.endif
  642. +
  643. # ZBA
  644. sh1add a0, a1, a2
  645. sh2add a0, a1, a2
  646. sh3add a0, a1, a2
  647. -
  648. .ifdef __64_bit__
  649. - slliu.w a0, a1, 1
  650. - slliu.w a0, a1, 63
  651. - addu.w a0, a1, a2
  652. - sh1addu.w a0, a1, a2
  653. - sh2addu.w a0, a1, a2
  654. - sh3addu.w a0, a1, a2
  655. + sh1add.uw a0, a1, a2
  656. + sh2add.uw a0, a1, a2
  657. + sh3add.uw a0, a1, a2
  658. + add.uw a0, a1, a2
  659. + slli.uw a0, a1, 0
  660. + slli.uw a0, a1, 63
  661. .endif
  662. # ZBB
  663. clz a0, a1
  664. ctz a0, a1
  665. - pcnt a0, a1
  666. + cpop a0, a1
  667. min a0, a1, a2
  668. max a0, a1, a2
  669. minu a0, a1, a2
  670. maxu a0, a1, a2
  671. + sext.b a0, a1
  672. + sext.h a0, a1
  673. andn a0, a1, a2
  674. orn a0, a1, a2
  675. xor a0, a1, a2
  676. - roli a0, a1, 1
  677. - roli a0, a1, 31
  678. - rol a0, a1, a2
  679. - rol a0, a1, 1
  680. - rol a0, a1, 31
  681. - rori a0, a1, 1
  682. + rori a0, a1, 0
  683. rori a0, a1, 31
  684. ror a0, a1, a2
  685. - ror a0, a1, 1
  686. + ror a0, a1, 0
  687. ror a0, a1, 31
  688. - sext.b a0, a1
  689. - sext.h a0, a1
  690. -
  691. + rol a0, a1, a2
  692. .ifdef __64_bit__
  693. clzw a0, a1
  694. ctzw a0, a1
  695. - pcntw a0, a1
  696. - roli a0, a1, 63
  697. - rol a0, a1, 63
  698. + cpopw a0, a1
  699. rori a0, a1, 63
  700. ror a0, a1, 63
  701. - roliw a0, a1, 1
  702. - roliw a0, a1, 31
  703. - roriw a0, a1, 1
  704. + roriw a0, a1, 0
  705. roriw a0, a1, 31
  706. - rolw a0, a1, a2
  707. - rolw a0, a1, 1
  708. - rolw a0, a1, 31
  709. rorw a0, a1, a2
  710. - rorw a0, a1, 1
  711. + rorw a0, a1, 0
  712. rorw a0, a1, 31
  713. + rolw a0, a1, a2
  714. .endif
  715. +
  716. + # ZBC
  717. + clmul a0, a1, a2
  718. + clmulh a0, a1, a2
  719. + clmulr a0, a1, a2
  720. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  721. index 1faa2a8a8a..d481d5e2e6 100644
  722. --- a/include/opcode/riscv-opc.h
  723. +++ b/include/opcode/riscv-opc.h
  724. @@ -203,14 +203,14 @@
  725. #define MASK_ROL 0xfe00707f
  726. #define MATCH_ROR 0x60005033
  727. #define MASK_ROR 0xfe00707f
  728. -#define MATCH_SBCLR 0x48001033
  729. -#define MASK_SBCLR 0xfe00707f
  730. -#define MATCH_SBSET 0x28001033
  731. -#define MASK_SBSET 0xfe00707f
  732. -#define MATCH_SBINV 0x68001033
  733. -#define MASK_SBINV 0xfe00707f
  734. -#define MATCH_SBEXT 0x48005033
  735. -#define MASK_SBEXT 0xfe00707f
  736. +#define MATCH_BCLR 0x48001033
  737. +#define MASK_BCLR 0xfe00707f
  738. +#define MATCH_BSET 0x28001033
  739. +#define MASK_BSET 0xfe00707f
  740. +#define MATCH_BINV 0x68001033
  741. +#define MASK_BINV 0xfe00707f
  742. +#define MATCH_BFEXT 0x48005033
  743. +#define MASK_BFEXT 0xfe00707f
  744. #define MATCH_GORC 0x28005033
  745. #define MASK_GORC 0xfe00707f
  746. #define MATCH_GREV 0x68005033
  747. @@ -221,14 +221,14 @@
  748. #define MASK_SROI 0xfc00707f
  749. #define MATCH_RORI 0x60005013
  750. #define MASK_RORI 0xfc00707f
  751. -#define MATCH_SBCLRI 0x48001013
  752. -#define MASK_SBCLRI 0xfc00707f
  753. -#define MATCH_SBSETI 0x28001013
  754. -#define MASK_SBSETI 0xfc00707f
  755. -#define MATCH_SBINVI 0x68001013
  756. -#define MASK_SBINVI 0xfc00707f
  757. -#define MATCH_SBEXTI 0x48005013
  758. -#define MASK_SBEXTI 0xfc00707f
  759. +#define MATCH_BCLRI 0x48001013
  760. +#define MASK_BCLRI 0xfc00707f
  761. +#define MATCH_BSETI 0x28001013
  762. +#define MASK_BSETI 0xfc00707f
  763. +#define MATCH_BINVI 0x68001013
  764. +#define MASK_BINVI 0xfc00707f
  765. +#define MATCH_BEXTI 0x48005013
  766. +#define MASK_BEXTI 0xfc00707f
  767. #define MATCH_GORCI 0x28005013
  768. #define MASK_GORCI 0xfc00707f
  769. #define MATCH_GREVI 0x68005013
  770. @@ -247,8 +247,8 @@
  771. #define MASK_CLZ 0xfff0707f
  772. #define MATCH_CTZ 0x60101013
  773. #define MASK_CTZ 0xfff0707f
  774. -#define MATCH_PCNT 0x60201013
  775. -#define MASK_PCNT 0xfff0707f
  776. +#define MATCH_CPOP 0x60201013
  777. +#define MASK_CPOP 0xfff0707f
  778. #define MATCH_SEXT_B 0x60401013
  779. #define MASK_SEXT_B 0xfff0707f
  780. #define MATCH_SEXT_H 0x60501013
  781. @@ -321,12 +321,12 @@
  782. #define MASK_BMATOR 0xfe00707f
  783. #define MATCH_BMATXOR 0x48003033
  784. #define MASK_BMATXOR 0xfe00707f
  785. -#define MATCH_SLLIU_W 0x800101b
  786. -#define MASK_SLLIU_W 0xfc00707f
  787. -#define MATCH_ADDU_W 0x800003b
  788. -#define MASK_ADDU_W 0xfe00707f
  789. -#define MATCH_SUBU_W 0x4800003b
  790. -#define MASK_SUBU_W 0xfe00707f
  791. +#define MATCH_SLLI_UW 0x800101b
  792. +#define MASK_SLLI_UW 0xfc00707f
  793. +#define MATCH_ADD_UW 0x800003b
  794. +#define MASK_ADD_UW 0xfe00707f
  795. +#define MATCH_SUB_UW 0x4800003b
  796. +#define MASK_SUB_UW 0xfe00707f
  797. #define MATCH_SLOW 0x2000103b
  798. #define MASK_SLOW 0xfe00707f
  799. #define MATCH_SROW 0x2000503b
  800. @@ -335,14 +335,14 @@
  801. #define MASK_ROLW 0xfe00707f
  802. #define MATCH_RORW 0x6000503b
  803. #define MASK_RORW 0xfe00707f
  804. -#define MATCH_SBCLRW 0x4800103b
  805. -#define MASK_SBCLRW 0xfe00707f
  806. -#define MATCH_SBSETW 0x2800103b
  807. -#define MASK_SBSETW 0xfe00707f
  808. -#define MATCH_SBINVW 0x6800103b
  809. -#define MASK_SBINVW 0xfe00707f
  810. -#define MATCH_SBEXTW 0x4800503b
  811. -#define MASK_SBEXTW 0xfe00707f
  812. +#define MATCH_BCLRW 0x4800103b
  813. +#define MASK_BCLRW 0xfe00707f
  814. +#define MATCH_BSETW 0x2800103b
  815. +#define MASK_BSETW 0xfe00707f
  816. +#define MATCH_BINVW 0x6800103b
  817. +#define MASK_BINVW 0xfe00707f
  818. +#define MATCH_BFEXTW 0x4800503b
  819. +#define MASK_BFEXTW 0xfe00707f
  820. #define MATCH_GORCW 0x2800503b
  821. #define MASK_GORCW 0xfe00707f
  822. #define MATCH_GREVW 0x6800503b
  823. @@ -353,12 +353,12 @@
  824. #define MASK_SROIW 0xfe00707f
  825. #define MATCH_RORIW 0x6000501b
  826. #define MASK_RORIW 0xfe00707f
  827. -#define MATCH_SBCLRIW 0x4800101b
  828. -#define MASK_SBCLRIW 0xfe00707f
  829. -#define MATCH_SBSETIW 0x2800101b
  830. -#define MASK_SBSETIW 0xfe00707f
  831. -#define MATCH_SBINVIW 0x6800101b
  832. -#define MASK_SBINVIW 0xfe00707f
  833. +#define MATCH_BCLRIW 0x4800101b
  834. +#define MASK_BCLRIW 0xfe00707f
  835. +#define MATCH_BSETIW 0x2800101b
  836. +#define MASK_BSETIW 0xfe00707f
  837. +#define MATCH_BINVIW 0x6800101b
  838. +#define MASK_BINVIW 0xfe00707f
  839. #define MATCH_GORCIW 0x2800501b
  840. #define MASK_GORCIW 0xfe00707f
  841. #define MATCH_GREVIW 0x6800501b
  842. @@ -373,14 +373,14 @@
  843. #define MASK_CLZW 0xfff0707f
  844. #define MATCH_CTZW 0x6010101b
  845. #define MASK_CTZW 0xfff0707f
  846. -#define MATCH_PCNTW 0x6020101b
  847. -#define MASK_PCNTW 0xfff0707f
  848. -#define MATCH_SH1ADDU_W 0x2000203b
  849. -#define MASK_SH1ADDU_W 0xfe00707f
  850. -#define MATCH_SH2ADDU_W 0x2000403b
  851. -#define MASK_SH2ADDU_W 0xfe00707f
  852. -#define MATCH_SH3ADDU_W 0x2000603b
  853. -#define MASK_SH3ADDU_W 0xfe00707f
  854. +#define MATCH_CPOPW 0x6020101b
  855. +#define MASK_CPOPW 0xfff0707f
  856. +#define MATCH_SH1ADD_UW 0x2000203b
  857. +#define MASK_SH1ADD_UW 0xfe00707f
  858. +#define MATCH_SH2ADD_UW 0x2000403b
  859. +#define MASK_SH2ADD_UW 0xfe00707f
  860. +#define MATCH_SH3ADD_UW 0x2000603b
  861. +#define MASK_SH3ADD_UW 0xfe00707f
  862. #define MATCH_SHFLW 0x800103b
  863. #define MASK_SHFLW 0xfe00707f
  864. #define MATCH_UNSHFLW 0x800503b
  865. @@ -3665,19 +3665,19 @@ DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
  866. DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
  867. DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
  868. DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
  869. -DECLARE_INSN(sbclr, MATCH_SBCLR, MASK_SBCLR)
  870. -DECLARE_INSN(sbset, MATCH_SBSET, MASK_SBSET)
  871. -DECLARE_INSN(sbinv, MATCH_SBINV, MASK_SBINV)
  872. -DECLARE_INSN(sbext, MATCH_SBEXT, MASK_SBEXT)
  873. +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
  874. +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
  875. +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
  876. +DECLARE_INSN(bfext, MATCH_BFEXT, MASK_BFEXT)
  877. DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
  878. DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
  879. DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
  880. DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
  881. DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
  882. -DECLARE_INSN(sbclri, MATCH_SBCLRI, MASK_SBCLRI)
  883. -DECLARE_INSN(sbseti, MATCH_SBSETI, MASK_SBSETI)
  884. -DECLARE_INSN(sbinvi, MATCH_SBINVI, MASK_SBINVI)
  885. -DECLARE_INSN(sbexti, MATCH_SBEXTI, MASK_SBEXTI)
  886. +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
  887. +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
  888. +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
  889. +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
  890. DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
  891. DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
  892. DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
  893. @@ -3687,7 +3687,7 @@ DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
  894. DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
  895. DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
  896. DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
  897. -DECLARE_INSN(pcnt, MATCH_PCNT, MASK_PCNT)
  898. +DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
  899. DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
  900. DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
  901. DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
  902. @@ -3724,25 +3724,25 @@ DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
  903. DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
  904. DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
  905. DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
  906. -DECLARE_INSN(slliu_w, MATCH_SLLIU_W, MASK_SLLIU_W)
  907. -DECLARE_INSN(addu_w, MATCH_ADDU_W, MASK_ADDU_W)
  908. -DECLARE_INSN(subu_w, MATCH_SUBU_W, MASK_SUBU_W)
  909. +DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
  910. +DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
  911. +DECLARE_INSN(sub_uw, MATCH_SUB_UW, MASK_SUB_UW)
  912. DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
  913. DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
  914. DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
  915. DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
  916. -DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
  917. -DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
  918. -DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
  919. -DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
  920. +DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
  921. +DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
  922. +DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
  923. +DECLARE_INSN(bfextw, MATCH_BFEXTW, MASK_BFEXTW)
  924. DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
  925. DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
  926. DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
  927. DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
  928. DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
  929. -DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
  930. -DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
  931. -DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
  932. +DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
  933. +DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
  934. +DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
  935. DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
  936. DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
  937. DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
  938. @@ -3750,10 +3750,10 @@ DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
  939. DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
  940. DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
  941. DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
  942. -DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW)
  943. -DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W)
  944. -DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W)
  945. -DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W)
  946. +DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
  947. +DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
  948. +DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
  949. +DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
  950. DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
  951. DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
  952. DECLARE_INSN(xperm_w, MATCH_XPERMW, MASK_XPERMW)
  953. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  954. index 02800fda64..6ff292d794 100644
  955. --- a/include/opcode/riscv.h
  956. +++ b/include/opcode/riscv.h
  957. @@ -391,18 +391,10 @@ enum riscv_insn_class
  958. INSN_CLASS_V_AND_ZVEDIV,
  959. INSN_CLASS_V_OR_ZVLSSEG,
  960. INSN_CLASS_V_AND_ZVQMAC,
  961. - INSN_CLASS_B_OR_ZBA,
  962. - INSN_CLASS_B_OR_ZBB,
  963. - INSN_CLASS_B_OR_ZBC,
  964. - INSN_CLASS_B_OR_ZBS,
  965. - INSN_CLASS_B_OR_ZBA_OR_ZBB,
  966. -
  967. - INSN_CLASS_B_OR_ZBE,
  968. - INSN_CLASS_B_OR_ZBF,
  969. - INSN_CLASS_B_OR_ZBM,
  970. - INSN_CLASS_B_OR_ZBP,
  971. - INSN_CLASS_ZBR,
  972. - INSN_CLASS_ZBT,
  973. + INSN_CLASS_ZBA,
  974. + INSN_CLASS_ZBB,
  975. + INSN_CLASS_ZBC,
  976. + INSN_CLASS_ZBA_OR_ZBB,
  977. };
  978. /* This structure holds information for a particular instruction. */
  979. @@ -448,7 +440,8 @@ enum riscv_isa_spec_class
  980. ISA_SPEC_CLASS_2P2,
  981. ISA_SPEC_CLASS_20190608,
  982. - ISA_SPEC_CLASS_20191213
  983. + ISA_SPEC_CLASS_20191213,
  984. + ISA_SPEC_CLASS_DRAFT
  985. };
  986. #define RISCV_UNKNOWN_VERSION -1
  987. @@ -582,8 +575,6 @@ enum
  988. M_LI,
  989. M_VMSGE,
  990. M_VMSGEU,
  991. - M_RL,
  992. - M_FL,
  993. M_ZEXTH,
  994. M_ZEXTW,
  995. M_SEXTB,
  996. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  997. index 5c07c0a2db..af408b041c 100644
  998. --- a/opcodes/riscv-opc.c
  999. +++ b/opcodes/riscv-opc.c
  1000. @@ -1053,8 +1053,6 @@ const struct riscv_opcode riscv_opcodes[] =
  1001. {"rev.h", 64, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERMH_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1002. {"rev16", 32, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM16_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1003. {"rev16", 64, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM16_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1004. -{"rev8", 32, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_GREVI | MATCH_PERM8_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1005. -{"rev8", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_GREVI | MATCH_PERM8_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1006. {"rev4", 32, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM4_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1007. {"rev4", 64, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM4_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1008. {"rev2", 32, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM2_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1009. @@ -1078,8 +1076,6 @@ const struct riscv_opcode riscv_opcodes[] =
  1010. {"orc4.b", 64, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM4B_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1011. {"orc2.b", 32, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM2B_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1012. {"orc2.b", 64, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM2B_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1013. -{"orc.b", 32, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_GORCI | MATCH_PERMB_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1014. -{"orc.b", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_GORCI | MATCH_PERMB_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1015. {"orc8.h", 32, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM8H_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1016. {"orc8.h", 64, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM8H_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1017. {"orc4.h", 32, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERM4H_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1018. @@ -1157,77 +1153,53 @@ const struct riscv_opcode riscv_opcodes[] =
  1019. {"unzip.w", 64, INSN_CLASS_B, "d,s", MATCH_UNSHFLI | MATCH_PERMW_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1020. {"unzip16", 64, INSN_CLASS_B, "d,s", MATCH_UNSHFLI | MATCH_PERM16_SHFL_IMM (64), MASK_UNSHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
  1021. -/* Bitmanip instruction subset - for sure */
  1022. -{"sh1add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
  1023. -{"sh2add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
  1024. -{"sh3add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
  1025. -{"slliu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,>", MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
  1026. -{"zext.w", 64, INSN_CLASS_B_OR_ZBA_OR_ZBB, "d,s", MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
  1027. -{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
  1028. -{"addu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
  1029. -{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
  1030. -{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
  1031. -{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
  1032. -
  1033. -{"clz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
  1034. -{"ctz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
  1035. -{"pcnt", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNT, MASK_PCNT, match_opcode, 0 },
  1036. -{"min", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
  1037. -{"max", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
  1038. -{"minu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
  1039. -{"maxu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
  1040. -{"andn", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
  1041. -{"orn", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
  1042. -{"xnor", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
  1043. -{"roli", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO }, /* rori */
  1044. -{"rol", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
  1045. -{"rol", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", 0, (int) M_RL, match_never, INSN_MACRO }, /* rori */
  1046. -{"rori", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
  1047. -{"ror", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
  1048. -{"ror", 0, INSN_CLASS_B_OR_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
  1049. -{"sext.b", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
  1050. -{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
  1051. -{"sext.h", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
  1052. -{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
  1053. -{"zext.h", 32, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS }, /* pack with rs2=x0 */
  1054. -{"zext.h", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS }, /* packw with rs2=x0 */
  1055. -{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
  1056. -{"clzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
  1057. -{"ctzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
  1058. -{"pcntw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
  1059. -{"roliw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO }, /* roriw */
  1060. -{"rolw", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
  1061. -{"rolw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", 0, (int) M_RL, match_never, INSN_MACRO }, /* roriw */
  1062. -{"roriw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
  1063. -{"rorw", 64, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
  1064. -{"rorw", 64, INSN_CLASS_B_OR_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
  1065. -
  1066. -{"clmul", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
  1067. -{"clmulh", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
  1068. -{"clmulr", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
  1069. -
  1070. -{"sbseti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
  1071. -{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
  1072. -{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
  1073. -{"sbclri", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
  1074. -{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
  1075. -{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
  1076. -{"sbinvi", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
  1077. -{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
  1078. -{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
  1079. -{"sbexti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
  1080. -{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
  1081. -{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
  1082. -{"sbsetiw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, 0 },
  1083. -{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSETW, MASK_SBSETW, match_opcode, 0 },
  1084. -{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, INSN_ALIAS },
  1085. -{"sbclriw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
  1086. -{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
  1087. -{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
  1088. -{"sbinviw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
  1089. -{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINVW, MASK_SBINVW, match_opcode, 0 },
  1090. -{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, INSN_ALIAS },
  1091. -{"sbextw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 }, /* No sbextiw */
  1092. +/* Bitmanip instruction subset - ZBA/ZBB/ZBC */
  1093. +{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
  1094. +{"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
  1095. +{"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
  1096. +{"sh1add.uw",64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
  1097. +{"sh2add.uw",64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
  1098. +{"sh3add.uw",64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
  1099. +{"zext.w", 64, INSN_CLASS_ZBA_OR_ZBB, "d,s", MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS },
  1100. +{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
  1101. +{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
  1102. +{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
  1103. +
  1104. +{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
  1105. +{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
  1106. +{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
  1107. +{"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
  1108. +{"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
  1109. +{"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
  1110. +{"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
  1111. +{"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
  1112. +{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
  1113. +{"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
  1114. +{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
  1115. +{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
  1116. +{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
  1117. +{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
  1118. +{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
  1119. +{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
  1120. +{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
  1121. +{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
  1122. +{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
  1123. +{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
  1124. +{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
  1125. +{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
  1126. +{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
  1127. +{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
  1128. +{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
  1129. +{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
  1130. +{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
  1131. +{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
  1132. +{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | ENCODE_ITYPE_IMM (0x18), MASK_GREVI | MASK_RVB_IMM, match_opcode, 0 },
  1133. +{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | ENCODE_ITYPE_IMM (0x38), MASK_GREVI | MASK_RVB_IMM, match_opcode, 0 },
  1134. +{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | ENCODE_ITYPE_IMM (0x7), MASK_GORCI | MASK_RVB_IMM, match_opcode, 0 },
  1135. +
  1136. +{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
  1137. +{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
  1138. +{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
  1139. /* Bitmanip instruction subset - unsure */
  1140. {"sloi", 0, INSN_CLASS_B, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
  1141. @@ -1260,7 +1232,7 @@ const struct riscv_opcode riscv_opcodes[] =
  1142. {"bmator", 64, INSN_CLASS_B, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
  1143. {"bmatxor", 64, INSN_CLASS_B, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
  1144. {"bfp", 0, INSN_CLASS_B, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
  1145. -{"subu.w", 64, INSN_CLASS_B, "d,s,t", MATCH_SUBU_W, MASK_SUBU_W, match_opcode, 0 },
  1146. +{"sub.uw", 64, INSN_CLASS_B, "d,s,t", MATCH_SUB_UW, MASK_SUB_UW, match_opcode, 0 },
  1147. {"sloiw", 64, INSN_CLASS_B, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
  1148. {"sroiw", 64, INSN_CLASS_B, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
  1149. {"slow", 64, INSN_CLASS_B, "d,s,t", MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
  1150. @@ -1282,29 +1254,48 @@ const struct riscv_opcode riscv_opcodes[] =
  1151. {"packuw", 64, INSN_CLASS_B, "d,s,t", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
  1152. {"bfpw", 64, INSN_CLASS_B, "d,s,t", MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
  1153. -{"cmix", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
  1154. -{"cmov", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
  1155. -{"fsli", 0, INSN_CLASS_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsri */
  1156. -{"fsl", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 },
  1157. -{"fsl", 0, INSN_CLASS_ZBT, "d,s,r,>", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsri */
  1158. -{"fsri", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
  1159. -{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
  1160. -{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
  1161. -{"fsliw", 64, INSN_CLASS_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsriw */
  1162. -{"fslw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
  1163. -{"fslw", 64, INSN_CLASS_ZBT, "d,s,r,<", 0, (int) M_FL, match_never, INSN_MACRO }, /* fsriw */
  1164. -{"fsriw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
  1165. -{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
  1166. -{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
  1167. -
  1168. -{"crc32.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
  1169. -{"crc32.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
  1170. -{"crc32.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
  1171. -{"crc32c.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
  1172. -{"crc32c.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
  1173. -{"crc32c.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
  1174. -{"crc32.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
  1175. -{"crc32c.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
  1176. +{"cmix", 0, INSN_CLASS_B, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
  1177. +{"cmov", 0, INSN_CLASS_B, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
  1178. +{"fsl", 0, INSN_CLASS_B, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 },
  1179. +{"fsri", 0, INSN_CLASS_B, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
  1180. +{"fsr", 0, INSN_CLASS_B, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
  1181. +{"fsr", 0, INSN_CLASS_B, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
  1182. +{"fslw", 64, INSN_CLASS_B, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
  1183. +{"fsriw", 64, INSN_CLASS_B, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
  1184. +{"fsrw", 64, INSN_CLASS_B, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
  1185. +{"fsrw", 64, INSN_CLASS_B, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
  1186. +
  1187. +{"bseti", 0, INSN_CLASS_B, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
  1188. +{"bset", 0, INSN_CLASS_B, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
  1189. +{"bset", 0, INSN_CLASS_B, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
  1190. +{"bclri", 0, INSN_CLASS_B, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
  1191. +{"bclr", 0, INSN_CLASS_B, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
  1192. +{"bclr", 0, INSN_CLASS_B, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
  1193. +{"binvi", 0, INSN_CLASS_B, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
  1194. +{"binv", 0, INSN_CLASS_B, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
  1195. +{"binv", 0, INSN_CLASS_B, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
  1196. +{"bexti", 0, INSN_CLASS_B, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
  1197. +{"bfext", 0, INSN_CLASS_B, "d,s,t", MATCH_BFEXT, MASK_BFEXT, match_opcode, 0 },
  1198. +{"bfext", 0, INSN_CLASS_B, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
  1199. +{"bsetiw", 64, INSN_CLASS_B, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
  1200. +{"bsetw", 64, INSN_CLASS_B, "d,s,t", MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
  1201. +{"bsetw", 64, INSN_CLASS_B, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, INSN_ALIAS },
  1202. +{"bclriw", 64, INSN_CLASS_B, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
  1203. +{"bclrw", 64, INSN_CLASS_B, "d,s,t", MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
  1204. +{"bclrw", 64, INSN_CLASS_B, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, INSN_ALIAS },
  1205. +{"binviw", 64, INSN_CLASS_B, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
  1206. +{"binvw", 64, INSN_CLASS_B, "d,s,t", MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
  1207. +{"binvw", 64, INSN_CLASS_B, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, INSN_ALIAS },
  1208. +{"bfextw", 64, INSN_CLASS_B, "d,s,t", MATCH_BFEXTW, MASK_BFEXTW, match_opcode, 0 }, /* No sbextiw */
  1209. +
  1210. +{"crc32.b", 0, INSN_CLASS_B, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
  1211. +{"crc32.h", 0, INSN_CLASS_B, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
  1212. +{"crc32.w", 0, INSN_CLASS_B, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
  1213. +{"crc32c.b", 0, INSN_CLASS_B, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
  1214. +{"crc32c.h", 0, INSN_CLASS_B, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
  1215. +{"crc32c.w", 0, INSN_CLASS_B, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
  1216. +{"crc32.d", 64, INSN_CLASS_B, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
  1217. +{"crc32c.d", 64, INSN_CLASS_B, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
  1218. /* Single-precision floating-point instruction subset */
  1219. {"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
  1220. @@ -2867,9 +2858,7 @@ const struct riscv_ext_version riscv_ext_version_table[] =
  1221. {"c", ISA_SPEC_CLASS_20190608, 2, 0},
  1222. {"c", ISA_SPEC_CLASS_2P2, 2, 0},
  1223. -{"b", ISA_SPEC_CLASS_NONE, 0, 92},
  1224. -
  1225. -{"v", ISA_SPEC_CLASS_NONE, 1, 0},
  1226. +{"v", ISA_SPEC_CLASS_DRAFT, 1, 0},
  1227. {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
  1228. {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
  1229. @@ -2877,23 +2866,16 @@ const struct riscv_ext_version riscv_ext_version_table[] =
  1230. {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
  1231. {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
  1232. -{"zfh", ISA_SPEC_CLASS_NONE, 0, 1},
  1233. -
  1234. -{"zba", ISA_SPEC_CLASS_NONE, 0, 92},
  1235. -{"zbb", ISA_SPEC_CLASS_NONE, 0, 92},
  1236. -{"zbc", ISA_SPEC_CLASS_NONE, 0, 92},
  1237. -{"zbe", ISA_SPEC_CLASS_NONE, 0, 92},
  1238. -{"zbf", ISA_SPEC_CLASS_NONE, 0, 92},
  1239. -{"zbm", ISA_SPEC_CLASS_NONE, 0, 92},
  1240. -{"zbp", ISA_SPEC_CLASS_NONE, 0, 92},
  1241. -{"zbr", ISA_SPEC_CLASS_NONE, 0, 92},
  1242. -{"zbs", ISA_SPEC_CLASS_NONE, 0, 92},
  1243. -{"zbt", ISA_SPEC_CLASS_NONE, 0, 92},
  1244. -
  1245. -{"zvamo", ISA_SPEC_CLASS_NONE, 1, 0},
  1246. -{"zvediv", ISA_SPEC_CLASS_NONE, 1, 0},
  1247. -{"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
  1248. -{"zvqmac", ISA_SPEC_CLASS_NONE, 1, 0},
  1249. +{"zfh", ISA_SPEC_CLASS_DRAFT, 0, 1},
  1250. +
  1251. +{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
  1252. +{"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
  1253. +{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
  1254. +
  1255. +{"zvamo", ISA_SPEC_CLASS_DRAFT, 1, 0},
  1256. +{"zvediv", ISA_SPEC_CLASS_DRAFT, 1, 0},
  1257. +{"zvlsseg", ISA_SPEC_CLASS_DRAFT, 1, 0},
  1258. +{"zvqmac", ISA_SPEC_CLASS_DRAFT, 1, 0},
  1259. /* Terminate the list. */
  1260. {NULL, 0, 0, 0}
  1261. --
  1262. 2.33.0