0028-RISC-V-Support-Zfh-standard-extension-for-half-preci.patch 25 KB

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  1. From 4003a9ae6f2e2cdbd92cb9d85c48ec672228894c Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Thu, 26 Mar 2020 18:38:27 +0800
  4. Subject: [PATCH 28/48] RISC-V: Support Zfh standard extension for
  5. half-precision floating-point.
  6. ---
  7. bfd/elfxx-riscv.c | 2 +-
  8. gas/config/tc-riscv.c | 23 +++++-
  9. gas/testsuite/gas/riscv/fp-zfh-insns.d | 71 ++++++++++++++++
  10. gas/testsuite/gas/riscv/fp-zfh-insns.s | 68 ++++++++++++++++
  11. include/opcode/riscv-opc.h | 108 +++++++++++++++++++++++++
  12. include/opcode/riscv.h | 9 ++-
  13. opcodes/riscv-opc.c | 65 +++++++++++++++
  14. 7 files changed, 340 insertions(+), 6 deletions(-)
  15. create mode 100644 gas/testsuite/gas/riscv/fp-zfh-insns.d
  16. create mode 100644 gas/testsuite/gas/riscv/fp-zfh-insns.s
  17. diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
  18. index f797d28f59..67dbc2e682 100644
  19. --- a/bfd/elfxx-riscv.c
  20. +++ b/bfd/elfxx-riscv.c
  21. @@ -1566,7 +1566,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
  22. static const char * const riscv_std_z_ext_strtab[] =
  23. {
  24. - "zicsr", "zifencei",
  25. + "zicsr", "zifencei", "zfh",
  26. "zvamo", "zvediv", "zvlsseg", "zvqmac",
  27. NULL
  28. };
  29. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  30. index eca9fabb3f..bb2819db4a 100644
  31. --- a/gas/config/tc-riscv.c
  32. +++ b/gas/config/tc-riscv.c
  33. @@ -229,15 +229,22 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
  34. case INSN_CLASS_C: return riscv_subset_supports ("c");
  35. case INSN_CLASS_A: return riscv_subset_supports ("a");
  36. case INSN_CLASS_M: return riscv_subset_supports ("m");
  37. +
  38. case INSN_CLASS_F: return riscv_subset_supports ("f");
  39. + case INSN_CLASS_F_AND_C:
  40. + return riscv_subset_supports ("f") && riscv_subset_supports ("c");
  41. + case INSN_CLASS_F_AND_ZFH:
  42. + return riscv_subset_supports ("f") && riscv_subset_supports ("zfh");
  43. +
  44. case INSN_CLASS_D: return riscv_subset_supports ("d");
  45. case INSN_CLASS_D_AND_C:
  46. return riscv_subset_supports ("d") && riscv_subset_supports ("c");
  47. -
  48. - case INSN_CLASS_F_AND_C:
  49. - return riscv_subset_supports ("f") && riscv_subset_supports ("c");
  50. + case INSN_CLASS_D_AND_ZFH:
  51. + return riscv_subset_supports ("d") && riscv_subset_supports ("zfh");
  52. case INSN_CLASS_Q: return riscv_subset_supports ("q");
  53. + case INSN_CLASS_Q_AND_ZFH:
  54. + return riscv_subset_supports ("q") && riscv_subset_supports ("zfh");
  55. case INSN_CLASS_V: return riscv_subset_supports ("v");
  56. case INSN_CLASS_V_AND_F:
  57. @@ -1624,6 +1631,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
  58. BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
  59. break;
  60. + case M_FLH:
  61. + pcrel_load (rd, rs1, imm_expr, "flh",
  62. + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
  63. + break;
  64. +
  65. case M_FLW:
  66. pcrel_load (rd, rs1, imm_expr, "flw",
  67. BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
  68. @@ -1654,6 +1666,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
  69. BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
  70. break;
  71. + case M_FSH:
  72. + pcrel_store (rs2, rs1, imm_expr, "fsh",
  73. + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
  74. + break;
  75. +
  76. case M_FSW:
  77. pcrel_store (rs2, rs1, imm_expr, "fsw",
  78. BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
  79. diff --git a/gas/testsuite/gas/riscv/fp-zfh-insns.d b/gas/testsuite/gas/riscv/fp-zfh-insns.d
  80. new file mode 100644
  81. index 0000000000..e6c0ac502e
  82. --- /dev/null
  83. +++ b/gas/testsuite/gas/riscv/fp-zfh-insns.d
  84. @@ -0,0 +1,71 @@
  85. +#as: -march=rv64ifdq_zfh
  86. +#source: fp-zfh-insns.s
  87. +#objdump: -dr
  88. +
  89. +.*:[ ]+file format .*
  90. +
  91. +
  92. +Disassembly of section .text:
  93. +
  94. +0+000 <.text>:
  95. +[ ]+[0-9a-f]+:[ ]+00059507[ ]+flh[ ]+fa0,0\(a1\)
  96. +[ ]+[0-9a-f]+:[ ]+00a59027[ ]+fsh[ ]+fa0,0\(a1\)
  97. +[ ]+[0-9a-f]+:[ ]+24b58553[ ]+fmv.h[ ]+fa0,fa1
  98. +[ ]+[0-9a-f]+:[ ]+24b59553[ ]+fneg.h[ ]+fa0,fa1
  99. +[ ]+[0-9a-f]+:[ ]+24b5a553[ ]+fabs.h[ ]+fa0,fa1
  100. +[ ]+[0-9a-f]+:[ ]+24c58553[ ]+fsgnj.h[ ]+fa0,fa1,fa2
  101. +[ ]+[0-9a-f]+:[ ]+24c59553[ ]+fsgnjn.h[ ]+fa0,fa1,fa2
  102. +[ ]+[0-9a-f]+:[ ]+24c5a553[ ]+fsgnjx.h[ ]+fa0,fa1,fa2
  103. +[ ]+[0-9a-f]+:[ ]+04c5f553[ ]+fadd.h[ ]+fa0,fa1,fa2
  104. +[ ]+[0-9a-f]+:[ ]+04c58553[ ]+fadd.h[ ]+fa0,fa1,fa2,rne
  105. +[ ]+[0-9a-f]+:[ ]+0cc5f553[ ]+fsub.h[ ]+fa0,fa1,fa2
  106. +[ ]+[0-9a-f]+:[ ]+0cc58553[ ]+fsub.h[ ]+fa0,fa1,fa2,rne
  107. +[ ]+[0-9a-f]+:[ ]+14c5f553[ ]+fmul.h[ ]+fa0,fa1,fa2
  108. +[ ]+[0-9a-f]+:[ ]+14c58553[ ]+fmul.h[ ]+fa0,fa1,fa2,rne
  109. +[ ]+[0-9a-f]+:[ ]+1cc5f553[ ]+fdiv.h[ ]+fa0,fa1,fa2
  110. +[ ]+[0-9a-f]+:[ ]+1cc58553[ ]+fdiv.h[ ]+fa0,fa1,fa2,rne
  111. +[ ]+[0-9a-f]+:[ ]+5c05f553[ ]+fsqrt.h[ ]+fa0,fa1
  112. +[ ]+[0-9a-f]+:[ ]+5c058553[ ]+fsqrt.h[ ]+fa0,fa1,rne
  113. +[ ]+[0-9a-f]+:[ ]+2cc58553[ ]+fmin.h[ ]+fa0,fa1,fa2
  114. +[ ]+[0-9a-f]+:[ ]+2cc59553[ ]+fmax.h[ ]+fa0,fa1,fa2
  115. +[ ]+[0-9a-f]+:[ ]+6cc5f543[ ]+fmadd.h[ ]+fa0,fa1,fa2,fa3
  116. +[ ]+[0-9a-f]+:[ ]+6cc58543[ ]+fmadd.h[ ]+fa0,fa1,fa2,fa3,rne
  117. +[ ]+[0-9a-f]+:[ ]+6cc5f54f[ ]+fnmadd.h[ ]+fa0,fa1,fa2,fa3
  118. +[ ]+[0-9a-f]+:[ ]+6cc5854f[ ]+fnmadd.h[ ]+fa0,fa1,fa2,fa3,rne
  119. +[ ]+[0-9a-f]+:[ ]+6cc5f547[ ]+fmsub.h[ ]+fa0,fa1,fa2,fa3
  120. +[ ]+[0-9a-f]+:[ ]+6cc58547[ ]+fmsub.h[ ]+fa0,fa1,fa2,fa3,rne
  121. +[ ]+[0-9a-f]+:[ ]+6cc5f54b[ ]+fnmsub.h[ ]+fa0,fa1,fa2,fa3
  122. +[ ]+[0-9a-f]+:[ ]+6cc5854b[ ]+fnmsub.h[ ]+fa0,fa1,fa2,fa3,rne
  123. +[ ]+[0-9a-f]+:[ ]+c405f553[ ]+fcvt.w.h[ ]+a0,fa1
  124. +[ ]+[0-9a-f]+:[ ]+c4058553[ ]+fcvt.w.h[ ]+a0,fa1,rne
  125. +[ ]+[0-9a-f]+:[ ]+c415f553[ ]+fcvt.wu.h[ ]+a0,fa1
  126. +[ ]+[0-9a-f]+:[ ]+c4158553[ ]+fcvt.wu.h[ ]+a0,fa1,rne
  127. +[ ]+[0-9a-f]+:[ ]+d405f553[ ]+fcvt.h.w[ ]+fa0,a1
  128. +[ ]+[0-9a-f]+:[ ]+d4058553[ ]+fcvt.h.w[ ]+fa0,a1,rne
  129. +[ ]+[0-9a-f]+:[ ]+d415f553[ ]+fcvt.h.wu[ ]+fa0,a1
  130. +[ ]+[0-9a-f]+:[ ]+d4158553[ ]+fcvt.h.wu[ ]+fa0,a1,rne
  131. +[ ]+[0-9a-f]+:[ ]+c425f553[ ]+fcvt.l.h[ ]+a0,fa1
  132. +[ ]+[0-9a-f]+:[ ]+c4258553[ ]+fcvt.l.h[ ]+a0,fa1,rne
  133. +[ ]+[0-9a-f]+:[ ]+c435f553[ ]+fcvt.lu.h[ ]+a0,fa1
  134. +[ ]+[0-9a-f]+:[ ]+c4358553[ ]+fcvt.lu.h[ ]+a0,fa1,rne
  135. +[ ]+[0-9a-f]+:[ ]+d425f553[ ]+fcvt.h.l[ ]+fa0,a1
  136. +[ ]+[0-9a-f]+:[ ]+d4258553[ ]+fcvt.h.l[ ]+fa0,a1,rne
  137. +[ ]+[0-9a-f]+:[ ]+d435f553[ ]+fcvt.h.lu[ ]+fa0,a1
  138. +[ ]+[0-9a-f]+:[ ]+d4358553[ ]+fcvt.h.lu[ ]+fa0,a1,rne
  139. +[ ]+[0-9a-f]+:[ ]+e4058553[ ]+fmv.x.h[ ]+a0,fa1
  140. +[ ]+[0-9a-f]+:[ ]+f4058553[ ]+fmv.h.x[ ]+fa0,a1
  141. +[ ]+[0-9a-f]+:[ ]+40258553[ ]+fcvt.s.h[ ]+fa0,fa1
  142. +[ ]+[0-9a-f]+:[ ]+42258553[ ]+fcvt.d.h[ ]+fa0,fa1
  143. +[ ]+[0-9a-f]+:[ ]+46358553[ ]+fcvt.q.h[ ]+fa0,fa1
  144. +[ ]+[0-9a-f]+:[ ]+4405f553[ ]+fcvt.h.s[ ]+fa0,fa1
  145. +[ ]+[0-9a-f]+:[ ]+44058553[ ]+fcvt.h.s[ ]+fa0,fa1,rne
  146. +[ ]+[0-9a-f]+:[ ]+4415f553[ ]+fcvt.h.d[ ]+fa0,fa1
  147. +[ ]+[0-9a-f]+:[ ]+44158553[ ]+fcvt.h.d[ ]+fa0,fa1,rne
  148. +[ ]+[0-9a-f]+:[ ]+4425f553[ ]+fcvt.h.q[ ]+fa0,fa1
  149. +[ ]+[0-9a-f]+:[ ]+44258553[ ]+fcvt.h.q[ ]+fa0,fa1,rne
  150. +[ ]+[0-9a-f]+:[ ]+e4059553[ ]+fclass.h[ ]+a0,fa1
  151. +[ ]+[0-9a-f]+:[ ]+a4c5a553[ ]+feq.h[ ]+a0,fa1,fa2
  152. +[ ]+[0-9a-f]+:[ ]+a4c59553[ ]+flt.h[ ]+a0,fa1,fa2
  153. +[ ]+[0-9a-f]+:[ ]+a4c58553[ ]+fle.h[ ]+a0,fa1,fa2
  154. +[ ]+[0-9a-f]+:[ ]+a4c59553[ ]+flt.h[ ]+a0,fa1,fa2
  155. +[ ]+[0-9a-f]+:[ ]+a4c58553[ ]+fle.h[ ]+a0,fa1,fa2
  156. diff --git a/gas/testsuite/gas/riscv/fp-zfh-insns.s b/gas/testsuite/gas/riscv/fp-zfh-insns.s
  157. new file mode 100644
  158. index 0000000000..1a04cc6400
  159. --- /dev/null
  160. +++ b/gas/testsuite/gas/riscv/fp-zfh-insns.s
  161. @@ -0,0 +1,68 @@
  162. + flh fa0, 0(a1)
  163. + fsh fa0, 0(a1)
  164. +
  165. + fmv.h fa0, fa1
  166. + fneg.h fa0, fa1
  167. + fabs.h fa0, fa1
  168. + fsgnj.h fa0, fa1, fa2
  169. + fsgnjn.h fa0, fa1, fa2
  170. + fsgnjx.h fa0, fa1, fa2
  171. +
  172. + fadd.h fa0, fa1, fa2
  173. + fadd.h fa0, fa1, fa2, rne
  174. + fsub.h fa0, fa1, fa2
  175. + fsub.h fa0, fa1, fa2, rne
  176. + fmul.h fa0, fa1, fa2
  177. + fmul.h fa0, fa1, fa2, rne
  178. + fdiv.h fa0, fa1, fa2
  179. + fdiv.h fa0, fa1, fa2, rne
  180. + fsqrt.h fa0, fa1
  181. + fsqrt.h fa0, fa1, rne
  182. + fmin.h fa0, fa1, fa2
  183. + fmax.h fa0, fa1, fa2
  184. +
  185. + fmadd.h fa0, fa1, fa2, fa3
  186. + fmadd.h fa0, fa1, fa2, fa3, rne
  187. + fnmadd.h fa0, fa1, fa2, fa3
  188. + fnmadd.h fa0, fa1, fa2, fa3, rne
  189. + fmsub.h fa0, fa1, fa2, fa3
  190. + fmsub.h fa0, fa1, fa2, fa3, rne
  191. + fnmsub.h fa0, fa1, fa2, fa3
  192. + fnmsub.h fa0, fa1, fa2, fa3, rne
  193. +
  194. + fcvt.w.h a0, fa1
  195. + fcvt.w.h a0, fa1, rne
  196. + fcvt.wu.h a0, fa1
  197. + fcvt.wu.h a0, fa1, rne
  198. + fcvt.h.w fa0, a1
  199. + fcvt.h.w fa0, a1, rne
  200. + fcvt.h.wu fa0, a1
  201. + fcvt.h.wu fa0, a1, rne
  202. + fcvt.l.h a0, fa1
  203. + fcvt.l.h a0, fa1, rne
  204. + fcvt.lu.h a0, fa1
  205. + fcvt.lu.h a0, fa1, rne
  206. + fcvt.h.l fa0, a1
  207. + fcvt.h.l fa0, a1, rne
  208. + fcvt.h.lu fa0, a1
  209. + fcvt.h.lu fa0, a1, rne
  210. +
  211. + fmv.x.h a0, fa1
  212. + fmv.h.x fa0, a1
  213. +
  214. + fcvt.s.h fa0, fa1
  215. + fcvt.d.h fa0, fa1
  216. + fcvt.q.h fa0, fa1
  217. + fcvt.h.s fa0, fa1
  218. + fcvt.h.s fa0, fa1, rne
  219. + fcvt.h.d fa0, fa1
  220. + fcvt.h.d fa0, fa1, rne
  221. + fcvt.h.q fa0, fa1
  222. + fcvt.h.q fa0, fa1, rne
  223. + fclass.h a0, fa1
  224. +
  225. + feq.h a0, fa1, fa2
  226. + flt.h a0, fa1, fa2
  227. + fle.h a0, fa1, fa2
  228. + fgt.h a0, fa2, fa1
  229. + fge.h a0, fa2, fa1
  230. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  231. index cd1395a010..743060ca18 100644
  232. --- a/include/opcode/riscv-opc.h
  233. +++ b/include/opcode/riscv-opc.h
  234. @@ -309,6 +309,38 @@
  235. #define MASK_FCVT_D_S 0xfff0007f
  236. #define MATCH_FSQRT_D 0x5a000053
  237. #define MASK_FSQRT_D 0xfff0007f
  238. +#define MATCH_FADD_H 0x4000053
  239. +#define MASK_FADD_H 0xfe00007f
  240. +#define MATCH_FSUB_H 0xc000053
  241. +#define MASK_FSUB_H 0xfe00007f
  242. +#define MATCH_FMUL_H 0x14000053
  243. +#define MASK_FMUL_H 0xfe00007f
  244. +#define MATCH_FDIV_H 0x1c000053
  245. +#define MASK_FDIV_H 0xfe00007f
  246. +#define MATCH_FSGNJ_H 0x24000053
  247. +#define MASK_FSGNJ_H 0xfe00707f
  248. +#define MATCH_FSGNJN_H 0x24001053
  249. +#define MASK_FSGNJN_H 0xfe00707f
  250. +#define MATCH_FSGNJX_H 0x24002053
  251. +#define MASK_FSGNJX_H 0xfe00707f
  252. +#define MATCH_FMIN_H 0x2c000053
  253. +#define MASK_FMIN_H 0xfe00707f
  254. +#define MATCH_FMAX_H 0x2c001053
  255. +#define MASK_FMAX_H 0xfe00707f
  256. +#define MATCH_FCVT_S_H 0x40200053
  257. +#define MASK_FCVT_S_H 0xfff0007f
  258. +#define MATCH_FCVT_H_S 0x44000053
  259. +#define MASK_FCVT_H_S 0xfff0007f
  260. +#define MATCH_FCVT_D_H 0x42200053
  261. +#define MASK_FCVT_D_H 0xfff0007f
  262. +#define MATCH_FCVT_H_D 0x44100053
  263. +#define MASK_FCVT_H_D 0xfff0007f
  264. +#define MATCH_FCVT_Q_H 0x46300053
  265. +#define MASK_FCVT_Q_H 0xfff0007f
  266. +#define MATCH_FCVT_H_Q 0x44200053
  267. +#define MASK_FCVT_H_Q 0xfff0007f
  268. +#define MATCH_FSQRT_H 0x5c000053
  269. +#define MASK_FSQRT_H 0xfff0007f
  270. #define MATCH_FADD_Q 0x6000053
  271. #define MASK_FADD_Q 0xfe00007f
  272. #define MATCH_FSUB_Q 0xe000053
  273. @@ -349,6 +381,12 @@
  274. #define MASK_FLT_D 0xfe00707f
  275. #define MATCH_FEQ_D 0xa2002053
  276. #define MASK_FEQ_D 0xfe00707f
  277. +#define MATCH_FLE_H 0xa4000053
  278. +#define MASK_FLE_H 0xfe00707f
  279. +#define MATCH_FLT_H 0xa4001053
  280. +#define MASK_FLT_H 0xfe00707f
  281. +#define MATCH_FEQ_H 0xa4002053
  282. +#define MASK_FEQ_H 0xfe00707f
  283. #define MATCH_FLE_Q 0xa6000053
  284. #define MASK_FLE_Q 0xfe00707f
  285. #define MATCH_FLT_Q 0xa6001053
  286. @@ -379,6 +417,18 @@
  287. #define MASK_FMV_X_D 0xfff0707f
  288. #define MATCH_FCLASS_D 0xe2001053
  289. #define MASK_FCLASS_D 0xfff0707f
  290. +#define MATCH_FCVT_W_H 0xc4000053
  291. +#define MASK_FCVT_W_H 0xfff0007f
  292. +#define MATCH_FCVT_WU_H 0xc4100053
  293. +#define MASK_FCVT_WU_H 0xfff0007f
  294. +#define MATCH_FCVT_L_H 0xc4200053
  295. +#define MASK_FCVT_L_H 0xfff0007f
  296. +#define MATCH_FCVT_LU_H 0xc4300053
  297. +#define MASK_FCVT_LU_H 0xfff0007f
  298. +#define MATCH_FMV_X_H 0xe4000053
  299. +#define MASK_FMV_X_H 0xfff0707f
  300. +#define MATCH_FCLASS_H 0xe4001053
  301. +#define MASK_FCLASS_H 0xfff0707f
  302. #define MATCH_FCVT_W_Q 0xc6000053
  303. #define MASK_FCVT_W_Q 0xfff0007f
  304. #define MATCH_FCVT_WU_Q 0xc6100053
  305. @@ -411,6 +461,16 @@
  306. #define MASK_FCVT_D_LU 0xfff0007f
  307. #define MATCH_FMV_D_X 0xf2000053
  308. #define MASK_FMV_D_X 0xfff0707f
  309. +#define MATCH_FCVT_H_W 0xd4000053
  310. +#define MASK_FCVT_H_W 0xfff0007f
  311. +#define MATCH_FCVT_H_WU 0xd4100053
  312. +#define MASK_FCVT_H_WU 0xfff0007f
  313. +#define MATCH_FCVT_H_L 0xd4200053
  314. +#define MASK_FCVT_H_L 0xfff0007f
  315. +#define MATCH_FCVT_H_LU 0xd4300053
  316. +#define MASK_FCVT_H_LU 0xfff0007f
  317. +#define MATCH_FMV_H_X 0xf4000053
  318. +#define MASK_FMV_H_X 0xfff0707f
  319. #define MATCH_FCVT_Q_W 0xd6000053
  320. #define MASK_FCVT_Q_W 0xfff0007f
  321. #define MATCH_FCVT_Q_WU 0xd6100053
  322. @@ -421,12 +481,16 @@
  323. #define MASK_FCVT_Q_LU 0xfff0007f
  324. #define MATCH_FMV_Q_X 0xf6000053
  325. #define MASK_FMV_Q_X 0xfff0707f
  326. +#define MATCH_FLH 0x1007
  327. +#define MASK_FLH 0x707f
  328. #define MATCH_FLW 0x2007
  329. #define MASK_FLW 0x707f
  330. #define MATCH_FLD 0x3007
  331. #define MASK_FLD 0x707f
  332. #define MATCH_FLQ 0x4007
  333. #define MASK_FLQ 0x707f
  334. +#define MATCH_FSH 0x1027
  335. +#define MASK_FSH 0x707f
  336. #define MATCH_FSW 0x2027
  337. #define MASK_FSW 0x707f
  338. #define MATCH_FSD 0x3027
  339. @@ -449,6 +513,14 @@
  340. #define MASK_FNMSUB_D 0x600007f
  341. #define MATCH_FNMADD_D 0x200004f
  342. #define MASK_FNMADD_D 0x600007f
  343. +#define MATCH_FMADD_H 0x4000043
  344. +#define MASK_FMADD_H 0x600007f
  345. +#define MATCH_FMSUB_H 0x4000047
  346. +#define MASK_FMSUB_H 0x600007f
  347. +#define MATCH_FNMSUB_H 0x400004b
  348. +#define MASK_FNMSUB_H 0x600007f
  349. +#define MATCH_FNMADD_H 0x400004f
  350. +#define MASK_FNMADD_H 0x600007f
  351. #define MATCH_FMADD_Q 0x6000043
  352. #define MASK_FMADD_Q 0x600007f
  353. #define MATCH_FMSUB_Q 0x6000047
  354. @@ -3177,6 +3249,22 @@ DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
  355. DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
  356. DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
  357. DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
  358. +DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
  359. +DECLARE_INSN(fsub_h, MATCH_FSUB_D, MASK_FSUB_H)
  360. +DECLARE_INSN(fmul_h, MATCH_FMUL_D, MASK_FMUL_H)
  361. +DECLARE_INSN(fdiv_h, MATCH_FDIV_D, MASK_FDIV_H)
  362. +DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_D, MASK_FSGNJ_H)
  363. +DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_D, MASK_FSGNJN_H)
  364. +DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_D, MASK_FSGNJX_H)
  365. +DECLARE_INSN(fmin_h, MATCH_FMIN_D, MASK_FMIN_H)
  366. +DECLARE_INSN(fmax_h, MATCH_FMAX_D, MASK_FMAX_H)
  367. +DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_D, MASK_FCVT_S_H)
  368. +DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
  369. +DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
  370. +DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
  371. +DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H)
  372. +DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q)
  373. +DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
  374. DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
  375. DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
  376. DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
  377. @@ -3197,6 +3285,9 @@ DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
  378. DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
  379. DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
  380. DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
  381. +DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
  382. +DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
  383. +DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
  384. DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
  385. DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
  386. DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
  387. @@ -3212,6 +3303,12 @@ DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
  388. DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
  389. DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
  390. DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
  391. +DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
  392. +DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
  393. +DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
  394. +DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
  395. +DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
  396. +DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H)
  397. DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
  398. DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
  399. DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
  400. @@ -3228,14 +3325,21 @@ DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
  401. DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
  402. DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
  403. DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
  404. +DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
  405. +DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
  406. +DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
  407. +DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
  408. +DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
  409. DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
  410. DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
  411. DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
  412. DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
  413. DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
  414. +DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
  415. DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
  416. DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
  417. DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
  418. +DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
  419. DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
  420. DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
  421. DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
  422. @@ -3247,6 +3351,10 @@ DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
  423. DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
  424. DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
  425. DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
  426. +DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
  427. +DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
  428. +DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
  429. +DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
  430. DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
  431. DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
  432. DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
  433. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  434. index 5fd18beb88..31bdcf95a9 100644
  435. --- a/include/opcode/riscv.h
  436. +++ b/include/opcode/riscv.h
  437. @@ -378,10 +378,13 @@ enum riscv_insn_class
  438. INSN_CLASS_M,
  439. INSN_CLASS_F,
  440. INSN_CLASS_D,
  441. - INSN_CLASS_D_AND_C,
  442. - INSN_CLASS_F_AND_C,
  443. INSN_CLASS_Q,
  444. INSN_CLASS_V,
  445. + INSN_CLASS_F_AND_C,
  446. + INSN_CLASS_F_AND_ZFH,
  447. + INSN_CLASS_D_AND_C,
  448. + INSN_CLASS_D_AND_ZFH,
  449. + INSN_CLASS_Q_AND_ZFH,
  450. INSN_CLASS_V_AND_F,
  451. INSN_CLASS_V_OR_ZVAMO,
  452. INSN_CLASS_V_AND_ZVEDIV,
  453. @@ -551,9 +554,11 @@ enum
  454. M_SH,
  455. M_SW,
  456. M_SD,
  457. + M_FLH,
  458. M_FLW,
  459. M_FLD,
  460. M_FLQ,
  461. + M_FSH,
  462. M_FSW,
  463. M_FSD,
  464. M_FSQ,
  465. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  466. index 7499abb7a6..89593ef979 100644
  467. --- a/opcodes/riscv-opc.c
  468. +++ b/opcodes/riscv-opc.c
  469. @@ -898,6 +898,71 @@ const struct riscv_opcode riscv_opcodes[] =
  470. {"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
  471. {"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
  472. +/* Half-precision floating-point instruction subset */
  473. +{"flh", 0, INSN_CLASS_F_AND_ZFH, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
  474. +{"flh", 0, INSN_CLASS_F_AND_ZFH, "D,A,s", 0, (int) M_FLH, match_never, INSN_MACRO },
  475. +{"fsh", 0, INSN_CLASS_F_AND_ZFH, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
  476. +{"fsh", 0, INSN_CLASS_F_AND_ZFH, "T,A,s", 0, (int) M_FSH, match_never, INSN_MACRO },
  477. +{"fmv.h", 0, INSN_CLASS_F_AND_ZFH, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
  478. +{"fneg.h", 0, INSN_CLASS_F_AND_ZFH, "D,U", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
  479. +{"fabs.h", 0, INSN_CLASS_F_AND_ZFH, "D,U", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
  480. +{"fsgnj.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
  481. +{"fsgnjn.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
  482. +{"fsgnjx.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
  483. +{"fadd.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T", MATCH_FADD_H | MASK_RM, MASK_FADD_H | MASK_RM, match_opcode, 0 },
  484. +{"fadd.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
  485. +{"fsub.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T", MATCH_FSUB_H | MASK_RM, MASK_FSUB_H | MASK_RM, match_opcode, 0 },
  486. +{"fsub.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
  487. +{"fmul.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T", MATCH_FMUL_H | MASK_RM, MASK_FMUL_H | MASK_RM, match_opcode, 0 },
  488. +{"fmul.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
  489. +{"fdiv.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T", MATCH_FDIV_H | MASK_RM, MASK_FDIV_H | MASK_RM, match_opcode, 0 },
  490. +{"fdiv.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
  491. +{"fsqrt.h", 0, INSN_CLASS_F_AND_ZFH, "D,S", MATCH_FSQRT_H | MASK_RM, MASK_FSQRT_H | MASK_RM, match_opcode, 0 },
  492. +{"fsqrt.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
  493. +{"fmin.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
  494. +{"fmax.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
  495. +{"fmadd.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,R", MATCH_FMADD_H | MASK_RM, MASK_FMADD_H | MASK_RM, match_opcode, 0 },
  496. +{"fmadd.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
  497. +{"fnmadd.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,R", MATCH_FNMADD_H | MASK_RM, MASK_FNMADD_H | MASK_RM, match_opcode, 0 },
  498. +{"fnmadd.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
  499. +{"fmsub.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,R", MATCH_FMSUB_H | MASK_RM, MASK_FMSUB_H | MASK_RM, match_opcode, 0 },
  500. +{"fmsub.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
  501. +{"fnmsub.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,R", MATCH_FNMSUB_H | MASK_RM, MASK_FNMSUB_H | MASK_RM, match_opcode, 0 },
  502. +{"fnmsub.h", 0, INSN_CLASS_F_AND_ZFH, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
  503. +{"fcvt.w.h", 0, INSN_CLASS_F_AND_ZFH, "d,S", MATCH_FCVT_W_H | MASK_RM, MASK_FCVT_W_H | MASK_RM, match_opcode, 0 },
  504. +{"fcvt.w.h", 0, INSN_CLASS_F_AND_ZFH, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
  505. +{"fcvt.wu.h", 0, INSN_CLASS_F_AND_ZFH, "d,S", MATCH_FCVT_WU_H | MASK_RM, MASK_FCVT_WU_H | MASK_RM, match_opcode, 0 },
  506. +{"fcvt.wu.h", 0, INSN_CLASS_F_AND_ZFH, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
  507. +{"fcvt.h.w", 0, INSN_CLASS_F_AND_ZFH, "D,s", MATCH_FCVT_H_W | MASK_RM, MASK_FCVT_H_W | MASK_RM, match_opcode, 0 },
  508. +{"fcvt.h.w", 0, INSN_CLASS_F_AND_ZFH, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
  509. +{"fcvt.h.wu", 0, INSN_CLASS_F_AND_ZFH, "D,s", MATCH_FCVT_H_WU | MASK_RM, MASK_FCVT_H_WU | MASK_RM, match_opcode, 0 },
  510. +{"fcvt.h.wu", 0, INSN_CLASS_F_AND_ZFH, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
  511. +{"fcvt.s.h", 0, INSN_CLASS_F_AND_ZFH, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H | MASK_RM, match_opcode, 0 },
  512. +{"fcvt.d.h", 0, INSN_CLASS_D_AND_ZFH, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H | MASK_RM, match_opcode, 0 },
  513. +{"fcvt.q.h", 0, INSN_CLASS_Q_AND_ZFH, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H | MASK_RM, match_opcode, 0 },
  514. +{"fcvt.h.s", 0, INSN_CLASS_F_AND_ZFH, "D,S", MATCH_FCVT_H_S | MASK_RM, MASK_FCVT_H_S | MASK_RM, match_opcode, 0 },
  515. +{"fcvt.h.s", 0, INSN_CLASS_F_AND_ZFH, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
  516. +{"fcvt.h.d", 0, INSN_CLASS_D_AND_ZFH, "D,S", MATCH_FCVT_H_D | MASK_RM, MASK_FCVT_H_D | MASK_RM, match_opcode, 0 },
  517. +{"fcvt.h.d", 0, INSN_CLASS_D_AND_ZFH, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
  518. +{"fcvt.h.q", 0, INSN_CLASS_Q_AND_ZFH, "D,S", MATCH_FCVT_H_Q | MASK_RM, MASK_FCVT_H_Q | MASK_RM, match_opcode, 0 },
  519. +{"fcvt.h.q", 0, INSN_CLASS_Q_AND_ZFH, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
  520. +{"fclass.h", 0, INSN_CLASS_F_AND_ZFH, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
  521. +{"feq.h", 0, INSN_CLASS_F_AND_ZFH, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
  522. +{"flt.h", 0, INSN_CLASS_F_AND_ZFH, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
  523. +{"fle.h", 0, INSN_CLASS_F_AND_ZFH, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
  524. +{"fgt.h", 0, INSN_CLASS_F_AND_ZFH, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
  525. +{"fge.h", 0, INSN_CLASS_F_AND_ZFH, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
  526. +{"fmv.x.h", 0, INSN_CLASS_F_AND_ZFH, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
  527. +{"fmv.h.x", 0, INSN_CLASS_F_AND_ZFH, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
  528. +{"fcvt.l.h", 64, INSN_CLASS_F_AND_ZFH, "d,S", MATCH_FCVT_L_H | MASK_RM, MASK_FCVT_L_H | MASK_RM, match_opcode, 0 },
  529. +{"fcvt.l.h", 64, INSN_CLASS_F_AND_ZFH, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
  530. +{"fcvt.lu.h", 64, INSN_CLASS_F_AND_ZFH, "d,S", MATCH_FCVT_LU_H | MASK_RM, MASK_FCVT_LU_H | MASK_RM, match_opcode, 0 },
  531. +{"fcvt.lu.h", 64, INSN_CLASS_F_AND_ZFH, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
  532. +{"fcvt.h.l", 64, INSN_CLASS_F_AND_ZFH, "D,s", MATCH_FCVT_H_L | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
  533. +{"fcvt.h.l", 64, INSN_CLASS_F_AND_ZFH, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
  534. +{"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH, "D,s", MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode, 0 },
  535. +{"fcvt.h.lu", 64, INSN_CLASS_F_AND_ZFH, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
  536. +
  537. /* Single-precision floating-point instruction subset */
  538. {"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
  539. {"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
  540. --
  541. 2.33.0