0017-Added-reciprocal-and-reciprocal-square-root-estimate.patch 5.4 KB

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  1. From aefce8023a15dad4835317dbc26c5e8bf93061f2 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Mon, 6 Jul 2020 15:31:05 +0800
  4. Subject: [PATCH 17/48] Added reciprocal and reciprocal square-root estimate
  5. instruction.
  6. Add new instruction vfrsqrte7.v and vfrece7.v. The former set VFUNARY1 (vs1)
  7. to 00100, and the later set VFUNARY1 to 00101.
  8. ---
  9. gas/testsuite/gas/riscv/vector-insns.d | 8 ++++++--
  10. gas/testsuite/gas/riscv/vector-insns.s | 9 ++++++---
  11. include/opcode/riscv-opc.h | 15 ++++++++++-----
  12. opcodes/riscv-opc.c | 5 +++--
  13. 4 files changed, 25 insertions(+), 12 deletions(-)
  14. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  15. index 99eb5abf70..8909e822a0 100644
  16. --- a/gas/testsuite/gas/riscv/vector-insns.d
  17. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  18. @@ -2168,6 +2168,12 @@ Disassembly of section .text:
  19. [ ]+[0-9a-f]+:[ ]+fc865257[ ]+vfwnmsac.vf[ ]+v4,fa2,v8,v0.t
  20. [ ]+[0-9a-f]+:[ ]+4e801257[ ]+vfsqrt.v[ ]+v4,v8
  21. [ ]+[0-9a-f]+:[ ]+4c801257[ ]+vfsqrt.v[ ]+v4,v8,v0.t
  22. +[ ]+[0-9a-f]+:[ ]+4e821257[ ]+vfrsqrte7.v[ ]+v4,v8
  23. +[ ]+[0-9a-f]+:[ ]+4c821257[ ]+vfrsqrte7.v[ ]+v4,v8,v0.t
  24. +[ ]+[0-9a-f]+:[ ]+4e829257[ ]+vfrece7.v[ ]+v4,v8
  25. +[ ]+[0-9a-f]+:[ ]+4c829257[ ]+vfrece7.v[ ]+v4,v8,v0.t
  26. +[ ]+[0-9a-f]+:[ ]+4e881257[ ]+vfclass.v[ ]+v4,v8
  27. +[ ]+[0-9a-f]+:[ ]+4c881257[ ]+vfclass.v[ ]+v4,v8,v0.t
  28. [ ]+[0-9a-f]+:[ ]+12861257[ ]+vfmin.vv[ ]+v4,v8,v12
  29. [ ]+[0-9a-f]+:[ ]+12865257[ ]+vfmin.vf[ ]+v4,v8,fa2
  30. [ ]+[0-9a-f]+:[ ]+1a861257[ ]+vfmax.vv[ ]+v4,v8,v12
  31. @@ -2212,8 +2218,6 @@ Disassembly of section .text:
  32. [ ]+[0-9a-f]+:[ ]+64865257[ ]+vmfle.vf[ ]+v4,v8,fa2,v0.t
  33. [ ]+[0-9a-f]+:[ ]+74865257[ ]+vmfgt.vf[ ]+v4,v8,fa2,v0.t
  34. [ ]+[0-9a-f]+:[ ]+7c865257[ ]+vmfge.vf[ ]+v4,v8,fa2,v0.t
  35. -[ ]+[0-9a-f]+:[ ]+4e881257[ ]+vfclass.v[ ]+v4,v8
  36. -[ ]+[0-9a-f]+:[ ]+4c881257[ ]+vfclass.v[ ]+v4,v8,v0.t
  37. [ ]+[0-9a-f]+:[ ]+5c865257[ ]+vfmerge.vfm[ ]+v4,v8,fa2,v0
  38. [ ]+[0-9a-f]+:[ ]+5e05d257[ ]+vfmv.v.f[ ]+v4,fa1
  39. [ ]+[0-9a-f]+:[ ]+4a801257[ ]+vfcvt.xu.f.v[ ]+v4,v8
  40. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  41. index 3b489685c9..39da92bab7 100644
  42. --- a/gas/testsuite/gas/riscv/vector-insns.s
  43. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  44. @@ -2474,6 +2474,12 @@
  45. vfsqrt.v v4, v8
  46. vfsqrt.v v4, v8, v0.t
  47. + vfrsqrte7.v v4, v8
  48. + vfrsqrte7.v v4, v8, v0.t
  49. + vfrece7.v v4, v8
  50. + vfrece7.v v4, v8, v0.t
  51. + vfclass.v v4, v8
  52. + vfclass.v v4, v8, v0.t
  53. vfmin.vv v4, v8, v12
  54. vfmin.vf v4, v8, fa2
  55. @@ -2524,9 +2530,6 @@
  56. vmfgt.vf v4, v8, fa2, v0.t
  57. vmfge.vf v4, v8, fa2, v0.t
  58. - vfclass.v v4, v8
  59. - vfclass.v v4, v8, v0.t
  60. -
  61. vfmerge.vfm v4, v8, fa2, v0
  62. vfmv.v.f v4, fa1
  63. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  64. index 71eb770f5a..2da0574cc0 100644
  65. --- a/include/opcode/riscv-opc.h
  66. +++ b/include/opcode/riscv-opc.h
  67. @@ -1950,6 +1950,8 @@ vs1
  68. VFUNARY1
  69. vs1
  70. 00000 vfsqrt.v
  71. +00100 vfrsqrte7.v
  72. +00101 vfrece7.v
  73. 10000 vfclass.v
  74. 31-26 25 24-20 19-15 14-12 11-7 6-0
  75. @@ -2441,8 +2443,14 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  76. #define MATCH_VFWNMSACVF 0xfc005057
  77. #define MASK_VFWNMSACVF 0xfc00707f
  78. -#define MATCH_VFSQRTV 0x4c001057
  79. -#define MASK_VFSQRTV 0xfc0ff07f
  80. +#define MATCH_VFSQRTV 0x4c001057
  81. +#define MASK_VFSQRTV 0xfc0ff07f
  82. +#define MATCH_VFRSQRTE7V 0x4c021057
  83. +#define MASK_VFRSQRTE7V 0xfc0ff07f
  84. +#define MATCH_VFRECE7V 0x4c029057
  85. +#define MASK_VFRECE7V 0xfc0ff07f
  86. +#define MATCH_VFCLASSV 0x4c081057
  87. +#define MASK_VFCLASSV 0xfc0ff07f
  88. #define MATCH_VFMINVV 0x10001057
  89. #define MASK_VFMINVV 0xfc00707f
  90. @@ -2487,9 +2495,6 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  91. #define MATCH_VMFGEVF 0x7c005057
  92. #define MASK_VMFGEVF 0xfc00707f
  93. -#define MATCH_VFCLASSV 0x4c081057
  94. -#define MASK_VFCLASSV 0xfc0ff07f
  95. -
  96. #define MATCH_VFMERGEVFM 0x5c005057
  97. #define MASK_VFMERGEVFM 0xfe00707f
  98. #define MATCH_VFMVVF 0x5e005057
  99. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  100. index 66c3046150..cb89f59208 100644
  101. --- a/opcodes/riscv-opc.c
  102. +++ b/opcodes/riscv-opc.c
  103. @@ -1875,6 +1875,9 @@ const struct riscv_opcode riscv_opcodes[] =
  104. {"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
  105. {"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0},
  106. +{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRTE7V, MASK_VFRSQRTE7V, match_opcode, 0},
  107. +{"vfrece7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRECE7V, MASK_VFRECE7V, match_opcode, 0},
  108. +{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
  109. {"vfmin.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
  110. {"vfmin.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
  111. @@ -1903,8 +1906,6 @@ const struct riscv_opcode riscv_opcodes[] =
  112. {"vmfgt.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
  113. {"vmfge.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
  114. -{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
  115. -
  116. {"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
  117. {"vfmv.v.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
  118. --
  119. 2.33.0