0033-RISC-V-Rename-vncvt.x.x.v-to-vncvt.x.x.w.patch 5.2 KB

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  1. From 661ff3b85995c4bd23f90074270685d1eb79ca4e Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Mon, 7 Dec 2020 01:46:08 -0800
  4. Subject: [PATCH 33/48] RISC-V: Rename vncvt.x.x.v to vncvt.x.x.w.
  5. ---
  6. .../gas/riscv/vector-insns-fail-arith-narrow.l | 8 ++++----
  7. .../gas/riscv/vector-insns-fail-arith-narrow.s | 10 +++++-----
  8. gas/testsuite/gas/riscv/vector-insns.d | 4 ++--
  9. gas/testsuite/gas/riscv/vector-insns.s | 4 ++--
  10. include/opcode/riscv-opc.h | 4 ++--
  11. opcodes/riscv-opc.c | 2 +-
  12. 6 files changed, 16 insertions(+), 16 deletions(-)
  13. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
  14. index defca03d6d..3a3634cd09 100644
  15. --- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
  16. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
  17. @@ -1,8 +1,8 @@
  18. .*: Assembler messages:
  19. -.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.v v2,v2'
  20. -.*Error: illegal operands vd must be multiple of 2 `vncvt.x.x.v v2,v3'
  21. -.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.v v3,v2'
  22. -.*Error: illegal operands vd cannot overlap vm `vncvt.x.x.v v0,v2,v0.t'
  23. +.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.w v2,v2'
  24. +.*Error: illegal operands vd must be multiple of 2 `vncvt.x.x.w v2,v3'
  25. +.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.w v3,v2'
  26. +.*Error: illegal operands vd cannot overlap vm `vncvt.x.x.w v0,v2,v0.t'
  27. .*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v2,v2,v4'
  28. .*Error: illegal operands vd must be multiple of 2 `vnsrl.wv v2,v3,v4'
  29. .*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v3,v2,v4'
  30. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
  31. index a843d076ff..73b96ef800 100644
  32. --- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
  33. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
  34. @@ -1,10 +1,10 @@
  35. # Vector Narrowing Integer Right Shift Instructions
  36. - # vncvt.x.x.v vd,vs,vm = vnsrl.wx vd,vs,x0,vm
  37. - vncvt.x.x.v v2, v2 # vd overlap vs2
  38. - vncvt.x.x.v v2, v3 # vs2 should be multiple of 2
  39. - vncvt.x.x.v v3, v2 # vd overlap vs2
  40. - vncvt.x.x.v v0, v2, v0.t # vd overlap vm
  41. + # vncvt.x.x.w vd,vs,vm = vnsrl.wx vd,vs,x0,vm
  42. + vncvt.x.x.w v2, v2 # vd overlap vs2
  43. + vncvt.x.x.w v2, v3 # vs2 should be multiple of 2
  44. + vncvt.x.x.w v3, v2 # vd overlap vs2
  45. + vncvt.x.x.w v0, v2, v0.t # vd overlap vm
  46. vnsrl.wv v2, v2, v4 # vd overlap vs2
  47. vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
  48. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  49. index d8a8aa6d09..865ec7644e 100644
  50. --- a/gas/testsuite/gas/riscv/vector-insns.d
  51. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  52. @@ -2210,8 +2210,8 @@ Disassembly of section .text:
  53. [ ]+[0-9a-f]+:[ ]+a485c257[ ]+vsra.vx[ ]+v4,v8,a1,v0.t
  54. [ ]+[0-9a-f]+:[ ]+a480b257[ ]+vsra.vi[ ]+v4,v8,1,v0.t
  55. [ ]+[0-9a-f]+:[ ]+a48fb257[ ]+vsra.vi[ ]+v4,v8,31,v0.t
  56. -[ ]+[0-9a-f]+:[ ]+b2804257[ ]+vncvt.x.x.v[ ]+v4,v8
  57. -[ ]+[0-9a-f]+:[ ]+b0804257[ ]+vncvt.x.x.v[ ]+v4,v8,v0.t
  58. +[ ]+[0-9a-f]+:[ ]+b2804257[ ]+vncvt.x.x.w[ ]+v4,v8
  59. +[ ]+[0-9a-f]+:[ ]+b0804257[ ]+vncvt.x.x.w[ ]+v4,v8,v0.t
  60. [ ]+[0-9a-f]+:[ ]+b2860257[ ]+vnsrl.wv[ ]+v4,v8,v12
  61. [ ]+[0-9a-f]+:[ ]+b285c257[ ]+vnsrl.wx[ ]+v4,v8,a1
  62. [ ]+[0-9a-f]+:[ ]+b280b257[ ]+vnsrl.wi[ ]+v4,v8,1
  63. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  64. index 5431863af9..204088151e 100644
  65. --- a/gas/testsuite/gas/riscv/vector-insns.s
  66. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  67. @@ -2551,8 +2551,8 @@
  68. vsra.vi v4, v8, 31, v0.t
  69. # Aliases
  70. - vncvt.x.x.v v4, v8
  71. - vncvt.x.x.v v4, v8, v0.t
  72. + vncvt.x.x.w v4, v8
  73. + vncvt.x.x.w v4, v8, v0.t
  74. vnsrl.wv v4, v8, v12
  75. vnsrl.wx v4, v8, a1
  76. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  77. index d74d3d5044..2355f14b73 100644
  78. --- a/include/opcode/riscv-opc.h
  79. +++ b/include/opcode/riscv-opc.h
  80. @@ -2474,8 +2474,8 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  81. #define MATCH_VSRAVI 0xa4003057
  82. #define MASK_VSRAVI 0xfc00707f
  83. -#define MATCH_VNCVTXXV 0xb0004057
  84. -#define MASK_VNCVTXXV 0xfc0ff07f
  85. +#define MATCH_VNCVTXXW 0xb0004057
  86. +#define MASK_VNCVTXXW 0xfc0ff07f
  87. #define MATCH_VNSRLWV 0xb0000057
  88. #define MASK_VNSRLWV 0xfc00707f
  89. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  90. index 076aea5f91..7b258ee982 100644
  91. --- a/opcodes/riscv-opc.c
  92. +++ b/opcodes/riscv-opc.c
  93. @@ -2040,7 +2040,7 @@ const struct riscv_opcode riscv_opcodes[] =
  94. {"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
  95. {"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
  96. -{"vncvt.x.x.v",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
  97. +{"vncvt.x.x.w",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
  98. {"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
  99. {"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
  100. --
  101. 2.33.0