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- From 661ff3b85995c4bd23f90074270685d1eb79ca4e Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Mon, 7 Dec 2020 01:46:08 -0800
- Subject: [PATCH 33/48] RISC-V: Rename vncvt.x.x.v to vncvt.x.x.w.
- ---
- .../gas/riscv/vector-insns-fail-arith-narrow.l | 8 ++++----
- .../gas/riscv/vector-insns-fail-arith-narrow.s | 10 +++++-----
- gas/testsuite/gas/riscv/vector-insns.d | 4 ++--
- gas/testsuite/gas/riscv/vector-insns.s | 4 ++--
- include/opcode/riscv-opc.h | 4 ++--
- opcodes/riscv-opc.c | 2 +-
- 6 files changed, 16 insertions(+), 16 deletions(-)
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
- index defca03d6d..3a3634cd09 100644
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
- @@ -1,8 +1,8 @@
- .*: Assembler messages:
- -.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.v v2,v2'
- -.*Error: illegal operands vd must be multiple of 2 `vncvt.x.x.v v2,v3'
- -.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.v v3,v2'
- -.*Error: illegal operands vd cannot overlap vm `vncvt.x.x.v v0,v2,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.w v2,v2'
- +.*Error: illegal operands vd must be multiple of 2 `vncvt.x.x.w v2,v3'
- +.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.w v3,v2'
- +.*Error: illegal operands vd cannot overlap vm `vncvt.x.x.w v0,v2,v0.t'
- .*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v2,v2,v4'
- .*Error: illegal operands vd must be multiple of 2 `vnsrl.wv v2,v3,v4'
- .*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v3,v2,v4'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
- index a843d076ff..73b96ef800 100644
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
- @@ -1,10 +1,10 @@
- # Vector Narrowing Integer Right Shift Instructions
-
- - # vncvt.x.x.v vd,vs,vm = vnsrl.wx vd,vs,x0,vm
- - vncvt.x.x.v v2, v2 # vd overlap vs2
- - vncvt.x.x.v v2, v3 # vs2 should be multiple of 2
- - vncvt.x.x.v v3, v2 # vd overlap vs2
- - vncvt.x.x.v v0, v2, v0.t # vd overlap vm
- + # vncvt.x.x.w vd,vs,vm = vnsrl.wx vd,vs,x0,vm
- + vncvt.x.x.w v2, v2 # vd overlap vs2
- + vncvt.x.x.w v2, v3 # vs2 should be multiple of 2
- + vncvt.x.x.w v3, v2 # vd overlap vs2
- + vncvt.x.x.w v0, v2, v0.t # vd overlap vm
-
- vnsrl.wv v2, v2, v4 # vd overlap vs2
- vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
- diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
- index d8a8aa6d09..865ec7644e 100644
- --- a/gas/testsuite/gas/riscv/vector-insns.d
- +++ b/gas/testsuite/gas/riscv/vector-insns.d
- @@ -2210,8 +2210,8 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+a485c257[ ]+vsra.vx[ ]+v4,v8,a1,v0.t
- [ ]+[0-9a-f]+:[ ]+a480b257[ ]+vsra.vi[ ]+v4,v8,1,v0.t
- [ ]+[0-9a-f]+:[ ]+a48fb257[ ]+vsra.vi[ ]+v4,v8,31,v0.t
- -[ ]+[0-9a-f]+:[ ]+b2804257[ ]+vncvt.x.x.v[ ]+v4,v8
- -[ ]+[0-9a-f]+:[ ]+b0804257[ ]+vncvt.x.x.v[ ]+v4,v8,v0.t
- +[ ]+[0-9a-f]+:[ ]+b2804257[ ]+vncvt.x.x.w[ ]+v4,v8
- +[ ]+[0-9a-f]+:[ ]+b0804257[ ]+vncvt.x.x.w[ ]+v4,v8,v0.t
- [ ]+[0-9a-f]+:[ ]+b2860257[ ]+vnsrl.wv[ ]+v4,v8,v12
- [ ]+[0-9a-f]+:[ ]+b285c257[ ]+vnsrl.wx[ ]+v4,v8,a1
- [ ]+[0-9a-f]+:[ ]+b280b257[ ]+vnsrl.wi[ ]+v4,v8,1
- diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
- index 5431863af9..204088151e 100644
- --- a/gas/testsuite/gas/riscv/vector-insns.s
- +++ b/gas/testsuite/gas/riscv/vector-insns.s
- @@ -2551,8 +2551,8 @@
- vsra.vi v4, v8, 31, v0.t
-
- # Aliases
- - vncvt.x.x.v v4, v8
- - vncvt.x.x.v v4, v8, v0.t
- + vncvt.x.x.w v4, v8
- + vncvt.x.x.w v4, v8, v0.t
-
- vnsrl.wv v4, v8, v12
- vnsrl.wx v4, v8, a1
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index d74d3d5044..2355f14b73 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -2474,8 +2474,8 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
- #define MATCH_VSRAVI 0xa4003057
- #define MASK_VSRAVI 0xfc00707f
-
- -#define MATCH_VNCVTXXV 0xb0004057
- -#define MASK_VNCVTXXV 0xfc0ff07f
- +#define MATCH_VNCVTXXW 0xb0004057
- +#define MASK_VNCVTXXW 0xfc0ff07f
-
- #define MATCH_VNSRLWV 0xb0000057
- #define MASK_VNSRLWV 0xfc00707f
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index 076aea5f91..7b258ee982 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -2040,7 +2040,7 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
- {"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
-
- -{"vncvt.x.x.v",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
- +{"vncvt.x.x.w",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
-
- {"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
- {"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
- --
- 2.33.0
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