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|
- From 0b3aaf2a0ee9650beec58c39ce6fb248f4bd6a81 Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Mon, 23 Nov 2020 13:32:07 +0800
- Subject: [PATCH 32/48] RISC-V: Added ordered/unordered vector indexed
- instructions.
- The mop field 01 is indexed-unordered LOAD/STORE; and 11 is indexed-ordered
- LOAD/STORE. Both vector indexed and vector indexed segment are need to
- support.
- ---
- .../gas/riscv/vector-insns-fail-load-store.l | 692 +++++----
- .../gas/riscv/vector-insns-fail-load-store.s | 749 ++++++----
- gas/testsuite/gas/riscv/vector-insns.d | 1068 +++++++++-----
- gas/testsuite/gas/riscv/vector-insns.s | 1234 +++++++++++------
- include/opcode/riscv-opc.h | 758 ++++++----
- opcodes/riscv-opc.c | 379 +++--
- 6 files changed, 3237 insertions(+), 1643 deletions(-)
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
- index 3e2a24390b..6de77bff4a 100644
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
- @@ -39,14 +39,18 @@
- .*Error: illegal operands vd cannot overlap vm `vsse256.v v0,\(a0\),a1,v0.t'
- .*Error: illegal operands vd cannot overlap vm `vsse512.v v0,\(a0\),a1,v0.t'
- .*Error: illegal operands vd cannot overlap vm `vsse1024.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands vd cannot overlap vm `vlxei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vm `vlxei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vm `vlxei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vm `vlxei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vm `vsxei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vm `vsxei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vm `vsxei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vm `vsxei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vloxei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vloxei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vloxei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vloxei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vsoxei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vsoxei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vsoxei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vsoxei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vluxei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vluxei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vluxei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vm `vluxei64.v v0,\(a0\),v4,v0.t'
- .*Error: illegal operands vd cannot overlap vm `vsuxei8.v v0,\(a0\),v4,v0.t'
- .*Error: illegal operands vd cannot overlap vm `vsuxei16.v v0,\(a0\),v4,v0.t'
- .*Error: illegal operands vd cannot overlap vm `vsuxei32.v v0,\(a0\),v4,v0.t'
- @@ -331,230 +335,454 @@
- .*Error: illegal operands vd cannot overlap vm `vssseg7e1024.v v0,\(a0\),a1,v0.t'
- .*Error: illegal operands vd cannot overlap vm `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
- .*Error: illegal operands vd cannot overlap vm `vssseg8e1024.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg2ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg2ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg3ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg3ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg4ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg4ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg5ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg5ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg6ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg6ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg7ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg7ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg8ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei8.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg8ei8.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg2ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg2ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg3ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg3ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg4ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg4ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg5ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg5ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg6ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg6ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg7ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg7ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg8ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei16.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg8ei16.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg2ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg2ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg3ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg3ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg4ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg4ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg5ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg5ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg6ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg6ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg7ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg7ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg8ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei32.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg8ei32.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg2ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg2ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg3ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg3ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg4ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg4ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg5ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg5ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg6ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg6ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg7ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg7ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg8ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei64.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg8ei64.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg2ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg2ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg3ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg3ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg4ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg4ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg5ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg5ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg6ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg6ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg7ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg7ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg8ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei128.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg8ei128.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg2ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg2ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg3ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg3ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg4ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg4ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg5ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg5ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg6ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg6ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg7ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg7ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg8ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei256.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg8ei256.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg2ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg2ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg3ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg3ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg4ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg4ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg5ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg5ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg6ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg6ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg7ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg7ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg8ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei512.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg8ei512.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg2ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg2ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg2ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg2ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg3ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg3ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg3ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg3ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg4ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg4ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg4ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg4ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg5ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg5ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg5ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg5ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg6ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg6ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg6ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg6ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg7ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg7ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg7ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg7ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vlxseg8ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vlxseg8ei1024.v v0,\(a0\),v4,v0.t'
- -.*Error: illegal operands vd cannot overlap vs2 `vsxseg8ei1024.v v4,\(a0\),v4'
- -.*Error: illegal operands vd cannot overlap vm `vsxseg8ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg2ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg3ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg4ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg5ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg6ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg7ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg8ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg2ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg3ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg4ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg5ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg6ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg7ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg8ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg2ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg3ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg4ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg5ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg6ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg7ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg8ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg2ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg3ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg4ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg5ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg6ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg7ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg8ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg2ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg3ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg4ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg5ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg6ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg7ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg8ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg2ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg3ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg4ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg5ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg6ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg7ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg8ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg2ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg3ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg4ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg5ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg6ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg7ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg8ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg2ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg3ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg4ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg5ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg6ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg7ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vloxseg8ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg2ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg3ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg4ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg5ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg6ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg7ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg8ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg2ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg3ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg4ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg5ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg6ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg7ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg8ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg2ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg3ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg4ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg5ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg6ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg7ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg8ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg2ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg3ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg4ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg5ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg6ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg7ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg8ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg2ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg3ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg4ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg5ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg6ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg7ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg8ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg2ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg3ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg4ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg5ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg6ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg7ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg8ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg2ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg3ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg4ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg5ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg6ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg7ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg8ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg2ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg3ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg4ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg5ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg6ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg7ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vluxseg8ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei1024.v v0,\(a0\),v4,v0.t'
- .*Error: illegal operands vd must be multiple of nf `vl2r.v v31,\(a0\)'
- .*Error: illegal operands vd must be multiple of nf `vl2re8.v v31,\(a0\)'
- .*Error: illegal operands vd must be multiple of nf `vl2re16.v v31,\(a0\)'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
- index e4f1085174..85bcb3d03e 100644
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
- @@ -46,25 +46,36 @@
- vsse512.v v0, (a0), a1, v0.t
- vsse1024.v v0, (a0), a1, v0.t
-
- -# Vector Indexed Loads and Stores
- -
- - vlxei8.v v4, (a0), v4 # OK
- - vlxei8.v v0, (a0), v4, v0.t # vd overlap vm
- - vlxei16.v v4, (a0), v4
- - vlxei16.v v0, (a0), v4, v0.t
- - vlxei32.v v4, (a0), v4
- - vlxei32.v v0, (a0), v4, v0.t
- - vlxei64.v v4, (a0), v4
- - vlxei64.v v0, (a0), v4, v0.t
- -
- - vsxei8.v v4, (a0), v4
- - vsxei8.v v0, (a0), v4, v0.t
- - vsxei16.v v4, (a0), v4
- - vsxei16.v v0, (a0), v4, v0.t
- - vsxei32.v v4, (a0), v4
- - vsxei32.v v0, (a0), v4, v0.t
- - vsxei64.v v4, (a0), v4
- - vsxei64.v v0, (a0), v4, v0.t
- +# Vector Ordered Indexed Loads and Stores
- +
- + vloxei8.v v4, (a0), v4 # OK
- + vloxei8.v v0, (a0), v4, v0.t # vd overlap vm
- + vloxei16.v v4, (a0), v4
- + vloxei16.v v0, (a0), v4, v0.t
- + vloxei32.v v4, (a0), v4
- + vloxei32.v v0, (a0), v4, v0.t
- + vloxei64.v v4, (a0), v4
- + vloxei64.v v0, (a0), v4, v0.t
- +
- + vsoxei8.v v4, (a0), v4
- + vsoxei8.v v0, (a0), v4, v0.t
- + vsoxei16.v v4, (a0), v4
- + vsoxei16.v v0, (a0), v4, v0.t
- + vsoxei32.v v4, (a0), v4
- + vsoxei32.v v0, (a0), v4, v0.t
- + vsoxei64.v v4, (a0), v4
- + vsoxei64.v v0, (a0), v4, v0.t
- +
- +# Vector Unordered Indexed Loads and Stores
- +
- + vluxei8.v v4, (a0), v4 # OK
- + vluxei8.v v0, (a0), v4, v0.t # vd overlap vm
- + vluxei16.v v4, (a0), v4
- + vluxei16.v v0, (a0), v4, v0.t
- + vluxei32.v v4, (a0), v4
- + vluxei32.v v0, (a0), v4, v0.t
- + vluxei64.v v4, (a0), v4
- + vluxei64.v v0, (a0), v4, v0.t
-
- vsuxei8.v v4, (a0), v4
- vsuxei8.v v0, (a0), v4, v0.t
- @@ -375,239 +386,473 @@
- vlsseg8e1024.v v0, (a0), a1, v0.t
- vssseg8e1024.v v0, (a0), a1, v0.t
-
- -# Vector Indexed Segment Loads and Stores
- -
- - vlxseg2ei8.v v4, (a0), v4 # vd overlap vs2
- - vlxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
- - vsxseg2ei8.v v4, (a0), v4 # vd overlap vs2
- - vsxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
- - vlxseg3ei8.v v4, (a0), v4
- - vlxseg3ei8.v v0, (a0), v4, v0.t
- - vsxseg3ei8.v v4, (a0), v4
- - vsxseg3ei8.v v0, (a0), v4, v0.t
- - vlxseg4ei8.v v4, (a0), v4
- - vlxseg4ei8.v v0, (a0), v4, v0.t
- - vsxseg4ei8.v v4, (a0), v4
- - vsxseg4ei8.v v0, (a0), v4, v0.t
- - vlxseg5ei8.v v4, (a0), v4
- - vlxseg5ei8.v v0, (a0), v4, v0.t
- - vsxseg5ei8.v v4, (a0), v4
- - vsxseg5ei8.v v0, (a0), v4, v0.t
- - vlxseg6ei8.v v4, (a0), v4
- - vlxseg6ei8.v v0, (a0), v4, v0.t
- - vsxseg6ei8.v v4, (a0), v4
- - vsxseg6ei8.v v0, (a0), v4, v0.t
- - vlxseg7ei8.v v4, (a0), v4
- - vlxseg7ei8.v v0, (a0), v4, v0.t
- - vsxseg7ei8.v v4, (a0), v4
- - vsxseg7ei8.v v0, (a0), v4, v0.t
- - vlxseg8ei8.v v4, (a0), v4
- - vlxseg8ei8.v v0, (a0), v4, v0.t
- - vsxseg8ei8.v v4, (a0), v4
- - vsxseg8ei8.v v0, (a0), v4, v0.t
- -
- - vlxseg2ei16.v v4, (a0), v4
- - vlxseg2ei16.v v0, (a0), v4, v0.t
- - vsxseg2ei16.v v4, (a0), v4
- - vsxseg2ei16.v v0, (a0), v4, v0.t
- - vlxseg3ei16.v v4, (a0), v4
- - vlxseg3ei16.v v0, (a0), v4, v0.t
- - vsxseg3ei16.v v4, (a0), v4
- - vsxseg3ei16.v v0, (a0), v4, v0.t
- - vlxseg4ei16.v v4, (a0), v4
- - vlxseg4ei16.v v0, (a0), v4, v0.t
- - vsxseg4ei16.v v4, (a0), v4
- - vsxseg4ei16.v v0, (a0), v4, v0.t
- - vlxseg5ei16.v v4, (a0), v4
- - vlxseg5ei16.v v0, (a0), v4, v0.t
- - vsxseg5ei16.v v4, (a0), v4
- - vsxseg5ei16.v v0, (a0), v4, v0.t
- - vlxseg6ei16.v v4, (a0), v4
- - vlxseg6ei16.v v0, (a0), v4, v0.t
- - vsxseg6ei16.v v4, (a0), v4
- - vsxseg6ei16.v v0, (a0), v4, v0.t
- - vlxseg7ei16.v v4, (a0), v4
- - vlxseg7ei16.v v0, (a0), v4, v0.t
- - vsxseg7ei16.v v4, (a0), v4
- - vsxseg7ei16.v v0, (a0), v4, v0.t
- - vlxseg8ei16.v v4, (a0), v4
- - vlxseg8ei16.v v0, (a0), v4, v0.t
- - vsxseg8ei16.v v4, (a0), v4
- - vsxseg8ei16.v v0, (a0), v4, v0.t
- -
- - vlxseg2ei32.v v4, (a0), v4
- - vlxseg2ei32.v v0, (a0), v4, v0.t
- - vsxseg2ei32.v v4, (a0), v4
- - vsxseg2ei32.v v0, (a0), v4, v0.t
- - vlxseg3ei32.v v4, (a0), v4
- - vlxseg3ei32.v v0, (a0), v4, v0.t
- - vsxseg3ei32.v v4, (a0), v4
- - vsxseg3ei32.v v0, (a0), v4, v0.t
- - vlxseg4ei32.v v4, (a0), v4
- - vlxseg4ei32.v v0, (a0), v4, v0.t
- - vsxseg4ei32.v v4, (a0), v4
- - vsxseg4ei32.v v0, (a0), v4, v0.t
- - vlxseg5ei32.v v4, (a0), v4
- - vlxseg5ei32.v v0, (a0), v4, v0.t
- - vsxseg5ei32.v v4, (a0), v4
- - vsxseg5ei32.v v0, (a0), v4, v0.t
- - vlxseg6ei32.v v4, (a0), v4
- - vlxseg6ei32.v v0, (a0), v4, v0.t
- - vsxseg6ei32.v v4, (a0), v4
- - vsxseg6ei32.v v0, (a0), v4, v0.t
- - vlxseg7ei32.v v4, (a0), v4
- - vlxseg7ei32.v v0, (a0), v4, v0.t
- - vsxseg7ei32.v v4, (a0), v4
- - vsxseg7ei32.v v0, (a0), v4, v0.t
- - vlxseg8ei32.v v4, (a0), v4
- - vlxseg8ei32.v v0, (a0), v4, v0.t
- - vsxseg8ei32.v v4, (a0), v4
- - vsxseg8ei32.v v0, (a0), v4, v0.t
- -
- - vlxseg2ei64.v v4, (a0), v4
- - vlxseg2ei64.v v0, (a0), v4, v0.t
- - vsxseg2ei64.v v4, (a0), v4
- - vsxseg2ei64.v v0, (a0), v4, v0.t
- - vlxseg3ei64.v v4, (a0), v4
- - vlxseg3ei64.v v0, (a0), v4, v0.t
- - vsxseg3ei64.v v4, (a0), v4
- - vsxseg3ei64.v v0, (a0), v4, v0.t
- - vlxseg4ei64.v v4, (a0), v4
- - vlxseg4ei64.v v0, (a0), v4, v0.t
- - vsxseg4ei64.v v4, (a0), v4
- - vsxseg4ei64.v v0, (a0), v4, v0.t
- - vlxseg5ei64.v v4, (a0), v4
- - vlxseg5ei64.v v0, (a0), v4, v0.t
- - vsxseg5ei64.v v4, (a0), v4
- - vsxseg5ei64.v v0, (a0), v4, v0.t
- - vlxseg6ei64.v v4, (a0), v4
- - vlxseg6ei64.v v0, (a0), v4, v0.t
- - vsxseg6ei64.v v4, (a0), v4
- - vsxseg6ei64.v v0, (a0), v4, v0.t
- - vlxseg7ei64.v v4, (a0), v4
- - vlxseg7ei64.v v0, (a0), v4, v0.t
- - vsxseg7ei64.v v4, (a0), v4
- - vsxseg7ei64.v v0, (a0), v4, v0.t
- - vlxseg8ei64.v v4, (a0), v4
- - vlxseg8ei64.v v0, (a0), v4, v0.t
- - vsxseg8ei64.v v4, (a0), v4
- - vsxseg8ei64.v v0, (a0), v4, v0.t
- -
- - vlxseg2ei128.v v4, (a0), v4
- - vlxseg2ei128.v v0, (a0), v4, v0.t
- - vsxseg2ei128.v v4, (a0), v4
- - vsxseg2ei128.v v0, (a0), v4, v0.t
- - vlxseg3ei128.v v4, (a0), v4
- - vlxseg3ei128.v v0, (a0), v4, v0.t
- - vsxseg3ei128.v v4, (a0), v4
- - vsxseg3ei128.v v0, (a0), v4, v0.t
- - vlxseg4ei128.v v4, (a0), v4
- - vlxseg4ei128.v v0, (a0), v4, v0.t
- - vsxseg4ei128.v v4, (a0), v4
- - vsxseg4ei128.v v0, (a0), v4, v0.t
- - vlxseg5ei128.v v4, (a0), v4
- - vlxseg5ei128.v v0, (a0), v4, v0.t
- - vsxseg5ei128.v v4, (a0), v4
- - vsxseg5ei128.v v0, (a0), v4, v0.t
- - vlxseg6ei128.v v4, (a0), v4
- - vlxseg6ei128.v v0, (a0), v4, v0.t
- - vsxseg6ei128.v v4, (a0), v4
- - vsxseg6ei128.v v0, (a0), v4, v0.t
- - vlxseg7ei128.v v4, (a0), v4
- - vlxseg7ei128.v v0, (a0), v4, v0.t
- - vsxseg7ei128.v v4, (a0), v4
- - vsxseg7ei128.v v0, (a0), v4, v0.t
- - vlxseg8ei128.v v4, (a0), v4
- - vlxseg8ei128.v v0, (a0), v4, v0.t
- - vsxseg8ei128.v v4, (a0), v4
- - vsxseg8ei128.v v0, (a0), v4, v0.t
- -
- - vlxseg2ei256.v v4, (a0), v4
- - vlxseg2ei256.v v0, (a0), v4, v0.t
- - vsxseg2ei256.v v4, (a0), v4
- - vsxseg2ei256.v v0, (a0), v4, v0.t
- - vlxseg3ei256.v v4, (a0), v4
- - vlxseg3ei256.v v0, (a0), v4, v0.t
- - vsxseg3ei256.v v4, (a0), v4
- - vsxseg3ei256.v v0, (a0), v4, v0.t
- - vlxseg4ei256.v v4, (a0), v4
- - vlxseg4ei256.v v0, (a0), v4, v0.t
- - vsxseg4ei256.v v4, (a0), v4
- - vsxseg4ei256.v v0, (a0), v4, v0.t
- - vlxseg5ei256.v v4, (a0), v4
- - vlxseg5ei256.v v0, (a0), v4, v0.t
- - vsxseg5ei256.v v4, (a0), v4
- - vsxseg5ei256.v v0, (a0), v4, v0.t
- - vlxseg6ei256.v v4, (a0), v4
- - vlxseg6ei256.v v0, (a0), v4, v0.t
- - vsxseg6ei256.v v4, (a0), v4
- - vsxseg6ei256.v v0, (a0), v4, v0.t
- - vlxseg7ei256.v v4, (a0), v4
- - vlxseg7ei256.v v0, (a0), v4, v0.t
- - vsxseg7ei256.v v4, (a0), v4
- - vsxseg7ei256.v v0, (a0), v4, v0.t
- - vlxseg8ei256.v v4, (a0), v4
- - vlxseg8ei256.v v0, (a0), v4, v0.t
- - vsxseg8ei256.v v4, (a0), v4
- - vsxseg8ei256.v v0, (a0), v4, v0.t
- -
- - vlxseg2ei512.v v4, (a0), v4
- - vlxseg2ei512.v v0, (a0), v4, v0.t
- - vsxseg2ei512.v v4, (a0), v4
- - vsxseg2ei512.v v0, (a0), v4, v0.t
- - vlxseg3ei512.v v4, (a0), v4
- - vlxseg3ei512.v v0, (a0), v4, v0.t
- - vsxseg3ei512.v v4, (a0), v4
- - vsxseg3ei512.v v0, (a0), v4, v0.t
- - vlxseg4ei512.v v4, (a0), v4
- - vlxseg4ei512.v v0, (a0), v4, v0.t
- - vsxseg4ei512.v v4, (a0), v4
- - vsxseg4ei512.v v0, (a0), v4, v0.t
- - vlxseg5ei512.v v4, (a0), v4
- - vlxseg5ei512.v v0, (a0), v4, v0.t
- - vsxseg5ei512.v v4, (a0), v4
- - vsxseg5ei512.v v0, (a0), v4, v0.t
- - vlxseg6ei512.v v4, (a0), v4
- - vlxseg6ei512.v v0, (a0), v4, v0.t
- - vsxseg6ei512.v v4, (a0), v4
- - vsxseg6ei512.v v0, (a0), v4, v0.t
- - vlxseg7ei512.v v4, (a0), v4
- - vlxseg7ei512.v v0, (a0), v4, v0.t
- - vsxseg7ei512.v v4, (a0), v4
- - vsxseg7ei512.v v0, (a0), v4, v0.t
- - vlxseg8ei512.v v4, (a0), v4
- - vlxseg8ei512.v v0, (a0), v4, v0.t
- - vsxseg8ei512.v v4, (a0), v4
- - vsxseg8ei512.v v0, (a0), v4, v0.t
- -
- - vlxseg2ei1024.v v4, (a0), v4
- - vlxseg2ei1024.v v0, (a0), v4, v0.t
- - vsxseg2ei1024.v v4, (a0), v4
- - vsxseg2ei1024.v v0, (a0), v4, v0.t
- - vlxseg3ei1024.v v4, (a0), v4
- - vlxseg3ei1024.v v0, (a0), v4, v0.t
- - vsxseg3ei1024.v v4, (a0), v4
- - vsxseg3ei1024.v v0, (a0), v4, v0.t
- - vlxseg4ei1024.v v4, (a0), v4
- - vlxseg4ei1024.v v0, (a0), v4, v0.t
- - vsxseg4ei1024.v v4, (a0), v4
- - vsxseg4ei1024.v v0, (a0), v4, v0.t
- - vlxseg5ei1024.v v4, (a0), v4
- - vlxseg5ei1024.v v0, (a0), v4, v0.t
- - vsxseg5ei1024.v v4, (a0), v4
- - vsxseg5ei1024.v v0, (a0), v4, v0.t
- - vlxseg6ei1024.v v4, (a0), v4
- - vlxseg6ei1024.v v0, (a0), v4, v0.t
- - vsxseg6ei1024.v v4, (a0), v4
- - vsxseg6ei1024.v v0, (a0), v4, v0.t
- - vlxseg7ei1024.v v4, (a0), v4
- - vlxseg7ei1024.v v0, (a0), v4, v0.t
- - vsxseg7ei1024.v v4, (a0), v4
- - vsxseg7ei1024.v v0, (a0), v4, v0.t
- - vlxseg8ei1024.v v4, (a0), v4
- - vlxseg8ei1024.v v0, (a0), v4, v0.t
- - vsxseg8ei1024.v v4, (a0), v4
- - vsxseg8ei1024.v v0, (a0), v4, v0.t
- +# Vector Ordered Indexed Segment Loads and Stores
- +
- + vloxseg2ei8.v v4, (a0), v4 # vd overlap vs2
- + vloxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
- + vsoxseg2ei8.v v4, (a0), v4 # vd overlap vs2
- + vsoxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
- + vloxseg3ei8.v v4, (a0), v4
- + vloxseg3ei8.v v0, (a0), v4, v0.t
- + vsoxseg3ei8.v v4, (a0), v4
- + vsoxseg3ei8.v v0, (a0), v4, v0.t
- + vloxseg4ei8.v v4, (a0), v4
- + vloxseg4ei8.v v0, (a0), v4, v0.t
- + vsoxseg4ei8.v v4, (a0), v4
- + vsoxseg4ei8.v v0, (a0), v4, v0.t
- + vloxseg5ei8.v v4, (a0), v4
- + vloxseg5ei8.v v0, (a0), v4, v0.t
- + vsoxseg5ei8.v v4, (a0), v4
- + vsoxseg5ei8.v v0, (a0), v4, v0.t
- + vloxseg6ei8.v v4, (a0), v4
- + vloxseg6ei8.v v0, (a0), v4, v0.t
- + vsoxseg6ei8.v v4, (a0), v4
- + vsoxseg6ei8.v v0, (a0), v4, v0.t
- + vloxseg7ei8.v v4, (a0), v4
- + vloxseg7ei8.v v0, (a0), v4, v0.t
- + vsoxseg7ei8.v v4, (a0), v4
- + vsoxseg7ei8.v v0, (a0), v4, v0.t
- + vloxseg8ei8.v v4, (a0), v4
- + vloxseg8ei8.v v0, (a0), v4, v0.t
- + vsoxseg8ei8.v v4, (a0), v4
- + vsoxseg8ei8.v v0, (a0), v4, v0.t
- +
- + vloxseg2ei16.v v4, (a0), v4
- + vloxseg2ei16.v v0, (a0), v4, v0.t
- + vsoxseg2ei16.v v4, (a0), v4
- + vsoxseg2ei16.v v0, (a0), v4, v0.t
- + vloxseg3ei16.v v4, (a0), v4
- + vloxseg3ei16.v v0, (a0), v4, v0.t
- + vsoxseg3ei16.v v4, (a0), v4
- + vsoxseg3ei16.v v0, (a0), v4, v0.t
- + vloxseg4ei16.v v4, (a0), v4
- + vloxseg4ei16.v v0, (a0), v4, v0.t
- + vsoxseg4ei16.v v4, (a0), v4
- + vsoxseg4ei16.v v0, (a0), v4, v0.t
- + vloxseg5ei16.v v4, (a0), v4
- + vloxseg5ei16.v v0, (a0), v4, v0.t
- + vsoxseg5ei16.v v4, (a0), v4
- + vsoxseg5ei16.v v0, (a0), v4, v0.t
- + vloxseg6ei16.v v4, (a0), v4
- + vloxseg6ei16.v v0, (a0), v4, v0.t
- + vsoxseg6ei16.v v4, (a0), v4
- + vsoxseg6ei16.v v0, (a0), v4, v0.t
- + vloxseg7ei16.v v4, (a0), v4
- + vloxseg7ei16.v v0, (a0), v4, v0.t
- + vsoxseg7ei16.v v4, (a0), v4
- + vsoxseg7ei16.v v0, (a0), v4, v0.t
- + vloxseg8ei16.v v4, (a0), v4
- + vloxseg8ei16.v v0, (a0), v4, v0.t
- + vsoxseg8ei16.v v4, (a0), v4
- + vsoxseg8ei16.v v0, (a0), v4, v0.t
- +
- + vloxseg2ei32.v v4, (a0), v4
- + vloxseg2ei32.v v0, (a0), v4, v0.t
- + vsoxseg2ei32.v v4, (a0), v4
- + vsoxseg2ei32.v v0, (a0), v4, v0.t
- + vloxseg3ei32.v v4, (a0), v4
- + vloxseg3ei32.v v0, (a0), v4, v0.t
- + vsoxseg3ei32.v v4, (a0), v4
- + vsoxseg3ei32.v v0, (a0), v4, v0.t
- + vloxseg4ei32.v v4, (a0), v4
- + vloxseg4ei32.v v0, (a0), v4, v0.t
- + vsoxseg4ei32.v v4, (a0), v4
- + vsoxseg4ei32.v v0, (a0), v4, v0.t
- + vloxseg5ei32.v v4, (a0), v4
- + vloxseg5ei32.v v0, (a0), v4, v0.t
- + vsoxseg5ei32.v v4, (a0), v4
- + vsoxseg5ei32.v v0, (a0), v4, v0.t
- + vloxseg6ei32.v v4, (a0), v4
- + vloxseg6ei32.v v0, (a0), v4, v0.t
- + vsoxseg6ei32.v v4, (a0), v4
- + vsoxseg6ei32.v v0, (a0), v4, v0.t
- + vloxseg7ei32.v v4, (a0), v4
- + vloxseg7ei32.v v0, (a0), v4, v0.t
- + vsoxseg7ei32.v v4, (a0), v4
- + vsoxseg7ei32.v v0, (a0), v4, v0.t
- + vloxseg8ei32.v v4, (a0), v4
- + vloxseg8ei32.v v0, (a0), v4, v0.t
- + vsoxseg8ei32.v v4, (a0), v4
- + vsoxseg8ei32.v v0, (a0), v4, v0.t
- +
- + vloxseg2ei64.v v4, (a0), v4
- + vloxseg2ei64.v v0, (a0), v4, v0.t
- + vsoxseg2ei64.v v4, (a0), v4
- + vsoxseg2ei64.v v0, (a0), v4, v0.t
- + vloxseg3ei64.v v4, (a0), v4
- + vloxseg3ei64.v v0, (a0), v4, v0.t
- + vsoxseg3ei64.v v4, (a0), v4
- + vsoxseg3ei64.v v0, (a0), v4, v0.t
- + vloxseg4ei64.v v4, (a0), v4
- + vloxseg4ei64.v v0, (a0), v4, v0.t
- + vsoxseg4ei64.v v4, (a0), v4
- + vsoxseg4ei64.v v0, (a0), v4, v0.t
- + vloxseg5ei64.v v4, (a0), v4
- + vloxseg5ei64.v v0, (a0), v4, v0.t
- + vsoxseg5ei64.v v4, (a0), v4
- + vsoxseg5ei64.v v0, (a0), v4, v0.t
- + vloxseg6ei64.v v4, (a0), v4
- + vloxseg6ei64.v v0, (a0), v4, v0.t
- + vsoxseg6ei64.v v4, (a0), v4
- + vsoxseg6ei64.v v0, (a0), v4, v0.t
- + vloxseg7ei64.v v4, (a0), v4
- + vloxseg7ei64.v v0, (a0), v4, v0.t
- + vsoxseg7ei64.v v4, (a0), v4
- + vsoxseg7ei64.v v0, (a0), v4, v0.t
- + vloxseg8ei64.v v4, (a0), v4
- + vloxseg8ei64.v v0, (a0), v4, v0.t
- + vsoxseg8ei64.v v4, (a0), v4
- + vsoxseg8ei64.v v0, (a0), v4, v0.t
- +
- + vloxseg2ei128.v v4, (a0), v4
- + vloxseg2ei128.v v0, (a0), v4, v0.t
- + vsoxseg2ei128.v v4, (a0), v4
- + vsoxseg2ei128.v v0, (a0), v4, v0.t
- + vloxseg3ei128.v v4, (a0), v4
- + vloxseg3ei128.v v0, (a0), v4, v0.t
- + vsoxseg3ei128.v v4, (a0), v4
- + vsoxseg3ei128.v v0, (a0), v4, v0.t
- + vloxseg4ei128.v v4, (a0), v4
- + vloxseg4ei128.v v0, (a0), v4, v0.t
- + vsoxseg4ei128.v v4, (a0), v4
- + vsoxseg4ei128.v v0, (a0), v4, v0.t
- + vloxseg5ei128.v v4, (a0), v4
- + vloxseg5ei128.v v0, (a0), v4, v0.t
- + vsoxseg5ei128.v v4, (a0), v4
- + vsoxseg5ei128.v v0, (a0), v4, v0.t
- + vloxseg6ei128.v v4, (a0), v4
- + vloxseg6ei128.v v0, (a0), v4, v0.t
- + vsoxseg6ei128.v v4, (a0), v4
- + vsoxseg6ei128.v v0, (a0), v4, v0.t
- + vloxseg7ei128.v v4, (a0), v4
- + vloxseg7ei128.v v0, (a0), v4, v0.t
- + vsoxseg7ei128.v v4, (a0), v4
- + vsoxseg7ei128.v v0, (a0), v4, v0.t
- + vloxseg8ei128.v v4, (a0), v4
- + vloxseg8ei128.v v0, (a0), v4, v0.t
- + vsoxseg8ei128.v v4, (a0), v4
- + vsoxseg8ei128.v v0, (a0), v4, v0.t
- +
- + vloxseg2ei256.v v4, (a0), v4
- + vloxseg2ei256.v v0, (a0), v4, v0.t
- + vsoxseg2ei256.v v4, (a0), v4
- + vsoxseg2ei256.v v0, (a0), v4, v0.t
- + vloxseg3ei256.v v4, (a0), v4
- + vloxseg3ei256.v v0, (a0), v4, v0.t
- + vsoxseg3ei256.v v4, (a0), v4
- + vsoxseg3ei256.v v0, (a0), v4, v0.t
- + vloxseg4ei256.v v4, (a0), v4
- + vloxseg4ei256.v v0, (a0), v4, v0.t
- + vsoxseg4ei256.v v4, (a0), v4
- + vsoxseg4ei256.v v0, (a0), v4, v0.t
- + vloxseg5ei256.v v4, (a0), v4
- + vloxseg5ei256.v v0, (a0), v4, v0.t
- + vsoxseg5ei256.v v4, (a0), v4
- + vsoxseg5ei256.v v0, (a0), v4, v0.t
- + vloxseg6ei256.v v4, (a0), v4
- + vloxseg6ei256.v v0, (a0), v4, v0.t
- + vsoxseg6ei256.v v4, (a0), v4
- + vsoxseg6ei256.v v0, (a0), v4, v0.t
- + vloxseg7ei256.v v4, (a0), v4
- + vloxseg7ei256.v v0, (a0), v4, v0.t
- + vsoxseg7ei256.v v4, (a0), v4
- + vsoxseg7ei256.v v0, (a0), v4, v0.t
- + vloxseg8ei256.v v4, (a0), v4
- + vloxseg8ei256.v v0, (a0), v4, v0.t
- + vsoxseg8ei256.v v4, (a0), v4
- + vsoxseg8ei256.v v0, (a0), v4, v0.t
- +
- + vloxseg2ei512.v v4, (a0), v4
- + vloxseg2ei512.v v0, (a0), v4, v0.t
- + vsoxseg2ei512.v v4, (a0), v4
- + vsoxseg2ei512.v v0, (a0), v4, v0.t
- + vloxseg3ei512.v v4, (a0), v4
- + vloxseg3ei512.v v0, (a0), v4, v0.t
- + vsoxseg3ei512.v v4, (a0), v4
- + vsoxseg3ei512.v v0, (a0), v4, v0.t
- + vloxseg4ei512.v v4, (a0), v4
- + vloxseg4ei512.v v0, (a0), v4, v0.t
- + vsoxseg4ei512.v v4, (a0), v4
- + vsoxseg4ei512.v v0, (a0), v4, v0.t
- + vloxseg5ei512.v v4, (a0), v4
- + vloxseg5ei512.v v0, (a0), v4, v0.t
- + vsoxseg5ei512.v v4, (a0), v4
- + vsoxseg5ei512.v v0, (a0), v4, v0.t
- + vloxseg6ei512.v v4, (a0), v4
- + vloxseg6ei512.v v0, (a0), v4, v0.t
- + vsoxseg6ei512.v v4, (a0), v4
- + vsoxseg6ei512.v v0, (a0), v4, v0.t
- + vloxseg7ei512.v v4, (a0), v4
- + vloxseg7ei512.v v0, (a0), v4, v0.t
- + vsoxseg7ei512.v v4, (a0), v4
- + vsoxseg7ei512.v v0, (a0), v4, v0.t
- + vloxseg8ei512.v v4, (a0), v4
- + vloxseg8ei512.v v0, (a0), v4, v0.t
- + vsoxseg8ei512.v v4, (a0), v4
- + vsoxseg8ei512.v v0, (a0), v4, v0.t
- +
- + vloxseg2ei1024.v v4, (a0), v4
- + vloxseg2ei1024.v v0, (a0), v4, v0.t
- + vsoxseg2ei1024.v v4, (a0), v4
- + vsoxseg2ei1024.v v0, (a0), v4, v0.t
- + vloxseg3ei1024.v v4, (a0), v4
- + vloxseg3ei1024.v v0, (a0), v4, v0.t
- + vsoxseg3ei1024.v v4, (a0), v4
- + vsoxseg3ei1024.v v0, (a0), v4, v0.t
- + vloxseg4ei1024.v v4, (a0), v4
- + vloxseg4ei1024.v v0, (a0), v4, v0.t
- + vsoxseg4ei1024.v v4, (a0), v4
- + vsoxseg4ei1024.v v0, (a0), v4, v0.t
- + vloxseg5ei1024.v v4, (a0), v4
- + vloxseg5ei1024.v v0, (a0), v4, v0.t
- + vsoxseg5ei1024.v v4, (a0), v4
- + vsoxseg5ei1024.v v0, (a0), v4, v0.t
- + vloxseg6ei1024.v v4, (a0), v4
- + vloxseg6ei1024.v v0, (a0), v4, v0.t
- + vsoxseg6ei1024.v v4, (a0), v4
- + vsoxseg6ei1024.v v0, (a0), v4, v0.t
- + vloxseg7ei1024.v v4, (a0), v4
- + vloxseg7ei1024.v v0, (a0), v4, v0.t
- + vsoxseg7ei1024.v v4, (a0), v4
- + vsoxseg7ei1024.v v0, (a0), v4, v0.t
- + vloxseg8ei1024.v v4, (a0), v4
- + vloxseg8ei1024.v v0, (a0), v4, v0.t
- + vsoxseg8ei1024.v v4, (a0), v4
- + vsoxseg8ei1024.v v0, (a0), v4, v0.t
- +
- +# Vector Unordered Indexed Segment Loads and Stores
- +
- + vluxseg2ei8.v v4, (a0), v4 # vd overlap vs2
- + vluxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
- + vsuxseg2ei8.v v4, (a0), v4 # vd overlap vs2
- + vsuxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
- + vluxseg3ei8.v v4, (a0), v4
- + vluxseg3ei8.v v0, (a0), v4, v0.t
- + vsuxseg3ei8.v v4, (a0), v4
- + vsuxseg3ei8.v v0, (a0), v4, v0.t
- + vluxseg4ei8.v v4, (a0), v4
- + vluxseg4ei8.v v0, (a0), v4, v0.t
- + vsuxseg4ei8.v v4, (a0), v4
- + vsuxseg4ei8.v v0, (a0), v4, v0.t
- + vluxseg5ei8.v v4, (a0), v4
- + vluxseg5ei8.v v0, (a0), v4, v0.t
- + vsuxseg5ei8.v v4, (a0), v4
- + vsuxseg5ei8.v v0, (a0), v4, v0.t
- + vluxseg6ei8.v v4, (a0), v4
- + vluxseg6ei8.v v0, (a0), v4, v0.t
- + vsuxseg6ei8.v v4, (a0), v4
- + vsuxseg6ei8.v v0, (a0), v4, v0.t
- + vluxseg7ei8.v v4, (a0), v4
- + vluxseg7ei8.v v0, (a0), v4, v0.t
- + vsuxseg7ei8.v v4, (a0), v4
- + vsuxseg7ei8.v v0, (a0), v4, v0.t
- + vluxseg8ei8.v v4, (a0), v4
- + vluxseg8ei8.v v0, (a0), v4, v0.t
- + vsuxseg8ei8.v v4, (a0), v4
- + vsuxseg8ei8.v v0, (a0), v4, v0.t
- +
- + vluxseg2ei16.v v4, (a0), v4
- + vluxseg2ei16.v v0, (a0), v4, v0.t
- + vsuxseg2ei16.v v4, (a0), v4
- + vsuxseg2ei16.v v0, (a0), v4, v0.t
- + vluxseg3ei16.v v4, (a0), v4
- + vluxseg3ei16.v v0, (a0), v4, v0.t
- + vsuxseg3ei16.v v4, (a0), v4
- + vsuxseg3ei16.v v0, (a0), v4, v0.t
- + vluxseg4ei16.v v4, (a0), v4
- + vluxseg4ei16.v v0, (a0), v4, v0.t
- + vsuxseg4ei16.v v4, (a0), v4
- + vsuxseg4ei16.v v0, (a0), v4, v0.t
- + vluxseg5ei16.v v4, (a0), v4
- + vluxseg5ei16.v v0, (a0), v4, v0.t
- + vsuxseg5ei16.v v4, (a0), v4
- + vsuxseg5ei16.v v0, (a0), v4, v0.t
- + vluxseg6ei16.v v4, (a0), v4
- + vluxseg6ei16.v v0, (a0), v4, v0.t
- + vsuxseg6ei16.v v4, (a0), v4
- + vsuxseg6ei16.v v0, (a0), v4, v0.t
- + vluxseg7ei16.v v4, (a0), v4
- + vluxseg7ei16.v v0, (a0), v4, v0.t
- + vsuxseg7ei16.v v4, (a0), v4
- + vsuxseg7ei16.v v0, (a0), v4, v0.t
- + vluxseg8ei16.v v4, (a0), v4
- + vluxseg8ei16.v v0, (a0), v4, v0.t
- + vsuxseg8ei16.v v4, (a0), v4
- + vsuxseg8ei16.v v0, (a0), v4, v0.t
- +
- + vluxseg2ei32.v v4, (a0), v4
- + vluxseg2ei32.v v0, (a0), v4, v0.t
- + vsuxseg2ei32.v v4, (a0), v4
- + vsuxseg2ei32.v v0, (a0), v4, v0.t
- + vluxseg3ei32.v v4, (a0), v4
- + vluxseg3ei32.v v0, (a0), v4, v0.t
- + vsuxseg3ei32.v v4, (a0), v4
- + vsuxseg3ei32.v v0, (a0), v4, v0.t
- + vluxseg4ei32.v v4, (a0), v4
- + vluxseg4ei32.v v0, (a0), v4, v0.t
- + vsuxseg4ei32.v v4, (a0), v4
- + vsuxseg4ei32.v v0, (a0), v4, v0.t
- + vluxseg5ei32.v v4, (a0), v4
- + vluxseg5ei32.v v0, (a0), v4, v0.t
- + vsuxseg5ei32.v v4, (a0), v4
- + vsuxseg5ei32.v v0, (a0), v4, v0.t
- + vluxseg6ei32.v v4, (a0), v4
- + vluxseg6ei32.v v0, (a0), v4, v0.t
- + vsuxseg6ei32.v v4, (a0), v4
- + vsuxseg6ei32.v v0, (a0), v4, v0.t
- + vluxseg7ei32.v v4, (a0), v4
- + vluxseg7ei32.v v0, (a0), v4, v0.t
- + vsuxseg7ei32.v v4, (a0), v4
- + vsuxseg7ei32.v v0, (a0), v4, v0.t
- + vluxseg8ei32.v v4, (a0), v4
- + vluxseg8ei32.v v0, (a0), v4, v0.t
- + vsuxseg8ei32.v v4, (a0), v4
- + vsuxseg8ei32.v v0, (a0), v4, v0.t
- +
- + vluxseg2ei64.v v4, (a0), v4
- + vluxseg2ei64.v v0, (a0), v4, v0.t
- + vsuxseg2ei64.v v4, (a0), v4
- + vsuxseg2ei64.v v0, (a0), v4, v0.t
- + vluxseg3ei64.v v4, (a0), v4
- + vluxseg3ei64.v v0, (a0), v4, v0.t
- + vsuxseg3ei64.v v4, (a0), v4
- + vsuxseg3ei64.v v0, (a0), v4, v0.t
- + vluxseg4ei64.v v4, (a0), v4
- + vluxseg4ei64.v v0, (a0), v4, v0.t
- + vsuxseg4ei64.v v4, (a0), v4
- + vsuxseg4ei64.v v0, (a0), v4, v0.t
- + vluxseg5ei64.v v4, (a0), v4
- + vluxseg5ei64.v v0, (a0), v4, v0.t
- + vsuxseg5ei64.v v4, (a0), v4
- + vsuxseg5ei64.v v0, (a0), v4, v0.t
- + vluxseg6ei64.v v4, (a0), v4
- + vluxseg6ei64.v v0, (a0), v4, v0.t
- + vsuxseg6ei64.v v4, (a0), v4
- + vsuxseg6ei64.v v0, (a0), v4, v0.t
- + vluxseg7ei64.v v4, (a0), v4
- + vluxseg7ei64.v v0, (a0), v4, v0.t
- + vsuxseg7ei64.v v4, (a0), v4
- + vsuxseg7ei64.v v0, (a0), v4, v0.t
- + vluxseg8ei64.v v4, (a0), v4
- + vluxseg8ei64.v v0, (a0), v4, v0.t
- + vsuxseg8ei64.v v4, (a0), v4
- + vsuxseg8ei64.v v0, (a0), v4, v0.t
- +
- + vluxseg2ei128.v v4, (a0), v4
- + vluxseg2ei128.v v0, (a0), v4, v0.t
- + vsuxseg2ei128.v v4, (a0), v4
- + vsuxseg2ei128.v v0, (a0), v4, v0.t
- + vluxseg3ei128.v v4, (a0), v4
- + vluxseg3ei128.v v0, (a0), v4, v0.t
- + vsuxseg3ei128.v v4, (a0), v4
- + vsuxseg3ei128.v v0, (a0), v4, v0.t
- + vluxseg4ei128.v v4, (a0), v4
- + vluxseg4ei128.v v0, (a0), v4, v0.t
- + vsuxseg4ei128.v v4, (a0), v4
- + vsuxseg4ei128.v v0, (a0), v4, v0.t
- + vluxseg5ei128.v v4, (a0), v4
- + vluxseg5ei128.v v0, (a0), v4, v0.t
- + vsuxseg5ei128.v v4, (a0), v4
- + vsuxseg5ei128.v v0, (a0), v4, v0.t
- + vluxseg6ei128.v v4, (a0), v4
- + vluxseg6ei128.v v0, (a0), v4, v0.t
- + vsuxseg6ei128.v v4, (a0), v4
- + vsuxseg6ei128.v v0, (a0), v4, v0.t
- + vluxseg7ei128.v v4, (a0), v4
- + vluxseg7ei128.v v0, (a0), v4, v0.t
- + vsuxseg7ei128.v v4, (a0), v4
- + vsuxseg7ei128.v v0, (a0), v4, v0.t
- + vluxseg8ei128.v v4, (a0), v4
- + vluxseg8ei128.v v0, (a0), v4, v0.t
- + vsuxseg8ei128.v v4, (a0), v4
- + vsuxseg8ei128.v v0, (a0), v4, v0.t
- +
- + vluxseg2ei256.v v4, (a0), v4
- + vluxseg2ei256.v v0, (a0), v4, v0.t
- + vsuxseg2ei256.v v4, (a0), v4
- + vsuxseg2ei256.v v0, (a0), v4, v0.t
- + vluxseg3ei256.v v4, (a0), v4
- + vluxseg3ei256.v v0, (a0), v4, v0.t
- + vsuxseg3ei256.v v4, (a0), v4
- + vsuxseg3ei256.v v0, (a0), v4, v0.t
- + vluxseg4ei256.v v4, (a0), v4
- + vluxseg4ei256.v v0, (a0), v4, v0.t
- + vsuxseg4ei256.v v4, (a0), v4
- + vsuxseg4ei256.v v0, (a0), v4, v0.t
- + vluxseg5ei256.v v4, (a0), v4
- + vluxseg5ei256.v v0, (a0), v4, v0.t
- + vsuxseg5ei256.v v4, (a0), v4
- + vsuxseg5ei256.v v0, (a0), v4, v0.t
- + vluxseg6ei256.v v4, (a0), v4
- + vluxseg6ei256.v v0, (a0), v4, v0.t
- + vsuxseg6ei256.v v4, (a0), v4
- + vsuxseg6ei256.v v0, (a0), v4, v0.t
- + vluxseg7ei256.v v4, (a0), v4
- + vluxseg7ei256.v v0, (a0), v4, v0.t
- + vsuxseg7ei256.v v4, (a0), v4
- + vsuxseg7ei256.v v0, (a0), v4, v0.t
- + vluxseg8ei256.v v4, (a0), v4
- + vluxseg8ei256.v v0, (a0), v4, v0.t
- + vsuxseg8ei256.v v4, (a0), v4
- + vsuxseg8ei256.v v0, (a0), v4, v0.t
- +
- + vluxseg2ei512.v v4, (a0), v4
- + vluxseg2ei512.v v0, (a0), v4, v0.t
- + vsuxseg2ei512.v v4, (a0), v4
- + vsuxseg2ei512.v v0, (a0), v4, v0.t
- + vluxseg3ei512.v v4, (a0), v4
- + vluxseg3ei512.v v0, (a0), v4, v0.t
- + vsuxseg3ei512.v v4, (a0), v4
- + vsuxseg3ei512.v v0, (a0), v4, v0.t
- + vluxseg4ei512.v v4, (a0), v4
- + vluxseg4ei512.v v0, (a0), v4, v0.t
- + vsuxseg4ei512.v v4, (a0), v4
- + vsuxseg4ei512.v v0, (a0), v4, v0.t
- + vluxseg5ei512.v v4, (a0), v4
- + vluxseg5ei512.v v0, (a0), v4, v0.t
- + vsuxseg5ei512.v v4, (a0), v4
- + vsuxseg5ei512.v v0, (a0), v4, v0.t
- + vluxseg6ei512.v v4, (a0), v4
- + vluxseg6ei512.v v0, (a0), v4, v0.t
- + vsuxseg6ei512.v v4, (a0), v4
- + vsuxseg6ei512.v v0, (a0), v4, v0.t
- + vluxseg7ei512.v v4, (a0), v4
- + vluxseg7ei512.v v0, (a0), v4, v0.t
- + vsuxseg7ei512.v v4, (a0), v4
- + vsuxseg7ei512.v v0, (a0), v4, v0.t
- + vluxseg8ei512.v v4, (a0), v4
- + vluxseg8ei512.v v0, (a0), v4, v0.t
- + vsuxseg8ei512.v v4, (a0), v4
- + vsuxseg8ei512.v v0, (a0), v4, v0.t
- +
- + vluxseg2ei1024.v v4, (a0), v4
- + vluxseg2ei1024.v v0, (a0), v4, v0.t
- + vsuxseg2ei1024.v v4, (a0), v4
- + vsuxseg2ei1024.v v0, (a0), v4, v0.t
- + vluxseg3ei1024.v v4, (a0), v4
- + vluxseg3ei1024.v v0, (a0), v4, v0.t
- + vsuxseg3ei1024.v v4, (a0), v4
- + vsuxseg3ei1024.v v0, (a0), v4, v0.t
- + vluxseg4ei1024.v v4, (a0), v4
- + vluxseg4ei1024.v v0, (a0), v4, v0.t
- + vsuxseg4ei1024.v v4, (a0), v4
- + vsuxseg4ei1024.v v0, (a0), v4, v0.t
- + vluxseg5ei1024.v v4, (a0), v4
- + vluxseg5ei1024.v v0, (a0), v4, v0.t
- + vsuxseg5ei1024.v v4, (a0), v4
- + vsuxseg5ei1024.v v0, (a0), v4, v0.t
- + vluxseg6ei1024.v v4, (a0), v4
- + vluxseg6ei1024.v v0, (a0), v4, v0.t
- + vsuxseg6ei1024.v v4, (a0), v4
- + vsuxseg6ei1024.v v0, (a0), v4, v0.t
- + vluxseg7ei1024.v v4, (a0), v4
- + vluxseg7ei1024.v v0, (a0), v4, v0.t
- + vsuxseg7ei1024.v v4, (a0), v4
- + vsuxseg7ei1024.v v0, (a0), v4, v0.t
- + vluxseg8ei1024.v v4, (a0), v4
- + vluxseg8ei1024.v v0, (a0), v4, v0.t
- + vsuxseg8ei1024.v v4, (a0), v4
- + vsuxseg8ei1024.v v0, (a0), v4, v0.t
-
- # Vector Load/Store Whole Register Instructions
-
- diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
- index 29a38b3716..d8a8aa6d09 100644
- --- a/gas/testsuite/gas/riscv/vector-insns.d
- +++ b/gas/testsuite/gas/riscv/vector-insns.d
- @@ -122,39 +122,51 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+1ab57227[ ]+vsse1024.v[ ]+v4,\(a0\),a1
- [ ]+[0-9a-f]+:[ ]+1ab57227[ ]+vsse1024.v[ ]+v4,\(a0\),a1
- [ ]+[0-9a-f]+:[ ]+18b57227[ ]+vsse1024.v[ ]+v4,\(a0\),a1,v0.t
- -[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vlxei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vlxei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0cc50207[ ]+vlxei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+vsxei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+vsxei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0cc50227[ ]+vsxei8.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vloxei8.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vloxei8.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0cc50207[ ]+vloxei8.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+vsoxei8.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+vsoxei8.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0cc50227[ ]+vsoxei8.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+06c50207[ ]+vluxei8.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+06c50207[ ]+vluxei8.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+04c50207[ ]+vluxei8.v[ ]+v4,\(a0\),v12,v0.t
- [ ]+[0-9a-f]+:[ ]+06c50227[ ]+vsuxei8.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+06c50227[ ]+vsuxei8.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+04c50227[ ]+vsuxei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+vlxei16.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+vlxei16.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0cc55207[ ]+vlxei16.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+0ec55227[ ]+vsxei16.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0ec55227[ ]+vsxei16.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0cc55227[ ]+vsxei16.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+vloxei16.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+vloxei16.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0cc55207[ ]+vloxei16.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+0ec55227[ ]+vsoxei16.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0ec55227[ ]+vsoxei16.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0cc55227[ ]+vsoxei16.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+06c55207[ ]+vluxei16.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+06c55207[ ]+vluxei16.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+04c55207[ ]+vluxei16.v[ ]+v4,\(a0\),v12,v0.t
- [ ]+[0-9a-f]+:[ ]+06c55227[ ]+vsuxei16.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+06c55227[ ]+vsuxei16.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+04c55227[ ]+vsuxei16.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+0ec56207[ ]+vlxei32.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0ec56207[ ]+vlxei32.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0cc56207[ ]+vlxei32.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+0ec56227[ ]+vsxei32.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0ec56227[ ]+vsxei32.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0cc56227[ ]+vsxei32.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+0ec56207[ ]+vloxei32.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0ec56207[ ]+vloxei32.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0cc56207[ ]+vloxei32.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+0ec56227[ ]+vsoxei32.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0ec56227[ ]+vsoxei32.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0cc56227[ ]+vsoxei32.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+06c56207[ ]+vluxei32.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+06c56207[ ]+vluxei32.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+04c56207[ ]+vluxei32.v[ ]+v4,\(a0\),v12,v0.t
- [ ]+[0-9a-f]+:[ ]+06c56227[ ]+vsuxei32.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+06c56227[ ]+vsuxei32.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+04c56227[ ]+vsuxei32.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+vlxei64.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+vlxei64.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0cc57207[ ]+vlxei64.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsxei64.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsxei64.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+0cc57227[ ]+vsxei64.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+vloxei64.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+vloxei64.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0cc57207[ ]+vloxei64.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+0cc57227[ ]+vsoxei64.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+06c57207[ ]+vluxei64.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+06c57207[ ]+vluxei64.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+04c57207[ ]+vluxei64.v[ ]+v4,\(a0\),v12,v0.t
- [ ]+[0-9a-f]+:[ ]+06c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+06c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12
- [ ]+[0-9a-f]+:[ ]+04c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12,v0.t
- @@ -854,342 +866,678 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+fab57227[ ]+vssseg8e1024.v[ ]+v4,\(a0\),a1
- [ ]+[0-9a-f]+:[ ]+fab57227[ ]+vssseg8e1024.v[ ]+v4,\(a0\),a1
- [ ]+[0-9a-f]+:[ ]+f8b57227[ ]+vssseg8e1024.v[ ]+v4,\(a0\),a1,v0.t
- -[ ]+[0-9a-f]+:[ ]+2ec50207[ ]+vlxseg2ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+2ec50207[ ]+vlxseg2ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+2cc50207[ ]+vlxseg2ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+2ec50227[ ]+vsxseg2ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+2ec50227[ ]+vsxseg2ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+2cc50227[ ]+vsxseg2ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+4ec50207[ ]+vlxseg3ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+4ec50207[ ]+vlxseg3ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+4cc50207[ ]+vlxseg3ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+4ec50227[ ]+vsxseg3ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+4ec50227[ ]+vsxseg3ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+4cc50227[ ]+vsxseg3ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+6ec50207[ ]+vlxseg4ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+6ec50207[ ]+vlxseg4ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+6cc50207[ ]+vlxseg4ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+6ec50227[ ]+vsxseg4ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+6ec50227[ ]+vsxseg4ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+6cc50227[ ]+vsxseg4ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+8ec50207[ ]+vlxseg5ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+8ec50207[ ]+vlxseg5ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+8cc50207[ ]+vlxseg5ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+8ec50227[ ]+vsxseg5ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+8ec50227[ ]+vsxseg5ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+8cc50227[ ]+vsxseg5ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+aec50207[ ]+vlxseg6ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+aec50207[ ]+vlxseg6ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+acc50207[ ]+vlxseg6ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+aec50227[ ]+vsxseg6ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+aec50227[ ]+vsxseg6ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+acc50227[ ]+vsxseg6ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+cec50207[ ]+vlxseg7ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+cec50207[ ]+vlxseg7ei8.v[ ]+v4,\(a0\),v12
- -[ ]+[0-9a-f]+:[ ]+ccc50207[ ]+vlxseg7ei8.v[ ]+v4,\(a0\),v12,v0.t
- -[ ]+[0-9a-f]+:[ ]+cec50227[ ]+vsxseg7ei8.v[ ]+v4,\(a0\),v12
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- +[ ]+[0-9a-f]+:[ ]+56c55207[ ]+vluxseg3ei256.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+56c55207[ ]+vluxseg3ei256.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+54c55207[ ]+vluxseg3ei256.v[ ]+v4,\(a0\),v12,v0.t
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- +[ ]+[0-9a-f]+:[ ]+b6c55207[ ]+vluxseg6ei256.v[ ]+v4,\(a0\),v12
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- +[ ]+[0-9a-f]+:[ ]+d6c55207[ ]+vluxseg7ei256.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d4c55207[ ]+vluxseg7ei256.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+d6c55227[ ]+vsuxseg7ei256.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d6c55227[ ]+vsuxseg7ei256.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d4c55227[ ]+vsuxseg7ei256.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+f6c55207[ ]+vluxseg8ei256.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f6c55207[ ]+vluxseg8ei256.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f4c55207[ ]+vluxseg8ei256.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+f6c55227[ ]+vsuxseg8ei256.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f6c55227[ ]+vsuxseg8ei256.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f4c55227[ ]+vsuxseg8ei256.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+36c56207[ ]+vluxseg2ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+36c56207[ ]+vluxseg2ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+34c56207[ ]+vluxseg2ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+36c56227[ ]+vsuxseg2ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+36c56227[ ]+vsuxseg2ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+34c56227[ ]+vsuxseg2ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+56c56207[ ]+vluxseg3ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+56c56207[ ]+vluxseg3ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+54c56207[ ]+vluxseg3ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+56c56227[ ]+vsuxseg3ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+56c56227[ ]+vsuxseg3ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+54c56227[ ]+vsuxseg3ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+76c56207[ ]+vluxseg4ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+76c56207[ ]+vluxseg4ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+74c56207[ ]+vluxseg4ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+76c56227[ ]+vsuxseg4ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+76c56227[ ]+vsuxseg4ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+74c56227[ ]+vsuxseg4ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+96c56207[ ]+vluxseg5ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+96c56207[ ]+vluxseg5ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+94c56207[ ]+vluxseg5ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+96c56227[ ]+vsuxseg5ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+96c56227[ ]+vsuxseg5ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+94c56227[ ]+vsuxseg5ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+b6c56207[ ]+vluxseg6ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+b6c56207[ ]+vluxseg6ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+b4c56207[ ]+vluxseg6ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+b6c56227[ ]+vsuxseg6ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+b6c56227[ ]+vsuxseg6ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+b4c56227[ ]+vsuxseg6ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+d6c56207[ ]+vluxseg7ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d6c56207[ ]+vluxseg7ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d4c56207[ ]+vluxseg7ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+d6c56227[ ]+vsuxseg7ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d6c56227[ ]+vsuxseg7ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d4c56227[ ]+vsuxseg7ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+f6c56207[ ]+vluxseg8ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f6c56207[ ]+vluxseg8ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f4c56207[ ]+vluxseg8ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+f6c56227[ ]+vsuxseg8ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f6c56227[ ]+vsuxseg8ei512.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f4c56227[ ]+vsuxseg8ei512.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+36c57207[ ]+vluxseg2ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+36c57207[ ]+vluxseg2ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+34c57207[ ]+vluxseg2ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+36c57227[ ]+vsuxseg2ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+36c57227[ ]+vsuxseg2ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+34c57227[ ]+vsuxseg2ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+56c57207[ ]+vluxseg3ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+56c57207[ ]+vluxseg3ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+54c57207[ ]+vluxseg3ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+56c57227[ ]+vsuxseg3ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+56c57227[ ]+vsuxseg3ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+54c57227[ ]+vsuxseg3ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+76c57207[ ]+vluxseg4ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+76c57207[ ]+vluxseg4ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+74c57207[ ]+vluxseg4ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+76c57227[ ]+vsuxseg4ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+76c57227[ ]+vsuxseg4ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+74c57227[ ]+vsuxseg4ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+96c57207[ ]+vluxseg5ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+96c57207[ ]+vluxseg5ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+94c57207[ ]+vluxseg5ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+96c57227[ ]+vsuxseg5ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+96c57227[ ]+vsuxseg5ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+94c57227[ ]+vsuxseg5ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+b6c57207[ ]+vluxseg6ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+b6c57207[ ]+vluxseg6ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+b4c57207[ ]+vluxseg6ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+b6c57227[ ]+vsuxseg6ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+b6c57227[ ]+vsuxseg6ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+b4c57227[ ]+vsuxseg6ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+d6c57207[ ]+vluxseg7ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d6c57207[ ]+vluxseg7ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d4c57207[ ]+vluxseg7ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+d6c57227[ ]+vsuxseg7ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d6c57227[ ]+vsuxseg7ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+d4c57227[ ]+vsuxseg7ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+f6c57207[ ]+vluxseg8ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f6c57207[ ]+vluxseg8ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f4c57207[ ]+vluxseg8ei1024.v[ ]+v4,\(a0\),v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+f6c57227[ ]+vsuxseg8ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f6c57227[ ]+vsuxseg8ei1024.v[ ]+v4,\(a0\),v12
- +[ ]+[0-9a-f]+:[ ]+f4c57227[ ]+vsuxseg8ei1024.v[ ]+v4,\(a0\),v12,v0.t
- [ ]+[0-9a-f]+:[ ]+23050207[ ]+vlseg2e8ff.v[ ]+v4,\(a0\)
- [ ]+[0-9a-f]+:[ ]+23050207[ ]+vlseg2e8ff.v[ ]+v4,\(a0\)
- [ ]+[0-9a-f]+:[ ]+21050207[ ]+vlseg2e8ff.v[ ]+v4,\(a0\),v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
- index b78604025a..5431863af9 100644
- --- a/gas/testsuite/gas/riscv/vector-insns.s
- +++ b/gas/testsuite/gas/riscv/vector-insns.s
- @@ -130,42 +130,54 @@
- vsse1024.v v4, 0(a0), a1
- vsse1024.v v4, (a0), a1, v0.t
-
- - vlxei8.v v4, (a0), v12
- - vlxei8.v v4, 0(a0), v12
- - vlxei8.v v4, (a0), v12, v0.t
- - vsxei8.v v4, (a0), v12
- - vsxei8.v v4, 0(a0), v12
- - vsxei8.v v4, (a0), v12, v0.t
- + vloxei8.v v4, (a0), v12
- + vloxei8.v v4, 0(a0), v12
- + vloxei8.v v4, (a0), v12, v0.t
- + vsoxei8.v v4, (a0), v12
- + vsoxei8.v v4, 0(a0), v12
- + vsoxei8.v v4, (a0), v12, v0.t
- + vluxei8.v v4, (a0), v12
- + vluxei8.v v4, 0(a0), v12
- + vluxei8.v v4, (a0), v12, v0.t
- vsuxei8.v v4, (a0), v12
- vsuxei8.v v4, 0(a0), v12
- vsuxei8.v v4, (a0), v12, v0.t
-
- - vlxei16.v v4, (a0), v12
- - vlxei16.v v4, 0(a0), v12
- - vlxei16.v v4, (a0), v12, v0.t
- - vsxei16.v v4, (a0), v12
- - vsxei16.v v4, 0(a0), v12
- - vsxei16.v v4, (a0), v12, v0.t
- + vloxei16.v v4, (a0), v12
- + vloxei16.v v4, 0(a0), v12
- + vloxei16.v v4, (a0), v12, v0.t
- + vsoxei16.v v4, (a0), v12
- + vsoxei16.v v4, 0(a0), v12
- + vsoxei16.v v4, (a0), v12, v0.t
- + vluxei16.v v4, (a0), v12
- + vluxei16.v v4, 0(a0), v12
- + vluxei16.v v4, (a0), v12, v0.t
- vsuxei16.v v4, (a0), v12
- vsuxei16.v v4, 0(a0), v12
- vsuxei16.v v4, (a0), v12, v0.t
-
- - vlxei32.v v4, (a0), v12
- - vlxei32.v v4, 0(a0), v12
- - vlxei32.v v4, (a0), v12, v0.t
- - vsxei32.v v4, (a0), v12
- - vsxei32.v v4, 0(a0), v12
- - vsxei32.v v4, (a0), v12, v0.t
- + vloxei32.v v4, (a0), v12
- + vloxei32.v v4, 0(a0), v12
- + vloxei32.v v4, (a0), v12, v0.t
- + vsoxei32.v v4, (a0), v12
- + vsoxei32.v v4, 0(a0), v12
- + vsoxei32.v v4, (a0), v12, v0.t
- + vluxei32.v v4, (a0), v12
- + vluxei32.v v4, 0(a0), v12
- + vluxei32.v v4, (a0), v12, v0.t
- vsuxei32.v v4, (a0), v12
- vsuxei32.v v4, 0(a0), v12
- vsuxei32.v v4, (a0), v12, v0.t
-
- - vlxei64.v v4, (a0), v12
- - vlxei64.v v4, 0(a0), v12
- - vlxei64.v v4, (a0), v12, v0.t
- - vsxei64.v v4, (a0), v12
- - vsxei64.v v4, 0(a0), v12
- - vsxei64.v v4, (a0), v12, v0.t
- + vloxei64.v v4, (a0), v12
- + vloxei64.v v4, 0(a0), v12
- + vloxei64.v v4, (a0), v12, v0.t
- + vsoxei64.v v4, (a0), v12
- + vsoxei64.v v4, 0(a0), v12
- + vsoxei64.v v4, (a0), v12, v0.t
- + vluxei64.v v4, (a0), v12
- + vluxei64.v v4, 0(a0), v12
- + vluxei64.v v4, (a0), v12, v0.t
- vsuxei64.v v4, (a0), v12
- vsuxei64.v v4, 0(a0), v12
- vsuxei64.v v4, (a0), v12, v0.t
- @@ -986,397 +998,789 @@
- vssseg8e1024.v v4, 0(a0), a1
- vssseg8e1024.v v4, (a0), a1, v0.t
-
- - vlxseg2ei8.v v4, (a0), v12
- - vlxseg2ei8.v v4, 0(a0), v12
- - vlxseg2ei8.v v4, (a0), v12, v0.t
- - vsxseg2ei8.v v4, (a0), v12
- - vsxseg2ei8.v v4, 0(a0), v12
- - vsxseg2ei8.v v4, (a0), v12, v0.t
- -
- - vlxseg3ei8.v v4, (a0), v12
- - vlxseg3ei8.v v4, 0(a0), v12
- - vlxseg3ei8.v v4, (a0), v12, v0.t
- - vsxseg3ei8.v v4, (a0), v12
- - vsxseg3ei8.v v4, 0(a0), v12
- - vsxseg3ei8.v v4, (a0), v12, v0.t
- -
- - vlxseg4ei8.v v4, (a0), v12
- - vlxseg4ei8.v v4, 0(a0), v12
- - vlxseg4ei8.v v4, (a0), v12, v0.t
- - vsxseg4ei8.v v4, (a0), v12
- - vsxseg4ei8.v v4, 0(a0), v12
- - vsxseg4ei8.v v4, (a0), v12, v0.t
- -
- - vlxseg5ei8.v v4, (a0), v12
- - vlxseg5ei8.v v4, 0(a0), v12
- - vlxseg5ei8.v v4, (a0), v12, v0.t
- - vsxseg5ei8.v v4, (a0), v12
- - vsxseg5ei8.v v4, 0(a0), v12
- - vsxseg5ei8.v v4, (a0), v12, v0.t
- -
- - vlxseg6ei8.v v4, (a0), v12
- - vlxseg6ei8.v v4, 0(a0), v12
- - vlxseg6ei8.v v4, (a0), v12, v0.t
- - vsxseg6ei8.v v4, (a0), v12
- - vsxseg6ei8.v v4, 0(a0), v12
- - vsxseg6ei8.v v4, (a0), v12, v0.t
- -
- - vlxseg7ei8.v v4, (a0), v12
- - vlxseg7ei8.v v4, 0(a0), v12
- - vlxseg7ei8.v v4, (a0), v12, v0.t
- - vsxseg7ei8.v v4, (a0), v12
- - vsxseg7ei8.v v4, 0(a0), v12
- - vsxseg7ei8.v v4, (a0), v12, v0.t
- -
- - vlxseg8ei8.v v4, (a0), v12
- - vlxseg8ei8.v v4, 0(a0), v12
- - vlxseg8ei8.v v4, (a0), v12, v0.t
- - vsxseg8ei8.v v4, (a0), v12
- - vsxseg8ei8.v v4, 0(a0), v12
- - vsxseg8ei8.v v4, (a0), v12, v0.t
- -
- - vlxseg2ei16.v v4, (a0), v12
- - vlxseg2ei16.v v4, 0(a0), v12
- - vlxseg2ei16.v v4, (a0), v12, v0.t
- - vsxseg2ei16.v v4, (a0), v12
- - vsxseg2ei16.v v4, 0(a0), v12
- - vsxseg2ei16.v v4, (a0), v12, v0.t
- -
- - vlxseg3ei16.v v4, (a0), v12
- - vlxseg3ei16.v v4, 0(a0), v12
- - vlxseg3ei16.v v4, (a0), v12, v0.t
- - vsxseg3ei16.v v4, (a0), v12
- - vsxseg3ei16.v v4, 0(a0), v12
- - vsxseg3ei16.v v4, (a0), v12, v0.t
- -
- - vlxseg4ei16.v v4, (a0), v12
- - vlxseg4ei16.v v4, 0(a0), v12
- - vlxseg4ei16.v v4, (a0), v12, v0.t
- - vsxseg4ei16.v v4, (a0), v12
- - vsxseg4ei16.v v4, 0(a0), v12
- - vsxseg4ei16.v v4, (a0), v12, v0.t
- -
- - vlxseg5ei16.v v4, (a0), v12
- - vlxseg5ei16.v v4, 0(a0), v12
- - vlxseg5ei16.v v4, (a0), v12, v0.t
- - vsxseg5ei16.v v4, (a0), v12
- - vsxseg5ei16.v v4, 0(a0), v12
- - vsxseg5ei16.v v4, (a0), v12, v0.t
- -
- - vlxseg6ei16.v v4, (a0), v12
- - vlxseg6ei16.v v4, 0(a0), v12
- - vlxseg6ei16.v v4, (a0), v12, v0.t
- - vsxseg6ei16.v v4, (a0), v12
- - vsxseg6ei16.v v4, 0(a0), v12
- - vsxseg6ei16.v v4, (a0), v12, v0.t
- -
- - vlxseg7ei16.v v4, (a0), v12
- - vlxseg7ei16.v v4, 0(a0), v12
- - vlxseg7ei16.v v4, (a0), v12, v0.t
- - vsxseg7ei16.v v4, (a0), v12
- - vsxseg7ei16.v v4, 0(a0), v12
- - vsxseg7ei16.v v4, (a0), v12, v0.t
- -
- - vlxseg8ei16.v v4, (a0), v12
- - vlxseg8ei16.v v4, 0(a0), v12
- - vlxseg8ei16.v v4, (a0), v12, v0.t
- - vsxseg8ei16.v v4, (a0), v12
- - vsxseg8ei16.v v4, 0(a0), v12
- - vsxseg8ei16.v v4, (a0), v12, v0.t
- -
- - vlxseg2ei32.v v4, (a0), v12
- - vlxseg2ei32.v v4, 0(a0), v12
- - vlxseg2ei32.v v4, (a0), v12, v0.t
- - vsxseg2ei32.v v4, (a0), v12
- - vsxseg2ei32.v v4, 0(a0), v12
- - vsxseg2ei32.v v4, (a0), v12, v0.t
- -
- - vlxseg3ei32.v v4, (a0), v12
- - vlxseg3ei32.v v4, 0(a0), v12
- - vlxseg3ei32.v v4, (a0), v12, v0.t
- - vsxseg3ei32.v v4, (a0), v12
- - vsxseg3ei32.v v4, 0(a0), v12
- - vsxseg3ei32.v v4, (a0), v12, v0.t
- -
- - vlxseg4ei32.v v4, (a0), v12
- - vlxseg4ei32.v v4, 0(a0), v12
- - vlxseg4ei32.v v4, (a0), v12, v0.t
- - vsxseg4ei32.v v4, (a0), v12
- - vsxseg4ei32.v v4, 0(a0), v12
- - vsxseg4ei32.v v4, (a0), v12, v0.t
- -
- - vlxseg5ei32.v v4, (a0), v12
- - vlxseg5ei32.v v4, 0(a0), v12
- - vlxseg5ei32.v v4, (a0), v12, v0.t
- - vsxseg5ei32.v v4, (a0), v12
- - vsxseg5ei32.v v4, 0(a0), v12
- - vsxseg5ei32.v v4, (a0), v12, v0.t
- -
- - vlxseg6ei32.v v4, (a0), v12
- - vlxseg6ei32.v v4, 0(a0), v12
- - vlxseg6ei32.v v4, (a0), v12, v0.t
- - vsxseg6ei32.v v4, (a0), v12
- - vsxseg6ei32.v v4, 0(a0), v12
- - vsxseg6ei32.v v4, (a0), v12, v0.t
- -
- - vlxseg7ei32.v v4, (a0), v12
- - vlxseg7ei32.v v4, 0(a0), v12
- - vlxseg7ei32.v v4, (a0), v12, v0.t
- - vsxseg7ei32.v v4, (a0), v12
- - vsxseg7ei32.v v4, 0(a0), v12
- - vsxseg7ei32.v v4, (a0), v12, v0.t
- -
- - vlxseg8ei32.v v4, (a0), v12
- - vlxseg8ei32.v v4, 0(a0), v12
- - vlxseg8ei32.v v4, (a0), v12, v0.t
- - vsxseg8ei32.v v4, (a0), v12
- - vsxseg8ei32.v v4, 0(a0), v12
- - vsxseg8ei32.v v4, (a0), v12, v0.t
- -
- - vlxseg2ei64.v v4, (a0), v12
- - vlxseg2ei64.v v4, 0(a0), v12
- - vlxseg2ei64.v v4, (a0), v12, v0.t
- - vsxseg2ei64.v v4, (a0), v12
- - vsxseg2ei64.v v4, 0(a0), v12
- - vsxseg2ei64.v v4, (a0), v12, v0.t
- -
- - vlxseg3ei64.v v4, (a0), v12
- - vlxseg3ei64.v v4, 0(a0), v12
- - vlxseg3ei64.v v4, (a0), v12, v0.t
- - vsxseg3ei64.v v4, (a0), v12
- - vsxseg3ei64.v v4, 0(a0), v12
- - vsxseg3ei64.v v4, (a0), v12, v0.t
- -
- - vlxseg4ei64.v v4, (a0), v12
- - vlxseg4ei64.v v4, 0(a0), v12
- - vlxseg4ei64.v v4, (a0), v12, v0.t
- - vsxseg4ei64.v v4, (a0), v12
- - vsxseg4ei64.v v4, 0(a0), v12
- - vsxseg4ei64.v v4, (a0), v12, v0.t
- -
- - vlxseg5ei64.v v4, (a0), v12
- - vlxseg5ei64.v v4, 0(a0), v12
- - vlxseg5ei64.v v4, (a0), v12, v0.t
- - vsxseg5ei64.v v4, (a0), v12
- - vsxseg5ei64.v v4, 0(a0), v12
- - vsxseg5ei64.v v4, (a0), v12, v0.t
- -
- - vlxseg6ei64.v v4, (a0), v12
- - vlxseg6ei64.v v4, 0(a0), v12
- - vlxseg6ei64.v v4, (a0), v12, v0.t
- - vsxseg6ei64.v v4, (a0), v12
- - vsxseg6ei64.v v4, 0(a0), v12
- - vsxseg6ei64.v v4, (a0), v12, v0.t
- -
- - vlxseg7ei64.v v4, (a0), v12
- - vlxseg7ei64.v v4, 0(a0), v12
- - vlxseg7ei64.v v4, (a0), v12, v0.t
- - vsxseg7ei64.v v4, (a0), v12
- - vsxseg7ei64.v v4, 0(a0), v12
- - vsxseg7ei64.v v4, (a0), v12, v0.t
- -
- - vlxseg8ei64.v v4, (a0), v12
- - vlxseg8ei64.v v4, 0(a0), v12
- - vlxseg8ei64.v v4, (a0), v12, v0.t
- - vsxseg8ei64.v v4, (a0), v12
- - vsxseg8ei64.v v4, 0(a0), v12
- - vsxseg8ei64.v v4, (a0), v12, v0.t
- -
- - vlxseg2ei128.v v4, (a0), v12
- - vlxseg2ei128.v v4, 0(a0), v12
- - vlxseg2ei128.v v4, (a0), v12, v0.t
- - vsxseg2ei128.v v4, (a0), v12
- - vsxseg2ei128.v v4, 0(a0), v12
- - vsxseg2ei128.v v4, (a0), v12, v0.t
- -
- - vlxseg3ei128.v v4, (a0), v12
- - vlxseg3ei128.v v4, 0(a0), v12
- - vlxseg3ei128.v v4, (a0), v12, v0.t
- - vsxseg3ei128.v v4, (a0), v12
- - vsxseg3ei128.v v4, 0(a0), v12
- - vsxseg3ei128.v v4, (a0), v12, v0.t
- -
- - vlxseg4ei128.v v4, (a0), v12
- - vlxseg4ei128.v v4, 0(a0), v12
- - vlxseg4ei128.v v4, (a0), v12, v0.t
- - vsxseg4ei128.v v4, (a0), v12
- - vsxseg4ei128.v v4, 0(a0), v12
- - vsxseg4ei128.v v4, (a0), v12, v0.t
- -
- - vlxseg5ei128.v v4, (a0), v12
- - vlxseg5ei128.v v4, 0(a0), v12
- - vlxseg5ei128.v v4, (a0), v12, v0.t
- - vsxseg5ei128.v v4, (a0), v12
- - vsxseg5ei128.v v4, 0(a0), v12
- - vsxseg5ei128.v v4, (a0), v12, v0.t
- -
- - vlxseg6ei128.v v4, (a0), v12
- - vlxseg6ei128.v v4, 0(a0), v12
- - vlxseg6ei128.v v4, (a0), v12, v0.t
- - vsxseg6ei128.v v4, (a0), v12
- - vsxseg6ei128.v v4, 0(a0), v12
- - vsxseg6ei128.v v4, (a0), v12, v0.t
- -
- - vlxseg7ei128.v v4, (a0), v12
- - vlxseg7ei128.v v4, 0(a0), v12
- - vlxseg7ei128.v v4, (a0), v12, v0.t
- - vsxseg7ei128.v v4, (a0), v12
- - vsxseg7ei128.v v4, 0(a0), v12
- - vsxseg7ei128.v v4, (a0), v12, v0.t
- -
- - vlxseg8ei128.v v4, (a0), v12
- - vlxseg8ei128.v v4, 0(a0), v12
- - vlxseg8ei128.v v4, (a0), v12, v0.t
- - vsxseg8ei128.v v4, (a0), v12
- - vsxseg8ei128.v v4, 0(a0), v12
- - vsxseg8ei128.v v4, (a0), v12, v0.t
- -
- - vlxseg2ei256.v v4, (a0), v12
- - vlxseg2ei256.v v4, 0(a0), v12
- - vlxseg2ei256.v v4, (a0), v12, v0.t
- - vsxseg2ei256.v v4, (a0), v12
- - vsxseg2ei256.v v4, 0(a0), v12
- - vsxseg2ei256.v v4, (a0), v12, v0.t
- -
- - vlxseg3ei256.v v4, (a0), v12
- - vlxseg3ei256.v v4, 0(a0), v12
- - vlxseg3ei256.v v4, (a0), v12, v0.t
- - vsxseg3ei256.v v4, (a0), v12
- - vsxseg3ei256.v v4, 0(a0), v12
- - vsxseg3ei256.v v4, (a0), v12, v0.t
- -
- - vlxseg4ei256.v v4, (a0), v12
- - vlxseg4ei256.v v4, 0(a0), v12
- - vlxseg4ei256.v v4, (a0), v12, v0.t
- - vsxseg4ei256.v v4, (a0), v12
- - vsxseg4ei256.v v4, 0(a0), v12
- - vsxseg4ei256.v v4, (a0), v12, v0.t
- -
- - vlxseg5ei256.v v4, (a0), v12
- - vlxseg5ei256.v v4, 0(a0), v12
- - vlxseg5ei256.v v4, (a0), v12, v0.t
- - vsxseg5ei256.v v4, (a0), v12
- - vsxseg5ei256.v v4, 0(a0), v12
- - vsxseg5ei256.v v4, (a0), v12, v0.t
- -
- - vlxseg6ei256.v v4, (a0), v12
- - vlxseg6ei256.v v4, 0(a0), v12
- - vlxseg6ei256.v v4, (a0), v12, v0.t
- - vsxseg6ei256.v v4, (a0), v12
- - vsxseg6ei256.v v4, 0(a0), v12
- - vsxseg6ei256.v v4, (a0), v12, v0.t
- -
- - vlxseg7ei256.v v4, (a0), v12
- - vlxseg7ei256.v v4, 0(a0), v12
- - vlxseg7ei256.v v4, (a0), v12, v0.t
- - vsxseg7ei256.v v4, (a0), v12
- - vsxseg7ei256.v v4, 0(a0), v12
- - vsxseg7ei256.v v4, (a0), v12, v0.t
- -
- - vlxseg8ei256.v v4, (a0), v12
- - vlxseg8ei256.v v4, 0(a0), v12
- - vlxseg8ei256.v v4, (a0), v12, v0.t
- - vsxseg8ei256.v v4, (a0), v12
- - vsxseg8ei256.v v4, 0(a0), v12
- - vsxseg8ei256.v v4, (a0), v12, v0.t
- -
- - vlxseg2ei512.v v4, (a0), v12
- - vlxseg2ei512.v v4, 0(a0), v12
- - vlxseg2ei512.v v4, (a0), v12, v0.t
- - vsxseg2ei512.v v4, (a0), v12
- - vsxseg2ei512.v v4, 0(a0), v12
- - vsxseg2ei512.v v4, (a0), v12, v0.t
- -
- - vlxseg3ei512.v v4, (a0), v12
- - vlxseg3ei512.v v4, 0(a0), v12
- - vlxseg3ei512.v v4, (a0), v12, v0.t
- - vsxseg3ei512.v v4, (a0), v12
- - vsxseg3ei512.v v4, 0(a0), v12
- - vsxseg3ei512.v v4, (a0), v12, v0.t
- -
- - vlxseg4ei512.v v4, (a0), v12
- - vlxseg4ei512.v v4, 0(a0), v12
- - vlxseg4ei512.v v4, (a0), v12, v0.t
- - vsxseg4ei512.v v4, (a0), v12
- - vsxseg4ei512.v v4, 0(a0), v12
- - vsxseg4ei512.v v4, (a0), v12, v0.t
- -
- - vlxseg5ei512.v v4, (a0), v12
- - vlxseg5ei512.v v4, 0(a0), v12
- - vlxseg5ei512.v v4, (a0), v12, v0.t
- - vsxseg5ei512.v v4, (a0), v12
- - vsxseg5ei512.v v4, 0(a0), v12
- - vsxseg5ei512.v v4, (a0), v12, v0.t
- -
- - vlxseg6ei512.v v4, (a0), v12
- - vlxseg6ei512.v v4, 0(a0), v12
- - vlxseg6ei512.v v4, (a0), v12, v0.t
- - vsxseg6ei512.v v4, (a0), v12
- - vsxseg6ei512.v v4, 0(a0), v12
- - vsxseg6ei512.v v4, (a0), v12, v0.t
- -
- - vlxseg7ei512.v v4, (a0), v12
- - vlxseg7ei512.v v4, 0(a0), v12
- - vlxseg7ei512.v v4, (a0), v12, v0.t
- - vsxseg7ei512.v v4, (a0), v12
- - vsxseg7ei512.v v4, 0(a0), v12
- - vsxseg7ei512.v v4, (a0), v12, v0.t
- -
- - vlxseg8ei512.v v4, (a0), v12
- - vlxseg8ei512.v v4, 0(a0), v12
- - vlxseg8ei512.v v4, (a0), v12, v0.t
- - vsxseg8ei512.v v4, (a0), v12
- - vsxseg8ei512.v v4, 0(a0), v12
- - vsxseg8ei512.v v4, (a0), v12, v0.t
- -
- - vlxseg2ei1024.v v4, (a0), v12
- - vlxseg2ei1024.v v4, 0(a0), v12
- - vlxseg2ei1024.v v4, (a0), v12, v0.t
- - vsxseg2ei1024.v v4, (a0), v12
- - vsxseg2ei1024.v v4, 0(a0), v12
- - vsxseg2ei1024.v v4, (a0), v12, v0.t
- -
- - vlxseg3ei1024.v v4, (a0), v12
- - vlxseg3ei1024.v v4, 0(a0), v12
- - vlxseg3ei1024.v v4, (a0), v12, v0.t
- - vsxseg3ei1024.v v4, (a0), v12
- - vsxseg3ei1024.v v4, 0(a0), v12
- - vsxseg3ei1024.v v4, (a0), v12, v0.t
- -
- - vlxseg4ei1024.v v4, (a0), v12
- - vlxseg4ei1024.v v4, 0(a0), v12
- - vlxseg4ei1024.v v4, (a0), v12, v0.t
- - vsxseg4ei1024.v v4, (a0), v12
- - vsxseg4ei1024.v v4, 0(a0), v12
- - vsxseg4ei1024.v v4, (a0), v12, v0.t
- -
- - vlxseg5ei1024.v v4, (a0), v12
- - vlxseg5ei1024.v v4, 0(a0), v12
- - vlxseg5ei1024.v v4, (a0), v12, v0.t
- - vsxseg5ei1024.v v4, (a0), v12
- - vsxseg5ei1024.v v4, 0(a0), v12
- - vsxseg5ei1024.v v4, (a0), v12, v0.t
- -
- - vlxseg6ei1024.v v4, (a0), v12
- - vlxseg6ei1024.v v4, 0(a0), v12
- - vlxseg6ei1024.v v4, (a0), v12, v0.t
- - vsxseg6ei1024.v v4, (a0), v12
- - vsxseg6ei1024.v v4, 0(a0), v12
- - vsxseg6ei1024.v v4, (a0), v12, v0.t
- -
- - vlxseg7ei1024.v v4, (a0), v12
- - vlxseg7ei1024.v v4, 0(a0), v12
- - vlxseg7ei1024.v v4, (a0), v12, v0.t
- - vsxseg7ei1024.v v4, (a0), v12
- - vsxseg7ei1024.v v4, 0(a0), v12
- - vsxseg7ei1024.v v4, (a0), v12, v0.t
- -
- - vlxseg8ei1024.v v4, (a0), v12
- - vlxseg8ei1024.v v4, 0(a0), v12
- - vlxseg8ei1024.v v4, (a0), v12, v0.t
- - vsxseg8ei1024.v v4, (a0), v12
- - vsxseg8ei1024.v v4, 0(a0), v12
- - vsxseg8ei1024.v v4, (a0), v12, v0.t
- + vloxseg2ei8.v v4, (a0), v12
- + vloxseg2ei8.v v4, 0(a0), v12
- + vloxseg2ei8.v v4, (a0), v12, v0.t
- + vsoxseg2ei8.v v4, (a0), v12
- + vsoxseg2ei8.v v4, 0(a0), v12
- + vsoxseg2ei8.v v4, (a0), v12, v0.t
- +
- + vloxseg3ei8.v v4, (a0), v12
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- + vsuxseg2ei8.v v4, 0(a0), v12
- + vsuxseg2ei8.v v4, (a0), v12, v0.t
- +
- + vluxseg3ei8.v v4, (a0), v12
- + vluxseg3ei8.v v4, 0(a0), v12
- + vluxseg3ei8.v v4, (a0), v12, v0.t
- + vsuxseg3ei8.v v4, (a0), v12
- + vsuxseg3ei8.v v4, 0(a0), v12
- + vsuxseg3ei8.v v4, (a0), v12, v0.t
- +
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- + vluxseg4ei8.v v4, 0(a0), v12
- + vluxseg4ei8.v v4, (a0), v12, v0.t
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- + vsuxseg4ei8.v v4, 0(a0), v12
- + vsuxseg4ei8.v v4, (a0), v12, v0.t
- +
- + vluxseg5ei8.v v4, (a0), v12
- + vluxseg5ei8.v v4, 0(a0), v12
- + vluxseg5ei8.v v4, (a0), v12, v0.t
- + vsuxseg5ei8.v v4, (a0), v12
- + vsuxseg5ei8.v v4, 0(a0), v12
- + vsuxseg5ei8.v v4, (a0), v12, v0.t
- +
- + vluxseg6ei8.v v4, (a0), v12
- + vluxseg6ei8.v v4, 0(a0), v12
- + vluxseg6ei8.v v4, (a0), v12, v0.t
- + vsuxseg6ei8.v v4, (a0), v12
- + vsuxseg6ei8.v v4, 0(a0), v12
- + vsuxseg6ei8.v v4, (a0), v12, v0.t
- +
- + vluxseg7ei8.v v4, (a0), v12
- + vluxseg7ei8.v v4, 0(a0), v12
- + vluxseg7ei8.v v4, (a0), v12, v0.t
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- + vsuxseg7ei8.v v4, 0(a0), v12
- + vsuxseg7ei8.v v4, (a0), v12, v0.t
- +
- + vluxseg8ei8.v v4, (a0), v12
- + vluxseg8ei8.v v4, 0(a0), v12
- + vluxseg8ei8.v v4, (a0), v12, v0.t
- + vsuxseg8ei8.v v4, (a0), v12
- + vsuxseg8ei8.v v4, 0(a0), v12
- + vsuxseg8ei8.v v4, (a0), v12, v0.t
- +
- + vluxseg2ei16.v v4, (a0), v12
- + vluxseg2ei16.v v4, 0(a0), v12
- + vluxseg2ei16.v v4, (a0), v12, v0.t
- + vsuxseg2ei16.v v4, (a0), v12
- + vsuxseg2ei16.v v4, 0(a0), v12
- + vsuxseg2ei16.v v4, (a0), v12, v0.t
- +
- + vluxseg3ei16.v v4, (a0), v12
- + vluxseg3ei16.v v4, 0(a0), v12
- + vluxseg3ei16.v v4, (a0), v12, v0.t
- + vsuxseg3ei16.v v4, (a0), v12
- + vsuxseg3ei16.v v4, 0(a0), v12
- + vsuxseg3ei16.v v4, (a0), v12, v0.t
- +
- + vluxseg4ei16.v v4, (a0), v12
- + vluxseg4ei16.v v4, 0(a0), v12
- + vluxseg4ei16.v v4, (a0), v12, v0.t
- + vsuxseg4ei16.v v4, (a0), v12
- + vsuxseg4ei16.v v4, 0(a0), v12
- + vsuxseg4ei16.v v4, (a0), v12, v0.t
- +
- + vluxseg5ei16.v v4, (a0), v12
- + vluxseg5ei16.v v4, 0(a0), v12
- + vluxseg5ei16.v v4, (a0), v12, v0.t
- + vsuxseg5ei16.v v4, (a0), v12
- + vsuxseg5ei16.v v4, 0(a0), v12
- + vsuxseg5ei16.v v4, (a0), v12, v0.t
- +
- + vluxseg6ei16.v v4, (a0), v12
- + vluxseg6ei16.v v4, 0(a0), v12
- + vluxseg6ei16.v v4, (a0), v12, v0.t
- + vsuxseg6ei16.v v4, (a0), v12
- + vsuxseg6ei16.v v4, 0(a0), v12
- + vsuxseg6ei16.v v4, (a0), v12, v0.t
- +
- + vluxseg7ei16.v v4, (a0), v12
- + vluxseg7ei16.v v4, 0(a0), v12
- + vluxseg7ei16.v v4, (a0), v12, v0.t
- + vsuxseg7ei16.v v4, (a0), v12
- + vsuxseg7ei16.v v4, 0(a0), v12
- + vsuxseg7ei16.v v4, (a0), v12, v0.t
- +
- + vluxseg8ei16.v v4, (a0), v12
- + vluxseg8ei16.v v4, 0(a0), v12
- + vluxseg8ei16.v v4, (a0), v12, v0.t
- + vsuxseg8ei16.v v4, (a0), v12
- + vsuxseg8ei16.v v4, 0(a0), v12
- + vsuxseg8ei16.v v4, (a0), v12, v0.t
- +
- + vluxseg2ei32.v v4, (a0), v12
- + vluxseg2ei32.v v4, 0(a0), v12
- + vluxseg2ei32.v v4, (a0), v12, v0.t
- + vsuxseg2ei32.v v4, (a0), v12
- + vsuxseg2ei32.v v4, 0(a0), v12
- + vsuxseg2ei32.v v4, (a0), v12, v0.t
- +
- + vluxseg3ei32.v v4, (a0), v12
- + vluxseg3ei32.v v4, 0(a0), v12
- + vluxseg3ei32.v v4, (a0), v12, v0.t
- + vsuxseg3ei32.v v4, (a0), v12
- + vsuxseg3ei32.v v4, 0(a0), v12
- + vsuxseg3ei32.v v4, (a0), v12, v0.t
- +
- + vluxseg4ei32.v v4, (a0), v12
- + vluxseg4ei32.v v4, 0(a0), v12
- + vluxseg4ei32.v v4, (a0), v12, v0.t
- + vsuxseg4ei32.v v4, (a0), v12
- + vsuxseg4ei32.v v4, 0(a0), v12
- + vsuxseg4ei32.v v4, (a0), v12, v0.t
- +
- + vluxseg5ei32.v v4, (a0), v12
- + vluxseg5ei32.v v4, 0(a0), v12
- + vluxseg5ei32.v v4, (a0), v12, v0.t
- + vsuxseg5ei32.v v4, (a0), v12
- + vsuxseg5ei32.v v4, 0(a0), v12
- + vsuxseg5ei32.v v4, (a0), v12, v0.t
- +
- + vluxseg6ei32.v v4, (a0), v12
- + vluxseg6ei32.v v4, 0(a0), v12
- + vluxseg6ei32.v v4, (a0), v12, v0.t
- + vsuxseg6ei32.v v4, (a0), v12
- + vsuxseg6ei32.v v4, 0(a0), v12
- + vsuxseg6ei32.v v4, (a0), v12, v0.t
- +
- + vluxseg7ei32.v v4, (a0), v12
- + vluxseg7ei32.v v4, 0(a0), v12
- + vluxseg7ei32.v v4, (a0), v12, v0.t
- + vsuxseg7ei32.v v4, (a0), v12
- + vsuxseg7ei32.v v4, 0(a0), v12
- + vsuxseg7ei32.v v4, (a0), v12, v0.t
- +
- + vluxseg8ei32.v v4, (a0), v12
- + vluxseg8ei32.v v4, 0(a0), v12
- + vluxseg8ei32.v v4, (a0), v12, v0.t
- + vsuxseg8ei32.v v4, (a0), v12
- + vsuxseg8ei32.v v4, 0(a0), v12
- + vsuxseg8ei32.v v4, (a0), v12, v0.t
- +
- + vluxseg2ei64.v v4, (a0), v12
- + vluxseg2ei64.v v4, 0(a0), v12
- + vluxseg2ei64.v v4, (a0), v12, v0.t
- + vsuxseg2ei64.v v4, (a0), v12
- + vsuxseg2ei64.v v4, 0(a0), v12
- + vsuxseg2ei64.v v4, (a0), v12, v0.t
- +
- + vluxseg3ei64.v v4, (a0), v12
- + vluxseg3ei64.v v4, 0(a0), v12
- + vluxseg3ei64.v v4, (a0), v12, v0.t
- + vsuxseg3ei64.v v4, (a0), v12
- + vsuxseg3ei64.v v4, 0(a0), v12
- + vsuxseg3ei64.v v4, (a0), v12, v0.t
- +
- + vluxseg4ei64.v v4, (a0), v12
- + vluxseg4ei64.v v4, 0(a0), v12
- + vluxseg4ei64.v v4, (a0), v12, v0.t
- + vsuxseg4ei64.v v4, (a0), v12
- + vsuxseg4ei64.v v4, 0(a0), v12
- + vsuxseg4ei64.v v4, (a0), v12, v0.t
- +
- + vluxseg5ei64.v v4, (a0), v12
- + vluxseg5ei64.v v4, 0(a0), v12
- + vluxseg5ei64.v v4, (a0), v12, v0.t
- + vsuxseg5ei64.v v4, (a0), v12
- + vsuxseg5ei64.v v4, 0(a0), v12
- + vsuxseg5ei64.v v4, (a0), v12, v0.t
- +
- + vluxseg6ei64.v v4, (a0), v12
- + vluxseg6ei64.v v4, 0(a0), v12
- + vluxseg6ei64.v v4, (a0), v12, v0.t
- + vsuxseg6ei64.v v4, (a0), v12
- + vsuxseg6ei64.v v4, 0(a0), v12
- + vsuxseg6ei64.v v4, (a0), v12, v0.t
- +
- + vluxseg7ei64.v v4, (a0), v12
- + vluxseg7ei64.v v4, 0(a0), v12
- + vluxseg7ei64.v v4, (a0), v12, v0.t
- + vsuxseg7ei64.v v4, (a0), v12
- + vsuxseg7ei64.v v4, 0(a0), v12
- + vsuxseg7ei64.v v4, (a0), v12, v0.t
- +
- + vluxseg8ei64.v v4, (a0), v12
- + vluxseg8ei64.v v4, 0(a0), v12
- + vluxseg8ei64.v v4, (a0), v12, v0.t
- + vsuxseg8ei64.v v4, (a0), v12
- + vsuxseg8ei64.v v4, 0(a0), v12
- + vsuxseg8ei64.v v4, (a0), v12, v0.t
- +
- + vluxseg2ei128.v v4, (a0), v12
- + vluxseg2ei128.v v4, 0(a0), v12
- + vluxseg2ei128.v v4, (a0), v12, v0.t
- + vsuxseg2ei128.v v4, (a0), v12
- + vsuxseg2ei128.v v4, 0(a0), v12
- + vsuxseg2ei128.v v4, (a0), v12, v0.t
- +
- + vluxseg3ei128.v v4, (a0), v12
- + vluxseg3ei128.v v4, 0(a0), v12
- + vluxseg3ei128.v v4, (a0), v12, v0.t
- + vsuxseg3ei128.v v4, (a0), v12
- + vsuxseg3ei128.v v4, 0(a0), v12
- + vsuxseg3ei128.v v4, (a0), v12, v0.t
- +
- + vluxseg4ei128.v v4, (a0), v12
- + vluxseg4ei128.v v4, 0(a0), v12
- + vluxseg4ei128.v v4, (a0), v12, v0.t
- + vsuxseg4ei128.v v4, (a0), v12
- + vsuxseg4ei128.v v4, 0(a0), v12
- + vsuxseg4ei128.v v4, (a0), v12, v0.t
- +
- + vluxseg5ei128.v v4, (a0), v12
- + vluxseg5ei128.v v4, 0(a0), v12
- + vluxseg5ei128.v v4, (a0), v12, v0.t
- + vsuxseg5ei128.v v4, (a0), v12
- + vsuxseg5ei128.v v4, 0(a0), v12
- + vsuxseg5ei128.v v4, (a0), v12, v0.t
- +
- + vluxseg6ei128.v v4, (a0), v12
- + vluxseg6ei128.v v4, 0(a0), v12
- + vluxseg6ei128.v v4, (a0), v12, v0.t
- + vsuxseg6ei128.v v4, (a0), v12
- + vsuxseg6ei128.v v4, 0(a0), v12
- + vsuxseg6ei128.v v4, (a0), v12, v0.t
- +
- + vluxseg7ei128.v v4, (a0), v12
- + vluxseg7ei128.v v4, 0(a0), v12
- + vluxseg7ei128.v v4, (a0), v12, v0.t
- + vsuxseg7ei128.v v4, (a0), v12
- + vsuxseg7ei128.v v4, 0(a0), v12
- + vsuxseg7ei128.v v4, (a0), v12, v0.t
- +
- + vluxseg8ei128.v v4, (a0), v12
- + vluxseg8ei128.v v4, 0(a0), v12
- + vluxseg8ei128.v v4, (a0), v12, v0.t
- + vsuxseg8ei128.v v4, (a0), v12
- + vsuxseg8ei128.v v4, 0(a0), v12
- + vsuxseg8ei128.v v4, (a0), v12, v0.t
- +
- + vluxseg2ei256.v v4, (a0), v12
- + vluxseg2ei256.v v4, 0(a0), v12
- + vluxseg2ei256.v v4, (a0), v12, v0.t
- + vsuxseg2ei256.v v4, (a0), v12
- + vsuxseg2ei256.v v4, 0(a0), v12
- + vsuxseg2ei256.v v4, (a0), v12, v0.t
- +
- + vluxseg3ei256.v v4, (a0), v12
- + vluxseg3ei256.v v4, 0(a0), v12
- + vluxseg3ei256.v v4, (a0), v12, v0.t
- + vsuxseg3ei256.v v4, (a0), v12
- + vsuxseg3ei256.v v4, 0(a0), v12
- + vsuxseg3ei256.v v4, (a0), v12, v0.t
- +
- + vluxseg4ei256.v v4, (a0), v12
- + vluxseg4ei256.v v4, 0(a0), v12
- + vluxseg4ei256.v v4, (a0), v12, v0.t
- + vsuxseg4ei256.v v4, (a0), v12
- + vsuxseg4ei256.v v4, 0(a0), v12
- + vsuxseg4ei256.v v4, (a0), v12, v0.t
- +
- + vluxseg5ei256.v v4, (a0), v12
- + vluxseg5ei256.v v4, 0(a0), v12
- + vluxseg5ei256.v v4, (a0), v12, v0.t
- + vsuxseg5ei256.v v4, (a0), v12
- + vsuxseg5ei256.v v4, 0(a0), v12
- + vsuxseg5ei256.v v4, (a0), v12, v0.t
- +
- + vluxseg6ei256.v v4, (a0), v12
- + vluxseg6ei256.v v4, 0(a0), v12
- + vluxseg6ei256.v v4, (a0), v12, v0.t
- + vsuxseg6ei256.v v4, (a0), v12
- + vsuxseg6ei256.v v4, 0(a0), v12
- + vsuxseg6ei256.v v4, (a0), v12, v0.t
- +
- + vluxseg7ei256.v v4, (a0), v12
- + vluxseg7ei256.v v4, 0(a0), v12
- + vluxseg7ei256.v v4, (a0), v12, v0.t
- + vsuxseg7ei256.v v4, (a0), v12
- + vsuxseg7ei256.v v4, 0(a0), v12
- + vsuxseg7ei256.v v4, (a0), v12, v0.t
- +
- + vluxseg8ei256.v v4, (a0), v12
- + vluxseg8ei256.v v4, 0(a0), v12
- + vluxseg8ei256.v v4, (a0), v12, v0.t
- + vsuxseg8ei256.v v4, (a0), v12
- + vsuxseg8ei256.v v4, 0(a0), v12
- + vsuxseg8ei256.v v4, (a0), v12, v0.t
- +
- + vluxseg2ei512.v v4, (a0), v12
- + vluxseg2ei512.v v4, 0(a0), v12
- + vluxseg2ei512.v v4, (a0), v12, v0.t
- + vsuxseg2ei512.v v4, (a0), v12
- + vsuxseg2ei512.v v4, 0(a0), v12
- + vsuxseg2ei512.v v4, (a0), v12, v0.t
- +
- + vluxseg3ei512.v v4, (a0), v12
- + vluxseg3ei512.v v4, 0(a0), v12
- + vluxseg3ei512.v v4, (a0), v12, v0.t
- + vsuxseg3ei512.v v4, (a0), v12
- + vsuxseg3ei512.v v4, 0(a0), v12
- + vsuxseg3ei512.v v4, (a0), v12, v0.t
- +
- + vluxseg4ei512.v v4, (a0), v12
- + vluxseg4ei512.v v4, 0(a0), v12
- + vluxseg4ei512.v v4, (a0), v12, v0.t
- + vsuxseg4ei512.v v4, (a0), v12
- + vsuxseg4ei512.v v4, 0(a0), v12
- + vsuxseg4ei512.v v4, (a0), v12, v0.t
- +
- + vluxseg5ei512.v v4, (a0), v12
- + vluxseg5ei512.v v4, 0(a0), v12
- + vluxseg5ei512.v v4, (a0), v12, v0.t
- + vsuxseg5ei512.v v4, (a0), v12
- + vsuxseg5ei512.v v4, 0(a0), v12
- + vsuxseg5ei512.v v4, (a0), v12, v0.t
- +
- + vluxseg6ei512.v v4, (a0), v12
- + vluxseg6ei512.v v4, 0(a0), v12
- + vluxseg6ei512.v v4, (a0), v12, v0.t
- + vsuxseg6ei512.v v4, (a0), v12
- + vsuxseg6ei512.v v4, 0(a0), v12
- + vsuxseg6ei512.v v4, (a0), v12, v0.t
- +
- + vluxseg7ei512.v v4, (a0), v12
- + vluxseg7ei512.v v4, 0(a0), v12
- + vluxseg7ei512.v v4, (a0), v12, v0.t
- + vsuxseg7ei512.v v4, (a0), v12
- + vsuxseg7ei512.v v4, 0(a0), v12
- + vsuxseg7ei512.v v4, (a0), v12, v0.t
- +
- + vluxseg8ei512.v v4, (a0), v12
- + vluxseg8ei512.v v4, 0(a0), v12
- + vluxseg8ei512.v v4, (a0), v12, v0.t
- + vsuxseg8ei512.v v4, (a0), v12
- + vsuxseg8ei512.v v4, 0(a0), v12
- + vsuxseg8ei512.v v4, (a0), v12, v0.t
- +
- + vluxseg2ei1024.v v4, (a0), v12
- + vluxseg2ei1024.v v4, 0(a0), v12
- + vluxseg2ei1024.v v4, (a0), v12, v0.t
- + vsuxseg2ei1024.v v4, (a0), v12
- + vsuxseg2ei1024.v v4, 0(a0), v12
- + vsuxseg2ei1024.v v4, (a0), v12, v0.t
- +
- + vluxseg3ei1024.v v4, (a0), v12
- + vluxseg3ei1024.v v4, 0(a0), v12
- + vluxseg3ei1024.v v4, (a0), v12, v0.t
- + vsuxseg3ei1024.v v4, (a0), v12
- + vsuxseg3ei1024.v v4, 0(a0), v12
- + vsuxseg3ei1024.v v4, (a0), v12, v0.t
- +
- + vluxseg4ei1024.v v4, (a0), v12
- + vluxseg4ei1024.v v4, 0(a0), v12
- + vluxseg4ei1024.v v4, (a0), v12, v0.t
- + vsuxseg4ei1024.v v4, (a0), v12
- + vsuxseg4ei1024.v v4, 0(a0), v12
- + vsuxseg4ei1024.v v4, (a0), v12, v0.t
- +
- + vluxseg5ei1024.v v4, (a0), v12
- + vluxseg5ei1024.v v4, 0(a0), v12
- + vluxseg5ei1024.v v4, (a0), v12, v0.t
- + vsuxseg5ei1024.v v4, (a0), v12
- + vsuxseg5ei1024.v v4, 0(a0), v12
- + vsuxseg5ei1024.v v4, (a0), v12, v0.t
- +
- + vluxseg6ei1024.v v4, (a0), v12
- + vluxseg6ei1024.v v4, 0(a0), v12
- + vluxseg6ei1024.v v4, (a0), v12, v0.t
- + vsuxseg6ei1024.v v4, (a0), v12
- + vsuxseg6ei1024.v v4, 0(a0), v12
- + vsuxseg6ei1024.v v4, (a0), v12, v0.t
- +
- + vluxseg7ei1024.v v4, (a0), v12
- + vluxseg7ei1024.v v4, 0(a0), v12
- + vluxseg7ei1024.v v4, (a0), v12, v0.t
- + vsuxseg7ei1024.v v4, (a0), v12
- + vsuxseg7ei1024.v v4, 0(a0), v12
- + vsuxseg7ei1024.v v4, (a0), v12, v0.t
- +
- + vluxseg8ei1024.v v4, (a0), v12
- + vluxseg8ei1024.v v4, 0(a0), v12
- + vluxseg8ei1024.v v4, (a0), v12, v0.t
- + vsuxseg8ei1024.v v4, (a0), v12
- + vsuxseg8ei1024.v v4, 0(a0), v12
- + vsuxseg8ei1024.v v4, (a0), v12, v0.t
-
- vlseg2e8ff.v v4, (a0)
- vlseg2e8ff.v v4, 0(a0)
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index 743060ca18..d74d3d5044 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -630,16 +630,16 @@
-
- /* Temporary Load/store encoding info
- MOP load
- -00 unit-stride VLE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
- -01 reserved
- -10 strided VLSE<EEW>
- -11 indexed VLXEI<EEW>
- +00 unit-stride LE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
- +01 indexed-unordered VLUXEI<EEW>
- +10 strided VLSE<EEW>
- +11 indexed-ordered VLOXEI<EEW>
-
- MOP store
- 00 unit-stride VSE<EEW>, VS<nf>R (nf = 1, 2, 4, 8)
- 01 indexed-unordered VSUXEI<EEW>
- 10 strided VSSE<EEW>
- -11 indexed-ordered VSXEI<EEW>
- +11 indexed-ordered VSOXEI<EEW>
-
- VM 0 masked
- VM 1 unmasked
- @@ -680,8 +680,9 @@ NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
- 000 - 00 x 00000 xxxxx --- xxxxx 0100111 VSE<EEW>
- 000 - 10 x xxxxx xxxxx --- xxxxx 0000111 VLSE<EEW>
- 000 - 10 x xxxxx xxxxx --- xxxxx 0100111 VSSE<EEW>
- -000 0 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
- -000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
- +000 0 11 x xxxxx xxxxx --- xxxxx 0000111 VLOXE<EEW>I
- +000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSOXE<EEW>I
- +000 0 01 x xxxxx xxxxx --- xxxxx 0000111 VLUXE<EEW>I
- 000 0 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
- 000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
- xxx - 00 1 01000 xxxxx --- xxxxx 0000111 VL<nf>RE<EEW>, nf = 1,2,4,8
- @@ -691,8 +692,10 @@ xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
- xxx - 00 x 00000 xxxxx --- xxxxx 0100111 VSSEG<nf>E<EEW>
- xxx - 10 x 00000 xxxxx --- xxxxx 0000111 VLSSEG<nf>E<EEW>
- xxx - 10 x 00000 xxxxx --- xxxxx 0100111 VSSSEG<nf>E<EEW>
- -xxx - 11 x 00000 xxxxx --- xxxxx 0000111 VLXSEG<nf>E<EEW>I
- -xxx - 11 x 00000 xxxxx --- xxxxx 0100111 VSXSEG<nf>E<EEW>I
- +xxx - 11 x 00000 xxxxx --- xxxxx 0000111 VLOXSEG<nf>E<EEW>I
- +xxx - 11 x 00000 xxxxx --- xxxxx 0100111 VSOXSEG<nf>E<EEW>I
- +xxx - 01 x 00000 xxxxx --- xxxxx 0000111 VLUXSEG<nf>E<EEW>I
- +xxx - 01 x 00000 xxxxx --- xxxxx 0100111 VSUXSEG<nf>E<EEW>I
- xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
- */
-
- @@ -764,23 +767,32 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
- #define MATCH_VSSE1024V 0x18007027
- #define MASK_VSSE1024V 0xfc00707f
-
- -#define MATCH_VLXEI8V 0x0c000007
- -#define MASK_VLXEI8V 0xfc00707f
- -#define MATCH_VLXEI16V 0x0c005007
- -#define MASK_VLXEI16V 0xfc00707f
- -#define MATCH_VLXEI32V 0x0c006007
- -#define MASK_VLXEI32V 0xfc00707f
- -#define MATCH_VLXEI64V 0x0c007007
- -#define MASK_VLXEI64V 0xfc00707f
- -
- -#define MATCH_VSXEI8V 0x0c000027
- -#define MASK_VSXEI8V 0xfc00707f
- -#define MATCH_VSXEI16V 0x0c005027
- -#define MASK_VSXEI16V 0xfc00707f
- -#define MATCH_VSXEI32V 0x0c006027
- -#define MASK_VSXEI32V 0xfc00707f
- -#define MATCH_VSXEI64V 0x0c007027
- -#define MASK_VSXEI64V 0xfc00707f
- +#define MATCH_VLOXEI8V 0x0c000007
- +#define MASK_VLOXEI8V 0xfc00707f
- +#define MATCH_VLOXEI16V 0x0c005007
- +#define MASK_VLOXEI16V 0xfc00707f
- +#define MATCH_VLOXEI32V 0x0c006007
- +#define MASK_VLOXEI32V 0xfc00707f
- +#define MATCH_VLOXEI64V 0x0c007007
- +#define MASK_VLOXEI64V 0xfc00707f
- +
- +#define MATCH_VSOXEI8V 0x0c000027
- +#define MASK_VSOXEI8V 0xfc00707f
- +#define MATCH_VSOXEI16V 0x0c005027
- +#define MASK_VSOXEI16V 0xfc00707f
- +#define MATCH_VSOXEI32V 0x0c006027
- +#define MASK_VSOXEI32V 0xfc00707f
- +#define MATCH_VSOXEI64V 0x0c007027
- +#define MASK_VSOXEI64V 0xfc00707f
- +
- +#define MATCH_VLUXEI8V 0x04000007
- +#define MASK_VLUXEI8V 0xfc00707f
- +#define MATCH_VLUXEI16V 0x04005007
- +#define MASK_VLUXEI16V 0xfc00707f
- +#define MATCH_VLUXEI32V 0x04006007
- +#define MASK_VLUXEI32V 0xfc00707f
- +#define MATCH_VLUXEI64V 0x04007007
- +#define MASK_VLUXEI64V 0xfc00707f
-
- #define MATCH_VSUXEI8V 0x04000027
- #define MASK_VSUXEI8V 0xfc00707f
- @@ -1272,237 +1284,469 @@ xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
- #define MATCH_VSSSEG8E1024V 0xf8007027
- #define MASK_VSSSEG8E1024V 0xfc00707f
-
- -#define MATCH_VLXSEG2EI8V 0x2c000007
- -#define MASK_VLXSEG2EI8V 0xfc00707f
- -#define MATCH_VSXSEG2EI8V 0x2c000027
- -#define MASK_VSXSEG2EI8V 0xfc00707f
- -#define MATCH_VLXSEG3EI8V 0x4c000007
- -#define MASK_VLXSEG3EI8V 0xfc00707f
- -#define MATCH_VSXSEG3EI8V 0x4c000027
- -#define MASK_VSXSEG3EI8V 0xfc00707f
- -#define MATCH_VLXSEG4EI8V 0x6c000007
- -#define MASK_VLXSEG4EI8V 0xfc00707f
- -#define MATCH_VSXSEG4EI8V 0x6c000027
- -#define MASK_VSXSEG4EI8V 0xfc00707f
- -#define MATCH_VLXSEG5EI8V 0x8c000007
- -#define MASK_VLXSEG5EI8V 0xfc00707f
- -#define MATCH_VSXSEG5EI8V 0x8c000027
- -#define MASK_VSXSEG5EI8V 0xfc00707f
- -#define MATCH_VLXSEG6EI8V 0xac000007
- -#define MASK_VLXSEG6EI8V 0xfc00707f
- -#define MATCH_VSXSEG6EI8V 0xac000027
- -#define MASK_VSXSEG6EI8V 0xfc00707f
- -#define MATCH_VLXSEG7EI8V 0xcc000007
- -#define MASK_VLXSEG7EI8V 0xfc00707f
- -#define MATCH_VSXSEG7EI8V 0xcc000027
- -#define MASK_VSXSEG7EI8V 0xfc00707f
- -#define MATCH_VLXSEG8EI8V 0xec000007
- -#define MASK_VLXSEG8EI8V 0xfc00707f
- -#define MATCH_VSXSEG8EI8V 0xec000027
- -#define MASK_VSXSEG8EI8V 0xfc00707f
- -
- -#define MATCH_VLXSEG2EI16V 0x2c005007
- -#define MASK_VLXSEG2EI16V 0xfc00707f
- -#define MATCH_VSXSEG2EI16V 0x2c005027
- -#define MASK_VSXSEG2EI16V 0xfc00707f
- -#define MATCH_VLXSEG3EI16V 0x4c005007
- -#define MASK_VLXSEG3EI16V 0xfc00707f
- -#define MATCH_VSXSEG3EI16V 0x4c005027
- -#define MASK_VSXSEG3EI16V 0xfc00707f
- -#define MATCH_VLXSEG4EI16V 0x6c005007
- -#define MASK_VLXSEG4EI16V 0xfc00707f
- -#define MATCH_VSXSEG4EI16V 0x6c005027
- -#define MASK_VSXSEG4EI16V 0xfc00707f
- -#define MATCH_VLXSEG5EI16V 0x8c005007
- -#define MASK_VLXSEG5EI16V 0xfc00707f
- -#define MATCH_VSXSEG5EI16V 0x8c005027
- -#define MASK_VSXSEG5EI16V 0xfc00707f
- -#define MATCH_VLXSEG6EI16V 0xac005007
- -#define MASK_VLXSEG6EI16V 0xfc00707f
- -#define MATCH_VSXSEG6EI16V 0xac005027
- -#define MASK_VSXSEG6EI16V 0xfc00707f
- -#define MATCH_VLXSEG7EI16V 0xcc005007
- -#define MASK_VLXSEG7EI16V 0xfc00707f
- -#define MATCH_VSXSEG7EI16V 0xcc005027
- -#define MASK_VSXSEG7EI16V 0xfc00707f
- -#define MATCH_VLXSEG8EI16V 0xec005007
- -#define MASK_VLXSEG8EI16V 0xfc00707f
- -#define MATCH_VSXSEG8EI16V 0xec005027
- -#define MASK_VSXSEG8EI16V 0xfc00707f
- -
- -#define MATCH_VLXSEG2EI32V 0x2c006007
- -#define MASK_VLXSEG2EI32V 0xfc00707f
- -#define MATCH_VSXSEG2EI32V 0x2c006027
- -#define MASK_VSXSEG2EI32V 0xfc00707f
- -#define MATCH_VLXSEG3EI32V 0x4c006007
- -#define MASK_VLXSEG3EI32V 0xfc00707f
- -#define MATCH_VSXSEG3EI32V 0x4c006027
- -#define MASK_VSXSEG3EI32V 0xfc00707f
- -#define MATCH_VLXSEG4EI32V 0x6c006007
- -#define MASK_VLXSEG4EI32V 0xfc00707f
- -#define MATCH_VSXSEG4EI32V 0x6c006027
- -#define MASK_VSXSEG4EI32V 0xfc00707f
- -#define MATCH_VLXSEG5EI32V 0x8c006007
- -#define MASK_VLXSEG5EI32V 0xfc00707f
- -#define MATCH_VSXSEG5EI32V 0x8c006027
- -#define MASK_VSXSEG5EI32V 0xfc00707f
- -#define MATCH_VLXSEG6EI32V 0xac006007
- -#define MASK_VLXSEG6EI32V 0xfc00707f
- -#define MATCH_VSXSEG6EI32V 0xac006027
- -#define MASK_VSXSEG6EI32V 0xfc00707f
- -#define MATCH_VLXSEG7EI32V 0xcc006007
- -#define MASK_VLXSEG7EI32V 0xfc00707f
- -#define MATCH_VSXSEG7EI32V 0xcc006027
- -#define MASK_VSXSEG7EI32V 0xfc00707f
- -#define MATCH_VLXSEG8EI32V 0xec006007
- -#define MASK_VLXSEG8EI32V 0xfc00707f
- -#define MATCH_VSXSEG8EI32V 0xec006027
- -#define MASK_VSXSEG8EI32V 0xfc00707f
- -
- -#define MATCH_VLXSEG2EI64V 0x2c007007
- -#define MASK_VLXSEG2EI64V 0xfc00707f
- -#define MATCH_VSXSEG2EI64V 0x2c007027
- -#define MASK_VSXSEG2EI64V 0xfc00707f
- -#define MATCH_VLXSEG3EI64V 0x4c007007
- -#define MASK_VLXSEG3EI64V 0xfc00707f
- -#define MATCH_VSXSEG3EI64V 0x4c007027
- -#define MASK_VSXSEG3EI64V 0xfc00707f
- -#define MATCH_VLXSEG4EI64V 0x6c007007
- -#define MASK_VLXSEG4EI64V 0xfc00707f
- -#define MATCH_VSXSEG4EI64V 0x6c007027
- -#define MASK_VSXSEG4EI64V 0xfc00707f
- -#define MATCH_VLXSEG5EI64V 0x8c007007
- -#define MASK_VLXSEG5EI64V 0xfc00707f
- -#define MATCH_VSXSEG5EI64V 0x8c007027
- -#define MASK_VSXSEG5EI64V 0xfc00707f
- -#define MATCH_VLXSEG6EI64V 0xac007007
- -#define MASK_VLXSEG6EI64V 0xfc00707f
- -#define MATCH_VSXSEG6EI64V 0xac007027
- -#define MASK_VSXSEG6EI64V 0xfc00707f
- -#define MATCH_VLXSEG7EI64V 0xcc007007
- -#define MASK_VLXSEG7EI64V 0xfc00707f
- -#define MATCH_VSXSEG7EI64V 0xcc007027
- -#define MASK_VSXSEG7EI64V 0xfc00707f
- -#define MATCH_VLXSEG8EI64V 0xec007007
- -#define MASK_VLXSEG8EI64V 0xfc00707f
- -#define MATCH_VSXSEG8EI64V 0xec007027
- -#define MASK_VSXSEG8EI64V 0xfc00707f
- -
- -#define MATCH_VLXSEG2EI128V 0x3c000007
- -#define MASK_VLXSEG2EI128V 0xfc00707f
- -#define MATCH_VSXSEG2EI128V 0x3c000027
- -#define MASK_VSXSEG2EI128V 0xfc00707f
- -#define MATCH_VLXSEG3EI128V 0x5c000007
- -#define MASK_VLXSEG3EI128V 0xfc00707f
- -#define MATCH_VSXSEG3EI128V 0x5c000027
- -#define MASK_VSXSEG3EI128V 0xfc00707f
- -#define MATCH_VLXSEG4EI128V 0x7c000007
- -#define MASK_VLXSEG4EI128V 0xfc00707f
- -#define MATCH_VSXSEG4EI128V 0x7c000027
- -#define MASK_VSXSEG4EI128V 0xfc00707f
- -#define MATCH_VLXSEG5EI128V 0x9c000007
- -#define MASK_VLXSEG5EI128V 0xfc00707f
- -#define MATCH_VSXSEG5EI128V 0x9c000027
- -#define MASK_VSXSEG5EI128V 0xfc00707f
- -#define MATCH_VLXSEG6EI128V 0xbc000007
- -#define MASK_VLXSEG6EI128V 0xfc00707f
- -#define MATCH_VSXSEG6EI128V 0xbc000027
- -#define MASK_VSXSEG6EI128V 0xfc00707f
- -#define MATCH_VLXSEG7EI128V 0xdc000007
- -#define MASK_VLXSEG7EI128V 0xfc00707f
- -#define MATCH_VSXSEG7EI128V 0xdc000027
- -#define MASK_VSXSEG7EI128V 0xfc00707f
- -#define MATCH_VLXSEG8EI128V 0xfc000007
- -#define MASK_VLXSEG8EI128V 0xfc00707f
- -#define MATCH_VSXSEG8EI128V 0xfc000027
- -#define MASK_VSXSEG8EI128V 0xfc00707f
- -
- -#define MATCH_VLXSEG2EI256V 0x3c005007
- -#define MASK_VLXSEG2EI256V 0xfc00707f
- -#define MATCH_VSXSEG2EI256V 0x3c005027
- -#define MASK_VSXSEG2EI256V 0xfc00707f
- -#define MATCH_VLXSEG3EI256V 0x5c005007
- -#define MASK_VLXSEG3EI256V 0xfc00707f
- -#define MATCH_VSXSEG3EI256V 0x5c005027
- -#define MASK_VSXSEG3EI256V 0xfc00707f
- -#define MATCH_VLXSEG4EI256V 0x7c005007
- -#define MASK_VLXSEG4EI256V 0xfc00707f
- -#define MATCH_VSXSEG4EI256V 0x7c005027
- -#define MASK_VSXSEG4EI256V 0xfc00707f
- -#define MATCH_VLXSEG5EI256V 0x9c005007
- -#define MASK_VLXSEG5EI256V 0xfc00707f
- -#define MATCH_VSXSEG5EI256V 0x9c005027
- -#define MASK_VSXSEG5EI256V 0xfc00707f
- -#define MATCH_VLXSEG6EI256V 0xbc005007
- -#define MASK_VLXSEG6EI256V 0xfc00707f
- -#define MATCH_VSXSEG6EI256V 0xbc005027
- -#define MASK_VSXSEG6EI256V 0xfc00707f
- -#define MATCH_VLXSEG7EI256V 0xdc005007
- -#define MASK_VLXSEG7EI256V 0xfc00707f
- -#define MATCH_VSXSEG7EI256V 0xdc005027
- -#define MASK_VSXSEG7EI256V 0xfc00707f
- -#define MATCH_VLXSEG8EI256V 0xfc005007
- -#define MASK_VLXSEG8EI256V 0xfc00707f
- -#define MATCH_VSXSEG8EI256V 0xfc005027
- -#define MASK_VSXSEG8EI256V 0xfc00707f
- -
- -#define MATCH_VLXSEG2EI512V 0x3c006007
- -#define MASK_VLXSEG2EI512V 0xfc00707f
- -#define MATCH_VSXSEG2EI512V 0x3c006027
- -#define MASK_VSXSEG2EI512V 0xfc00707f
- -#define MATCH_VLXSEG3EI512V 0x5c006007
- -#define MASK_VLXSEG3EI512V 0xfc00707f
- -#define MATCH_VSXSEG3EI512V 0x5c006027
- -#define MASK_VSXSEG3EI512V 0xfc00707f
- -#define MATCH_VLXSEG4EI512V 0x7c006007
- -#define MASK_VLXSEG4EI512V 0xfc00707f
- -#define MATCH_VSXSEG4EI512V 0x7c006027
- -#define MASK_VSXSEG4EI512V 0xfc00707f
- -#define MATCH_VLXSEG5EI512V 0x9c006007
- -#define MASK_VLXSEG5EI512V 0xfc00707f
- -#define MATCH_VSXSEG5EI512V 0x9c006027
- -#define MASK_VSXSEG5EI512V 0xfc00707f
- -#define MATCH_VLXSEG6EI512V 0xbc006007
- -#define MASK_VLXSEG6EI512V 0xfc00707f
- -#define MATCH_VSXSEG6EI512V 0xbc006027
- -#define MASK_VSXSEG6EI512V 0xfc00707f
- -#define MATCH_VLXSEG7EI512V 0xdc006007
- -#define MASK_VLXSEG7EI512V 0xfc00707f
- -#define MATCH_VSXSEG7EI512V 0xdc006027
- -#define MASK_VSXSEG7EI512V 0xfc00707f
- -#define MATCH_VLXSEG8EI512V 0xfc006007
- -#define MASK_VLXSEG8EI512V 0xfc00707f
- -#define MATCH_VSXSEG8EI512V 0xfc006027
- -#define MASK_VSXSEG8EI512V 0xfc00707f
- -
- -#define MATCH_VLXSEG2EI1024V 0x3c007007
- -#define MASK_VLXSEG2EI1024V 0xfc00707f
- -#define MATCH_VSXSEG2EI1024V 0x3c007027
- -#define MASK_VSXSEG2EI1024V 0xfc00707f
- -#define MATCH_VLXSEG3EI1024V 0x5c007007
- -#define MASK_VLXSEG3EI1024V 0xfc00707f
- -#define MATCH_VSXSEG3EI1024V 0x5c007027
- -#define MASK_VSXSEG3EI1024V 0xfc00707f
- -#define MATCH_VLXSEG4EI1024V 0x7c007007
- -#define MASK_VLXSEG4EI1024V 0xfc00707f
- -#define MATCH_VSXSEG4EI1024V 0x7c007027
- -#define MASK_VSXSEG4EI1024V 0xfc00707f
- -#define MATCH_VLXSEG5EI1024V 0x9c007007
- -#define MASK_VLXSEG5EI1024V 0xfc00707f
- -#define MATCH_VSXSEG5EI1024V 0x9c007027
- -#define MASK_VSXSEG5EI1024V 0xfc00707f
- -#define MATCH_VLXSEG6EI1024V 0xbc007007
- -#define MASK_VLXSEG6EI1024V 0xfc00707f
- -#define MATCH_VSXSEG6EI1024V 0xbc007027
- -#define MASK_VSXSEG6EI1024V 0xfc00707f
- -#define MATCH_VLXSEG7EI1024V 0xdc007007
- -#define MASK_VLXSEG7EI1024V 0xfc00707f
- -#define MATCH_VSXSEG7EI1024V 0xdc007027
- -#define MASK_VSXSEG7EI1024V 0xfc00707f
- -#define MATCH_VLXSEG8EI1024V 0xfc007007
- -#define MASK_VLXSEG8EI1024V 0xfc00707f
- -#define MATCH_VSXSEG8EI1024V 0xfc007027
- -#define MASK_VSXSEG8EI1024V 0xfc00707f
- +#define MATCH_VLOXSEG2EI8V 0x2c000007
- +#define MASK_VLOXSEG2EI8V 0xfc00707f
- +#define MATCH_VSOXSEG2EI8V 0x2c000027
- +#define MASK_VSOXSEG2EI8V 0xfc00707f
- +#define MATCH_VLOXSEG3EI8V 0x4c000007
- +#define MASK_VLOXSEG3EI8V 0xfc00707f
- +#define MATCH_VSOXSEG3EI8V 0x4c000027
- +#define MASK_VSOXSEG3EI8V 0xfc00707f
- +#define MATCH_VLOXSEG4EI8V 0x6c000007
- +#define MASK_VLOXSEG4EI8V 0xfc00707f
- +#define MATCH_VSOXSEG4EI8V 0x6c000027
- +#define MASK_VSOXSEG4EI8V 0xfc00707f
- +#define MATCH_VLOXSEG5EI8V 0x8c000007
- +#define MASK_VLOXSEG5EI8V 0xfc00707f
- +#define MATCH_VSOXSEG5EI8V 0x8c000027
- +#define MASK_VSOXSEG5EI8V 0xfc00707f
- +#define MATCH_VLOXSEG6EI8V 0xac000007
- +#define MASK_VLOXSEG6EI8V 0xfc00707f
- +#define MATCH_VSOXSEG6EI8V 0xac000027
- +#define MASK_VSOXSEG6EI8V 0xfc00707f
- +#define MATCH_VLOXSEG7EI8V 0xcc000007
- +#define MASK_VLOXSEG7EI8V 0xfc00707f
- +#define MATCH_VSOXSEG7EI8V 0xcc000027
- +#define MASK_VSOXSEG7EI8V 0xfc00707f
- +#define MATCH_VLOXSEG8EI8V 0xec000007
- +#define MASK_VLOXSEG8EI8V 0xfc00707f
- +#define MATCH_VSOXSEG8EI8V 0xec000027
- +#define MASK_VSOXSEG8EI8V 0xfc00707f
- +
- +#define MATCH_VLUXSEG2EI8V 0x24000007
- +#define MASK_VLUXSEG2EI8V 0xfc00707f
- +#define MATCH_VSUXSEG2EI8V 0x24000027
- +#define MASK_VSUXSEG2EI8V 0xfc00707f
- +#define MATCH_VLUXSEG3EI8V 0x44000007
- +#define MASK_VLUXSEG3EI8V 0xfc00707f
- +#define MATCH_VSUXSEG3EI8V 0x44000027
- +#define MASK_VSUXSEG3EI8V 0xfc00707f
- +#define MATCH_VLUXSEG4EI8V 0x64000007
- +#define MASK_VLUXSEG4EI8V 0xfc00707f
- +#define MATCH_VSUXSEG4EI8V 0x64000027
- +#define MASK_VSUXSEG4EI8V 0xfc00707f
- +#define MATCH_VLUXSEG5EI8V 0x84000007
- +#define MASK_VLUXSEG5EI8V 0xfc00707f
- +#define MATCH_VSUXSEG5EI8V 0x84000027
- +#define MASK_VSUXSEG5EI8V 0xfc00707f
- +#define MATCH_VLUXSEG6EI8V 0xa4000007
- +#define MASK_VLUXSEG6EI8V 0xfc00707f
- +#define MATCH_VSUXSEG6EI8V 0xa4000027
- +#define MASK_VSUXSEG6EI8V 0xfc00707f
- +#define MATCH_VLUXSEG7EI8V 0xc4000007
- +#define MASK_VLUXSEG7EI8V 0xfc00707f
- +#define MATCH_VSUXSEG7EI8V 0xc4000027
- +#define MASK_VSUXSEG7EI8V 0xfc00707f
- +#define MATCH_VLUXSEG8EI8V 0xe4000007
- +#define MASK_VLUXSEG8EI8V 0xfc00707f
- +#define MATCH_VSUXSEG8EI8V 0xe4000027
- +#define MASK_VSUXSEG8EI8V 0xfc00707f
- +
- +#define MATCH_VLOXSEG2EI16V 0x2c005007
- +#define MASK_VLOXSEG2EI16V 0xfc00707f
- +#define MATCH_VSOXSEG2EI16V 0x2c005027
- +#define MASK_VSOXSEG2EI16V 0xfc00707f
- +#define MATCH_VLOXSEG3EI16V 0x4c005007
- +#define MASK_VLOXSEG3EI16V 0xfc00707f
- +#define MATCH_VSOXSEG3EI16V 0x4c005027
- +#define MASK_VSOXSEG3EI16V 0xfc00707f
- +#define MATCH_VLOXSEG4EI16V 0x6c005007
- +#define MASK_VLOXSEG4EI16V 0xfc00707f
- +#define MATCH_VSOXSEG4EI16V 0x6c005027
- +#define MASK_VSOXSEG4EI16V 0xfc00707f
- +#define MATCH_VLOXSEG5EI16V 0x8c005007
- +#define MASK_VLOXSEG5EI16V 0xfc00707f
- +#define MATCH_VSOXSEG5EI16V 0x8c005027
- +#define MASK_VSOXSEG5EI16V 0xfc00707f
- +#define MATCH_VLOXSEG6EI16V 0xac005007
- +#define MASK_VLOXSEG6EI16V 0xfc00707f
- +#define MATCH_VSOXSEG6EI16V 0xac005027
- +#define MASK_VSOXSEG6EI16V 0xfc00707f
- +#define MATCH_VLOXSEG7EI16V 0xcc005007
- +#define MASK_VLOXSEG7EI16V 0xfc00707f
- +#define MATCH_VSOXSEG7EI16V 0xcc005027
- +#define MASK_VSOXSEG7EI16V 0xfc00707f
- +#define MATCH_VLOXSEG8EI16V 0xec005007
- +#define MASK_VLOXSEG8EI16V 0xfc00707f
- +#define MATCH_VSOXSEG8EI16V 0xec005027
- +#define MASK_VSOXSEG8EI16V 0xfc00707f
- +
- +#define MATCH_VLUXSEG2EI16V 0x24005007
- +#define MASK_VLUXSEG2EI16V 0xfc00707f
- +#define MATCH_VSUXSEG2EI16V 0x24005027
- +#define MASK_VSUXSEG2EI16V 0xfc00707f
- +#define MATCH_VLUXSEG3EI16V 0x44005007
- +#define MASK_VLUXSEG3EI16V 0xfc00707f
- +#define MATCH_VSUXSEG3EI16V 0x44005027
- +#define MASK_VSUXSEG3EI16V 0xfc00707f
- +#define MATCH_VLUXSEG4EI16V 0x64005007
- +#define MASK_VLUXSEG4EI16V 0xfc00707f
- +#define MATCH_VSUXSEG4EI16V 0x64005027
- +#define MASK_VSUXSEG4EI16V 0xfc00707f
- +#define MATCH_VLUXSEG5EI16V 0x84005007
- +#define MASK_VLUXSEG5EI16V 0xfc00707f
- +#define MATCH_VSUXSEG5EI16V 0x84005027
- +#define MASK_VSUXSEG5EI16V 0xfc00707f
- +#define MATCH_VLUXSEG6EI16V 0xa4005007
- +#define MASK_VLUXSEG6EI16V 0xfc00707f
- +#define MATCH_VSUXSEG6EI16V 0xa4005027
- +#define MASK_VSUXSEG6EI16V 0xfc00707f
- +#define MATCH_VLUXSEG7EI16V 0xc4005007
- +#define MASK_VLUXSEG7EI16V 0xfc00707f
- +#define MATCH_VSUXSEG7EI16V 0xc4005027
- +#define MASK_VSUXSEG7EI16V 0xfc00707f
- +#define MATCH_VLUXSEG8EI16V 0xe4005007
- +#define MASK_VLUXSEG8EI16V 0xfc00707f
- +#define MATCH_VSUXSEG8EI16V 0xe4005027
- +#define MASK_VSUXSEG8EI16V 0xfc00707f
- +
- +#define MATCH_VLOXSEG2EI32V 0x2c006007
- +#define MASK_VLOXSEG2EI32V 0xfc00707f
- +#define MATCH_VSOXSEG2EI32V 0x2c006027
- +#define MASK_VSOXSEG2EI32V 0xfc00707f
- +#define MATCH_VLOXSEG3EI32V 0x4c006007
- +#define MASK_VLOXSEG3EI32V 0xfc00707f
- +#define MATCH_VSOXSEG3EI32V 0x4c006027
- +#define MASK_VSOXSEG3EI32V 0xfc00707f
- +#define MATCH_VLOXSEG4EI32V 0x6c006007
- +#define MASK_VLOXSEG4EI32V 0xfc00707f
- +#define MATCH_VSOXSEG4EI32V 0x6c006027
- +#define MASK_VSOXSEG4EI32V 0xfc00707f
- +#define MATCH_VLOXSEG5EI32V 0x8c006007
- +#define MASK_VLOXSEG5EI32V 0xfc00707f
- +#define MATCH_VSOXSEG5EI32V 0x8c006027
- +#define MASK_VSOXSEG5EI32V 0xfc00707f
- +#define MATCH_VLOXSEG6EI32V 0xac006007
- +#define MASK_VLOXSEG6EI32V 0xfc00707f
- +#define MATCH_VSOXSEG6EI32V 0xac006027
- +#define MASK_VSOXSEG6EI32V 0xfc00707f
- +#define MATCH_VLOXSEG7EI32V 0xcc006007
- +#define MASK_VLOXSEG7EI32V 0xfc00707f
- +#define MATCH_VSOXSEG7EI32V 0xcc006027
- +#define MASK_VSOXSEG7EI32V 0xfc00707f
- +#define MATCH_VLOXSEG8EI32V 0xec006007
- +#define MASK_VLOXSEG8EI32V 0xfc00707f
- +#define MATCH_VSOXSEG8EI32V 0xec006027
- +#define MASK_VSOXSEG8EI32V 0xfc00707f
- +
- +#define MATCH_VLUXSEG2EI32V 0x24006007
- +#define MASK_VLUXSEG2EI32V 0xfc00707f
- +#define MATCH_VSUXSEG2EI32V 0x24006027
- +#define MASK_VSUXSEG2EI32V 0xfc00707f
- +#define MATCH_VLUXSEG3EI32V 0x44006007
- +#define MASK_VLUXSEG3EI32V 0xfc00707f
- +#define MATCH_VSUXSEG3EI32V 0x44006027
- +#define MASK_VSUXSEG3EI32V 0xfc00707f
- +#define MATCH_VLUXSEG4EI32V 0x64006007
- +#define MASK_VLUXSEG4EI32V 0xfc00707f
- +#define MATCH_VSUXSEG4EI32V 0x64006027
- +#define MASK_VSUXSEG4EI32V 0xfc00707f
- +#define MATCH_VLUXSEG5EI32V 0x84006007
- +#define MASK_VLUXSEG5EI32V 0xfc00707f
- +#define MATCH_VSUXSEG5EI32V 0x84006027
- +#define MASK_VSUXSEG5EI32V 0xfc00707f
- +#define MATCH_VLUXSEG6EI32V 0xa4006007
- +#define MASK_VLUXSEG6EI32V 0xfc00707f
- +#define MATCH_VSUXSEG6EI32V 0xa4006027
- +#define MASK_VSUXSEG6EI32V 0xfc00707f
- +#define MATCH_VLUXSEG7EI32V 0xc4006007
- +#define MASK_VLUXSEG7EI32V 0xfc00707f
- +#define MATCH_VSUXSEG7EI32V 0xc4006027
- +#define MASK_VSUXSEG7EI32V 0xfc00707f
- +#define MATCH_VLUXSEG8EI32V 0xe4006007
- +#define MASK_VLUXSEG8EI32V 0xfc00707f
- +#define MATCH_VSUXSEG8EI32V 0xe4006027
- +#define MASK_VSUXSEG8EI32V 0xfc00707f
- +
- +#define MATCH_VLOXSEG2EI64V 0x2c007007
- +#define MASK_VLOXSEG2EI64V 0xfc00707f
- +#define MATCH_VSOXSEG2EI64V 0x2c007027
- +#define MASK_VSOXSEG2EI64V 0xfc00707f
- +#define MATCH_VLOXSEG3EI64V 0x4c007007
- +#define MASK_VLOXSEG3EI64V 0xfc00707f
- +#define MATCH_VSOXSEG3EI64V 0x4c007027
- +#define MASK_VSOXSEG3EI64V 0xfc00707f
- +#define MATCH_VLOXSEG4EI64V 0x6c007007
- +#define MASK_VLOXSEG4EI64V 0xfc00707f
- +#define MATCH_VSOXSEG4EI64V 0x6c007027
- +#define MASK_VSOXSEG4EI64V 0xfc00707f
- +#define MATCH_VLOXSEG5EI64V 0x8c007007
- +#define MASK_VLOXSEG5EI64V 0xfc00707f
- +#define MATCH_VSOXSEG5EI64V 0x8c007027
- +#define MASK_VSOXSEG5EI64V 0xfc00707f
- +#define MATCH_VLOXSEG6EI64V 0xac007007
- +#define MASK_VLOXSEG6EI64V 0xfc00707f
- +#define MATCH_VSOXSEG6EI64V 0xac007027
- +#define MASK_VSOXSEG6EI64V 0xfc00707f
- +#define MATCH_VLOXSEG7EI64V 0xcc007007
- +#define MASK_VLOXSEG7EI64V 0xfc00707f
- +#define MATCH_VSOXSEG7EI64V 0xcc007027
- +#define MASK_VSOXSEG7EI64V 0xfc00707f
- +#define MATCH_VLOXSEG8EI64V 0xec007007
- +#define MASK_VLOXSEG8EI64V 0xfc00707f
- +#define MATCH_VSOXSEG8EI64V 0xec007027
- +#define MASK_VSOXSEG8EI64V 0xfc00707f
- +
- +#define MATCH_VLUXSEG2EI64V 0x24007007
- +#define MASK_VLUXSEG2EI64V 0xfc00707f
- +#define MATCH_VSUXSEG2EI64V 0x24007027
- +#define MASK_VSUXSEG2EI64V 0xfc00707f
- +#define MATCH_VLUXSEG3EI64V 0x44007007
- +#define MASK_VLUXSEG3EI64V 0xfc00707f
- +#define MATCH_VSUXSEG3EI64V 0x44007027
- +#define MASK_VSUXSEG3EI64V 0xfc00707f
- +#define MATCH_VLUXSEG4EI64V 0x64007007
- +#define MASK_VLUXSEG4EI64V 0xfc00707f
- +#define MATCH_VSUXSEG4EI64V 0x64007027
- +#define MASK_VSUXSEG4EI64V 0xfc00707f
- +#define MATCH_VLUXSEG5EI64V 0x84007007
- +#define MASK_VLUXSEG5EI64V 0xfc00707f
- +#define MATCH_VSUXSEG5EI64V 0x84007027
- +#define MASK_VSUXSEG5EI64V 0xfc00707f
- +#define MATCH_VLUXSEG6EI64V 0xa4007007
- +#define MASK_VLUXSEG6EI64V 0xfc00707f
- +#define MATCH_VSUXSEG6EI64V 0xa4007027
- +#define MASK_VSUXSEG6EI64V 0xfc00707f
- +#define MATCH_VLUXSEG7EI64V 0xc4007007
- +#define MASK_VLUXSEG7EI64V 0xfc00707f
- +#define MATCH_VSUXSEG7EI64V 0xc4007027
- +#define MASK_VSUXSEG7EI64V 0xfc00707f
- +#define MATCH_VLUXSEG8EI64V 0xe4007007
- +#define MASK_VLUXSEG8EI64V 0xfc00707f
- +#define MATCH_VSUXSEG8EI64V 0xe4007027
- +#define MASK_VSUXSEG8EI64V 0xfc00707f
- +
- +#define MATCH_VLOXSEG2EI128V 0x3c000007
- +#define MASK_VLOXSEG2EI128V 0xfc00707f
- +#define MATCH_VSOXSEG2EI128V 0x3c000027
- +#define MASK_VSOXSEG2EI128V 0xfc00707f
- +#define MATCH_VLOXSEG3EI128V 0x5c000007
- +#define MASK_VLOXSEG3EI128V 0xfc00707f
- +#define MATCH_VSOXSEG3EI128V 0x5c000027
- +#define MASK_VSOXSEG3EI128V 0xfc00707f
- +#define MATCH_VLOXSEG4EI128V 0x7c000007
- +#define MASK_VLOXSEG4EI128V 0xfc00707f
- +#define MATCH_VSOXSEG4EI128V 0x7c000027
- +#define MASK_VSOXSEG4EI128V 0xfc00707f
- +#define MATCH_VLOXSEG5EI128V 0x9c000007
- +#define MASK_VLOXSEG5EI128V 0xfc00707f
- +#define MATCH_VSOXSEG5EI128V 0x9c000027
- +#define MASK_VSOXSEG5EI128V 0xfc00707f
- +#define MATCH_VLOXSEG6EI128V 0xbc000007
- +#define MASK_VLOXSEG6EI128V 0xfc00707f
- +#define MATCH_VSOXSEG6EI128V 0xbc000027
- +#define MASK_VSOXSEG6EI128V 0xfc00707f
- +#define MATCH_VLOXSEG7EI128V 0xdc000007
- +#define MASK_VLOXSEG7EI128V 0xfc00707f
- +#define MATCH_VSOXSEG7EI128V 0xdc000027
- +#define MASK_VSOXSEG7EI128V 0xfc00707f
- +#define MATCH_VLOXSEG8EI128V 0xfc000007
- +#define MASK_VLOXSEG8EI128V 0xfc00707f
- +#define MATCH_VSOXSEG8EI128V 0xfc000027
- +#define MASK_VSOXSEG8EI128V 0xfc00707f
- +
- +#define MATCH_VLUXSEG2EI128V 0x34000007
- +#define MASK_VLUXSEG2EI128V 0xfc00707f
- +#define MATCH_VSUXSEG2EI128V 0x34000027
- +#define MASK_VSUXSEG2EI128V 0xfc00707f
- +#define MATCH_VLUXSEG3EI128V 0x54000007
- +#define MASK_VLUXSEG3EI128V 0xfc00707f
- +#define MATCH_VSUXSEG3EI128V 0x54000027
- +#define MASK_VSUXSEG3EI128V 0xfc00707f
- +#define MATCH_VLUXSEG4EI128V 0x74000007
- +#define MASK_VLUXSEG4EI128V 0xfc00707f
- +#define MATCH_VSUXSEG4EI128V 0x74000027
- +#define MASK_VSUXSEG4EI128V 0xfc00707f
- +#define MATCH_VLUXSEG5EI128V 0x94000007
- +#define MASK_VLUXSEG5EI128V 0xfc00707f
- +#define MATCH_VSUXSEG5EI128V 0x94000027
- +#define MASK_VSUXSEG5EI128V 0xfc00707f
- +#define MATCH_VLUXSEG6EI128V 0xb4000007
- +#define MASK_VLUXSEG6EI128V 0xfc00707f
- +#define MATCH_VSUXSEG6EI128V 0xb4000027
- +#define MASK_VSUXSEG6EI128V 0xfc00707f
- +#define MATCH_VLUXSEG7EI128V 0xd4000007
- +#define MASK_VLUXSEG7EI128V 0xfc00707f
- +#define MATCH_VSUXSEG7EI128V 0xd4000027
- +#define MASK_VSUXSEG7EI128V 0xfc00707f
- +#define MATCH_VLUXSEG8EI128V 0xf4000007
- +#define MASK_VLUXSEG8EI128V 0xfc00707f
- +#define MATCH_VSUXSEG8EI128V 0xf4000027
- +#define MASK_VSUXSEG8EI128V 0xfc00707f
- +
- +#define MATCH_VLOXSEG2EI256V 0x3c005007
- +#define MASK_VLOXSEG2EI256V 0xfc00707f
- +#define MATCH_VSOXSEG2EI256V 0x3c005027
- +#define MASK_VSOXSEG2EI256V 0xfc00707f
- +#define MATCH_VLOXSEG3EI256V 0x5c005007
- +#define MASK_VLOXSEG3EI256V 0xfc00707f
- +#define MATCH_VSOXSEG3EI256V 0x5c005027
- +#define MASK_VSOXSEG3EI256V 0xfc00707f
- +#define MATCH_VLOXSEG4EI256V 0x7c005007
- +#define MASK_VLOXSEG4EI256V 0xfc00707f
- +#define MATCH_VSOXSEG4EI256V 0x7c005027
- +#define MASK_VSOXSEG4EI256V 0xfc00707f
- +#define MATCH_VLOXSEG5EI256V 0x9c005007
- +#define MASK_VLOXSEG5EI256V 0xfc00707f
- +#define MATCH_VSOXSEG5EI256V 0x9c005027
- +#define MASK_VSOXSEG5EI256V 0xfc00707f
- +#define MATCH_VLOXSEG6EI256V 0xbc005007
- +#define MASK_VLOXSEG6EI256V 0xfc00707f
- +#define MATCH_VSOXSEG6EI256V 0xbc005027
- +#define MASK_VSOXSEG6EI256V 0xfc00707f
- +#define MATCH_VLOXSEG7EI256V 0xdc005007
- +#define MASK_VLOXSEG7EI256V 0xfc00707f
- +#define MATCH_VSOXSEG7EI256V 0xdc005027
- +#define MASK_VSOXSEG7EI256V 0xfc00707f
- +#define MATCH_VLOXSEG8EI256V 0xfc005007
- +#define MASK_VLOXSEG8EI256V 0xfc00707f
- +#define MATCH_VSOXSEG8EI256V 0xfc005027
- +#define MASK_VSOXSEG8EI256V 0xfc00707f
- +
- +#define MATCH_VLUXSEG2EI256V 0x34005007
- +#define MASK_VLUXSEG2EI256V 0xfc00707f
- +#define MATCH_VSUXSEG2EI256V 0x34005027
- +#define MASK_VSUXSEG2EI256V 0xfc00707f
- +#define MATCH_VLUXSEG3EI256V 0x54005007
- +#define MASK_VLUXSEG3EI256V 0xfc00707f
- +#define MATCH_VSUXSEG3EI256V 0x54005027
- +#define MASK_VSUXSEG3EI256V 0xfc00707f
- +#define MATCH_VLUXSEG4EI256V 0x74005007
- +#define MASK_VLUXSEG4EI256V 0xfc00707f
- +#define MATCH_VSUXSEG4EI256V 0x74005027
- +#define MASK_VSUXSEG4EI256V 0xfc00707f
- +#define MATCH_VLUXSEG5EI256V 0x94005007
- +#define MASK_VLUXSEG5EI256V 0xfc00707f
- +#define MATCH_VSUXSEG5EI256V 0x94005027
- +#define MASK_VSUXSEG5EI256V 0xfc00707f
- +#define MATCH_VLUXSEG6EI256V 0xb4005007
- +#define MASK_VLUXSEG6EI256V 0xfc00707f
- +#define MATCH_VSUXSEG6EI256V 0xb4005027
- +#define MASK_VSUXSEG6EI256V 0xfc00707f
- +#define MATCH_VLUXSEG7EI256V 0xd4005007
- +#define MASK_VLUXSEG7EI256V 0xfc00707f
- +#define MATCH_VSUXSEG7EI256V 0xd4005027
- +#define MASK_VSUXSEG7EI256V 0xfc00707f
- +#define MATCH_VLUXSEG8EI256V 0xf4005007
- +#define MASK_VLUXSEG8EI256V 0xfc00707f
- +#define MATCH_VSUXSEG8EI256V 0xf4005027
- +#define MASK_VSUXSEG8EI256V 0xfc00707f
- +
- +#define MATCH_VLOXSEG2EI512V 0x3c006007
- +#define MASK_VLOXSEG2EI512V 0xfc00707f
- +#define MATCH_VSOXSEG2EI512V 0x3c006027
- +#define MASK_VSOXSEG2EI512V 0xfc00707f
- +#define MATCH_VLOXSEG3EI512V 0x5c006007
- +#define MASK_VLOXSEG3EI512V 0xfc00707f
- +#define MATCH_VSOXSEG3EI512V 0x5c006027
- +#define MASK_VSOXSEG3EI512V 0xfc00707f
- +#define MATCH_VLOXSEG4EI512V 0x7c006007
- +#define MASK_VLOXSEG4EI512V 0xfc00707f
- +#define MATCH_VSOXSEG4EI512V 0x7c006027
- +#define MASK_VSOXSEG4EI512V 0xfc00707f
- +#define MATCH_VLOXSEG5EI512V 0x9c006007
- +#define MASK_VLOXSEG5EI512V 0xfc00707f
- +#define MATCH_VSOXSEG5EI512V 0x9c006027
- +#define MASK_VSOXSEG5EI512V 0xfc00707f
- +#define MATCH_VLOXSEG6EI512V 0xbc006007
- +#define MASK_VLOXSEG6EI512V 0xfc00707f
- +#define MATCH_VSOXSEG6EI512V 0xbc006027
- +#define MASK_VSOXSEG6EI512V 0xfc00707f
- +#define MATCH_VLOXSEG7EI512V 0xdc006007
- +#define MASK_VLOXSEG7EI512V 0xfc00707f
- +#define MATCH_VSOXSEG7EI512V 0xdc006027
- +#define MASK_VSOXSEG7EI512V 0xfc00707f
- +#define MATCH_VLOXSEG8EI512V 0xfc006007
- +#define MASK_VLOXSEG8EI512V 0xfc00707f
- +#define MATCH_VSOXSEG8EI512V 0xfc006027
- +#define MASK_VSOXSEG8EI512V 0xfc00707f
- +
- +#define MATCH_VLUXSEG2EI512V 0x34006007
- +#define MASK_VLUXSEG2EI512V 0xfc00707f
- +#define MATCH_VSUXSEG2EI512V 0x34006027
- +#define MASK_VSUXSEG2EI512V 0xfc00707f
- +#define MATCH_VLUXSEG3EI512V 0x54006007
- +#define MASK_VLUXSEG3EI512V 0xfc00707f
- +#define MATCH_VSUXSEG3EI512V 0x54006027
- +#define MASK_VSUXSEG3EI512V 0xfc00707f
- +#define MATCH_VLUXSEG4EI512V 0x74006007
- +#define MASK_VLUXSEG4EI512V 0xfc00707f
- +#define MATCH_VSUXSEG4EI512V 0x74006027
- +#define MASK_VSUXSEG4EI512V 0xfc00707f
- +#define MATCH_VLUXSEG5EI512V 0x94006007
- +#define MASK_VLUXSEG5EI512V 0xfc00707f
- +#define MATCH_VSUXSEG5EI512V 0x94006027
- +#define MASK_VSUXSEG5EI512V 0xfc00707f
- +#define MATCH_VLUXSEG6EI512V 0xb4006007
- +#define MASK_VLUXSEG6EI512V 0xfc00707f
- +#define MATCH_VSUXSEG6EI512V 0xb4006027
- +#define MASK_VSUXSEG6EI512V 0xfc00707f
- +#define MATCH_VLUXSEG7EI512V 0xd4006007
- +#define MASK_VLUXSEG7EI512V 0xfc00707f
- +#define MATCH_VSUXSEG7EI512V 0xd4006027
- +#define MASK_VSUXSEG7EI512V 0xfc00707f
- +#define MATCH_VLUXSEG8EI512V 0xf4006007
- +#define MASK_VLUXSEG8EI512V 0xfc00707f
- +#define MATCH_VSUXSEG8EI512V 0xf4006027
- +#define MASK_VSUXSEG8EI512V 0xfc00707f
- +
- +#define MATCH_VLOXSEG2EI1024V 0x3c007007
- +#define MASK_VLOXSEG2EI1024V 0xfc00707f
- +#define MATCH_VSOXSEG2EI1024V 0x3c007027
- +#define MASK_VSOXSEG2EI1024V 0xfc00707f
- +#define MATCH_VLOXSEG3EI1024V 0x5c007007
- +#define MASK_VLOXSEG3EI1024V 0xfc00707f
- +#define MATCH_VSOXSEG3EI1024V 0x5c007027
- +#define MASK_VSOXSEG3EI1024V 0xfc00707f
- +#define MATCH_VLOXSEG4EI1024V 0x7c007007
- +#define MASK_VLOXSEG4EI1024V 0xfc00707f
- +#define MATCH_VSOXSEG4EI1024V 0x7c007027
- +#define MASK_VSOXSEG4EI1024V 0xfc00707f
- +#define MATCH_VLOXSEG5EI1024V 0x9c007007
- +#define MASK_VLOXSEG5EI1024V 0xfc00707f
- +#define MATCH_VSOXSEG5EI1024V 0x9c007027
- +#define MASK_VSOXSEG5EI1024V 0xfc00707f
- +#define MATCH_VLOXSEG6EI1024V 0xbc007007
- +#define MASK_VLOXSEG6EI1024V 0xfc00707f
- +#define MATCH_VSOXSEG6EI1024V 0xbc007027
- +#define MASK_VSOXSEG6EI1024V 0xfc00707f
- +#define MATCH_VLOXSEG7EI1024V 0xdc007007
- +#define MASK_VLOXSEG7EI1024V 0xfc00707f
- +#define MATCH_VSOXSEG7EI1024V 0xdc007027
- +#define MASK_VSOXSEG7EI1024V 0xfc00707f
- +#define MATCH_VLOXSEG8EI1024V 0xfc007007
- +#define MASK_VLOXSEG8EI1024V 0xfc00707f
- +#define MATCH_VSOXSEG8EI1024V 0xfc007027
- +#define MASK_VSOXSEG8EI1024V 0xfc00707f
- +
- +#define MATCH_VLUXSEG2EI1024V 0x34007007
- +#define MASK_VLUXSEG2EI1024V 0xfc00707f
- +#define MATCH_VSUXSEG2EI1024V 0x34007027
- +#define MASK_VSUXSEG2EI1024V 0xfc00707f
- +#define MATCH_VLUXSEG3EI1024V 0x54007007
- +#define MASK_VLUXSEG3EI1024V 0xfc00707f
- +#define MATCH_VSUXSEG3EI1024V 0x54007027
- +#define MASK_VSUXSEG3EI1024V 0xfc00707f
- +#define MATCH_VLUXSEG4EI1024V 0x74007007
- +#define MASK_VLUXSEG4EI1024V 0xfc00707f
- +#define MATCH_VSUXSEG4EI1024V 0x74007027
- +#define MASK_VSUXSEG4EI1024V 0xfc00707f
- +#define MATCH_VLUXSEG5EI1024V 0x94007007
- +#define MASK_VLUXSEG5EI1024V 0xfc00707f
- +#define MATCH_VSUXSEG5EI1024V 0x94007027
- +#define MASK_VSUXSEG5EI1024V 0xfc00707f
- +#define MATCH_VLUXSEG6EI1024V 0xb4007007
- +#define MASK_VLUXSEG6EI1024V 0xfc00707f
- +#define MATCH_VSUXSEG6EI1024V 0xb4007027
- +#define MASK_VSUXSEG6EI1024V 0xfc00707f
- +#define MATCH_VLUXSEG7EI1024V 0xd4007007
- +#define MASK_VLUXSEG7EI1024V 0xfc00707f
- +#define MATCH_VSUXSEG7EI1024V 0xd4007027
- +#define MASK_VSUXSEG7EI1024V 0xfc00707f
- +#define MATCH_VLUXSEG8EI1024V 0xf4007007
- +#define MASK_VLUXSEG8EI1024V 0xfc00707f
- +#define MATCH_VSUXSEG8EI1024V 0xf4007027
- +#define MASK_VSUXSEG8EI1024V 0xfc00707f
-
- #define MATCH_VLSEG2E8FFV 0x21000007
- #define MASK_VLSEG2E8FFV 0xfdf0707f
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index e0383d08e9..076aea5f91 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -1307,15 +1307,20 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vsse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_vd_neq_vm, INSN_DREF },
- {"vsse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_vd_neq_vm, INSN_DREF },
-
- -{"vlxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_vd_neq_vm, INSN_DREF },
- -{"vlxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_vd_neq_vm, INSN_DREF },
- -{"vlxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_vd_neq_vm, INSN_DREF },
- -{"vlxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_vd_neq_vm, INSN_DREF },
- +{"vloxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_vd_neq_vm, INSN_DREF },
- +{"vloxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_vd_neq_vm, INSN_DREF },
- +{"vloxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_vd_neq_vm, INSN_DREF },
- +{"vloxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_vd_neq_vm, INSN_DREF },
-
- -{"vsxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_vd_neq_vm, INSN_DREF },
- -{"vsxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_vd_neq_vm, INSN_DREF },
- -{"vsxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_vd_neq_vm, INSN_DREF },
- -{"vsxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_vd_neq_vm, INSN_DREF },
- +{"vsoxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_vd_neq_vm, INSN_DREF },
- +{"vsoxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_vd_neq_vm, INSN_DREF },
- +{"vsoxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
- +{"vsoxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
- +
- +{"vluxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_vd_neq_vm, INSN_DREF },
- +{"vluxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_vd_neq_vm, INSN_DREF },
- +{"vluxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_vd_neq_vm, INSN_DREF },
- +{"vluxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF },
-
- {"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
- {"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
- @@ -1571,125 +1576,245 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vlsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E1024V, MASK_VLSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
- {"vssseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
-
- -{"vlxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI8V, MASK_VLXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI8V, MASK_VSXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI8V, MASK_VLXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI8V, MASK_VSXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI8V, MASK_VLXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI8V, MASK_VSXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI8V, MASK_VLXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI8V, MASK_VSXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI8V, MASK_VLXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI8V, MASK_VSXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI8V, MASK_VLXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI8V, MASK_VSXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI8V, MASK_VLXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI8V, MASK_VSXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -
- -{"vlxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI16V, MASK_VLXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI16V, MASK_VSXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI16V, MASK_VLXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI16V, MASK_VSXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI16V, MASK_VLXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI16V, MASK_VSXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI16V, MASK_VLXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI16V, MASK_VSXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI16V, MASK_VLXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI16V, MASK_VSXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI16V, MASK_VLXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI16V, MASK_VSXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI16V, MASK_VLXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI16V, MASK_VSXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -
- -{"vlxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI32V, MASK_VLXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI32V, MASK_VSXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI32V, MASK_VLXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI32V, MASK_VSXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI32V, MASK_VLXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI32V, MASK_VSXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI32V, MASK_VLXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI32V, MASK_VSXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI32V, MASK_VLXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI32V, MASK_VSXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI32V, MASK_VLXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI32V, MASK_VSXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI32V, MASK_VLXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI32V, MASK_VSXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -
- -{"vlxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI64V, MASK_VLXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI64V, MASK_VSXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI64V, MASK_VLXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI64V, MASK_VSXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI64V, MASK_VLXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI64V, MASK_VSXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI64V, MASK_VLXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI64V, MASK_VSXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI64V, MASK_VLXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI64V, MASK_VSXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI64V, MASK_VLXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI64V, MASK_VSXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI64V, MASK_VLXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI64V, MASK_VSXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -
- -{"vlxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI128V, MASK_VLXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI128V, MASK_VSXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI128V, MASK_VLXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI128V, MASK_VSXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI128V, MASK_VLXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI128V, MASK_VSXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI128V, MASK_VLXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI128V, MASK_VSXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI128V, MASK_VLXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI128V, MASK_VSXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI128V, MASK_VLXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI128V, MASK_VSXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI128V, MASK_VLXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI128V, MASK_VSXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -
- -{"vlxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI256V, MASK_VLXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI256V, MASK_VSXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI256V, MASK_VLXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI256V, MASK_VSXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI256V, MASK_VLXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI256V, MASK_VSXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI256V, MASK_VLXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI256V, MASK_VSXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI256V, MASK_VLXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI256V, MASK_VSXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI256V, MASK_VLXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI256V, MASK_VSXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI256V, MASK_VLXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI256V, MASK_VSXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -
- -{"vlxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI512V, MASK_VLXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI512V, MASK_VSXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI512V, MASK_VLXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI512V, MASK_VSXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI512V, MASK_VLXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI512V, MASK_VSXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI512V, MASK_VLXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI512V, MASK_VSXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI512V, MASK_VLXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI512V, MASK_VSXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI512V, MASK_VLXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI512V, MASK_VSXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI512V, MASK_VLXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI512V, MASK_VSXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -
- -{"vlxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI1024V, MASK_VLXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI1024V, MASK_VSXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI1024V, MASK_VLXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI1024V, MASK_VSXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI1024V, MASK_VLXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI1024V, MASK_VSXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI1024V, MASK_VLXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI1024V, MASK_VSXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI1024V, MASK_VLXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI1024V, MASK_VSXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI1024V, MASK_VLXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI1024V, MASK_VSXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vlxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI1024V, MASK_VLXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- -{"vsxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI1024V, MASK_VSXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vloxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vloxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vloxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vloxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI128V, MASK_VLOXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI128V, MASK_VSOXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI128V, MASK_VLOXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI128V, MASK_VSOXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI128V, MASK_VLOXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI128V, MASK_VSOXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI128V, MASK_VLOXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI128V, MASK_VSOXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI128V, MASK_VLOXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI128V, MASK_VSOXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI128V, MASK_VLOXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI128V, MASK_VSOXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI128V, MASK_VLOXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI128V, MASK_VSOXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vloxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI256V, MASK_VLOXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI256V, MASK_VSOXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI256V, MASK_VLOXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI256V, MASK_VSOXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI256V, MASK_VLOXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI256V, MASK_VSOXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI256V, MASK_VLOXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI256V, MASK_VSOXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI256V, MASK_VLOXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI256V, MASK_VSOXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI256V, MASK_VLOXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI256V, MASK_VSOXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI256V, MASK_VLOXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI256V, MASK_VSOXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vloxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI512V, MASK_VLOXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI512V, MASK_VSOXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI512V, MASK_VLOXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI512V, MASK_VSOXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI512V, MASK_VLOXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI512V, MASK_VSOXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI512V, MASK_VLOXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI512V, MASK_VSOXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI512V, MASK_VLOXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI512V, MASK_VSOXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI512V, MASK_VLOXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI512V, MASK_VSOXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI512V, MASK_VLOXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI512V, MASK_VSOXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vloxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI1024V, MASK_VLOXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI1024V, MASK_VSOXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI1024V, MASK_VLOXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI1024V, MASK_VSOXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI1024V, MASK_VLOXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI1024V, MASK_VSOXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI1024V, MASK_VLOXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI1024V, MASK_VSOXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI1024V, MASK_VLOXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI1024V, MASK_VSOXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI1024V, MASK_VLOXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI1024V, MASK_VSOXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vloxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI1024V, MASK_VLOXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsoxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI1024V, MASK_VSOXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vluxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V, MASK_VLUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V, MASK_VSUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V, MASK_VLUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V, MASK_VSUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V, MASK_VLUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V, MASK_VSUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V, MASK_VLUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V, MASK_VSUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V, MASK_VLUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V, MASK_VSUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V, MASK_VLUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V, MASK_VSUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vluxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V, MASK_VLUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V, MASK_VSUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V, MASK_VLUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V, MASK_VSUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V, MASK_VLUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V, MASK_VSUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V, MASK_VLUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V, MASK_VSUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V, MASK_VLUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V, MASK_VSUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V, MASK_VLUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V, MASK_VSUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V, MASK_VLUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V, MASK_VSUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vluxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V, MASK_VLUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V, MASK_VSUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V, MASK_VLUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V, MASK_VSUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V, MASK_VLUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V, MASK_VSUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V, MASK_VLUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V, MASK_VSUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V, MASK_VLUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V, MASK_VSUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V, MASK_VLUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V, MASK_VSUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vluxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vluxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI128V, MASK_VLUXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI128V, MASK_VSUXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI128V, MASK_VLUXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI128V, MASK_VSUXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI128V, MASK_VLUXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI128V, MASK_VSUXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI128V, MASK_VLUXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI128V, MASK_VSUXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI128V, MASK_VLUXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI128V, MASK_VSUXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI128V, MASK_VLUXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI128V, MASK_VSUXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI128V, MASK_VLUXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI128V, MASK_VSUXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vluxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI256V, MASK_VLUXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI256V, MASK_VSUXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI256V, MASK_VLUXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI256V, MASK_VSUXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI256V, MASK_VLUXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI256V, MASK_VSUXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI256V, MASK_VLUXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI256V, MASK_VSUXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI256V, MASK_VLUXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI256V, MASK_VSUXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI256V, MASK_VLUXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI256V, MASK_VSUXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI256V, MASK_VLUXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI256V, MASK_VSUXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vluxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI512V, MASK_VLUXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI512V, MASK_VSUXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI512V, MASK_VLUXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI512V, MASK_VSUXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI512V, MASK_VLUXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI512V, MASK_VSUXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI512V, MASK_VLUXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI512V, MASK_VSUXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI512V, MASK_VLUXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI512V, MASK_VSUXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI512V, MASK_VLUXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI512V, MASK_VSUXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI512V, MASK_VLUXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI512V, MASK_VSUXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vluxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI1024V, MASK_VLUXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI1024V, MASK_VSUXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI1024V, MASK_VLUXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI1024V, MASK_VSUXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI1024V, MASK_VLUXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI1024V, MASK_VSUXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI1024V, MASK_VLUXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI1024V, MASK_VSUXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI1024V, MASK_VLUXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI1024V, MASK_VSUXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI1024V, MASK_VLUXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI1024V, MASK_VSUXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vluxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI1024V, MASK_VLUXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsuxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI1024V, MASK_VSUXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-
- {"vlseg2e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
- {"vlseg3e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
- --
- 2.33.0
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