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- From 2f7ac1fcdd1dda2c8a097ccf34e9c49482b8b781 Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Fri, 31 Jan 2020 14:47:51 +0800
- Subject: [PATCH 35/48] SiFive: Support SiFive specific cache control
- instructions.
- There are three cache control instructions,
- 1. CFLUSH.D.L1 RS1
- 2. CDISCARD.D.L1 RS1
- 3. CFLUSH.I.L1
- These instructions use the same funct3 0x0 [14:12]. CFLUSH.D.L1 use 0xfc000073
- opcode (0xfc0 [31:20] + 0x0 [11:7] + SYSTEM OP [6:2] + 0x3 [1:0]) with optional
- rs1. CDISCARD.D.L1 use 0xfc200073 opcode (0xfc2 [31:20], ...) with optional
- rs1. CFLUSH.I.L1 use 0xfc100073 opcode.
- ---
- gas/testsuite/gas/riscv/cache-control.d | 15 +++++++++++++++
- gas/testsuite/gas/riscv/cache-control.s | 7 +++++++
- include/opcode/riscv-opc.h | 10 ++++++++++
- opcodes/riscv-opc.c | 5 +++++
- 4 files changed, 37 insertions(+)
- create mode 100644 gas/testsuite/gas/riscv/cache-control.d
- create mode 100644 gas/testsuite/gas/riscv/cache-control.s
- diff --git a/gas/testsuite/gas/riscv/cache-control.d b/gas/testsuite/gas/riscv/cache-control.d
- new file mode 100644
- index 0000000000..b3c3be4a4d
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/cache-control.d
- @@ -0,0 +1,15 @@
- +#as: -march=rv32i
- +#objdump: -dr
- +
- +.*:[ ]+file format .*
- +
- +
- +Disassembly of section .text:
- +
- +0+000 <.text>:
- +[ ]+0:[ ]+fc050073[ ]+cflush.d.l1[ ]+a0
- +[ ]+4:[ ]+fc250073[ ]+cdiscard.d.l1[ ]+a0
- +[ ]+8:[ ]+fc100073[ ]+cflush.i.l1
- +[ ]+c:[ ]+fc050073[ ]+cflush.d.l1[ ]+a0
- +[ ]+10:[ ]+fc250073[ ]+cdiscard.d.l1[ ]+a0
- +[ ]+14:[ ]+fc100073[ ]+cflush.i.l1
- diff --git a/gas/testsuite/gas/riscv/cache-control.s b/gas/testsuite/gas/riscv/cache-control.s
- new file mode 100644
- index 0000000000..354bca169a
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/cache-control.s
- @@ -0,0 +1,7 @@
- + .insn i 0x73, 0, x0, x10, -0x40
- + .insn i 0x73, 0, x0, x10, -0x3E
- + .insn i 0x73, 0, x0, x0, -0x3F
- +
- + cflush.d.l1 x10
- + cdiscard.d.l1 x10
- + cflush.i.l1
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index 66e3f8f652..545bda3ed4 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -3094,6 +3094,13 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
- #define MASK_CUSTOM3_RD_RS1 0x707f
- #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
- #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
- +/* SiFive specific cache control instruction. */
- +#define MATCH_CFLUSH_D_L1 0xfc000073
- +#define MASK_CFLUSH_D_L1 0xfff07fff
- +#define MATCH_CDISCARD_D_L1 0xfc200073
- +#define MASK_CDISCARD_D_L1 0xfff07fff
- +#define MATCH_CFLUSH_I_L1 0xfc100073
- +#define MASK_CFLUSH_I_L1 0xffffffff
- /* Privileged CSR addresses (v1.11). */
- #define CSR_USTATUS 0x0
- #define CSR_UIE 0x4
- @@ -3673,6 +3680,9 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
- DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
- DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
- DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
- +DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1)
- +DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1)
- +DECLARE_INSN(cflush_i_l1, MATCH_CFLUSH_I_L1, MASK_CFLUSH_I_L1)
- #endif /* DECLARE_INSN. */
- #ifdef DECLARE_CSR
- /* Privileged. */
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index 7b258ee982..778c5d2f45 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -1267,6 +1267,11 @@ const struct riscv_opcode riscv_opcodes[] =
- {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
- {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
-
- +/* SiFive specific cache control instruction. */
- +{"cflush.d.l1", 0, INSN_CLASS_I, "s", MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1, match_opcode, 0 },
- +{"cdiscard.d.l1", 0, INSN_CLASS_I, "s", MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1, match_opcode, 0 },
- +{"cflush.i.l1", 0, INSN_CLASS_I, "", MATCH_CFLUSH_I_L1, MASK_CFLUSH_I_L1, match_opcode, 0 },
- +
- /* RVV */
- {"vsetvl", 0, INSN_CLASS_V, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
- {"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
- --
- 2.33.0
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