0035-SiFive-Support-SiFive-specific-cache-control-instruc.patch 4.1 KB

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  1. From 2f7ac1fcdd1dda2c8a097ccf34e9c49482b8b781 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Fri, 31 Jan 2020 14:47:51 +0800
  4. Subject: [PATCH 35/48] SiFive: Support SiFive specific cache control
  5. instructions.
  6. There are three cache control instructions,
  7. 1. CFLUSH.D.L1 RS1
  8. 2. CDISCARD.D.L1 RS1
  9. 3. CFLUSH.I.L1
  10. These instructions use the same funct3 0x0 [14:12]. CFLUSH.D.L1 use 0xfc000073
  11. opcode (0xfc0 [31:20] + 0x0 [11:7] + SYSTEM OP [6:2] + 0x3 [1:0]) with optional
  12. rs1. CDISCARD.D.L1 use 0xfc200073 opcode (0xfc2 [31:20], ...) with optional
  13. rs1. CFLUSH.I.L1 use 0xfc100073 opcode.
  14. ---
  15. gas/testsuite/gas/riscv/cache-control.d | 15 +++++++++++++++
  16. gas/testsuite/gas/riscv/cache-control.s | 7 +++++++
  17. include/opcode/riscv-opc.h | 10 ++++++++++
  18. opcodes/riscv-opc.c | 5 +++++
  19. 4 files changed, 37 insertions(+)
  20. create mode 100644 gas/testsuite/gas/riscv/cache-control.d
  21. create mode 100644 gas/testsuite/gas/riscv/cache-control.s
  22. diff --git a/gas/testsuite/gas/riscv/cache-control.d b/gas/testsuite/gas/riscv/cache-control.d
  23. new file mode 100644
  24. index 0000000000..b3c3be4a4d
  25. --- /dev/null
  26. +++ b/gas/testsuite/gas/riscv/cache-control.d
  27. @@ -0,0 +1,15 @@
  28. +#as: -march=rv32i
  29. +#objdump: -dr
  30. +
  31. +.*:[ ]+file format .*
  32. +
  33. +
  34. +Disassembly of section .text:
  35. +
  36. +0+000 <.text>:
  37. +[ ]+0:[ ]+fc050073[ ]+cflush.d.l1[ ]+a0
  38. +[ ]+4:[ ]+fc250073[ ]+cdiscard.d.l1[ ]+a0
  39. +[ ]+8:[ ]+fc100073[ ]+cflush.i.l1
  40. +[ ]+c:[ ]+fc050073[ ]+cflush.d.l1[ ]+a0
  41. +[ ]+10:[ ]+fc250073[ ]+cdiscard.d.l1[ ]+a0
  42. +[ ]+14:[ ]+fc100073[ ]+cflush.i.l1
  43. diff --git a/gas/testsuite/gas/riscv/cache-control.s b/gas/testsuite/gas/riscv/cache-control.s
  44. new file mode 100644
  45. index 0000000000..354bca169a
  46. --- /dev/null
  47. +++ b/gas/testsuite/gas/riscv/cache-control.s
  48. @@ -0,0 +1,7 @@
  49. + .insn i 0x73, 0, x0, x10, -0x40
  50. + .insn i 0x73, 0, x0, x10, -0x3E
  51. + .insn i 0x73, 0, x0, x0, -0x3F
  52. +
  53. + cflush.d.l1 x10
  54. + cdiscard.d.l1 x10
  55. + cflush.i.l1
  56. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  57. index 66e3f8f652..545bda3ed4 100644
  58. --- a/include/opcode/riscv-opc.h
  59. +++ b/include/opcode/riscv-opc.h
  60. @@ -3094,6 +3094,13 @@ funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  61. #define MASK_CUSTOM3_RD_RS1 0x707f
  62. #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
  63. #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
  64. +/* SiFive specific cache control instruction. */
  65. +#define MATCH_CFLUSH_D_L1 0xfc000073
  66. +#define MASK_CFLUSH_D_L1 0xfff07fff
  67. +#define MATCH_CDISCARD_D_L1 0xfc200073
  68. +#define MASK_CDISCARD_D_L1 0xfff07fff
  69. +#define MATCH_CFLUSH_I_L1 0xfc100073
  70. +#define MASK_CFLUSH_I_L1 0xffffffff
  71. /* Privileged CSR addresses (v1.11). */
  72. #define CSR_USTATUS 0x0
  73. #define CSR_UIE 0x4
  74. @@ -3673,6 +3680,9 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
  75. DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
  76. DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
  77. DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
  78. +DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1)
  79. +DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1)
  80. +DECLARE_INSN(cflush_i_l1, MATCH_CFLUSH_I_L1, MASK_CFLUSH_I_L1)
  81. #endif /* DECLARE_INSN. */
  82. #ifdef DECLARE_CSR
  83. /* Privileged. */
  84. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  85. index 7b258ee982..778c5d2f45 100644
  86. --- a/opcodes/riscv-opc.c
  87. +++ b/opcodes/riscv-opc.c
  88. @@ -1267,6 +1267,11 @@ const struct riscv_opcode riscv_opcodes[] =
  89. {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
  90. {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
  91. +/* SiFive specific cache control instruction. */
  92. +{"cflush.d.l1", 0, INSN_CLASS_I, "s", MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1, match_opcode, 0 },
  93. +{"cdiscard.d.l1", 0, INSN_CLASS_I, "s", MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1, match_opcode, 0 },
  94. +{"cflush.i.l1", 0, INSN_CLASS_I, "", MATCH_CFLUSH_I_L1, MASK_CFLUSH_I_L1, match_opcode, 0 },
  95. +
  96. /* RVV */
  97. {"vsetvl", 0, INSN_CLASS_V, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
  98. {"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
  99. --
  100. 2.33.0