0012-RISC-V-Support-RVV-according-to-vector-spec-v1.0-dra.patch 558 KB

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  1. From 9fc7114a93d01d5c4e656331ba38fcd0b0d458f9 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Wed, 8 Jul 2020 14:50:08 +0800
  4. Subject: [PATCH 12/48] RISC-V: Support RVV according to vector spec
  5. v1.0-draft-20200516.
  6. 2020-05-16 Jim Wilson <jimw@sifive.com>
  7. Kito Cheng <kito.cheng@sifive.com>
  8. Nelson Chu <nelson.chu@sifive.com>
  9. ---
  10. bfd/elfxx-riscv.c | 4 +-
  11. gas/config/tc-riscv.c | 438 ++-
  12. gas/testsuite/gas/riscv/csr-dw-regnums.d | 9 +-
  13. gas/testsuite/gas/riscv/csr-dw-regnums.s | 7 +
  14. gas/testsuite/gas/riscv/insn.d | 69 +-
  15. gas/testsuite/gas/riscv/insn.s | 84 +
  16. .../gas/riscv/march-fail-s-with-version | 2 +
  17. .../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
  18. .../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
  19. .../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
  20. gas/testsuite/gas/riscv/priv-reg-fail-vext.d | 3 +
  21. gas/testsuite/gas/riscv/priv-reg-fail-vext.l | 9 +
  22. .../gas/riscv/priv-reg-version-1p10.d | 9 +-
  23. .../gas/riscv/priv-reg-version-1p11.d | 9 +-
  24. .../gas/riscv/priv-reg-version-1p9p1.d | 9 +-
  25. gas/testsuite/gas/riscv/priv-reg.s | 9 +
  26. gas/testsuite/gas/riscv/v-zero-imm.d | 17 +
  27. gas/testsuite/gas/riscv/v-zero-imm.s | 8 +
  28. .../gas/riscv/vector-insns-fail-01.d | 3 +
  29. .../gas/riscv/vector-insns-fail-01.l | 393 +++
  30. .../gas/riscv/vector-insns-fail-01.s | 1037 +++++++
  31. .../gas/riscv/vector-insns-fail-02.d | 3 +
  32. .../gas/riscv/vector-insns-fail-02.l | 121 +
  33. .../gas/riscv/vector-insns-fail-02.s | 162 +
  34. .../gas/riscv/vector-insns-fail-03.d | 3 +
  35. .../gas/riscv/vector-insns-fail-03.l | 125 +
  36. .../gas/riscv/vector-insns-fail-03.s | 187 ++
  37. .../gas/riscv/vector-insns-fail-04.d | 3 +
  38. .../gas/riscv/vector-insns-fail-04.l | 49 +
  39. .../gas/riscv/vector-insns-fail-04.s | 85 +
  40. .../gas/riscv/vector-insns-fail-05.d | 3 +
  41. .../gas/riscv/vector-insns-fail-05.l | 61 +
  42. .../gas/riscv/vector-insns-fail-05.s | 133 +
  43. .../gas/riscv/vector-insns-fail-06.d | 3 +
  44. .../gas/riscv/vector-insns-fail-06.l | 22 +
  45. .../gas/riscv/vector-insns-fail-06.s | 67 +
  46. .../gas/riscv/vector-insns-fail-zvediv.d | 20 +
  47. .../gas/riscv/vector-insns-fail-zvediv.l | 6 +
  48. .../gas/riscv/vector-insns-fail-zvediv.s | 9 +
  49. .../gas/riscv/vector-insns-vmsgtvx.d | 29 +
  50. .../gas/riscv/vector-insns-vmsgtvx.s | 9 +
  51. gas/testsuite/gas/riscv/vector-insns.d | 2384 +++++++++++++++
  52. gas/testsuite/gas/riscv/vector-insns.s | 2718 +++++++++++++++++
  53. include/opcode/riscv-opc.h | 2138 +++++++++++++
  54. include/opcode/riscv.h | 99 +-
  55. opcodes/riscv-dis.c | 86 +-
  56. opcodes/riscv-opc.c | 1306 +++++++-
  57. 47 files changed, 11910 insertions(+), 46 deletions(-)
  58. create mode 100644 gas/testsuite/gas/riscv/march-fail-s-with-version
  59. create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-vext.d
  60. create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-vext.l
  61. create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.d
  62. create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.s
  63. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.d
  64. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.l
  65. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.s
  66. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.d
  67. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.l
  68. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.s
  69. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.d
  70. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.l
  71. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.s
  72. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.d
  73. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.l
  74. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.s
  75. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.d
  76. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.l
  77. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.s
  78. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.d
  79. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.l
  80. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.s
  81. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d
  82. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l
  83. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s
  84. create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
  85. create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
  86. create mode 100644 gas/testsuite/gas/riscv/vector-insns.d
  87. create mode 100644 gas/testsuite/gas/riscv/vector-insns.s
  88. diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
  89. index 86c0d94d0e..f797d28f59 100644
  90. --- a/bfd/elfxx-riscv.c
  91. +++ b/bfd/elfxx-riscv.c
  92. @@ -1566,7 +1566,9 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
  93. static const char * const riscv_std_z_ext_strtab[] =
  94. {
  95. - "zicsr", "zifencei", NULL
  96. + "zicsr", "zifencei",
  97. + "zvamo", "zvediv", "zvlsseg", "zvqmac",
  98. + NULL
  99. };
  100. static const char * const riscv_std_s_ext_strtab[] =
  101. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  102. index c21bb719d8..222214d7e4 100644
  103. --- a/gas/config/tc-riscv.c
  104. +++ b/gas/config/tc-riscv.c
  105. @@ -178,6 +178,7 @@ struct riscv_set_options
  106. int relax; /* Emit relocs the linker is allowed to relax. */
  107. int arch_attr; /* Emit arch attribute. */
  108. int csr_check; /* Enable the CSR checking. */
  109. + int check_constraints; /* Enable/disable the match_func checking. */
  110. };
  111. static struct riscv_set_options riscv_opts =
  112. @@ -187,7 +188,8 @@ static struct riscv_set_options riscv_opts =
  113. 0, /* rve */
  114. 1, /* relax */
  115. DEFAULT_RISCV_ATTR, /* arch_attr */
  116. - 0. /* csr_check */
  117. + 0, /* csr_check */
  118. + 0, /* check_constraints */
  119. };
  120. static void
  121. @@ -237,6 +239,20 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
  122. case INSN_CLASS_Q: return riscv_subset_supports ("q");
  123. + case INSN_CLASS_V: return riscv_subset_supports ("v");
  124. + case INSN_CLASS_V_AND_F:
  125. + return riscv_subset_supports ("v") && riscv_subset_supports ("f");
  126. + case INSN_CLASS_V_OR_ZVAMO:
  127. + return (riscv_subset_supports ("a")
  128. + && (riscv_subset_supports ("v")
  129. + || riscv_subset_supports ("zvamo")));
  130. + case INSN_CLASS_V_AND_ZVEDIV:
  131. + return riscv_subset_supports ("v") && riscv_subset_supports ("zvediv");
  132. + case INSN_CLASS_V_OR_ZVLSSEG:
  133. + return riscv_subset_supports ("v") || riscv_subset_supports ("zvlsseg");
  134. + case INSN_CLASS_V_AND_ZVQMAC:
  135. + return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
  136. +
  137. default:
  138. as_fatal ("Unreachable");
  139. return FALSE;
  140. @@ -598,6 +614,8 @@ enum reg_class
  141. {
  142. RCLASS_GPR,
  143. RCLASS_FPR,
  144. + RCLASS_VECR,
  145. + RCLASS_VECM,
  146. RCLASS_MAX,
  147. RCLASS_CSR
  148. @@ -696,6 +714,12 @@ riscv_csr_address (const char *csr_name,
  149. result = riscv_subset_supports ("f");
  150. need_check_version = FALSE;
  151. break;
  152. + case CSR_CLASS_V:
  153. + result = (riscv_subset_supports ("v")
  154. + || riscv_subset_supports ("zvamo")
  155. + || riscv_subset_supports ("zvlsseg"));
  156. + need_check_version = FALSE;
  157. + break;
  158. case CSR_CLASS_DEBUG:
  159. need_check_version = FALSE;
  160. break;
  161. @@ -735,10 +759,8 @@ riscv_csr_address (const char *csr_name,
  162. return saved_entry->address;
  163. }
  164. -/* Once the CSR is defined, including the old privilege spec, then we call
  165. - riscv_csr_class_check and riscv_csr_version_check to do the further checking
  166. - and get the corresponding address. Return -1 if the CSR is never been
  167. - defined. Otherwise, return the address. */
  168. +/* Return -1 if the CSR is never been defined. Otherwise, return the
  169. + address. */
  170. static unsigned int
  171. reg_csr_lookup_internal (const char *s)
  172. @@ -773,6 +795,11 @@ reg_lookup_internal (const char *s, enum reg_class class)
  173. if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
  174. return -1;
  175. + if (class == RCLASS_CSR
  176. + && riscv_opts.csr_check
  177. + && !reg_csr_lookup_internal (s))
  178. + return -1;
  179. +
  180. return DECODE_REG_NUM (r);
  181. }
  182. @@ -965,6 +992,32 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
  183. return FALSE;
  184. }
  185. break;
  186. +
  187. + case 'V': /* RVV */
  188. + switch (c = *p++)
  189. + {
  190. + case 'd':
  191. + case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break;
  192. + case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break;
  193. + case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break;
  194. + case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
  195. + case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1);
  196. + USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
  197. + case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD);
  198. + USE_BITS (OP_MASK_VS1, OP_SH_VS1);
  199. + USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
  200. + case '0': break;
  201. + case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break;
  202. + case 'i':
  203. + case 'j':
  204. + case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
  205. + case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
  206. + default:
  207. + as_bad (_("internal: bad RISC-V opcode (unknown operand type `V%c'): %s %s"),
  208. + c, opc->name, opc->args);
  209. + }
  210. + break;
  211. +
  212. default:
  213. as_bad (_("internal: bad RISC-V opcode "
  214. "(unknown operand type `%c'): %s %s"),
  215. @@ -1043,6 +1096,8 @@ md_begin (void)
  216. hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
  217. hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
  218. hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
  219. + hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR);
  220. + hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM);
  221. /* Add "fp" as an alias for "s0". */
  222. hash_reg_name (RCLASS_GPR, "fp", 8);
  223. @@ -1201,6 +1256,42 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
  224. break;
  225. case ',':
  226. continue;
  227. +
  228. + case 'V': /* RVV */
  229. + {
  230. + switch (*fmt++)
  231. + {
  232. + case 'd':
  233. + INSERT_OPERAND (VD, insn, va_arg (args, int));
  234. + continue;
  235. +
  236. + case 's':
  237. + INSERT_OPERAND (VS1, insn, va_arg (args, int));
  238. + continue;
  239. +
  240. + case 't':
  241. + INSERT_OPERAND (VS2, insn, va_arg (args, int));
  242. + continue;
  243. +
  244. + case 'm':
  245. + {
  246. + int reg = va_arg (args, int);
  247. + if (reg == -1)
  248. + {
  249. + INSERT_OPERAND (VMASK, insn, 1);
  250. + continue;
  251. + }
  252. + else if (reg == 0)
  253. + {
  254. + INSERT_OPERAND (VMASK, insn, 0);
  255. + continue;
  256. + }
  257. + }
  258. + /* fallthru */
  259. + }
  260. + }
  261. + /* fallthru */
  262. +
  263. default:
  264. as_fatal (_("internal error: invalid macro"));
  265. }
  266. @@ -1365,6 +1456,96 @@ load_const (int reg, expressionS *ep)
  267. }
  268. }
  269. +/* Expand RISC-V Vector macros into one of more instructions. */
  270. +
  271. +static void
  272. +vector_macro (struct riscv_cl_insn *ip)
  273. +{
  274. + int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD;
  275. + int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1;
  276. + int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2;
  277. + int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK;
  278. + int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6;
  279. + int mask = ip->insn_mo->mask;
  280. +
  281. + switch (mask)
  282. + {
  283. + case M_VMSGE:
  284. + if (vm)
  285. + {
  286. + /* Unmasked. */
  287. + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
  288. + macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
  289. + break;
  290. + }
  291. + if (vtemp != 0)
  292. + {
  293. + /* Masked. Have vtemp to avoid overlap constraints. */
  294. + if (vd == vm)
  295. + {
  296. + macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
  297. + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
  298. + }
  299. + else
  300. + {
  301. + /* Preserve the value of vd if not updating by vm. */
  302. + macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
  303. + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
  304. + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
  305. + macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
  306. + }
  307. + }
  308. + else if (vd != vm)
  309. + {
  310. + /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
  311. + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
  312. + macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
  313. + }
  314. + else
  315. + as_bad (_("must provide temp if destination overlaps mask"));
  316. + break;
  317. +
  318. + case M_VMSGEU:
  319. + if (vm)
  320. + {
  321. + /* Unmasked. */
  322. + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
  323. + macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
  324. + break;
  325. + }
  326. + if (vtemp != 0)
  327. + {
  328. + /* Masked. Have vtemp to avoid overlap constraints. */
  329. + if (vd == vm)
  330. + {
  331. + macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
  332. + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
  333. + }
  334. + else
  335. + {
  336. + /* Preserve the value of vd if not updating by vm. */
  337. + macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
  338. + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
  339. + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
  340. + macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
  341. + }
  342. + }
  343. + else if (vd != vm)
  344. + {
  345. + /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
  346. + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
  347. + macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
  348. + }
  349. + else
  350. + as_bad (_("must provide temp if destination overlaps mask"));
  351. + break;
  352. +
  353. + default:
  354. + as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
  355. + break;
  356. + }
  357. +}
  358. +
  359. /* Expand RISC-V assembly macros into one or more instructions. */
  360. static void
  361. macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
  362. @@ -1486,6 +1667,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
  363. riscv_call (rd, rs1, imm_expr, *imm_reloc);
  364. break;
  365. + case M_VMSGE:
  366. + case M_VMSGEU:
  367. + vector_macro (ip);
  368. + break;
  369. +
  370. default:
  371. as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
  372. break;
  373. @@ -1639,6 +1825,81 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
  374. return reloc_index;
  375. }
  376. +/* Parse string STR as a vsetvli operand. Store the expression in *EP.
  377. + On exit, EXPR_END points to the first character after the expression. */
  378. +
  379. +static void
  380. +my_getVsetvliExpression (expressionS *ep, char *str)
  381. +{
  382. + unsigned int vsew_value = 0, vlmul_value = 0, vediv_value = 0;
  383. + unsigned int vta_value = 0, vma_value = 0;
  384. + bfd_boolean vsew_found = FALSE, vlmul_found = FALSE, vediv_found = FALSE;
  385. + bfd_boolean vta_found = FALSE, vma_found = FALSE;
  386. +
  387. + if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
  388. + {
  389. + if (*str == ',')
  390. + ++str;
  391. + if (vsew_found)
  392. + as_bad (_("multiple vsew constants"));
  393. + vsew_found = TRUE;
  394. + }
  395. + if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
  396. + {
  397. + if (*str == ',')
  398. + ++str;
  399. + if (vlmul_found)
  400. + as_bad (_("multiple vlmul constants"));
  401. + vlmul_found = TRUE;
  402. + }
  403. + if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value))
  404. + {
  405. + if (*str == ',')
  406. + ++str;
  407. + if (vta_found)
  408. + as_bad (_("multiple vta constants"));
  409. + vta_found = TRUE;
  410. + }
  411. + if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value))
  412. + {
  413. + if (*str == ',')
  414. + ++str;
  415. + if (vma_found)
  416. + as_bad (_("multiple vma constants"));
  417. + vma_found = TRUE;
  418. + }
  419. + if (arg_lookup (&str, riscv_vediv, ARRAY_SIZE (riscv_vediv), &vediv_value))
  420. + {
  421. + if (*str == ',')
  422. + ++str;
  423. + if (vediv_found)
  424. + as_bad (_("multiple vediv constants"));
  425. + vediv_found = TRUE;
  426. + }
  427. +
  428. + if (vsew_found || vlmul_found || vediv_found || vta_found || vma_found)
  429. + {
  430. + ep->X_op = O_constant;
  431. + ep->X_add_number = (vediv_value << OP_SH_VEDIV)
  432. + | (vsew_value << OP_SH_VSEW)
  433. + | (vta_value << OP_SH_VTA)
  434. + | (vma_value << OP_SH_VMA) ;
  435. + INSERT_VLMUL (ep->X_add_number, vlmul_value);
  436. + expr_end = str;
  437. + }
  438. + else
  439. + {
  440. + my_getExpression (ep, str);
  441. + str = expr_end;
  442. + }
  443. +
  444. + /* Report warning message if the vediv field is set, but the Zvediv
  445. + extension isn't enabled. */
  446. + if (!riscv_multi_subset_supports (INSN_CLASS_V_AND_ZVEDIV)
  447. + && (ep->X_add_number & (OP_MASK_VEDIV << OP_SH_VEDIV)))
  448. + as_warn ("vediv is set but Zvediv extension isn't enabled");
  449. +}
  450. +
  451. /* Parse opcode name, could be an mnemonics or number. */
  452. static size_t
  453. my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
  454. @@ -1811,7 +2072,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
  455. case '\0': /* End of args. */
  456. if (insn->pinfo != INSN_MACRO)
  457. {
  458. - if (!insn->match_func (insn, ip->insn_opcode))
  459. + if (!insn->match_func (insn, ip->insn_opcode,
  460. + riscv_opts.check_constraints))
  461. break;
  462. /* For .insn, insn->match and insn->mask are 0. */
  463. @@ -2502,6 +2764,154 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
  464. imm_expr->X_op = O_absent;
  465. continue;
  466. + case 'V': /* RVV */
  467. + switch (*++args)
  468. + {
  469. + case 'd': /* VD */
  470. + if (!reg_lookup (&s, RCLASS_VECR, &regno))
  471. + break;
  472. + INSERT_OPERAND (VD, *ip, regno);
  473. + continue;
  474. +
  475. + case 'e': /* AMO VD */
  476. + if (reg_lookup (&s, RCLASS_GPR, &regno) && regno == 0)
  477. + INSERT_OPERAND (VWD, *ip, 0);
  478. + else if (reg_lookup (&s, RCLASS_VECR, &regno))
  479. + {
  480. + INSERT_OPERAND (VWD, *ip, 1);
  481. + INSERT_OPERAND (VD, *ip, regno);
  482. + }
  483. + else
  484. + break;
  485. + continue;
  486. +
  487. + case 'f': /* AMO VS3 */
  488. + if (!reg_lookup (&s, RCLASS_VECR, &regno))
  489. + break;
  490. + if (!EXTRACT_OPERAND (VWD, ip->insn_opcode))
  491. + INSERT_OPERAND (VD, *ip, regno);
  492. + else
  493. + {
  494. + /* VS3 must match VD. */
  495. + if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno)
  496. + break;
  497. + }
  498. + continue;
  499. +
  500. + case 's': /* VS1 */
  501. + if (!reg_lookup (&s, RCLASS_VECR, &regno))
  502. + break;
  503. + INSERT_OPERAND (VS1, *ip, regno);
  504. + continue;
  505. +
  506. + case 't': /* VS2 */
  507. + if (!reg_lookup (&s, RCLASS_VECR, &regno))
  508. + break;
  509. + INSERT_OPERAND (VS2, *ip, regno);
  510. + continue;
  511. +
  512. + case 'u': /* VS1 == VS2 */
  513. + if (!reg_lookup (&s, RCLASS_VECR, &regno))
  514. + break;
  515. + INSERT_OPERAND (VS1, *ip, regno);
  516. + INSERT_OPERAND (VS2, *ip, regno);
  517. + continue;
  518. +
  519. + case 'v': /* VD == VS1 == VS2 */
  520. + if (!reg_lookup (&s, RCLASS_VECR, &regno))
  521. + break;
  522. + INSERT_OPERAND (VD, *ip, regno);
  523. + INSERT_OPERAND (VS1, *ip, regno);
  524. + INSERT_OPERAND (VS2, *ip, regno);
  525. + continue;
  526. +
  527. + case '0': /* required vector mask register without .t */
  528. + if (reg_lookup (&s, RCLASS_VECR, &regno) && regno == 0)
  529. + continue;
  530. + break;
  531. +
  532. + case 'c': /* vtypei for vsetvli */
  533. + my_getVsetvliExpression (imm_expr, s);
  534. + check_absolute_expr (ip, imm_expr, FALSE);
  535. + if (!VALID_RVV_VC_IMM (imm_expr->X_add_number))
  536. + as_bad (_("bad value for vsetvli immediate field, "
  537. + "value must be 0..2047"));
  538. + ip->insn_opcode
  539. + |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number);
  540. + imm_expr->X_op = O_absent;
  541. + s = expr_end;
  542. + continue;
  543. +
  544. + case 'i': /* vector arith signed immediate */
  545. + my_getExpression (imm_expr, s);
  546. + check_absolute_expr (ip, imm_expr, FALSE);
  547. + if (imm_expr->X_add_number > 15
  548. + || imm_expr->X_add_number < -16)
  549. + as_bad (_("bad value for vector immediate field, "
  550. + "value must be -16...15"));
  551. + INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
  552. + imm_expr->X_op = O_absent;
  553. + s = expr_end;
  554. + continue;
  555. +
  556. + case 'j': /* vector arith unsigned immediate */
  557. + my_getExpression (imm_expr, s);
  558. + check_absolute_expr (ip, imm_expr, FALSE);
  559. + if (imm_expr->X_add_number < 0
  560. + || imm_expr->X_add_number >= 32)
  561. + as_bad (_("bad value for vector immediate field, "
  562. + "value must be 0...31"));
  563. + INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
  564. + imm_expr->X_op = O_absent;
  565. + s = expr_end;
  566. + continue;
  567. +
  568. + case 'k': /* vector arith signed immediate, minus 1 */
  569. + my_getExpression (imm_expr, s);
  570. + check_absolute_expr (ip, imm_expr, FALSE);
  571. + if (imm_expr->X_add_number > 16
  572. + || imm_expr->X_add_number < -15)
  573. + as_bad (_("bad value for vector immediate field, "
  574. + "value must be -15...16"));
  575. + INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1);
  576. + imm_expr->X_op = O_absent;
  577. + s = expr_end;
  578. + continue;
  579. +
  580. + case 'm': /* optional vector mask */
  581. + if (*s == '\0')
  582. + {
  583. + INSERT_OPERAND (VMASK, *ip, 1);
  584. + continue;
  585. + }
  586. + else if (*s == ',' && s++
  587. + && reg_lookup (&s, RCLASS_VECM, &regno)
  588. + && regno == 0)
  589. + {
  590. + INSERT_OPERAND (VMASK, *ip, 0);
  591. + continue;
  592. + }
  593. + break;
  594. +
  595. + /* The following ones are only used in macros. */
  596. + case 'M': /* required vector mask */
  597. + if (reg_lookup (&s, RCLASS_VECM, &regno) && regno == 0)
  598. + {
  599. + INSERT_OPERAND (VMASK, *ip, 0);
  600. + continue;
  601. + }
  602. + break;
  603. +
  604. + case 'T': /* vector macro temporary register */
  605. + if (!reg_lookup (&s, RCLASS_VECR, &regno) || regno == 0)
  606. + break;
  607. + /* Store it in the FUNCT6 field as we don't have anyplace
  608. + else to store it. */
  609. + INSERT_OPERAND (VFUNCT6, *ip, regno);
  610. + continue;
  611. + }
  612. + break;
  613. +
  614. default:
  615. as_fatal (_("internal error: bad argument type %c"), *args);
  616. }
  617. @@ -2579,6 +2989,8 @@ enum options
  618. OPTION_NO_CSR_CHECK,
  619. OPTION_MISA_SPEC,
  620. OPTION_MPRIV_SPEC,
  621. + OPTION_CHECK_CONSTRAINTS,
  622. + OPTION_NO_CHECK_CONSTRAINTS,
  623. OPTION_END_OF_ENUM
  624. };
  625. @@ -2597,6 +3009,8 @@ struct option md_longopts[] =
  626. {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
  627. {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
  628. {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
  629. + {"mcheck-constraints", no_argument, NULL, OPTION_CHECK_CONSTRAINTS},
  630. + {"mno-check-constraints", no_argument, NULL, OPTION_NO_CHECK_CONSTRAINTS},
  631. {NULL, no_argument, NULL, 0}
  632. };
  633. @@ -2691,6 +3105,14 @@ md_parse_option (int c, const char *arg)
  634. case OPTION_MPRIV_SPEC:
  635. return riscv_set_default_priv_spec (arg);
  636. + case OPTION_CHECK_CONSTRAINTS:
  637. + riscv_opts.check_constraints = TRUE;
  638. + break;
  639. +
  640. + case OPTION_NO_CHECK_CONSTRAINTS:
  641. + riscv_opts.check_constraints = FALSE;
  642. + break;
  643. +
  644. default:
  645. return 0;
  646. }
  647. @@ -3117,6 +3539,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
  648. riscv_opts.csr_check = TRUE;
  649. else if (strcmp (name, "no-csr-check") == 0)
  650. riscv_opts.csr_check = FALSE;
  651. + else if (strcmp (name, "checkconstraints") == 0)
  652. + riscv_opts.check_constraints = TRUE;
  653. + else if (strcmp (name, "nocheckconstraints") == 0)
  654. + riscv_opts.check_constraints = FALSE;
  655. else if (strcmp (name, "push") == 0)
  656. {
  657. struct riscv_option_stack *s;
  658. diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
  659. index de17ad81fb..06b62fd808 100644
  660. --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
  661. +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
  662. @@ -1,4 +1,4 @@
  663. -#as: -march=rv32if -mpriv-spec=1.11
  664. +#as: -march=rv32ifv -mpriv-spec=1.11
  665. #objdump: --dwarf=frames
  666. @@ -250,6 +250,13 @@ Contents of the .* section:
  667. DW_CFA_offset_extended_sf: r4097 \(fflags\) at cfa\+4
  668. DW_CFA_offset_extended_sf: r4098 \(frm\) at cfa\+8
  669. DW_CFA_offset_extended_sf: r4099 \(fcsr\) at cfa\+12
  670. + DW_CFA_offset_extended_sf: r4104 \(vstart\) at cfa\+32
  671. + DW_CFA_offset_extended_sf: r4105 \(vxsat\) at cfa\+36
  672. + DW_CFA_offset_extended_sf: r4106 \(vxrm\) at cfa\+40
  673. + DW_CFA_offset_extended_sf: r4111 \(vcsr\) at cfa\+60
  674. + DW_CFA_offset_extended_sf: r7200 \(vl\) at cfa\+12416
  675. + DW_CFA_offset_extended_sf: r7201 \(vtype\) at cfa\+12420
  676. + DW_CFA_offset_extended_sf: r7202 \(vlenb\) at cfa\+12424
  677. DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
  678. DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
  679. DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
  680. diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
  681. index ecc8014697..399e786440 100644
  682. --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
  683. +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
  684. @@ -242,6 +242,13 @@ _start:
  685. .cfi_offset fflags, 4
  686. .cfi_offset frm, 8
  687. .cfi_offset fcsr, 12
  688. + .cfi_offset vstart, 32
  689. + .cfi_offset vxsat, 36
  690. + .cfi_offset vxrm, 40
  691. + .cfi_offset vcsr, 60
  692. + .cfi_offset vl, 12416
  693. + .cfi_offset vtype, 12420
  694. + .cfi_offset vlenb, 12424
  695. .cfi_offset dcsr, 7872
  696. .cfi_offset dpc, 7876
  697. .cfi_offset dscratch0, 7880
  698. diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
  699. index 8f0badfce1..9d417b0794 100644
  700. --- a/gas/testsuite/gas/riscv/insn.d
  701. +++ b/gas/testsuite/gas/riscv/insn.d
  702. @@ -1,4 +1,4 @@
  703. -#as: -march=rv32ifc
  704. +#as: -march=rv32ifcv
  705. #objdump: -dr
  706. .*:[ ]+file format .*
  707. @@ -63,3 +63,70 @@ Disassembly of section .text:
  708. [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
  709. [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
  710. [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
  711. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  712. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  713. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  714. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  715. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  716. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  717. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  718. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  719. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  720. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  721. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  722. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  723. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  724. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  725. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  726. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  727. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  728. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  729. +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
  730. +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
  731. +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
  732. +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
  733. +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
  734. +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
  735. +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
  736. +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
  737. +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
  738. +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
  739. +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
  740. +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
  741. +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
  742. +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
  743. +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
  744. +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
  745. +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
  746. +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
  747. +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
  748. +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
  749. +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
  750. +[^:]+:[ ]+00067587[ ]+vle64.v[ ]+v11,\(a2\),v0.t
  751. +[^:]+:[ ]+03067587[ ]+vle64ff.v[ ]+v11,\(a2\)
  752. +[^:]+:[ ]+000675a7[ ]+vse64.v[ ]+v11,\(a2\),v0.t
  753. +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
  754. +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
  755. +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
  756. +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
  757. +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
  758. +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
  759. +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
  760. +[^:]+:[ ]+00d615d7[ ]+vfadd.vv[ ]+v11,v13,v12,v0.t
  761. +[^:]+:[ ]+00d615d7[ ]+vfadd.vv[ ]+v11,v13,v12,v0.t
  762. +[^:]+:[ ]+00d625d7[ ]+vredsum.vs[ ]+v11,v13,v12,v0.t
  763. +[^:]+:[ ]+00d625d7[ ]+vredsum.vs[ ]+v11,v13,v12,v0.t
  764. +[^:]+:[ ]+00d645d7[ ]+vadd.vx[ ]+v11,v13,a2,v0.t
  765. +[^:]+:[ ]+00d645d7[ ]+vadd.vx[ ]+v11,v13,a2,v0.t
  766. +[^:]+:[ ]+00d655d7[ ]+vfadd.vf[ ]+v11,v13,fa2,v0.t
  767. +[^:]+:[ ]+00d655d7[ ]+vfadd.vf[ ]+v11,v13,fa2,v0.t
  768. +[^:]+:[ ]+38d665d7[ ]+vslide1up.vx[ ]+v11,v13,a2,v0.t
  769. +[^:]+:[ ]+3cd665d7[ ]+vslide1down.vx[ ]+v11,v13,a2,v0.t
  770. +[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e64,m2,tu,mu,d1
  771. +[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e64,m2,tu,mu,d1
  772. +[^:]+:[ ]+00d035d7[ ]+vadd.vi[ ]+v11,v13,0,v0.t
  773. +[^:]+:[ ]+00d0b5d7[ ]+vadd.vi[ ]+v11,v13,1,v0.t
  774. +[^:]+:[ ]+00d7b5d7[ ]+vadd.vi[ ]+v11,v13,15,v0.t
  775. +[^:]+:[ ]+00d835d7[ ]+vadd.vi[ ]+v11,v13,-16,v0.t
  776. +[^:]+:[ ]+00df35d7[ ]+vadd.vi[ ]+v11,v13,-2,v0.t
  777. +[^:]+:[ ]+00dfb5d7[ ]+vadd.vi[ ]+v11,v13,-1,v0.t
  778. diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
  779. index 6c08f49d43..b7cd92e96d 100644
  780. --- a/gas/testsuite/gas/riscv/insn.s
  781. +++ b/gas/testsuite/gas/riscv/insn.s
  782. @@ -47,3 +47,87 @@ target:
  783. .insn r 0x33, 0, 0, fa0, a1, fa2
  784. .insn r 0x33, 0, 0, a0, fa1, fa2
  785. .insn r 0x33, 0, 0, fa0, fa1, fa2
  786. +
  787. +# vamo
  788. +# F3: width[14:12]
  789. +# F7: amoop[31:27] + wd[26] + vm[25]
  790. +
  791. + .insn r AMO, 0x7, 0x0, v11, a2, a3
  792. + .insn r AMO, 0x7, 0x0, v11, fa2, a3
  793. + .insn r AMO, 0x7, 0x0, v11, a2, fa3
  794. + .insn r AMO, 0x7, 0x0, v11, fa2, fa3
  795. + .insn r AMO, 0x7, 0x0, a1, v12, a3
  796. + .insn r AMO, 0x7, 0x0, fa1, v12, a3
  797. + .insn r AMO, 0x7, 0x0, a1, v12, fa3
  798. + .insn r AMO, 0x7, 0x0, fa1, v12, fa3
  799. + .insn r AMO, 0x7, 0x0, a1, a2, v13
  800. + .insn r AMO, 0x7, 0x0, fa1, a2, v13
  801. + .insn r 0x2f, 0x7, 0x0, a1, fa2, v13
  802. + .insn r 0x2f, 0x7, 0x0, fa1, fa2, v13
  803. + .insn r 0x2f, 0x7, 0x0, a1, v12, v13
  804. + .insn r 0x2f, 0x7, 0x0, fa1, v12, v13
  805. + .insn r 0x2f, 0x7, 0x0, v11, a2, v13
  806. + .insn r 0x2f, 0x7, 0x0, v11, fa2, v13
  807. + .insn r 0x2f, 0x7, 0x0, v11, v12, a3
  808. + .insn r 0x2f, 0x7, 0x0, v11, v12, fa3
  809. + .insn r 0x2f, 0x7, 0x0, v11, v12, v13
  810. +
  811. +# vmem
  812. +# F3: width[14:12]
  813. +# F7: nf[31:29] + mop[28:26] + vm[25]
  814. +
  815. + .insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
  816. + .insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
  817. + .insn r LOAD_FP, 0x7, 0x4, v11, fa2, a3
  818. + .insn r LOAD_FP, 0x7, 0x4, v11, a2, fa3
  819. + .insn r LOAD_FP, 0x7, 0x4, v11, fa2, fa3
  820. + .insn r 0x7, 0x7, 0x5, a1, v12, a3
  821. + .insn r 0x7, 0x7, 0x5, fa1, v12, a3
  822. + .insn r 0x7, 0x7, 0x5, a1, v12, fa3
  823. + .insn r 0x7, 0x7, 0x5, fa1, v12, fa3
  824. + .insn r 0x7, 0x7, 0x5, a1, a2, v13
  825. + .insn r STORE_FP, 0x7, 0x4, fa1, a2, v13
  826. + .insn r STORE_FP, 0x7, 0x4, a1, fa2, v13
  827. + .insn r STORE_FP, 0x7, 0x4, fa1, fa2, v13
  828. + .insn r STORE_FP, 0x7, 0x4, a1, v12, v13
  829. + .insn r STORE_FP, 0x7, 0x4, fa1, v12, v13
  830. + .insn r 0x27, 0x7, 0x5, v11, a2, v13
  831. + .insn r 0x27, 0x7, 0x5, v11, fa2, v13
  832. + .insn r 0x27, 0x7, 0x5, v11, v12, a3
  833. + .insn r 0x27, 0x7, 0x5, v11, v12, fa3
  834. + .insn r 0x27, 0x7, 0x5, v11, v12, v13
  835. + # unit-stride
  836. + .insn r LOAD_FP, 0x7, 0x0, v11, a2, x0
  837. + .insn r LOAD_FP, 0x7, 0x1, v11, a2, x16
  838. + .insn r STORE_FP, 0x7, 0x0, v11, a2, x0
  839. +
  840. +# valu and vcfg
  841. +# F3: funct3[14:12]
  842. +# F7: F6[31:26] + vm[25]
  843. +
  844. + .insn r 0x57, 0x0, 0x0, v11, a2, a3
  845. + .insn r 0x57, 0x0, 0x0, v11, fa2, a3
  846. + .insn r 0x57, 0x0, 0x0, v11, a2, fa3
  847. + .insn r 0x57, 0x0, 0x0, v11, fa2, fa3
  848. + .insn r 0x57, 0x0, 0x0, a1, v12, a3
  849. + .insn r 0x57, 0x0, 0x0, fa1, v12, a3
  850. + .insn r 0x57, 0x0, 0x0, a1, v12, fa3
  851. + .insn r 0x57, 0x1, 0x0, fa1, v12, fa3
  852. + .insn r 0x57, 0x1, 0x0, a1, a2, v13
  853. + .insn r 0x57, 0x2, 0x0, fa1, a2, v13
  854. + .insn r 0x57, 0x2, 0x0, a1, fa2, v13
  855. + .insn r 0x57, 0x4, 0x0, fa1, fa2, v13
  856. + .insn r 0x57, 0x4, 0x0, a1, v12, v13
  857. + .insn r 0x57, 0x5, 0x0, fa1, v12, v13
  858. + .insn r 0x57, 0x5, 0x0, v11, a2, v13
  859. + .insn r 0x57, 0x6, 0x1c, v11, fa2, v13
  860. + .insn r 0x57, 0x6, 0x1e, v11, v12, a3
  861. + .insn r 0x57, 0x7, 0x0, v11, v12, fa3
  862. + .insn r 0x57, 0x7, 0x0, v11, v12, v13
  863. + # OPIVI
  864. + .insn r 0x57, 0x3, 0x0, v11, x0, a3
  865. + .insn r 0x57, 0x3, 0x0, v11, x1, a3
  866. + .insn r 0x57, 0x3, 0x0, v11, x15, a3
  867. + .insn r 0x57, 0x3, 0x0, v11, x16, a3
  868. + .insn r 0x57, 0x3, 0x0, v11, x30, a3
  869. + .insn r 0x57, 0x3, 0x0, v11, x31, a3
  870. diff --git a/gas/testsuite/gas/riscv/march-fail-s-with-version b/gas/testsuite/gas/riscv/march-fail-s-with-version
  871. new file mode 100644
  872. index 0000000000..a514d4aec7
  873. --- /dev/null
  874. +++ b/gas/testsuite/gas/riscv/march-fail-s-with-version
  875. @@ -0,0 +1,2 @@
  876. +Assembler messages:
  877. +.*: Invalid or unknown s ISA extension: 'sfoo'
  878. \ No newline at end of file
  879. diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
  880. index 07cf05a9c2..4fa2b18911 100644
  881. --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
  882. +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
  883. @@ -1,4 +1,4 @@
  884. -#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr
  885. +#as: -march=rv32ifv -mcsr-check -mpriv-spec=1.10 -march-attr
  886. #source: priv-reg.s
  887. #warning_output: priv-reg-fail-version-1p10.l
  888. #readelf: -A
  889. diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
  890. index bf4b1db3ed..852ce8bf64 100644
  891. --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
  892. +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
  893. @@ -1,4 +1,4 @@
  894. -#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr
  895. +#as: -march=rv32ifv -mcsr-check -mpriv-spec=1.11 -march-attr
  896. #source: priv-reg.s
  897. #warning_output: priv-reg-fail-version-1p11.l
  898. #readelf: -A
  899. diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
  900. index e2c33d81dc..e6f9fc9500 100644
  901. --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
  902. +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
  903. @@ -1,4 +1,4 @@
  904. -#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr
  905. +#as: -march=rv32ifv -mcsr-check -mpriv-spec=1.9.1 -march-attr
  906. #source: priv-reg.s
  907. #warning_output: priv-reg-fail-version-1p9p1.l
  908. #readelf: -A
  909. diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-vext.d b/gas/testsuite/gas/riscv/priv-reg-fail-vext.d
  910. new file mode 100644
  911. index 0000000000..13e731c2e7
  912. --- /dev/null
  913. +++ b/gas/testsuite/gas/riscv/priv-reg-fail-vext.d
  914. @@ -0,0 +1,3 @@
  915. +#as: -march=rv32if -mcsr-check
  916. +#source: priv-reg.s
  917. +#warning_output: priv-reg-fail-vext.l
  918. diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-vext.l b/gas/testsuite/gas/riscv/priv-reg-fail-vext.l
  919. new file mode 100644
  920. index 0000000000..1243fc7c12
  921. --- /dev/null
  922. +++ b/gas/testsuite/gas/riscv/priv-reg-fail-vext.l
  923. @@ -0,0 +1,9 @@
  924. +.*Assembler messages:
  925. +#...
  926. +.*Warning: Invalid CSR `vstart' for the current ISA
  927. +.*Warning: Invalid CSR `vxsat' for the current ISA
  928. +.*Warning: Invalid CSR `vxrm' for the current ISA
  929. +.*Warning: Invalid CSR `vcsr' for the current ISA
  930. +.*Warning: Invalid CSR `vl' for the current ISA
  931. +.*Warning: Invalid CSR `vtype' for the current ISA
  932. +#...
  933. diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
  934. index 3ad8eebe85..0a023ea5a2 100644
  935. --- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
  936. +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
  937. @@ -1,4 +1,4 @@
  938. -#as: -march=rv32if -mpriv-spec=1.10
  939. +#as: -march=rv32ifv -mpriv-spec=1.10
  940. #source: priv-reg.s
  941. #objdump: -dr -Mpriv-spec=1.10
  942. @@ -246,6 +246,13 @@ Disassembly of section .text:
  943. [ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
  944. [ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
  945. [ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
  946. +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
  947. +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
  948. +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
  949. +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
  950. +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
  951. +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
  952. +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
  953. [ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
  954. [ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
  955. [ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
  956. diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
  957. index 5824bc5e1f..5956b0d9fd 100644
  958. --- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
  959. +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
  960. @@ -1,4 +1,4 @@
  961. -#as: -march=rv32if -mpriv-spec=1.11
  962. +#as: -march=rv32ifv -mpriv-spec=1.11
  963. #source: priv-reg.s
  964. #objdump: -dr -Mpriv-spec=1.11
  965. @@ -246,6 +246,13 @@ Disassembly of section .text:
  966. [ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
  967. [ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
  968. [ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
  969. +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
  970. +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
  971. +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
  972. +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
  973. +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
  974. +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
  975. +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
  976. [ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
  977. [ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
  978. [ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
  979. diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
  980. index 569b9587e2..3fea56d947 100644
  981. --- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
  982. +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
  983. @@ -1,4 +1,4 @@
  984. -#as: -march=rv32if -mpriv-spec=1.9.1
  985. +#as: -march=rv32ifv -mpriv-spec=1.9.1
  986. #source: priv-reg.s
  987. #objdump: -dr -Mpriv-spec=1.9.1
  988. @@ -246,6 +246,13 @@ Disassembly of section .text:
  989. [ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
  990. [ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
  991. [ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
  992. +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
  993. +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
  994. +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
  995. +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
  996. +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
  997. +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
  998. +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
  999. [ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
  1000. [ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
  1001. [ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
  1002. diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
  1003. index c40d28862b..8f625054c1 100644
  1004. --- a/gas/testsuite/gas/riscv/priv-reg.s
  1005. +++ b/gas/testsuite/gas/riscv/priv-reg.s
  1006. @@ -260,6 +260,15 @@
  1007. csr frm
  1008. csr fcsr
  1009. + # Vector
  1010. + csr vstart
  1011. + csr vxsat
  1012. + csr vxrm
  1013. + csr vcsr
  1014. + csr vl
  1015. + csr vtype
  1016. + csr vlenb
  1017. +
  1018. # Core debug
  1019. csr dcsr
  1020. csr dpc
  1021. diff --git a/gas/testsuite/gas/riscv/v-zero-imm.d b/gas/testsuite/gas/riscv/v-zero-imm.d
  1022. new file mode 100644
  1023. index 0000000000..f6fe2ffaa8
  1024. --- /dev/null
  1025. +++ b/gas/testsuite/gas/riscv/v-zero-imm.d
  1026. @@ -0,0 +1,17 @@
  1027. +#as: -march=rv32ifv
  1028. +#objdump: -dr
  1029. +
  1030. +.*:[ ]+file format .*
  1031. +
  1032. +
  1033. +Disassembly of section .text:
  1034. +
  1035. +0+000 <.text>:
  1036. +[ ]+[0-9a-f]+:[ ]+768fb257[ ]+vmsle.vi[ ]+v4,v8,-1
  1037. +[ ]+[0-9a-f]+:[ ]+748fb257[ ]+vmsle.vi[ ]+v4,v8,-1,v0.t
  1038. +[ ]+[0-9a-f]+:[ ]+66840257[ ]+vmsne.vv[ ]+v4,v8,v8
  1039. +[ ]+[0-9a-f]+:[ ]+64840257[ ]+vmsne.vv[ ]+v4,v8,v8,v0.t
  1040. +[ ]+[0-9a-f]+:[ ]+7e8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1
  1041. +[ ]+[0-9a-f]+:[ ]+7c8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1,v0.t
  1042. +[ ]+[0-9a-f]+:[ ]+62840257[ ]+vmseq.vv[ ]+v4,v8,v8
  1043. +[ ]+[0-9a-f]+:[ ]+60840257[ ]+vmseq.vv[ ]+v4,v8,v8,v0.t
  1044. diff --git a/gas/testsuite/gas/riscv/v-zero-imm.s b/gas/testsuite/gas/riscv/v-zero-imm.s
  1045. new file mode 100644
  1046. index 0000000000..98b7063880
  1047. --- /dev/null
  1048. +++ b/gas/testsuite/gas/riscv/v-zero-imm.s
  1049. @@ -0,0 +1,8 @@
  1050. + vmslt.vi v4, v8, 0
  1051. + vmslt.vi v4, v8, 0, v0.t
  1052. + vmsltu.vi v4, v8, 0
  1053. + vmsltu.vi v4, v8, 0, v0.t
  1054. + vmsge.vi v4, v8, 0
  1055. + vmsge.vi v4, v8, 0, v0.t
  1056. + vmsgeu.vi v4, v8, 0
  1057. + vmsgeu.vi v4, v8, 0, v0.t
  1058. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.d b/gas/testsuite/gas/riscv/vector-insns-fail-01.d
  1059. new file mode 100644
  1060. index 0000000000..ade7888937
  1061. --- /dev/null
  1062. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-01.d
  1063. @@ -0,0 +1,3 @@
  1064. +#as: -march=rv32ifv -mcheck-constraints
  1065. +#source: vector-insns-fail-01.s
  1066. +#error_output: vector-insns-fail-01.l
  1067. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.l b/gas/testsuite/gas/riscv/vector-insns-fail-01.l
  1068. new file mode 100644
  1069. index 0000000000..61687938c9
  1070. --- /dev/null
  1071. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-01.l
  1072. @@ -0,0 +1,393 @@
  1073. +.*: Assembler messages:
  1074. +.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
  1075. +.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
  1076. +.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
  1077. +.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
  1078. +.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
  1079. +.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
  1080. +.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
  1081. +.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
  1082. +.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
  1083. +.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
  1084. +.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
  1085. +.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
  1086. +.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
  1087. +.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
  1088. +.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
  1089. +.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
  1090. +.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
  1091. +.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
  1092. +.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
  1093. +.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
  1094. +.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
  1095. +.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
  1096. +.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
  1097. +.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
  1098. +.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
  1099. +.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
  1100. +.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
  1101. +.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
  1102. +.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
  1103. +.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
  1104. +.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
  1105. +.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
  1106. +.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
  1107. +.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
  1108. +.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
  1109. +.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
  1110. +.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
  1111. +.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
  1112. +.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
  1113. +.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
  1114. +.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
  1115. +.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
  1116. +.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
  1117. +.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
  1118. +.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
  1119. +.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
  1120. +.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
  1121. +.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
  1122. +.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
  1123. +.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
  1124. +.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
  1125. +.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
  1126. +.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
  1127. +.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
  1128. +.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
  1129. +.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
  1130. +.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
  1131. +.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
  1132. +.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
  1133. +.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
  1134. +.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
  1135. +.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
  1136. +.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
  1137. +.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
  1138. +.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
  1139. +.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
  1140. +.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
  1141. +.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
  1142. +.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
  1143. +.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
  1144. +.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
  1145. +.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
  1146. +.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
  1147. +.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
  1148. +.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
  1149. +.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
  1150. +.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
  1151. +.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
  1152. +.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
  1153. +.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
  1154. +.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
  1155. +.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
  1156. +.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
  1157. +.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
  1158. +.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
  1159. +.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
  1160. +.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
  1161. +.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
  1162. +.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
  1163. +.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
  1164. +.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
  1165. +.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
  1166. +.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
  1167. +.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
  1168. +.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
  1169. +.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
  1170. +.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
  1171. +.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
  1172. +.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
  1173. +.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
  1174. +.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
  1175. +.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
  1176. +.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
  1177. +.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
  1178. +.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
  1179. +.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
  1180. +.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
  1181. +.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
  1182. +.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
  1183. +.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
  1184. +.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
  1185. +.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
  1186. +.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
  1187. +.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
  1188. +.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
  1189. +.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
  1190. +.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
  1191. +.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
  1192. +.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
  1193. +.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
  1194. +.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
  1195. +.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
  1196. +.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
  1197. +.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
  1198. +.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
  1199. +.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
  1200. +.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
  1201. +.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
  1202. +.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
  1203. +.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
  1204. +.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
  1205. +.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
  1206. +.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
  1207. +.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
  1208. +.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
  1209. +.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
  1210. +.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
  1211. +.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
  1212. +.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
  1213. +.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
  1214. +.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
  1215. +.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
  1216. +.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
  1217. +.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
  1218. +.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
  1219. +.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
  1220. +.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
  1221. +.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
  1222. +.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
  1223. +.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
  1224. +.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
  1225. +.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
  1226. +.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
  1227. +.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
  1228. +.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
  1229. +.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
  1230. +.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
  1231. +.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
  1232. +.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
  1233. +.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
  1234. +.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
  1235. +.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
  1236. +.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
  1237. +.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
  1238. +.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
  1239. +.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
  1240. +.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
  1241. +.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
  1242. +.*Error: illegal operands `vlxseg2ei8.v v2,\(a0\),v2'
  1243. +.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v2,v0.t'
  1244. +.*Error: illegal operands `vsxseg2ei8.v v2,\(a0\),v2'
  1245. +.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v2,v0.t'
  1246. +.*Error: illegal operands `vlxseg3ei8.v v2,\(a0\),v2'
  1247. +.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v2,v0.t'
  1248. +.*Error: illegal operands `vsxseg3ei8.v v2,\(a0\),v2'
  1249. +.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v2,v0.t'
  1250. +.*Error: illegal operands `vlxseg4ei8.v v2,\(a0\),v2'
  1251. +.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v2,v0.t'
  1252. +.*Error: illegal operands `vsxseg4ei8.v v2,\(a0\),v2'
  1253. +.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v2,v0.t'
  1254. +.*Error: illegal operands `vlxseg5ei8.v v2,\(a0\),v2'
  1255. +.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v2,v0.t'
  1256. +.*Error: illegal operands `vsxseg5ei8.v v2,\(a0\),v2'
  1257. +.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v2,v0.t'
  1258. +.*Error: illegal operands `vlxseg6ei8.v v2,\(a0\),v2'
  1259. +.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v2,v0.t'
  1260. +.*Error: illegal operands `vsxseg6ei8.v v2,\(a0\),v2'
  1261. +.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v2,v0.t'
  1262. +.*Error: illegal operands `vlxseg7ei8.v v2,\(a0\),v2'
  1263. +.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v2,v0.t'
  1264. +.*Error: illegal operands `vsxseg7ei8.v v2,\(a0\),v2'
  1265. +.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v2,v0.t'
  1266. +.*Error: illegal operands `vlxseg8ei8.v v2,\(a0\),v2'
  1267. +.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v2,v0.t'
  1268. +.*Error: illegal operands `vsxseg8ei8.v v2,\(a0\),v2'
  1269. +.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v2,v0.t'
  1270. +.*Error: illegal operands `vlxseg2ei16.v v2,\(a0\),v2'
  1271. +.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v2,v0.t'
  1272. +.*Error: illegal operands `vsxseg2ei16.v v2,\(a0\),v2'
  1273. +.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v2,v0.t'
  1274. +.*Error: illegal operands `vlxseg3ei16.v v2,\(a0\),v2'
  1275. +.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v2,v0.t'
  1276. +.*Error: illegal operands `vsxseg3ei16.v v2,\(a0\),v2'
  1277. +.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v2,v0.t'
  1278. +.*Error: illegal operands `vlxseg4ei16.v v2,\(a0\),v2'
  1279. +.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v2,v0.t'
  1280. +.*Error: illegal operands `vsxseg4ei16.v v2,\(a0\),v2'
  1281. +.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v2,v0.t'
  1282. +.*Error: illegal operands `vlxseg5ei16.v v2,\(a0\),v2'
  1283. +.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v2,v0.t'
  1284. +.*Error: illegal operands `vsxseg5ei16.v v2,\(a0\),v2'
  1285. +.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v2,v0.t'
  1286. +.*Error: illegal operands `vlxseg6ei16.v v2,\(a0\),v2'
  1287. +.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v2,v0.t'
  1288. +.*Error: illegal operands `vsxseg6ei16.v v2,\(a0\),v2'
  1289. +.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v2,v0.t'
  1290. +.*Error: illegal operands `vlxseg7ei16.v v2,\(a0\),v2'
  1291. +.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v2,v0.t'
  1292. +.*Error: illegal operands `vsxseg7ei16.v v2,\(a0\),v2'
  1293. +.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v2,v0.t'
  1294. +.*Error: illegal operands `vlxseg8ei16.v v2,\(a0\),v2'
  1295. +.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v2,v0.t'
  1296. +.*Error: illegal operands `vsxseg8ei16.v v2,\(a0\),v2'
  1297. +.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v2,v0.t'
  1298. +.*Error: illegal operands `vlxseg2ei32.v v2,\(a0\),v2'
  1299. +.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v2,v0.t'
  1300. +.*Error: illegal operands `vsxseg2ei32.v v2,\(a0\),v2'
  1301. +.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v2,v0.t'
  1302. +.*Error: illegal operands `vlxseg3ei32.v v2,\(a0\),v2'
  1303. +.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v2,v0.t'
  1304. +.*Error: illegal operands `vsxseg3ei32.v v2,\(a0\),v2'
  1305. +.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v2,v0.t'
  1306. +.*Error: illegal operands `vlxseg4ei32.v v2,\(a0\),v2'
  1307. +.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v2,v0.t'
  1308. +.*Error: illegal operands `vsxseg4ei32.v v2,\(a0\),v2'
  1309. +.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v2,v0.t'
  1310. +.*Error: illegal operands `vlxseg5ei32.v v2,\(a0\),v2'
  1311. +.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v2,v0.t'
  1312. +.*Error: illegal operands `vsxseg5ei32.v v2,\(a0\),v2'
  1313. +.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v2,v0.t'
  1314. +.*Error: illegal operands `vlxseg6ei32.v v2,\(a0\),v2'
  1315. +.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v2,v0.t'
  1316. +.*Error: illegal operands `vsxseg6ei32.v v2,\(a0\),v2'
  1317. +.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v2,v0.t'
  1318. +.*Error: illegal operands `vlxseg7ei32.v v2,\(a0\),v2'
  1319. +.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v2,v0.t'
  1320. +.*Error: illegal operands `vsxseg7ei32.v v2,\(a0\),v2'
  1321. +.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v2,v0.t'
  1322. +.*Error: illegal operands `vlxseg8ei32.v v2,\(a0\),v2'
  1323. +.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v2,v0.t'
  1324. +.*Error: illegal operands `vsxseg8ei32.v v2,\(a0\),v2'
  1325. +.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v2,v0.t'
  1326. +.*Error: illegal operands `vlxseg2ei64.v v2,\(a0\),v2'
  1327. +.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v2,v0.t'
  1328. +.*Error: illegal operands `vsxseg2ei64.v v2,\(a0\),v2'
  1329. +.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v2,v0.t'
  1330. +.*Error: illegal operands `vlxseg3ei64.v v2,\(a0\),v2'
  1331. +.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v2,v0.t'
  1332. +.*Error: illegal operands `vsxseg3ei64.v v2,\(a0\),v2'
  1333. +.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v2,v0.t'
  1334. +.*Error: illegal operands `vlxseg4ei64.v v2,\(a0\),v2'
  1335. +.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v2,v0.t'
  1336. +.*Error: illegal operands `vsxseg4ei64.v v2,\(a0\),v2'
  1337. +.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v2,v0.t'
  1338. +.*Error: illegal operands `vlxseg5ei64.v v2,\(a0\),v2'
  1339. +.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v2,v0.t'
  1340. +.*Error: illegal operands `vsxseg5ei64.v v2,\(a0\),v2'
  1341. +.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v2,v0.t'
  1342. +.*Error: illegal operands `vlxseg6ei64.v v2,\(a0\),v2'
  1343. +.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v2,v0.t'
  1344. +.*Error: illegal operands `vsxseg6ei64.v v2,\(a0\),v2'
  1345. +.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v2,v0.t'
  1346. +.*Error: illegal operands `vlxseg7ei64.v v2,\(a0\),v2'
  1347. +.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v2,v0.t'
  1348. +.*Error: illegal operands `vsxseg7ei64.v v2,\(a0\),v2'
  1349. +.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v2,v0.t'
  1350. +.*Error: illegal operands `vlxseg8ei64.v v2,\(a0\),v2'
  1351. +.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v2,v0.t'
  1352. +.*Error: illegal operands `vsxseg8ei64.v v2,\(a0\),v2'
  1353. +.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v2,v0.t'
  1354. +.*Error: illegal operands `vlxseg2ei128.v v2,\(a0\),v2'
  1355. +.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v2,v0.t'
  1356. +.*Error: illegal operands `vsxseg2ei128.v v2,\(a0\),v2'
  1357. +.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v2,v0.t'
  1358. +.*Error: illegal operands `vlxseg3ei128.v v2,\(a0\),v2'
  1359. +.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v2,v0.t'
  1360. +.*Error: illegal operands `vsxseg3ei128.v v2,\(a0\),v2'
  1361. +.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v2,v0.t'
  1362. +.*Error: illegal operands `vlxseg4ei128.v v2,\(a0\),v2'
  1363. +.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v2,v0.t'
  1364. +.*Error: illegal operands `vsxseg4ei128.v v2,\(a0\),v2'
  1365. +.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v2,v0.t'
  1366. +.*Error: illegal operands `vlxseg5ei128.v v2,\(a0\),v2'
  1367. +.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v2,v0.t'
  1368. +.*Error: illegal operands `vsxseg5ei128.v v2,\(a0\),v2'
  1369. +.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v2,v0.t'
  1370. +.*Error: illegal operands `vlxseg6ei128.v v2,\(a0\),v2'
  1371. +.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v2,v0.t'
  1372. +.*Error: illegal operands `vsxseg6ei128.v v2,\(a0\),v2'
  1373. +.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v2,v0.t'
  1374. +.*Error: illegal operands `vlxseg7ei128.v v2,\(a0\),v2'
  1375. +.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v2,v0.t'
  1376. +.*Error: illegal operands `vsxseg7ei128.v v2,\(a0\),v2'
  1377. +.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v2,v0.t'
  1378. +.*Error: illegal operands `vlxseg8ei128.v v2,\(a0\),v2'
  1379. +.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v2,v0.t'
  1380. +.*Error: illegal operands `vsxseg8ei128.v v2,\(a0\),v2'
  1381. +.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v2,v0.t'
  1382. +.*Error: illegal operands `vlxseg2ei256.v v2,\(a0\),v2'
  1383. +.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v2,v0.t'
  1384. +.*Error: illegal operands `vsxseg2ei256.v v2,\(a0\),v2'
  1385. +.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v2,v0.t'
  1386. +.*Error: illegal operands `vlxseg3ei256.v v2,\(a0\),v2'
  1387. +.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v2,v0.t'
  1388. +.*Error: illegal operands `vsxseg3ei256.v v2,\(a0\),v2'
  1389. +.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v2,v0.t'
  1390. +.*Error: illegal operands `vlxseg4ei256.v v2,\(a0\),v2'
  1391. +.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v2,v0.t'
  1392. +.*Error: illegal operands `vsxseg4ei256.v v2,\(a0\),v2'
  1393. +.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v2,v0.t'
  1394. +.*Error: illegal operands `vlxseg5ei256.v v2,\(a0\),v2'
  1395. +.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v2,v0.t'
  1396. +.*Error: illegal operands `vsxseg5ei256.v v2,\(a0\),v2'
  1397. +.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v2,v0.t'
  1398. +.*Error: illegal operands `vlxseg6ei256.v v2,\(a0\),v2'
  1399. +.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v2,v0.t'
  1400. +.*Error: illegal operands `vsxseg6ei256.v v2,\(a0\),v2'
  1401. +.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v2,v0.t'
  1402. +.*Error: illegal operands `vlxseg7ei256.v v2,\(a0\),v2'
  1403. +.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v2,v0.t'
  1404. +.*Error: illegal operands `vsxseg7ei256.v v2,\(a0\),v2'
  1405. +.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v2,v0.t'
  1406. +.*Error: illegal operands `vlxseg8ei256.v v2,\(a0\),v2'
  1407. +.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v2,v0.t'
  1408. +.*Error: illegal operands `vsxseg8ei256.v v2,\(a0\),v2'
  1409. +.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v2,v0.t'
  1410. +.*Error: illegal operands `vlxseg2ei512.v v2,\(a0\),v2'
  1411. +.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v2,v0.t'
  1412. +.*Error: illegal operands `vsxseg2ei512.v v2,\(a0\),v2'
  1413. +.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v2,v0.t'
  1414. +.*Error: illegal operands `vlxseg3ei512.v v2,\(a0\),v2'
  1415. +.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v2,v0.t'
  1416. +.*Error: illegal operands `vsxseg3ei512.v v2,\(a0\),v2'
  1417. +.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v2,v0.t'
  1418. +.*Error: illegal operands `vlxseg4ei512.v v2,\(a0\),v2'
  1419. +.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v2,v0.t'
  1420. +.*Error: illegal operands `vsxseg4ei512.v v2,\(a0\),v2'
  1421. +.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v2,v0.t'
  1422. +.*Error: illegal operands `vlxseg5ei512.v v2,\(a0\),v2'
  1423. +.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v2,v0.t'
  1424. +.*Error: illegal operands `vsxseg5ei512.v v2,\(a0\),v2'
  1425. +.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v2,v0.t'
  1426. +.*Error: illegal operands `vlxseg6ei512.v v2,\(a0\),v2'
  1427. +.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v2,v0.t'
  1428. +.*Error: illegal operands `vsxseg6ei512.v v2,\(a0\),v2'
  1429. +.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v2,v0.t'
  1430. +.*Error: illegal operands `vlxseg7ei512.v v2,\(a0\),v2'
  1431. +.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v2,v0.t'
  1432. +.*Error: illegal operands `vsxseg7ei512.v v2,\(a0\),v2'
  1433. +.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v2,v0.t'
  1434. +.*Error: illegal operands `vlxseg8ei512.v v2,\(a0\),v2'
  1435. +.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v2,v0.t'
  1436. +.*Error: illegal operands `vsxseg8ei512.v v2,\(a0\),v2'
  1437. +.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v2,v0.t'
  1438. +.*Error: illegal operands `vlxseg2ei1024.v v2,\(a0\),v2'
  1439. +.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v2,v0.t'
  1440. +.*Error: illegal operands `vsxseg2ei1024.v v2,\(a0\),v2'
  1441. +.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v2,v0.t'
  1442. +.*Error: illegal operands `vlxseg3ei1024.v v2,\(a0\),v2'
  1443. +.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v2,v0.t'
  1444. +.*Error: illegal operands `vsxseg3ei1024.v v2,\(a0\),v2'
  1445. +.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v2,v0.t'
  1446. +.*Error: illegal operands `vlxseg4ei1024.v v2,\(a0\),v2'
  1447. +.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v2,v0.t'
  1448. +.*Error: illegal operands `vsxseg4ei1024.v v2,\(a0\),v2'
  1449. +.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v2,v0.t'
  1450. +.*Error: illegal operands `vlxseg5ei1024.v v2,\(a0\),v2'
  1451. +.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v2,v0.t'
  1452. +.*Error: illegal operands `vsxseg5ei1024.v v2,\(a0\),v2'
  1453. +.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v2,v0.t'
  1454. +.*Error: illegal operands `vlxseg6ei1024.v v2,\(a0\),v2'
  1455. +.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v2,v0.t'
  1456. +.*Error: illegal operands `vsxseg6ei1024.v v2,\(a0\),v2'
  1457. +.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v2,v0.t'
  1458. +.*Error: illegal operands `vlxseg7ei1024.v v2,\(a0\),v2'
  1459. +.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v2,v0.t'
  1460. +.*Error: illegal operands `vsxseg7ei1024.v v2,\(a0\),v2'
  1461. +.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v2,v0.t'
  1462. +.*Error: illegal operands `vlxseg8ei1024.v v2,\(a0\),v2'
  1463. +.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v2,v0.t'
  1464. +.*Error: illegal operands `vsxseg8ei1024.v v2,\(a0\),v2'
  1465. +.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v2,v0.t'
  1466. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.s b/gas/testsuite/gas/riscv/vector-insns-fail-01.s
  1467. new file mode 100644
  1468. index 0000000000..4c1a913f2d
  1469. --- /dev/null
  1470. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-01.s
  1471. @@ -0,0 +1,1037 @@
  1472. +# Vector Unit-Stride Segment Loads and Stores
  1473. +
  1474. + vlseg2e8.v v0, (a0), v0.t # vd overlap vm
  1475. + vlseg2e8.v v4, (a0), v0.t # OK
  1476. + vsseg2e8.v v0, (a0), v0.t # OK
  1477. + vsseg2e8.v v4, (a0), v0.t # OK
  1478. + vlseg2e8ff.v v0, (a0), v0.t # vd overlap vm
  1479. + vlseg2e8ff.v v4, (a0), v0.t # OK
  1480. + vlseg3e8.v v0, (a0), v0.t # vd overlap vm
  1481. + vlseg3e8.v v4, (a0), v0.t # OK
  1482. + vsseg3e8.v v0, (a0), v0.t # OK
  1483. + vsseg3e8.v v4, (a0), v0.t # OK
  1484. + vlseg3e8ff.v v0, (a0), v0.t # vd overlap vm
  1485. + vlseg3e8ff.v v4, (a0), v0.t # OK
  1486. + vlseg4e8.v v0, (a0), v0.t # vd overlap vm
  1487. + vlseg4e8.v v4, (a0), v0.t # OK
  1488. + vsseg4e8.v v0, (a0), v0.t # OK
  1489. + vsseg4e8.v v4, (a0), v0.t # OK
  1490. + vlseg4e8ff.v v0, (a0), v0.t # vd overlap vm
  1491. + vlseg4e8ff.v v4, (a0), v0.t # OK
  1492. + vlseg5e8.v v0, (a0), v0.t # vd overlap vm
  1493. + vlseg5e8.v v4, (a0), v0.t # OK
  1494. + vsseg5e8.v v0, (a0), v0.t # OK
  1495. + vsseg5e8.v v4, (a0), v0.t # OK
  1496. + vlseg5e8ff.v v0, (a0), v0.t # vd overlap vm
  1497. + vlseg5e8ff.v v4, (a0), v0.t # OK
  1498. + vlseg6e8.v v0, (a0), v0.t # vd overlap vm
  1499. + vlseg6e8.v v4, (a0), v0.t # OK
  1500. + vsseg6e8.v v0, (a0), v0.t # OK
  1501. + vsseg6e8.v v4, (a0), v0.t # OK
  1502. + vlseg6e8ff.v v0, (a0), v0.t # vd overlap vm
  1503. + vlseg6e8ff.v v4, (a0), v0.t # OK
  1504. + vlseg7e8.v v0, (a0), v0.t # vd overlap vm
  1505. + vlseg7e8.v v4, (a0), v0.t # OK
  1506. + vsseg7e8.v v0, (a0), v0.t # OK
  1507. + vsseg7e8.v v4, (a0), v0.t # OK
  1508. + vlseg7e8ff.v v0, (a0), v0.t # vd overlap vm
  1509. + vlseg7e8ff.v v4, (a0), v0.t # OK
  1510. + vlseg8e8.v v0, (a0), v0.t # vd overlap vm
  1511. + vlseg8e8.v v4, (a0), v0.t # OK
  1512. + vsseg8e8.v v0, (a0), v0.t # OK
  1513. + vsseg8e8.v v4, (a0), v0.t # OK
  1514. + vlseg8e8ff.v v0, (a0), v0.t # vd overlap vm
  1515. + vlseg8e8ff.v v4, (a0), v0.t # OK
  1516. +
  1517. + vlseg2e16.v v0, (a0), v0.t # vd overlap vm
  1518. + vlseg2e16.v v4, (a0), v0.t # OK
  1519. + vsseg2e16.v v0, (a0), v0.t # OK
  1520. + vsseg2e16.v v4, (a0), v0.t # OK
  1521. + vlseg2e16ff.v v0, (a0), v0.t # vd overlap vm
  1522. + vlseg2e16ff.v v4, (a0), v0.t # OK
  1523. + vlseg3e16.v v0, (a0), v0.t # vd overlap vm
  1524. + vlseg3e16.v v4, (a0), v0.t # OK
  1525. + vsseg3e16.v v0, (a0), v0.t # OK
  1526. + vsseg3e16.v v4, (a0), v0.t # OK
  1527. + vlseg3e16ff.v v0, (a0), v0.t # vd overlap vm
  1528. + vlseg3e16ff.v v4, (a0), v0.t # OK
  1529. + vlseg4e16.v v0, (a0), v0.t # vd overlap vm
  1530. + vlseg4e16.v v4, (a0), v0.t # OK
  1531. + vsseg4e16.v v0, (a0), v0.t # OK
  1532. + vsseg4e16.v v4, (a0), v0.t # OK
  1533. + vlseg4e16ff.v v0, (a0), v0.t # vd overlap vm
  1534. + vlseg4e16ff.v v4, (a0), v0.t # OK
  1535. + vlseg5e16.v v0, (a0), v0.t # vd overlap vm
  1536. + vlseg5e16.v v4, (a0), v0.t # OK
  1537. + vsseg5e16.v v0, (a0), v0.t # OK
  1538. + vsseg5e16.v v4, (a0), v0.t # OK
  1539. + vlseg5e16ff.v v0, (a0), v0.t # vd overlap vm
  1540. + vlseg5e16ff.v v4, (a0), v0.t # OK
  1541. + vlseg6e16.v v0, (a0), v0.t # vd overlap vm
  1542. + vlseg6e16.v v4, (a0), v0.t # OK
  1543. + vsseg6e16.v v0, (a0), v0.t # OK
  1544. + vsseg6e16.v v4, (a0), v0.t # OK
  1545. + vlseg6e16ff.v v0, (a0), v0.t # vd overlap vm
  1546. + vlseg6e16ff.v v4, (a0), v0.t # OK
  1547. + vlseg7e16.v v0, (a0), v0.t # vd overlap vm
  1548. + vlseg7e16.v v4, (a0), v0.t # OK
  1549. + vsseg7e16.v v0, (a0), v0.t # OK
  1550. + vsseg7e16.v v4, (a0), v0.t # OK
  1551. + vlseg7e16ff.v v0, (a0), v0.t # vd overlap vm
  1552. + vlseg7e16ff.v v4, (a0), v0.t # OK
  1553. + vlseg8e16.v v0, (a0), v0.t # vd overlap vm
  1554. + vlseg8e16.v v4, (a0), v0.t # OK
  1555. + vsseg8e16.v v0, (a0), v0.t # OK
  1556. + vsseg8e16.v v4, (a0), v0.t # OK
  1557. + vlseg8e16ff.v v0, (a0), v0.t # vd overlap vm
  1558. + vlseg8e16ff.v v4, (a0), v0.t # OK
  1559. +
  1560. + vlseg2e32.v v0, (a0), v0.t # vd overlap vm
  1561. + vlseg2e32.v v4, (a0), v0.t # OK
  1562. + vsseg2e32.v v0, (a0), v0.t # OK
  1563. + vsseg2e32.v v4, (a0), v0.t # OK
  1564. + vlseg2e32ff.v v0, (a0), v0.t # vd overlap vm
  1565. + vlseg2e32ff.v v4, (a0), v0.t # OK
  1566. + vlseg3e32.v v0, (a0), v0.t # vd overlap vm
  1567. + vlseg3e32.v v4, (a0), v0.t # OK
  1568. + vsseg3e32.v v0, (a0), v0.t # OK
  1569. + vsseg3e32.v v4, (a0), v0.t # OK
  1570. + vlseg3e32ff.v v0, (a0), v0.t # vd overlap vm
  1571. + vlseg3e32ff.v v4, (a0), v0.t # OK
  1572. + vlseg4e32.v v0, (a0), v0.t # vd overlap vm
  1573. + vlseg4e32.v v4, (a0), v0.t # OK
  1574. + vsseg4e32.v v0, (a0), v0.t # OK
  1575. + vsseg4e32.v v4, (a0), v0.t # OK
  1576. + vlseg4e32ff.v v0, (a0), v0.t # vd overlap vm
  1577. + vlseg4e32ff.v v4, (a0), v0.t # OK
  1578. + vlseg5e32.v v0, (a0), v0.t # vd overlap vm
  1579. + vlseg5e32.v v4, (a0), v0.t # OK
  1580. + vsseg5e32.v v0, (a0), v0.t # OK
  1581. + vsseg5e32.v v4, (a0), v0.t # OK
  1582. + vlseg5e32ff.v v0, (a0), v0.t # vd overlap vm
  1583. + vlseg5e32ff.v v4, (a0), v0.t # OK
  1584. + vlseg6e32.v v0, (a0), v0.t # vd overlap vm
  1585. + vlseg6e32.v v4, (a0), v0.t # OK
  1586. + vsseg6e32.v v0, (a0), v0.t # OK
  1587. + vsseg6e32.v v4, (a0), v0.t # OK
  1588. + vlseg6e32ff.v v0, (a0), v0.t # vd overlap vm
  1589. + vlseg6e32ff.v v4, (a0), v0.t # OK
  1590. + vlseg7e32.v v0, (a0), v0.t # vd overlap vm
  1591. + vlseg7e32.v v4, (a0), v0.t # OK
  1592. + vsseg7e32.v v0, (a0), v0.t # OK
  1593. + vsseg7e32.v v4, (a0), v0.t # OK
  1594. + vlseg7e32ff.v v0, (a0), v0.t # vd overlap vm
  1595. + vlseg7e32ff.v v4, (a0), v0.t # OK
  1596. + vlseg8e32.v v0, (a0), v0.t # vd overlap vm
  1597. + vlseg8e32.v v4, (a0), v0.t # OK
  1598. + vsseg8e32.v v0, (a0), v0.t # OK
  1599. + vsseg8e32.v v4, (a0), v0.t # OK
  1600. + vlseg8e32ff.v v0, (a0), v0.t # vd overlap vm
  1601. + vlseg8e32ff.v v4, (a0), v0.t # OK
  1602. +
  1603. + vlseg2e64.v v0, (a0), v0.t # vd overlap vm
  1604. + vlseg2e64.v v4, (a0), v0.t # OK
  1605. + vsseg2e64.v v0, (a0), v0.t # OK
  1606. + vsseg2e64.v v4, (a0), v0.t # OK
  1607. + vlseg2e64ff.v v0, (a0), v0.t # vd overlap vm
  1608. + vlseg2e64ff.v v4, (a0), v0.t # OK
  1609. + vlseg3e64.v v0, (a0), v0.t # vd overlap vm
  1610. + vlseg3e64.v v4, (a0), v0.t # OK
  1611. + vsseg3e64.v v0, (a0), v0.t # OK
  1612. + vsseg3e64.v v4, (a0), v0.t # OK
  1613. + vlseg3e64ff.v v0, (a0), v0.t # vd overlap vm
  1614. + vlseg3e64ff.v v4, (a0), v0.t # OK
  1615. + vlseg4e64.v v0, (a0), v0.t # vd overlap vm
  1616. + vlseg4e64.v v4, (a0), v0.t # OK
  1617. + vsseg4e64.v v0, (a0), v0.t # OK
  1618. + vsseg4e64.v v4, (a0), v0.t # OK
  1619. + vlseg4e64ff.v v0, (a0), v0.t # vd overlap vm
  1620. + vlseg4e64ff.v v4, (a0), v0.t # OK
  1621. + vlseg5e64.v v0, (a0), v0.t # vd overlap vm
  1622. + vlseg5e64.v v4, (a0), v0.t # OK
  1623. + vsseg5e64.v v0, (a0), v0.t # OK
  1624. + vsseg5e64.v v4, (a0), v0.t # OK
  1625. + vlseg5e64ff.v v0, (a0), v0.t # vd overlap vm
  1626. + vlseg5e64ff.v v4, (a0), v0.t # OK
  1627. + vlseg6e64.v v0, (a0), v0.t # vd overlap vm
  1628. + vlseg6e64.v v4, (a0), v0.t # OK
  1629. + vsseg6e64.v v0, (a0), v0.t # OK
  1630. + vsseg6e64.v v4, (a0), v0.t # OK
  1631. + vlseg6e64ff.v v0, (a0), v0.t # vd overlap vm
  1632. + vlseg6e64ff.v v4, (a0), v0.t # OK
  1633. + vlseg7e64.v v0, (a0), v0.t # vd overlap vm
  1634. + vlseg7e64.v v4, (a0), v0.t # OK
  1635. + vsseg7e64.v v0, (a0), v0.t # OK
  1636. + vsseg7e64.v v4, (a0), v0.t # OK
  1637. + vlseg7e64ff.v v0, (a0), v0.t # vd overlap vm
  1638. + vlseg7e64ff.v v4, (a0), v0.t # OK
  1639. + vlseg8e64.v v0, (a0), v0.t # vd overlap vm
  1640. + vlseg8e64.v v4, (a0), v0.t # OK
  1641. + vsseg8e64.v v0, (a0), v0.t # OK
  1642. + vsseg8e64.v v4, (a0), v0.t # OK
  1643. + vlseg8e64ff.v v0, (a0), v0.t # vd overlap vm
  1644. + vlseg8e64ff.v v4, (a0), v0.t # OK
  1645. +
  1646. + vlseg2e128.v v0, (a0), v0.t # vd overlap vm
  1647. + vlseg2e128.v v4, (a0), v0.t # OK
  1648. + vsseg2e128.v v0, (a0), v0.t # OK
  1649. + vsseg2e128.v v4, (a0), v0.t # OK
  1650. + vlseg2e128ff.v v0, (a0), v0.t # vd overlap vm
  1651. + vlseg2e128ff.v v4, (a0), v0.t # OK
  1652. + vlseg3e128.v v0, (a0), v0.t # vd overlap vm
  1653. + vlseg3e128.v v4, (a0), v0.t # OK
  1654. + vsseg3e128.v v0, (a0), v0.t # OK
  1655. + vsseg3e128.v v4, (a0), v0.t # OK
  1656. + vlseg3e128ff.v v0, (a0), v0.t # vd overlap vm
  1657. + vlseg3e128ff.v v4, (a0), v0.t # OK
  1658. + vlseg4e128.v v0, (a0), v0.t # vd overlap vm
  1659. + vlseg4e128.v v4, (a0), v0.t # OK
  1660. + vsseg4e128.v v0, (a0), v0.t # OK
  1661. + vsseg4e128.v v4, (a0), v0.t # OK
  1662. + vlseg4e128ff.v v0, (a0), v0.t # vd overlap vm
  1663. + vlseg4e128ff.v v4, (a0), v0.t # OK
  1664. + vlseg5e128.v v0, (a0), v0.t # vd overlap vm
  1665. + vlseg5e128.v v4, (a0), v0.t # OK
  1666. + vsseg5e128.v v0, (a0), v0.t # OK
  1667. + vsseg5e128.v v4, (a0), v0.t # OK
  1668. + vlseg5e128ff.v v0, (a0), v0.t # vd overlap vm
  1669. + vlseg5e128ff.v v4, (a0), v0.t # OK
  1670. + vlseg6e128.v v0, (a0), v0.t # vd overlap vm
  1671. + vlseg6e128.v v4, (a0), v0.t # OK
  1672. + vsseg6e128.v v0, (a0), v0.t # OK
  1673. + vsseg6e128.v v4, (a0), v0.t # OK
  1674. + vlseg6e128ff.v v0, (a0), v0.t # vd overlap vm
  1675. + vlseg6e128ff.v v4, (a0), v0.t # OK
  1676. + vlseg7e128.v v0, (a0), v0.t # vd overlap vm
  1677. + vlseg7e128.v v4, (a0), v0.t # OK
  1678. + vsseg7e128.v v0, (a0), v0.t # OK
  1679. + vsseg7e128.v v4, (a0), v0.t # OK
  1680. + vlseg7e128ff.v v0, (a0), v0.t # vd overlap vm
  1681. + vlseg7e128ff.v v4, (a0), v0.t # OK
  1682. + vlseg8e128.v v0, (a0), v0.t # vd overlap vm
  1683. + vlseg8e128.v v4, (a0), v0.t # OK
  1684. + vsseg8e128.v v0, (a0), v0.t # OK
  1685. + vsseg8e128.v v4, (a0), v0.t # OK
  1686. + vlseg8e128ff.v v0, (a0), v0.t # vd overlap vm
  1687. + vlseg8e128ff.v v4, (a0), v0.t # OK
  1688. +
  1689. + vlseg2e256.v v0, (a0), v0.t # vd overlap vm
  1690. + vlseg2e256.v v4, (a0), v0.t # OK
  1691. + vsseg2e256.v v0, (a0), v0.t # OK
  1692. + vsseg2e256.v v4, (a0), v0.t # OK
  1693. + vlseg2e256ff.v v0, (a0), v0.t # vd overlap vm
  1694. + vlseg2e256ff.v v4, (a0), v0.t # OK
  1695. + vlseg3e256.v v0, (a0), v0.t # vd overlap vm
  1696. + vlseg3e256.v v4, (a0), v0.t # OK
  1697. + vsseg3e256.v v0, (a0), v0.t # OK
  1698. + vsseg3e256.v v4, (a0), v0.t # OK
  1699. + vlseg3e256ff.v v0, (a0), v0.t # vd overlap vm
  1700. + vlseg3e256ff.v v4, (a0), v0.t # OK
  1701. + vlseg4e256.v v0, (a0), v0.t # vd overlap vm
  1702. + vlseg4e256.v v4, (a0), v0.t # OK
  1703. + vsseg4e256.v v0, (a0), v0.t # OK
  1704. + vsseg4e256.v v4, (a0), v0.t # OK
  1705. + vlseg4e256ff.v v0, (a0), v0.t # vd overlap vm
  1706. + vlseg4e256ff.v v4, (a0), v0.t # OK
  1707. + vlseg5e256.v v0, (a0), v0.t # vd overlap vm
  1708. + vlseg5e256.v v4, (a0), v0.t # OK
  1709. + vsseg5e256.v v0, (a0), v0.t # OK
  1710. + vsseg5e256.v v4, (a0), v0.t # OK
  1711. + vlseg5e256ff.v v0, (a0), v0.t # vd overlap vm
  1712. + vlseg5e256ff.v v4, (a0), v0.t # OK
  1713. + vlseg6e256.v v0, (a0), v0.t # vd overlap vm
  1714. + vlseg6e256.v v4, (a0), v0.t # OK
  1715. + vsseg6e256.v v0, (a0), v0.t # OK
  1716. + vsseg6e256.v v4, (a0), v0.t # OK
  1717. + vlseg6e256ff.v v0, (a0), v0.t # vd overlap vm
  1718. + vlseg6e256ff.v v4, (a0), v0.t # OK
  1719. + vlseg7e256.v v0, (a0), v0.t # vd overlap vm
  1720. + vlseg7e256.v v4, (a0), v0.t # OK
  1721. + vsseg7e256.v v0, (a0), v0.t # OK
  1722. + vsseg7e256.v v4, (a0), v0.t # OK
  1723. + vlseg7e256ff.v v0, (a0), v0.t # vd overlap vm
  1724. + vlseg7e256ff.v v4, (a0), v0.t # OK
  1725. + vlseg8e256.v v0, (a0), v0.t # vd overlap vm
  1726. + vlseg8e256.v v4, (a0), v0.t # OK
  1727. + vsseg8e256.v v0, (a0), v0.t # OK
  1728. + vsseg8e256.v v4, (a0), v0.t # OK
  1729. + vlseg8e256ff.v v0, (a0), v0.t # vd overlap vm
  1730. + vlseg8e256ff.v v4, (a0), v0.t # OK
  1731. +
  1732. + vlseg2e512.v v0, (a0), v0.t # vd overlap vm
  1733. + vlseg2e512.v v4, (a0), v0.t # OK
  1734. + vsseg2e512.v v0, (a0), v0.t # OK
  1735. + vsseg2e512.v v4, (a0), v0.t # OK
  1736. + vlseg2e512ff.v v0, (a0), v0.t # vd overlap vm
  1737. + vlseg2e512ff.v v4, (a0), v0.t # OK
  1738. + vlseg3e512.v v0, (a0), v0.t # vd overlap vm
  1739. + vlseg3e512.v v4, (a0), v0.t # OK
  1740. + vsseg3e512.v v0, (a0), v0.t # OK
  1741. + vsseg3e512.v v4, (a0), v0.t # OK
  1742. + vlseg3e512ff.v v0, (a0), v0.t # vd overlap vm
  1743. + vlseg3e512ff.v v4, (a0), v0.t # OK
  1744. + vlseg4e512.v v0, (a0), v0.t # vd overlap vm
  1745. + vlseg4e512.v v4, (a0), v0.t # OK
  1746. + vsseg4e512.v v0, (a0), v0.t # OK
  1747. + vsseg4e512.v v4, (a0), v0.t # OK
  1748. + vlseg4e512ff.v v0, (a0), v0.t # vd overlap vm
  1749. + vlseg4e512ff.v v4, (a0), v0.t # OK
  1750. + vlseg5e512.v v0, (a0), v0.t # vd overlap vm
  1751. + vlseg5e512.v v4, (a0), v0.t # OK
  1752. + vsseg5e512.v v0, (a0), v0.t # OK
  1753. + vsseg5e512.v v4, (a0), v0.t # OK
  1754. + vlseg5e512ff.v v0, (a0), v0.t # vd overlap vm
  1755. + vlseg5e512ff.v v4, (a0), v0.t # OK
  1756. + vlseg6e512.v v0, (a0), v0.t # vd overlap vm
  1757. + vlseg6e512.v v4, (a0), v0.t # OK
  1758. + vsseg6e512.v v0, (a0), v0.t # OK
  1759. + vsseg6e512.v v4, (a0), v0.t # OK
  1760. + vlseg6e512ff.v v0, (a0), v0.t # vd overlap vm
  1761. + vlseg6e512ff.v v4, (a0), v0.t # OK
  1762. + vlseg7e512.v v0, (a0), v0.t # vd overlap vm
  1763. + vlseg7e512.v v4, (a0), v0.t # OK
  1764. + vsseg7e512.v v0, (a0), v0.t # OK
  1765. + vsseg7e512.v v4, (a0), v0.t # OK
  1766. + vlseg7e512ff.v v0, (a0), v0.t # vd overlap vm
  1767. + vlseg7e512ff.v v4, (a0), v0.t # OK
  1768. + vlseg8e512.v v0, (a0), v0.t # vd overlap vm
  1769. + vlseg8e512.v v4, (a0), v0.t # OK
  1770. + vsseg8e512.v v0, (a0), v0.t # OK
  1771. + vsseg8e512.v v4, (a0), v0.t # OK
  1772. + vlseg8e512ff.v v0, (a0), v0.t # vd overlap vm
  1773. + vlseg8e512ff.v v4, (a0), v0.t # OK
  1774. +
  1775. + vlseg2e1024.v v0, (a0), v0.t # vd overlap vm
  1776. + vlseg2e1024.v v4, (a0), v0.t # OK
  1777. + vsseg2e1024.v v0, (a0), v0.t # OK
  1778. + vsseg2e1024.v v4, (a0), v0.t # OK
  1779. + vlseg2e1024ff.v v0, (a0), v0.t # vd overlap vm
  1780. + vlseg2e1024ff.v v4, (a0), v0.t # OK
  1781. + vlseg3e1024.v v0, (a0), v0.t # vd overlap vm
  1782. + vlseg3e1024.v v4, (a0), v0.t # OK
  1783. + vsseg3e1024.v v0, (a0), v0.t # OK
  1784. + vsseg3e1024.v v4, (a0), v0.t # OK
  1785. + vlseg3e1024ff.v v0, (a0), v0.t # vd overlap vm
  1786. + vlseg3e1024ff.v v4, (a0), v0.t # OK
  1787. + vlseg4e1024.v v0, (a0), v0.t # vd overlap vm
  1788. + vlseg4e1024.v v4, (a0), v0.t # OK
  1789. + vsseg4e1024.v v0, (a0), v0.t # OK
  1790. + vsseg4e1024.v v4, (a0), v0.t # OK
  1791. + vlseg4e1024ff.v v0, (a0), v0.t # vd overlap vm
  1792. + vlseg4e1024ff.v v4, (a0), v0.t # OK
  1793. + vlseg5e1024.v v0, (a0), v0.t # vd overlap vm
  1794. + vlseg5e1024.v v4, (a0), v0.t # OK
  1795. + vsseg5e1024.v v0, (a0), v0.t # OK
  1796. + vsseg5e1024.v v4, (a0), v0.t # OK
  1797. + vlseg5e1024ff.v v0, (a0), v0.t # vd overlap vm
  1798. + vlseg5e1024ff.v v4, (a0), v0.t # OK
  1799. + vlseg6e1024.v v0, (a0), v0.t # vd overlap vm
  1800. + vlseg6e1024.v v4, (a0), v0.t # OK
  1801. + vsseg6e1024.v v0, (a0), v0.t # OK
  1802. + vsseg6e1024.v v4, (a0), v0.t # OK
  1803. + vlseg6e1024ff.v v0, (a0), v0.t # vd overlap vm
  1804. + vlseg6e1024ff.v v4, (a0), v0.t # OK
  1805. + vlseg7e1024.v v0, (a0), v0.t # vd overlap vm
  1806. + vlseg7e1024.v v4, (a0), v0.t # OK
  1807. + vsseg7e1024.v v0, (a0), v0.t # OK
  1808. + vsseg7e1024.v v4, (a0), v0.t # OK
  1809. + vlseg7e1024ff.v v0, (a0), v0.t # vd overlap vm
  1810. + vlseg7e1024ff.v v4, (a0), v0.t # OK
  1811. + vlseg8e1024.v v0, (a0), v0.t # vd overlap vm
  1812. + vlseg8e1024.v v4, (a0), v0.t # OK
  1813. + vsseg8e1024.v v0, (a0), v0.t # OK
  1814. + vsseg8e1024.v v4, (a0), v0.t # OK
  1815. + vlseg8e1024ff.v v0, (a0), v0.t # vd overlap vm
  1816. + vlseg8e1024ff.v v4, (a0), v0.t # OK
  1817. +
  1818. +# Vector Strided Segment Loads and Stores
  1819. +
  1820. + vlsseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
  1821. + vlsseg2e8.v v4, (a0), a1, v0.t # OK
  1822. + vssseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
  1823. + vssseg2e8.v v4, (a0), a1, v0.t # OK
  1824. + vlsseg3e8.v v0, (a0), a1, v0.t # vd overlap vm
  1825. + vlsseg3e8.v v4, (a0), a1, v0.t # OK
  1826. + vssseg3e8.v v0, (a0), a1, v0.t # vd overlap vm
  1827. + vssseg3e8.v v4, (a0), a1, v0.t # OK
  1828. + vlsseg4e8.v v0, (a0), a1, v0.t # vd overlap vm
  1829. + vlsseg4e8.v v4, (a0), a1, v0.t # OK
  1830. + vssseg4e8.v v0, (a0), a1, v0.t # vd overlap vm
  1831. + vssseg4e8.v v4, (a0), a1, v0.t # OK
  1832. + vlsseg5e8.v v0, (a0), a1, v0.t # vd overlap vm
  1833. + vlsseg5e8.v v4, (a0), a1, v0.t # OK
  1834. + vssseg5e8.v v0, (a0), a1, v0.t # vd overlap vm
  1835. + vssseg5e8.v v4, (a0), a1, v0.t # OK
  1836. + vlsseg6e8.v v0, (a0), a1, v0.t # vd overlap vm
  1837. + vlsseg6e8.v v4, (a0), a1, v0.t # OK
  1838. + vssseg6e8.v v0, (a0), a1, v0.t # vd overlap vm
  1839. + vssseg6e8.v v4, (a0), a1, v0.t # OK
  1840. + vlsseg7e8.v v0, (a0), a1, v0.t # vd overlap vm
  1841. + vlsseg7e8.v v4, (a0), a1, v0.t # OK
  1842. + vssseg7e8.v v0, (a0), a1, v0.t # vd overlap vm
  1843. + vssseg7e8.v v4, (a0), a1, v0.t # OK
  1844. + vlsseg8e8.v v0, (a0), a1, v0.t # vd overlap vm
  1845. + vlsseg8e8.v v4, (a0), a1, v0.t # OK
  1846. + vssseg8e8.v v0, (a0), a1, v0.t # vd overlap vm
  1847. + vssseg8e8.v v4, (a0), a1, v0.t # OK
  1848. +
  1849. + vlsseg2e16.v v0, (a0), a1, v0.t # vd overlap vm
  1850. + vlsseg2e16.v v4, (a0), a1, v0.t # OK
  1851. + vssseg2e16.v v0, (a0), a1, v0.t # vd overlap vm
  1852. + vssseg2e16.v v4, (a0), a1, v0.t # OK
  1853. + vlsseg3e16.v v0, (a0), a1, v0.t # vd overlap vm
  1854. + vlsseg3e16.v v4, (a0), a1, v0.t # OK
  1855. + vssseg3e16.v v0, (a0), a1, v0.t # vd overlap vm
  1856. + vssseg3e16.v v4, (a0), a1, v0.t # OK
  1857. + vlsseg4e16.v v0, (a0), a1, v0.t # vd overlap vm
  1858. + vlsseg4e16.v v4, (a0), a1, v0.t # OK
  1859. + vssseg4e16.v v0, (a0), a1, v0.t # vd overlap vm
  1860. + vssseg4e16.v v4, (a0), a1, v0.t # OK
  1861. + vlsseg5e16.v v0, (a0), a1, v0.t # vd overlap vm
  1862. + vlsseg5e16.v v4, (a0), a1, v0.t # OK
  1863. + vssseg5e16.v v0, (a0), a1, v0.t # vd overlap vm
  1864. + vssseg5e16.v v4, (a0), a1, v0.t # OK
  1865. + vlsseg6e16.v v0, (a0), a1, v0.t # vd overlap vm
  1866. + vlsseg6e16.v v4, (a0), a1, v0.t # OK
  1867. + vssseg6e16.v v0, (a0), a1, v0.t # vd overlap vm
  1868. + vssseg6e16.v v4, (a0), a1, v0.t # OK
  1869. + vlsseg7e16.v v0, (a0), a1, v0.t # vd overlap vm
  1870. + vlsseg7e16.v v4, (a0), a1, v0.t # OK
  1871. + vssseg7e16.v v0, (a0), a1, v0.t # vd overlap vm
  1872. + vssseg7e16.v v4, (a0), a1, v0.t # OK
  1873. + vlsseg8e16.v v0, (a0), a1, v0.t # vd overlap vm
  1874. + vlsseg8e16.v v4, (a0), a1, v0.t # OK
  1875. + vssseg8e16.v v0, (a0), a1, v0.t # vd overlap vm
  1876. + vssseg8e16.v v4, (a0), a1, v0.t # OK
  1877. +
  1878. + vlsseg2e32.v v0, (a0), a1, v0.t # vd overlap vm
  1879. + vlsseg2e32.v v4, (a0), a1, v0.t # OK
  1880. + vssseg2e32.v v0, (a0), a1, v0.t # vd overlap vm
  1881. + vssseg2e32.v v4, (a0), a1, v0.t # OK
  1882. + vlsseg3e32.v v0, (a0), a1, v0.t # vd overlap vm
  1883. + vlsseg3e32.v v4, (a0), a1, v0.t # OK
  1884. + vssseg3e32.v v0, (a0), a1, v0.t # vd overlap vm
  1885. + vssseg3e32.v v4, (a0), a1, v0.t # OK
  1886. + vlsseg4e32.v v0, (a0), a1, v0.t # vd overlap vm
  1887. + vlsseg4e32.v v4, (a0), a1, v0.t # OK
  1888. + vssseg4e32.v v0, (a0), a1, v0.t # vd overlap vm
  1889. + vssseg4e32.v v4, (a0), a1, v0.t # OK
  1890. + vlsseg5e32.v v0, (a0), a1, v0.t # vd overlap vm
  1891. + vlsseg5e32.v v4, (a0), a1, v0.t # OK
  1892. + vssseg5e32.v v0, (a0), a1, v0.t # vd overlap vm
  1893. + vssseg5e32.v v4, (a0), a1, v0.t # OK
  1894. + vlsseg6e32.v v0, (a0), a1, v0.t # vd overlap vm
  1895. + vlsseg6e32.v v4, (a0), a1, v0.t # OK
  1896. + vssseg6e32.v v0, (a0), a1, v0.t # vd overlap vm
  1897. + vssseg6e32.v v4, (a0), a1, v0.t # OK
  1898. + vlsseg7e32.v v0, (a0), a1, v0.t # vd overlap vm
  1899. + vlsseg7e32.v v4, (a0), a1, v0.t # OK
  1900. + vssseg7e32.v v0, (a0), a1, v0.t # vd overlap vm
  1901. + vssseg7e32.v v4, (a0), a1, v0.t # OK
  1902. + vlsseg8e32.v v0, (a0), a1, v0.t # vd overlap vm
  1903. + vlsseg8e32.v v4, (a0), a1, v0.t # OK
  1904. + vssseg8e32.v v0, (a0), a1, v0.t # vd overlap vm
  1905. + vssseg8e32.v v4, (a0), a1, v0.t # OK
  1906. +
  1907. + vlsseg2e64.v v0, (a0), a1, v0.t # vd overlap vm
  1908. + vlsseg2e64.v v4, (a0), a1, v0.t # OK
  1909. + vssseg2e64.v v0, (a0), a1, v0.t # vd overlap vm
  1910. + vssseg2e64.v v4, (a0), a1, v0.t # OK
  1911. + vlsseg3e64.v v0, (a0), a1, v0.t # vd overlap vm
  1912. + vlsseg3e64.v v4, (a0), a1, v0.t # OK
  1913. + vssseg3e64.v v0, (a0), a1, v0.t # vd overlap vm
  1914. + vssseg3e64.v v4, (a0), a1, v0.t # OK
  1915. + vlsseg4e64.v v0, (a0), a1, v0.t # vd overlap vm
  1916. + vlsseg4e64.v v4, (a0), a1, v0.t # OK
  1917. + vssseg4e64.v v0, (a0), a1, v0.t # vd overlap vm
  1918. + vssseg4e64.v v4, (a0), a1, v0.t # OK
  1919. + vlsseg5e64.v v0, (a0), a1, v0.t # vd overlap vm
  1920. + vlsseg5e64.v v4, (a0), a1, v0.t # OK
  1921. + vssseg5e64.v v0, (a0), a1, v0.t # vd overlap vm
  1922. + vssseg5e64.v v4, (a0), a1, v0.t # OK
  1923. + vlsseg6e64.v v0, (a0), a1, v0.t # vd overlap vm
  1924. + vlsseg6e64.v v4, (a0), a1, v0.t # OK
  1925. + vssseg6e64.v v0, (a0), a1, v0.t # vd overlap vm
  1926. + vssseg6e64.v v4, (a0), a1, v0.t # OK
  1927. + vlsseg7e64.v v0, (a0), a1, v0.t # vd overlap vm
  1928. + vlsseg7e64.v v4, (a0), a1, v0.t # OK
  1929. + vssseg7e64.v v0, (a0), a1, v0.t # vd overlap vm
  1930. + vssseg7e64.v v4, (a0), a1, v0.t # OK
  1931. + vlsseg8e64.v v0, (a0), a1, v0.t # vd overlap vm
  1932. + vlsseg8e64.v v4, (a0), a1, v0.t # OK
  1933. + vssseg8e64.v v0, (a0), a1, v0.t # vd overlap vm
  1934. + vssseg8e64.v v4, (a0), a1, v0.t # OK
  1935. +
  1936. + vlsseg2e128.v v0, (a0), a1, v0.t # vd overlap vm
  1937. + vlsseg2e128.v v4, (a0), a1, v0.t # OK
  1938. + vssseg2e128.v v0, (a0), a1, v0.t # vd overlap vm
  1939. + vssseg2e128.v v4, (a0), a1, v0.t # OK
  1940. + vlsseg3e128.v v0, (a0), a1, v0.t # vd overlap vm
  1941. + vlsseg3e128.v v4, (a0), a1, v0.t # OK
  1942. + vssseg3e128.v v0, (a0), a1, v0.t # vd overlap vm
  1943. + vssseg3e128.v v4, (a0), a1, v0.t # OK
  1944. + vlsseg4e128.v v0, (a0), a1, v0.t # vd overlap vm
  1945. + vlsseg4e128.v v4, (a0), a1, v0.t # OK
  1946. + vssseg4e128.v v0, (a0), a1, v0.t # vd overlap vm
  1947. + vssseg4e128.v v4, (a0), a1, v0.t # OK
  1948. + vlsseg5e128.v v0, (a0), a1, v0.t # vd overlap vm
  1949. + vlsseg5e128.v v4, (a0), a1, v0.t # OK
  1950. + vssseg5e128.v v0, (a0), a1, v0.t # vd overlap vm
  1951. + vssseg5e128.v v4, (a0), a1, v0.t # OK
  1952. + vlsseg6e128.v v0, (a0), a1, v0.t # vd overlap vm
  1953. + vlsseg6e128.v v4, (a0), a1, v0.t # OK
  1954. + vssseg6e128.v v0, (a0), a1, v0.t # vd overlap vm
  1955. + vssseg6e128.v v4, (a0), a1, v0.t # OK
  1956. + vlsseg7e128.v v0, (a0), a1, v0.t # vd overlap vm
  1957. + vlsseg7e128.v v4, (a0), a1, v0.t # OK
  1958. + vssseg7e128.v v0, (a0), a1, v0.t # vd overlap vm
  1959. + vssseg7e128.v v4, (a0), a1, v0.t # OK
  1960. + vlsseg8e128.v v0, (a0), a1, v0.t # vd overlap vm
  1961. + vlsseg8e128.v v4, (a0), a1, v0.t # OK
  1962. + vssseg8e128.v v0, (a0), a1, v0.t # vd overlap vm
  1963. + vssseg8e128.v v4, (a0), a1, v0.t # OK
  1964. +
  1965. + vlsseg2e256.v v0, (a0), a1, v0.t # vd overlap vm
  1966. + vlsseg2e256.v v4, (a0), a1, v0.t # OK
  1967. + vssseg2e256.v v0, (a0), a1, v0.t # vd overlap vm
  1968. + vssseg2e256.v v4, (a0), a1, v0.t # OK
  1969. + vlsseg3e256.v v0, (a0), a1, v0.t # vd overlap vm
  1970. + vlsseg3e256.v v4, (a0), a1, v0.t # OK
  1971. + vssseg3e256.v v0, (a0), a1, v0.t # vd overlap vm
  1972. + vssseg3e256.v v4, (a0), a1, v0.t # OK
  1973. + vlsseg4e256.v v0, (a0), a1, v0.t # vd overlap vm
  1974. + vlsseg4e256.v v4, (a0), a1, v0.t # OK
  1975. + vssseg4e256.v v0, (a0), a1, v0.t # vd overlap vm
  1976. + vssseg4e256.v v4, (a0), a1, v0.t # OK
  1977. + vlsseg5e256.v v0, (a0), a1, v0.t # vd overlap vm
  1978. + vlsseg5e256.v v4, (a0), a1, v0.t # OK
  1979. + vssseg5e256.v v0, (a0), a1, v0.t # vd overlap vm
  1980. + vssseg5e256.v v4, (a0), a1, v0.t # OK
  1981. + vlsseg6e256.v v0, (a0), a1, v0.t # vd overlap vm
  1982. + vlsseg6e256.v v4, (a0), a1, v0.t # OK
  1983. + vssseg6e256.v v0, (a0), a1, v0.t # vd overlap vm
  1984. + vssseg6e256.v v4, (a0), a1, v0.t # OK
  1985. + vlsseg7e256.v v0, (a0), a1, v0.t # vd overlap vm
  1986. + vlsseg7e256.v v4, (a0), a1, v0.t # OK
  1987. + vssseg7e256.v v0, (a0), a1, v0.t # vd overlap vm
  1988. + vssseg7e256.v v4, (a0), a1, v0.t # OK
  1989. + vlsseg8e256.v v0, (a0), a1, v0.t # vd overlap vm
  1990. + vlsseg8e256.v v4, (a0), a1, v0.t # OK
  1991. + vssseg8e256.v v0, (a0), a1, v0.t # vd overlap vm
  1992. + vssseg8e256.v v4, (a0), a1, v0.t # OK
  1993. +
  1994. + vlsseg2e512.v v0, (a0), a1, v0.t # vd overlap vm
  1995. + vlsseg2e512.v v4, (a0), a1, v0.t # OK
  1996. + vssseg2e512.v v0, (a0), a1, v0.t # vd overlap vm
  1997. + vssseg2e512.v v4, (a0), a1, v0.t # OK
  1998. + vlsseg3e512.v v0, (a0), a1, v0.t # vd overlap vm
  1999. + vlsseg3e512.v v4, (a0), a1, v0.t # OK
  2000. + vssseg3e512.v v0, (a0), a1, v0.t # vd overlap vm
  2001. + vssseg3e512.v v4, (a0), a1, v0.t # OK
  2002. + vlsseg4e512.v v0, (a0), a1, v0.t # vd overlap vm
  2003. + vlsseg4e512.v v4, (a0), a1, v0.t # OK
  2004. + vssseg4e512.v v0, (a0), a1, v0.t # vd overlap vm
  2005. + vssseg4e512.v v4, (a0), a1, v0.t # OK
  2006. + vlsseg5e512.v v0, (a0), a1, v0.t # vd overlap vm
  2007. + vlsseg5e512.v v4, (a0), a1, v0.t # OK
  2008. + vssseg5e512.v v0, (a0), a1, v0.t # vd overlap vm
  2009. + vssseg5e512.v v4, (a0), a1, v0.t # OK
  2010. + vlsseg6e512.v v0, (a0), a1, v0.t # vd overlap vm
  2011. + vlsseg6e512.v v4, (a0), a1, v0.t # OK
  2012. + vssseg6e512.v v0, (a0), a1, v0.t # vd overlap vm
  2013. + vssseg6e512.v v4, (a0), a1, v0.t # OK
  2014. + vlsseg7e512.v v0, (a0), a1, v0.t # vd overlap vm
  2015. + vlsseg7e512.v v4, (a0), a1, v0.t # OK
  2016. + vssseg7e512.v v0, (a0), a1, v0.t # vd overlap vm
  2017. + vssseg7e512.v v4, (a0), a1, v0.t # OK
  2018. + vlsseg8e512.v v0, (a0), a1, v0.t # vd overlap vm
  2019. + vlsseg8e512.v v4, (a0), a1, v0.t # OK
  2020. + vssseg8e512.v v0, (a0), a1, v0.t # vd overlap vm
  2021. + vssseg8e512.v v4, (a0), a1, v0.t # OK
  2022. +
  2023. + vlsseg2e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2024. + vlsseg2e1024.v v4, (a0), a1, v0.t # OK
  2025. + vssseg2e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2026. + vssseg2e1024.v v4, (a0), a1, v0.t # OK
  2027. + vlsseg3e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2028. + vlsseg3e1024.v v4, (a0), a1, v0.t # OK
  2029. + vssseg3e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2030. + vssseg3e1024.v v4, (a0), a1, v0.t # OK
  2031. + vlsseg4e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2032. + vlsseg4e1024.v v4, (a0), a1, v0.t # OK
  2033. + vssseg4e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2034. + vssseg4e1024.v v4, (a0), a1, v0.t # OK
  2035. + vlsseg5e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2036. + vlsseg5e1024.v v4, (a0), a1, v0.t # OK
  2037. + vssseg5e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2038. + vssseg5e1024.v v4, (a0), a1, v0.t # OK
  2039. + vlsseg6e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2040. + vlsseg6e1024.v v4, (a0), a1, v0.t # OK
  2041. + vssseg6e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2042. + vssseg6e1024.v v4, (a0), a1, v0.t # OK
  2043. + vlsseg7e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2044. + vlsseg7e1024.v v4, (a0), a1, v0.t # OK
  2045. + vssseg7e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2046. + vssseg7e1024.v v4, (a0), a1, v0.t # OK
  2047. + vlsseg8e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2048. + vlsseg8e1024.v v4, (a0), a1, v0.t # OK
  2049. + vssseg8e1024.v v0, (a0), a1, v0.t # vd overlap vm
  2050. + vssseg8e1024.v v4, (a0), a1, v0.t # OK
  2051. +
  2052. +# Vector Indexed Segment Loads and Stores
  2053. +
  2054. + vlxseg2ei8.v v0, (a0), v2 # OK
  2055. + vlxseg2ei8.v v1, (a0), v2 # OK
  2056. + vlxseg2ei8.v v2, (a0), v2 # vd overlap vs2
  2057. + vlxseg2ei8.v v0, (a0), v2, v0.t # vd overlap vm
  2058. + vsxseg2ei8.v v0, (a0), v2
  2059. + vsxseg2ei8.v v1, (a0), v2
  2060. + vsxseg2ei8.v v2, (a0), v2
  2061. + vsxseg2ei8.v v0, (a0), v2, v0.t
  2062. + vlxseg3ei8.v v0, (a0), v2
  2063. + vlxseg3ei8.v v1, (a0), v2
  2064. + vlxseg3ei8.v v2, (a0), v2
  2065. + vlxseg3ei8.v v0, (a0), v2, v0.t
  2066. + vsxseg3ei8.v v0, (a0), v2
  2067. + vsxseg3ei8.v v1, (a0), v2
  2068. + vsxseg3ei8.v v2, (a0), v2
  2069. + vsxseg3ei8.v v0, (a0), v2, v0.t
  2070. + vlxseg4ei8.v v0, (a0), v2
  2071. + vlxseg4ei8.v v1, (a0), v2
  2072. + vlxseg4ei8.v v2, (a0), v2
  2073. + vlxseg4ei8.v v0, (a0), v2, v0.t
  2074. + vsxseg4ei8.v v0, (a0), v2
  2075. + vsxseg4ei8.v v1, (a0), v2
  2076. + vsxseg4ei8.v v2, (a0), v2
  2077. + vsxseg4ei8.v v0, (a0), v2, v0.t
  2078. + vlxseg5ei8.v v0, (a0), v2
  2079. + vlxseg5ei8.v v1, (a0), v2
  2080. + vlxseg5ei8.v v2, (a0), v2
  2081. + vlxseg5ei8.v v0, (a0), v2, v0.t
  2082. + vsxseg5ei8.v v0, (a0), v2
  2083. + vsxseg5ei8.v v1, (a0), v2
  2084. + vsxseg5ei8.v v2, (a0), v2
  2085. + vsxseg5ei8.v v0, (a0), v2, v0.t
  2086. + vlxseg6ei8.v v0, (a0), v2
  2087. + vlxseg6ei8.v v1, (a0), v2
  2088. + vlxseg6ei8.v v2, (a0), v2
  2089. + vlxseg6ei8.v v0, (a0), v2, v0.t
  2090. + vsxseg6ei8.v v0, (a0), v2
  2091. + vsxseg6ei8.v v1, (a0), v2
  2092. + vsxseg6ei8.v v2, (a0), v2
  2093. + vsxseg6ei8.v v0, (a0), v2, v0.t
  2094. + vlxseg7ei8.v v0, (a0), v2
  2095. + vlxseg7ei8.v v1, (a0), v2
  2096. + vlxseg7ei8.v v2, (a0), v2
  2097. + vlxseg7ei8.v v0, (a0), v2, v0.t
  2098. + vsxseg7ei8.v v0, (a0), v2
  2099. + vsxseg7ei8.v v1, (a0), v2
  2100. + vsxseg7ei8.v v2, (a0), v2
  2101. + vsxseg7ei8.v v0, (a0), v2, v0.t
  2102. + vlxseg8ei8.v v0, (a0), v2
  2103. + vlxseg8ei8.v v1, (a0), v2
  2104. + vlxseg8ei8.v v2, (a0), v2
  2105. + vlxseg8ei8.v v0, (a0), v2, v0.t
  2106. + vsxseg8ei8.v v0, (a0), v2
  2107. + vsxseg8ei8.v v1, (a0), v2
  2108. + vsxseg8ei8.v v2, (a0), v2
  2109. + vsxseg8ei8.v v0, (a0), v2, v0.t
  2110. +
  2111. + vlxseg2ei16.v v0, (a0), v2 # OK
  2112. + vlxseg2ei16.v v1, (a0), v2 # OK
  2113. + vlxseg2ei16.v v2, (a0), v2 # vd overlap vs2
  2114. + vlxseg2ei16.v v0, (a0), v2, v0.t # vd overlap vm
  2115. + vsxseg2ei16.v v0, (a0), v2
  2116. + vsxseg2ei16.v v1, (a0), v2
  2117. + vsxseg2ei16.v v2, (a0), v2
  2118. + vsxseg2ei16.v v0, (a0), v2, v0.t
  2119. + vlxseg3ei16.v v0, (a0), v2
  2120. + vlxseg3ei16.v v1, (a0), v2
  2121. + vlxseg3ei16.v v2, (a0), v2
  2122. + vlxseg3ei16.v v0, (a0), v2, v0.t
  2123. + vsxseg3ei16.v v0, (a0), v2
  2124. + vsxseg3ei16.v v1, (a0), v2
  2125. + vsxseg3ei16.v v2, (a0), v2
  2126. + vsxseg3ei16.v v0, (a0), v2, v0.t
  2127. + vlxseg4ei16.v v0, (a0), v2
  2128. + vlxseg4ei16.v v1, (a0), v2
  2129. + vlxseg4ei16.v v2, (a0), v2
  2130. + vlxseg4ei16.v v0, (a0), v2, v0.t
  2131. + vsxseg4ei16.v v0, (a0), v2
  2132. + vsxseg4ei16.v v1, (a0), v2
  2133. + vsxseg4ei16.v v2, (a0), v2
  2134. + vsxseg4ei16.v v0, (a0), v2, v0.t
  2135. + vlxseg5ei16.v v0, (a0), v2
  2136. + vlxseg5ei16.v v1, (a0), v2
  2137. + vlxseg5ei16.v v2, (a0), v2
  2138. + vlxseg5ei16.v v0, (a0), v2, v0.t
  2139. + vsxseg5ei16.v v0, (a0), v2
  2140. + vsxseg5ei16.v v1, (a0), v2
  2141. + vsxseg5ei16.v v2, (a0), v2
  2142. + vsxseg5ei16.v v0, (a0), v2, v0.t
  2143. + vlxseg6ei16.v v0, (a0), v2
  2144. + vlxseg6ei16.v v1, (a0), v2
  2145. + vlxseg6ei16.v v2, (a0), v2
  2146. + vlxseg6ei16.v v0, (a0), v2, v0.t
  2147. + vsxseg6ei16.v v0, (a0), v2
  2148. + vsxseg6ei16.v v1, (a0), v2
  2149. + vsxseg6ei16.v v2, (a0), v2
  2150. + vsxseg6ei16.v v0, (a0), v2, v0.t
  2151. + vlxseg7ei16.v v0, (a0), v2
  2152. + vlxseg7ei16.v v1, (a0), v2
  2153. + vlxseg7ei16.v v2, (a0), v2
  2154. + vlxseg7ei16.v v0, (a0), v2, v0.t
  2155. + vsxseg7ei16.v v0, (a0), v2
  2156. + vsxseg7ei16.v v1, (a0), v2
  2157. + vsxseg7ei16.v v2, (a0), v2
  2158. + vsxseg7ei16.v v0, (a0), v2, v0.t
  2159. + vlxseg8ei16.v v0, (a0), v2
  2160. + vlxseg8ei16.v v1, (a0), v2
  2161. + vlxseg8ei16.v v2, (a0), v2
  2162. + vlxseg8ei16.v v0, (a0), v2, v0.t
  2163. + vsxseg8ei16.v v0, (a0), v2
  2164. + vsxseg8ei16.v v1, (a0), v2
  2165. + vsxseg8ei16.v v2, (a0), v2
  2166. + vsxseg8ei16.v v0, (a0), v2, v0.t
  2167. +
  2168. + vlxseg2ei32.v v0, (a0), v2 # OK
  2169. + vlxseg2ei32.v v1, (a0), v2 # OK
  2170. + vlxseg2ei32.v v2, (a0), v2 # vd overlap vs2
  2171. + vlxseg2ei32.v v0, (a0), v2, v0.t # vd overlap vm
  2172. + vsxseg2ei32.v v0, (a0), v2
  2173. + vsxseg2ei32.v v1, (a0), v2
  2174. + vsxseg2ei32.v v2, (a0), v2
  2175. + vsxseg2ei32.v v0, (a0), v2, v0.t
  2176. + vlxseg3ei32.v v0, (a0), v2
  2177. + vlxseg3ei32.v v1, (a0), v2
  2178. + vlxseg3ei32.v v2, (a0), v2
  2179. + vlxseg3ei32.v v0, (a0), v2, v0.t
  2180. + vsxseg3ei32.v v0, (a0), v2
  2181. + vsxseg3ei32.v v1, (a0), v2
  2182. + vsxseg3ei32.v v2, (a0), v2
  2183. + vsxseg3ei32.v v0, (a0), v2, v0.t
  2184. + vlxseg4ei32.v v0, (a0), v2
  2185. + vlxseg4ei32.v v1, (a0), v2
  2186. + vlxseg4ei32.v v2, (a0), v2
  2187. + vlxseg4ei32.v v0, (a0), v2, v0.t
  2188. + vsxseg4ei32.v v0, (a0), v2
  2189. + vsxseg4ei32.v v1, (a0), v2
  2190. + vsxseg4ei32.v v2, (a0), v2
  2191. + vsxseg4ei32.v v0, (a0), v2, v0.t
  2192. + vlxseg5ei32.v v0, (a0), v2
  2193. + vlxseg5ei32.v v1, (a0), v2
  2194. + vlxseg5ei32.v v2, (a0), v2
  2195. + vlxseg5ei32.v v0, (a0), v2, v0.t
  2196. + vsxseg5ei32.v v0, (a0), v2
  2197. + vsxseg5ei32.v v1, (a0), v2
  2198. + vsxseg5ei32.v v2, (a0), v2
  2199. + vsxseg5ei32.v v0, (a0), v2, v0.t
  2200. + vlxseg6ei32.v v0, (a0), v2
  2201. + vlxseg6ei32.v v1, (a0), v2
  2202. + vlxseg6ei32.v v2, (a0), v2
  2203. + vlxseg6ei32.v v0, (a0), v2, v0.t
  2204. + vsxseg6ei32.v v0, (a0), v2
  2205. + vsxseg6ei32.v v1, (a0), v2
  2206. + vsxseg6ei32.v v2, (a0), v2
  2207. + vsxseg6ei32.v v0, (a0), v2, v0.t
  2208. + vlxseg7ei32.v v0, (a0), v2
  2209. + vlxseg7ei32.v v1, (a0), v2
  2210. + vlxseg7ei32.v v2, (a0), v2
  2211. + vlxseg7ei32.v v0, (a0), v2, v0.t
  2212. + vsxseg7ei32.v v0, (a0), v2
  2213. + vsxseg7ei32.v v1, (a0), v2
  2214. + vsxseg7ei32.v v2, (a0), v2
  2215. + vsxseg7ei32.v v0, (a0), v2, v0.t
  2216. + vlxseg8ei32.v v0, (a0), v2
  2217. + vlxseg8ei32.v v1, (a0), v2
  2218. + vlxseg8ei32.v v2, (a0), v2
  2219. + vlxseg8ei32.v v0, (a0), v2, v0.t
  2220. + vsxseg8ei32.v v0, (a0), v2
  2221. + vsxseg8ei32.v v1, (a0), v2
  2222. + vsxseg8ei32.v v2, (a0), v2
  2223. + vsxseg8ei32.v v0, (a0), v2, v0.t
  2224. +
  2225. + vlxseg2ei64.v v0, (a0), v2 # OK
  2226. + vlxseg2ei64.v v1, (a0), v2 # OK
  2227. + vlxseg2ei64.v v2, (a0), v2 # vd overlap vs2
  2228. + vlxseg2ei64.v v0, (a0), v2, v0.t # vd overlap vm
  2229. + vsxseg2ei64.v v0, (a0), v2
  2230. + vsxseg2ei64.v v1, (a0), v2
  2231. + vsxseg2ei64.v v2, (a0), v2
  2232. + vsxseg2ei64.v v0, (a0), v2, v0.t
  2233. + vlxseg3ei64.v v0, (a0), v2
  2234. + vlxseg3ei64.v v1, (a0), v2
  2235. + vlxseg3ei64.v v2, (a0), v2
  2236. + vlxseg3ei64.v v0, (a0), v2, v0.t
  2237. + vsxseg3ei64.v v0, (a0), v2
  2238. + vsxseg3ei64.v v1, (a0), v2
  2239. + vsxseg3ei64.v v2, (a0), v2
  2240. + vsxseg3ei64.v v0, (a0), v2, v0.t
  2241. + vlxseg4ei64.v v0, (a0), v2
  2242. + vlxseg4ei64.v v1, (a0), v2
  2243. + vlxseg4ei64.v v2, (a0), v2
  2244. + vlxseg4ei64.v v0, (a0), v2, v0.t
  2245. + vsxseg4ei64.v v0, (a0), v2
  2246. + vsxseg4ei64.v v1, (a0), v2
  2247. + vsxseg4ei64.v v2, (a0), v2
  2248. + vsxseg4ei64.v v0, (a0), v2, v0.t
  2249. + vlxseg5ei64.v v0, (a0), v2
  2250. + vlxseg5ei64.v v1, (a0), v2
  2251. + vlxseg5ei64.v v2, (a0), v2
  2252. + vlxseg5ei64.v v0, (a0), v2, v0.t
  2253. + vsxseg5ei64.v v0, (a0), v2
  2254. + vsxseg5ei64.v v1, (a0), v2
  2255. + vsxseg5ei64.v v2, (a0), v2
  2256. + vsxseg5ei64.v v0, (a0), v2, v0.t
  2257. + vlxseg6ei64.v v0, (a0), v2
  2258. + vlxseg6ei64.v v1, (a0), v2
  2259. + vlxseg6ei64.v v2, (a0), v2
  2260. + vlxseg6ei64.v v0, (a0), v2, v0.t
  2261. + vsxseg6ei64.v v0, (a0), v2
  2262. + vsxseg6ei64.v v1, (a0), v2
  2263. + vsxseg6ei64.v v2, (a0), v2
  2264. + vsxseg6ei64.v v0, (a0), v2, v0.t
  2265. + vlxseg7ei64.v v0, (a0), v2
  2266. + vlxseg7ei64.v v1, (a0), v2
  2267. + vlxseg7ei64.v v2, (a0), v2
  2268. + vlxseg7ei64.v v0, (a0), v2, v0.t
  2269. + vsxseg7ei64.v v0, (a0), v2
  2270. + vsxseg7ei64.v v1, (a0), v2
  2271. + vsxseg7ei64.v v2, (a0), v2
  2272. + vsxseg7ei64.v v0, (a0), v2, v0.t
  2273. + vlxseg8ei64.v v0, (a0), v2
  2274. + vlxseg8ei64.v v1, (a0), v2
  2275. + vlxseg8ei64.v v2, (a0), v2
  2276. + vlxseg8ei64.v v0, (a0), v2, v0.t
  2277. + vsxseg8ei64.v v0, (a0), v2
  2278. + vsxseg8ei64.v v1, (a0), v2
  2279. + vsxseg8ei64.v v2, (a0), v2
  2280. + vsxseg8ei64.v v0, (a0), v2, v0.t
  2281. +
  2282. + vlxseg2ei128.v v0, (a0), v2 # OK
  2283. + vlxseg2ei128.v v1, (a0), v2 # OK
  2284. + vlxseg2ei128.v v2, (a0), v2 # vd overlap vs2
  2285. + vlxseg2ei128.v v0, (a0), v2, v0.t # vd overlap vm
  2286. + vsxseg2ei128.v v0, (a0), v2
  2287. + vsxseg2ei128.v v1, (a0), v2
  2288. + vsxseg2ei128.v v2, (a0), v2
  2289. + vsxseg2ei128.v v0, (a0), v2, v0.t
  2290. + vlxseg3ei128.v v0, (a0), v2
  2291. + vlxseg3ei128.v v1, (a0), v2
  2292. + vlxseg3ei128.v v2, (a0), v2
  2293. + vlxseg3ei128.v v0, (a0), v2, v0.t
  2294. + vsxseg3ei128.v v0, (a0), v2
  2295. + vsxseg3ei128.v v1, (a0), v2
  2296. + vsxseg3ei128.v v2, (a0), v2
  2297. + vsxseg3ei128.v v0, (a0), v2, v0.t
  2298. + vlxseg4ei128.v v0, (a0), v2
  2299. + vlxseg4ei128.v v1, (a0), v2
  2300. + vlxseg4ei128.v v2, (a0), v2
  2301. + vlxseg4ei128.v v0, (a0), v2, v0.t
  2302. + vsxseg4ei128.v v0, (a0), v2
  2303. + vsxseg4ei128.v v1, (a0), v2
  2304. + vsxseg4ei128.v v2, (a0), v2
  2305. + vsxseg4ei128.v v0, (a0), v2, v0.t
  2306. + vlxseg5ei128.v v0, (a0), v2
  2307. + vlxseg5ei128.v v1, (a0), v2
  2308. + vlxseg5ei128.v v2, (a0), v2
  2309. + vlxseg5ei128.v v0, (a0), v2, v0.t
  2310. + vsxseg5ei128.v v0, (a0), v2
  2311. + vsxseg5ei128.v v1, (a0), v2
  2312. + vsxseg5ei128.v v2, (a0), v2
  2313. + vsxseg5ei128.v v0, (a0), v2, v0.t
  2314. + vlxseg6ei128.v v0, (a0), v2
  2315. + vlxseg6ei128.v v1, (a0), v2
  2316. + vlxseg6ei128.v v2, (a0), v2
  2317. + vlxseg6ei128.v v0, (a0), v2, v0.t
  2318. + vsxseg6ei128.v v0, (a0), v2
  2319. + vsxseg6ei128.v v1, (a0), v2
  2320. + vsxseg6ei128.v v2, (a0), v2
  2321. + vsxseg6ei128.v v0, (a0), v2, v0.t
  2322. + vlxseg7ei128.v v0, (a0), v2
  2323. + vlxseg7ei128.v v1, (a0), v2
  2324. + vlxseg7ei128.v v2, (a0), v2
  2325. + vlxseg7ei128.v v0, (a0), v2, v0.t
  2326. + vsxseg7ei128.v v0, (a0), v2
  2327. + vsxseg7ei128.v v1, (a0), v2
  2328. + vsxseg7ei128.v v2, (a0), v2
  2329. + vsxseg7ei128.v v0, (a0), v2, v0.t
  2330. + vlxseg8ei128.v v0, (a0), v2
  2331. + vlxseg8ei128.v v1, (a0), v2
  2332. + vlxseg8ei128.v v2, (a0), v2
  2333. + vlxseg8ei128.v v0, (a0), v2, v0.t
  2334. + vsxseg8ei128.v v0, (a0), v2
  2335. + vsxseg8ei128.v v1, (a0), v2
  2336. + vsxseg8ei128.v v2, (a0), v2
  2337. + vsxseg8ei128.v v0, (a0), v2, v0.t
  2338. +
  2339. + vlxseg2ei256.v v0, (a0), v2 # OK
  2340. + vlxseg2ei256.v v1, (a0), v2 # OK
  2341. + vlxseg2ei256.v v2, (a0), v2 # vd overlap vs2
  2342. + vlxseg2ei256.v v0, (a0), v2, v0.t # vd overlap vm
  2343. + vsxseg2ei256.v v0, (a0), v2
  2344. + vsxseg2ei256.v v1, (a0), v2
  2345. + vsxseg2ei256.v v2, (a0), v2
  2346. + vsxseg2ei256.v v0, (a0), v2, v0.t
  2347. + vlxseg3ei256.v v0, (a0), v2
  2348. + vlxseg3ei256.v v1, (a0), v2
  2349. + vlxseg3ei256.v v2, (a0), v2
  2350. + vlxseg3ei256.v v0, (a0), v2, v0.t
  2351. + vsxseg3ei256.v v0, (a0), v2
  2352. + vsxseg3ei256.v v1, (a0), v2
  2353. + vsxseg3ei256.v v2, (a0), v2
  2354. + vsxseg3ei256.v v0, (a0), v2, v0.t
  2355. + vlxseg4ei256.v v0, (a0), v2
  2356. + vlxseg4ei256.v v1, (a0), v2
  2357. + vlxseg4ei256.v v2, (a0), v2
  2358. + vlxseg4ei256.v v0, (a0), v2, v0.t
  2359. + vsxseg4ei256.v v0, (a0), v2
  2360. + vsxseg4ei256.v v1, (a0), v2
  2361. + vsxseg4ei256.v v2, (a0), v2
  2362. + vsxseg4ei256.v v0, (a0), v2, v0.t
  2363. + vlxseg5ei256.v v0, (a0), v2
  2364. + vlxseg5ei256.v v1, (a0), v2
  2365. + vlxseg5ei256.v v2, (a0), v2
  2366. + vlxseg5ei256.v v0, (a0), v2, v0.t
  2367. + vsxseg5ei256.v v0, (a0), v2
  2368. + vsxseg5ei256.v v1, (a0), v2
  2369. + vsxseg5ei256.v v2, (a0), v2
  2370. + vsxseg5ei256.v v0, (a0), v2, v0.t
  2371. + vlxseg6ei256.v v0, (a0), v2
  2372. + vlxseg6ei256.v v1, (a0), v2
  2373. + vlxseg6ei256.v v2, (a0), v2
  2374. + vlxseg6ei256.v v0, (a0), v2, v0.t
  2375. + vsxseg6ei256.v v0, (a0), v2
  2376. + vsxseg6ei256.v v1, (a0), v2
  2377. + vsxseg6ei256.v v2, (a0), v2
  2378. + vsxseg6ei256.v v0, (a0), v2, v0.t
  2379. + vlxseg7ei256.v v0, (a0), v2
  2380. + vlxseg7ei256.v v1, (a0), v2
  2381. + vlxseg7ei256.v v2, (a0), v2
  2382. + vlxseg7ei256.v v0, (a0), v2, v0.t
  2383. + vsxseg7ei256.v v0, (a0), v2
  2384. + vsxseg7ei256.v v1, (a0), v2
  2385. + vsxseg7ei256.v v2, (a0), v2
  2386. + vsxseg7ei256.v v0, (a0), v2, v0.t
  2387. + vlxseg8ei256.v v0, (a0), v2
  2388. + vlxseg8ei256.v v1, (a0), v2
  2389. + vlxseg8ei256.v v2, (a0), v2
  2390. + vlxseg8ei256.v v0, (a0), v2, v0.t
  2391. + vsxseg8ei256.v v0, (a0), v2
  2392. + vsxseg8ei256.v v1, (a0), v2
  2393. + vsxseg8ei256.v v2, (a0), v2
  2394. + vsxseg8ei256.v v0, (a0), v2, v0.t
  2395. +
  2396. + vlxseg2ei512.v v0, (a0), v2 # OK
  2397. + vlxseg2ei512.v v1, (a0), v2 # OK
  2398. + vlxseg2ei512.v v2, (a0), v2 # vd overlap vs2
  2399. + vlxseg2ei512.v v0, (a0), v2, v0.t # vd overlap vm
  2400. + vsxseg2ei512.v v0, (a0), v2
  2401. + vsxseg2ei512.v v1, (a0), v2
  2402. + vsxseg2ei512.v v2, (a0), v2
  2403. + vsxseg2ei512.v v0, (a0), v2, v0.t
  2404. + vlxseg3ei512.v v0, (a0), v2
  2405. + vlxseg3ei512.v v1, (a0), v2
  2406. + vlxseg3ei512.v v2, (a0), v2
  2407. + vlxseg3ei512.v v0, (a0), v2, v0.t
  2408. + vsxseg3ei512.v v0, (a0), v2
  2409. + vsxseg3ei512.v v1, (a0), v2
  2410. + vsxseg3ei512.v v2, (a0), v2
  2411. + vsxseg3ei512.v v0, (a0), v2, v0.t
  2412. + vlxseg4ei512.v v0, (a0), v2
  2413. + vlxseg4ei512.v v1, (a0), v2
  2414. + vlxseg4ei512.v v2, (a0), v2
  2415. + vlxseg4ei512.v v0, (a0), v2, v0.t
  2416. + vsxseg4ei512.v v0, (a0), v2
  2417. + vsxseg4ei512.v v1, (a0), v2
  2418. + vsxseg4ei512.v v2, (a0), v2
  2419. + vsxseg4ei512.v v0, (a0), v2, v0.t
  2420. + vlxseg5ei512.v v0, (a0), v2
  2421. + vlxseg5ei512.v v1, (a0), v2
  2422. + vlxseg5ei512.v v2, (a0), v2
  2423. + vlxseg5ei512.v v0, (a0), v2, v0.t
  2424. + vsxseg5ei512.v v0, (a0), v2
  2425. + vsxseg5ei512.v v1, (a0), v2
  2426. + vsxseg5ei512.v v2, (a0), v2
  2427. + vsxseg5ei512.v v0, (a0), v2, v0.t
  2428. + vlxseg6ei512.v v0, (a0), v2
  2429. + vlxseg6ei512.v v1, (a0), v2
  2430. + vlxseg6ei512.v v2, (a0), v2
  2431. + vlxseg6ei512.v v0, (a0), v2, v0.t
  2432. + vsxseg6ei512.v v0, (a0), v2
  2433. + vsxseg6ei512.v v1, (a0), v2
  2434. + vsxseg6ei512.v v2, (a0), v2
  2435. + vsxseg6ei512.v v0, (a0), v2, v0.t
  2436. + vlxseg7ei512.v v0, (a0), v2
  2437. + vlxseg7ei512.v v1, (a0), v2
  2438. + vlxseg7ei512.v v2, (a0), v2
  2439. + vlxseg7ei512.v v0, (a0), v2, v0.t
  2440. + vsxseg7ei512.v v0, (a0), v2
  2441. + vsxseg7ei512.v v1, (a0), v2
  2442. + vsxseg7ei512.v v2, (a0), v2
  2443. + vsxseg7ei512.v v0, (a0), v2, v0.t
  2444. + vlxseg8ei512.v v0, (a0), v2
  2445. + vlxseg8ei512.v v1, (a0), v2
  2446. + vlxseg8ei512.v v2, (a0), v2
  2447. + vlxseg8ei512.v v0, (a0), v2, v0.t
  2448. + vsxseg8ei512.v v0, (a0), v2
  2449. + vsxseg8ei512.v v1, (a0), v2
  2450. + vsxseg8ei512.v v2, (a0), v2
  2451. + vsxseg8ei512.v v0, (a0), v2, v0.t
  2452. +
  2453. + vlxseg2ei1024.v v0, (a0), v2 # OK
  2454. + vlxseg2ei1024.v v1, (a0), v2 # OK
  2455. + vlxseg2ei1024.v v2, (a0), v2 # vd overlap vs2
  2456. + vlxseg2ei1024.v v0, (a0), v2, v0.t # vd overlap vm
  2457. + vsxseg2ei1024.v v0, (a0), v2
  2458. + vsxseg2ei1024.v v1, (a0), v2
  2459. + vsxseg2ei1024.v v2, (a0), v2
  2460. + vsxseg2ei1024.v v0, (a0), v2, v0.t
  2461. + vlxseg3ei1024.v v0, (a0), v2
  2462. + vlxseg3ei1024.v v1, (a0), v2
  2463. + vlxseg3ei1024.v v2, (a0), v2
  2464. + vlxseg3ei1024.v v0, (a0), v2, v0.t
  2465. + vsxseg3ei1024.v v0, (a0), v2
  2466. + vsxseg3ei1024.v v1, (a0), v2
  2467. + vsxseg3ei1024.v v2, (a0), v2
  2468. + vsxseg3ei1024.v v0, (a0), v2, v0.t
  2469. + vlxseg4ei1024.v v0, (a0), v2
  2470. + vlxseg4ei1024.v v1, (a0), v2
  2471. + vlxseg4ei1024.v v2, (a0), v2
  2472. + vlxseg4ei1024.v v0, (a0), v2, v0.t
  2473. + vsxseg4ei1024.v v0, (a0), v2
  2474. + vsxseg4ei1024.v v1, (a0), v2
  2475. + vsxseg4ei1024.v v2, (a0), v2
  2476. + vsxseg4ei1024.v v0, (a0), v2, v0.t
  2477. + vlxseg5ei1024.v v0, (a0), v2
  2478. + vlxseg5ei1024.v v1, (a0), v2
  2479. + vlxseg5ei1024.v v2, (a0), v2
  2480. + vlxseg5ei1024.v v0, (a0), v2, v0.t
  2481. + vsxseg5ei1024.v v0, (a0), v2
  2482. + vsxseg5ei1024.v v1, (a0), v2
  2483. + vsxseg5ei1024.v v2, (a0), v2
  2484. + vsxseg5ei1024.v v0, (a0), v2, v0.t
  2485. + vlxseg6ei1024.v v0, (a0), v2
  2486. + vlxseg6ei1024.v v1, (a0), v2
  2487. + vlxseg6ei1024.v v2, (a0), v2
  2488. + vlxseg6ei1024.v v0, (a0), v2, v0.t
  2489. + vsxseg6ei1024.v v0, (a0), v2
  2490. + vsxseg6ei1024.v v1, (a0), v2
  2491. + vsxseg6ei1024.v v2, (a0), v2
  2492. + vsxseg6ei1024.v v0, (a0), v2, v0.t
  2493. + vlxseg7ei1024.v v0, (a0), v2
  2494. + vlxseg7ei1024.v v1, (a0), v2
  2495. + vlxseg7ei1024.v v2, (a0), v2
  2496. + vlxseg7ei1024.v v0, (a0), v2, v0.t
  2497. + vsxseg7ei1024.v v0, (a0), v2
  2498. + vsxseg7ei1024.v v1, (a0), v2
  2499. + vsxseg7ei1024.v v2, (a0), v2
  2500. + vsxseg7ei1024.v v0, (a0), v2, v0.t
  2501. + vlxseg8ei1024.v v0, (a0), v2
  2502. + vlxseg8ei1024.v v1, (a0), v2
  2503. + vlxseg8ei1024.v v2, (a0), v2
  2504. + vlxseg8ei1024.v v0, (a0), v2, v0.t
  2505. + vsxseg8ei1024.v v0, (a0), v2
  2506. + vsxseg8ei1024.v v1, (a0), v2
  2507. + vsxseg8ei1024.v v2, (a0), v2
  2508. + vsxseg8ei1024.v v0, (a0), v2, v0.t
  2509. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.d b/gas/testsuite/gas/riscv/vector-insns-fail-02.d
  2510. new file mode 100644
  2511. index 0000000000..6780b8553d
  2512. --- /dev/null
  2513. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-02.d
  2514. @@ -0,0 +1,3 @@
  2515. +#as: -march=rv32ifv_zvqmac -mcheck-constraints
  2516. +#source: vector-insns-fail-02.s
  2517. +#error_output: vector-insns-fail-02.l
  2518. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.l b/gas/testsuite/gas/riscv/vector-insns-fail-02.l
  2519. new file mode 100644
  2520. index 0000000000..c015fd75fc
  2521. --- /dev/null
  2522. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-02.l
  2523. @@ -0,0 +1,121 @@
  2524. +.*: Assembler messages:
  2525. +.*Error: illegal operands `vwaddu.vv v1,v2,v4'
  2526. +.*Error: illegal operands `vwaddu.vv v2,v2,v4'
  2527. +.*Error: illegal operands `vwaddu.vv v2,v3,v4'
  2528. +.*Error: illegal operands `vwaddu.vv v4,v2,v4'
  2529. +.*Error: illegal operands `vwaddu.vv v4,v2,v5'
  2530. +.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
  2531. +.*Error: illegal operands `vwsubu.vv v1,v2,v4'
  2532. +.*Error: illegal operands `vwsubu.vv v2,v2,v4'
  2533. +.*Error: illegal operands `vwsubu.vv v2,v3,v4'
  2534. +.*Error: illegal operands `vwsubu.vv v4,v2,v4'
  2535. +.*Error: illegal operands `vwsubu.vv v4,v2,v5'
  2536. +.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
  2537. +.*Error: illegal operands `vwadd.vv v1,v2,v4'
  2538. +.*Error: illegal operands `vwadd.vv v2,v2,v4'
  2539. +.*Error: illegal operands `vwadd.vv v2,v3,v4'
  2540. +.*Error: illegal operands `vwadd.vv v4,v2,v4'
  2541. +.*Error: illegal operands `vwadd.vv v4,v2,v5'
  2542. +.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
  2543. +.*Error: illegal operands `vwsub.vv v1,v2,v4'
  2544. +.*Error: illegal operands `vwsub.vv v2,v2,v4'
  2545. +.*Error: illegal operands `vwsub.vv v2,v3,v4'
  2546. +.*Error: illegal operands `vwsub.vv v4,v2,v4'
  2547. +.*Error: illegal operands `vwsub.vv v4,v2,v5'
  2548. +.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
  2549. +.*Error: illegal operands `vwmul.vv v1,v2,v4'
  2550. +.*Error: illegal operands `vwmul.vv v2,v2,v4'
  2551. +.*Error: illegal operands `vwmul.vv v2,v3,v4'
  2552. +.*Error: illegal operands `vwmul.vv v4,v2,v4'
  2553. +.*Error: illegal operands `vwmul.vv v4,v2,v5'
  2554. +.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
  2555. +.*Error: illegal operands `vwmulu.vv v1,v2,v4'
  2556. +.*Error: illegal operands `vwmulu.vv v2,v2,v4'
  2557. +.*Error: illegal operands `vwmulu.vv v2,v3,v4'
  2558. +.*Error: illegal operands `vwmulu.vv v4,v2,v4'
  2559. +.*Error: illegal operands `vwmulu.vv v4,v2,v5'
  2560. +.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
  2561. +.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
  2562. +.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
  2563. +.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
  2564. +.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
  2565. +.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
  2566. +.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
  2567. +.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
  2568. +.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
  2569. +.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
  2570. +.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
  2571. +.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
  2572. +.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
  2573. +.*Error: illegal operands `vwmacc.vv v1,v2,v4'
  2574. +.*Error: illegal operands `vwmacc.vv v2,v2,v4'
  2575. +.*Error: illegal operands `vwmacc.vv v2,v3,v4'
  2576. +.*Error: illegal operands `vwmacc.vv v4,v2,v4'
  2577. +.*Error: illegal operands `vwmacc.vv v4,v2,v5'
  2578. +.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
  2579. +.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
  2580. +.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
  2581. +.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
  2582. +.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
  2583. +.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
  2584. +.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
  2585. +.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
  2586. +.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
  2587. +.*Error: illegal operands `vqmaccu.vv v4,v6,v8'
  2588. +.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
  2589. +.*Error: illegal operands `vqmaccu.vv v8,v4,v10'
  2590. +.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
  2591. +.*Error: illegal operands `vqmacc.vv v2,v4,v8'
  2592. +.*Error: illegal operands `vqmacc.vv v4,v4,v8'
  2593. +.*Error: illegal operands `vqmacc.vv v4,v6,v8'
  2594. +.*Error: illegal operands `vqmacc.vv v8,v4,v8'
  2595. +.*Error: illegal operands `vqmacc.vv v8,v4,v10'
  2596. +.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
  2597. +.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
  2598. +.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
  2599. +.*Error: illegal operands `vqmaccsu.vv v4,v6,v8'
  2600. +.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
  2601. +.*Error: illegal operands `vqmaccsu.vv v8,v4,v10'
  2602. +.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
  2603. +.*Error: illegal operands `vfwadd.vv v1,v2,v4'
  2604. +.*Error: illegal operands `vfwadd.vv v2,v2,v4'
  2605. +.*Error: illegal operands `vfwadd.vv v2,v3,v4'
  2606. +.*Error: illegal operands `vfwadd.vv v4,v2,v4'
  2607. +.*Error: illegal operands `vfwadd.vv v4,v2,v5'
  2608. +.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
  2609. +.*Error: illegal operands `vfwsub.vv v1,v2,v4'
  2610. +.*Error: illegal operands `vfwsub.vv v2,v2,v4'
  2611. +.*Error: illegal operands `vfwsub.vv v2,v3,v4'
  2612. +.*Error: illegal operands `vfwsub.vv v4,v2,v4'
  2613. +.*Error: illegal operands `vfwsub.vv v4,v2,v5'
  2614. +.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
  2615. +.*Error: illegal operands `vfwmul.vv v1,v2,v4'
  2616. +.*Error: illegal operands `vfwmul.vv v2,v2,v4'
  2617. +.*Error: illegal operands `vfwmul.vv v2,v3,v4'
  2618. +.*Error: illegal operands `vfwmul.vv v4,v2,v4'
  2619. +.*Error: illegal operands `vfwmul.vv v4,v2,v5'
  2620. +.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
  2621. +.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
  2622. +.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
  2623. +.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
  2624. +.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
  2625. +.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
  2626. +.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
  2627. +.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
  2628. +.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
  2629. +.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
  2630. +.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
  2631. +.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
  2632. +.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
  2633. +.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
  2634. +.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
  2635. +.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
  2636. +.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
  2637. +.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
  2638. +.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
  2639. +.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
  2640. +.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
  2641. +.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
  2642. +.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
  2643. +.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
  2644. +.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
  2645. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.s b/gas/testsuite/gas/riscv/vector-insns-fail-02.s
  2646. new file mode 100644
  2647. index 0000000000..bf493c8ddb
  2648. --- /dev/null
  2649. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-02.s
  2650. @@ -0,0 +1,162 @@
  2651. +# Widening Vector Arithmetic Instructions (VV)
  2652. +# Quad-Widening Vector Arithmetic Instructions (VV)
  2653. +
  2654. + vwaddu.vv v0, v2, v4 # OK
  2655. + vwaddu.vv v1, v2, v4 # vd should be multiple of 2
  2656. + vwaddu.vv v2, v2, v4 # vd overlap vs2
  2657. + vwaddu.vv v2, v3, v4 # vd overlap vs2
  2658. + vwaddu.vv v4, v2, v4 # vd overlap vs1
  2659. + vwaddu.vv v4, v2, v5 # vd overlap vs1
  2660. + vwaddu.vv v0, v2, v4, v0.t # vd overlap vm
  2661. +
  2662. + vwsubu.vv v0, v2, v4 # OK
  2663. + vwsubu.vv v1, v2, v4 # vd should be multiple of 2
  2664. + vwsubu.vv v2, v2, v4 # vd overlap vs2
  2665. + vwsubu.vv v2, v3, v4 # vd overlap vs2
  2666. + vwsubu.vv v4, v2, v4 # vd overlap vs1
  2667. + vwsubu.vv v4, v2, v5 # vd overlap vs1
  2668. + vwsubu.vv v0, v2, v4, v0.t # vd overlap vm
  2669. +
  2670. + vwadd.vv v0, v2, v4 # OK
  2671. + vwadd.vv v1, v2, v4 # vd should be multiple of 2
  2672. + vwadd.vv v2, v2, v4 # vd overlap vs2
  2673. + vwadd.vv v2, v3, v4 # vd overlap vs2
  2674. + vwadd.vv v4, v2, v4 # vd overlap vs1
  2675. + vwadd.vv v4, v2, v5 # vd overlap vs1
  2676. + vwadd.vv v0, v2, v4, v0.t # vd overlap vm
  2677. +
  2678. + vwsub.vv v0, v2, v4 # OK
  2679. + vwsub.vv v1, v2, v4 # vd should be multiple of 2
  2680. + vwsub.vv v2, v2, v4 # vd overlap vs2
  2681. + vwsub.vv v2, v3, v4 # vd overlap vs2
  2682. + vwsub.vv v4, v2, v4 # vd overlap vs1
  2683. + vwsub.vv v4, v2, v5 # vd overlap vs1
  2684. + vwsub.vv v0, v2, v4, v0.t # vd overlap vm
  2685. +
  2686. + vwmul.vv v0, v2, v4 # OK
  2687. + vwmul.vv v1, v2, v4 # vd should be multiple of 2
  2688. + vwmul.vv v2, v2, v4 # vd overlap vs2
  2689. + vwmul.vv v2, v3, v4 # vd overlap vs2
  2690. + vwmul.vv v4, v2, v4 # vd overlap vs1
  2691. + vwmul.vv v4, v2, v5 # vd overlap vs1
  2692. + vwmul.vv v0, v2, v4, v0.t # vd overlap vm
  2693. +
  2694. + vwmulu.vv v0, v2, v4 # OK
  2695. + vwmulu.vv v1, v2, v4 # vd should be multiple of 2
  2696. + vwmulu.vv v2, v2, v4 # vd overlap vs2
  2697. + vwmulu.vv v2, v3, v4 # vd overlap vs2
  2698. + vwmulu.vv v4, v2, v4 # vd overlap vs1
  2699. + vwmulu.vv v4, v2, v5 # vd overlap vs1
  2700. + vwmulu.vv v0, v2, v4, v0.t # vd overlap vm
  2701. +
  2702. + vwmulsu.vv v0, v2, v4 # OK
  2703. + vwmulsu.vv v1, v2, v4 # vd should be multiple of 2
  2704. + vwmulsu.vv v2, v2, v4 # vd overlap vs2
  2705. + vwmulsu.vv v2, v3, v4 # vd overlap vs2
  2706. + vwmulsu.vv v4, v2, v4 # vd overlap vs1
  2707. + vwmulsu.vv v4, v2, v5 # vd overlap vs1
  2708. + vwmulsu.vv v0, v2, v4, v0.t # vd overlap vm
  2709. +
  2710. + vwmaccu.vv v0, v2, v4 # OK
  2711. + vwmaccu.vv v1, v2, v4 # vd should be multiple of 2
  2712. + vwmaccu.vv v2, v2, v4 # vd overlap vs1
  2713. + vwmaccu.vv v2, v3, v4 # vd overlap vs1
  2714. + vwmaccu.vv v4, v2, v4 # vd overlap vs2
  2715. + vwmaccu.vv v4, v2, v5 # vd overlap vs2
  2716. + vwmaccu.vv v0, v2, v4, v0.t # vd overlap vm
  2717. +
  2718. + vwmacc.vv v0, v2, v4 # OK
  2719. + vwmacc.vv v1, v2, v4 # vd should be multiple of 2
  2720. + vwmacc.vv v2, v2, v4 # vd overlap vs1
  2721. + vwmacc.vv v2, v3, v4 # vd overlap vs1
  2722. + vwmacc.vv v4, v2, v4 # vd overlap vs2
  2723. + vwmacc.vv v4, v2, v5 # vd overlap vs2
  2724. + vwmacc.vv v0, v2, v4, v0.t # vd overlap vm
  2725. +
  2726. + vwmaccsu.vv v0, v2, v4 # OK
  2727. + vwmaccsu.vv v1, v2, v4 # vd should be multiple of 2
  2728. + vwmaccsu.vv v2, v2, v4 # vd overlap vs1
  2729. + vwmaccsu.vv v2, v3, v4 # vd overlap vs1
  2730. + vwmaccsu.vv v4, v2, v4 # vd overlap vs2
  2731. + vwmaccsu.vv v4, v2, v5 # vd overlap vs2
  2732. + vwmaccsu.vv v0, v2, v4, v0.t # vd overlap vm
  2733. +
  2734. + vqmaccu.vv v0, v4, v8 # OK
  2735. + vqmaccu.vv v2, v4, v8 # vd should be multiple of 4
  2736. + vqmaccu.vv v4, v4, v8 # vd overlap vs1
  2737. + vqmaccu.vv v4, v6, v8 # vd overlap vs1
  2738. + vqmaccu.vv v8, v4, v8 # vd overlap vs2
  2739. + vqmaccu.vv v8, v4, v10 # vd overlap vs2
  2740. + vqmaccu.vv v0, v4, v8, v0.t # vd overlap vm
  2741. +
  2742. + vqmacc.vv v0, v4, v8 # OK
  2743. + vqmacc.vv v2, v4, v8 # vd should be multiple of 4
  2744. + vqmacc.vv v4, v4, v8 # vd overlap vs1
  2745. + vqmacc.vv v4, v6, v8 # vd overlap vs1
  2746. + vqmacc.vv v8, v4, v8 # vd overlap vs2
  2747. + vqmacc.vv v8, v4, v10 # vd overlap vs2
  2748. + vqmacc.vv v0, v4, v8, v0.t # vd overlap vm
  2749. +
  2750. + vqmaccsu.vv v0, v4, v8 # OK
  2751. + vqmaccsu.vv v2, v4, v8 # vd should be multiple of 4
  2752. + vqmaccsu.vv v4, v4, v8 # vd overlap vs1
  2753. + vqmaccsu.vv v4, v6, v8 # vd overlap vs1
  2754. + vqmaccsu.vv v8, v4, v8 # vd overlap vs2
  2755. + vqmaccsu.vv v8, v4, v10 # vd overlap vs2
  2756. + vqmaccsu.vv v0, v4, v8, v0.t # vd overlap vm
  2757. +
  2758. + vfwadd.vv v0, v2, v4 # OK
  2759. + vfwadd.vv v1, v2, v4 # vd should be multiple of 2
  2760. + vfwadd.vv v2, v2, v4 # vd overlap vs2
  2761. + vfwadd.vv v2, v3, v4 # vd overlap vs2
  2762. + vfwadd.vv v4, v2, v4 # vd overlap vs1
  2763. + vfwadd.vv v4, v2, v5 # vd overlap vs1
  2764. + vfwadd.vv v0, v2, v4, v0.t # vd overlap vm
  2765. +
  2766. + vfwsub.vv v0, v2, v4 # OK
  2767. + vfwsub.vv v1, v2, v4 # vd should be multiple of 2
  2768. + vfwsub.vv v2, v2, v4 # vd overlap vs2
  2769. + vfwsub.vv v2, v3, v4 # vd overlap vs2
  2770. + vfwsub.vv v4, v2, v4 # vd overlap vs1
  2771. + vfwsub.vv v4, v2, v5 # vd overlap vs1
  2772. + vfwsub.vv v0, v2, v4, v0.t # vd overlap vm
  2773. +
  2774. + vfwmul.vv v0, v2, v4 # OK
  2775. + vfwmul.vv v1, v2, v4 # vd should be multiple of 2
  2776. + vfwmul.vv v2, v2, v4 # vd overlap vs2
  2777. + vfwmul.vv v2, v3, v4 # vd overlap vs2
  2778. + vfwmul.vv v4, v2, v4 # vd overlap vs1
  2779. + vfwmul.vv v4, v2, v5 # vd overlap vs1
  2780. + vfwmul.vv v0, v2, v4, v0.t # vd overlap vm
  2781. +
  2782. + vfwmacc.vv v0, v2, v4 # OK
  2783. + vfwmacc.vv v1, v2, v4 # vd should be multiple of 2
  2784. + vfwmacc.vv v2, v2, v4 # vd overlap vs1
  2785. + vfwmacc.vv v2, v3, v4 # vd overlap vs1
  2786. + vfwmacc.vv v4, v2, v4 # vd overlap vs2
  2787. + vfwmacc.vv v4, v2, v5 # vd overlap vs2
  2788. + vfwmacc.vv v0, v2, v4, v0.t # vd overlap vm
  2789. +
  2790. + vfwnmacc.vv v0, v2, v4 # OK
  2791. + vfwnmacc.vv v1, v2, v4 # vd should be multiple of 2
  2792. + vfwnmacc.vv v2, v2, v4 # vd overlap vs1
  2793. + vfwnmacc.vv v2, v3, v4 # vd overlap vs1
  2794. + vfwnmacc.vv v4, v2, v4 # vd overlap vs2
  2795. + vfwnmacc.vv v4, v2, v5 # vd overlap vs2
  2796. + vfwnmacc.vv v0, v2, v4, v0.t # vd overlap vm
  2797. +
  2798. + vfwmsac.vv v0, v2, v4 # OK
  2799. + vfwmsac.vv v1, v2, v4 # vd should be multiple of 2
  2800. + vfwmsac.vv v2, v2, v4 # vd overlap vs1
  2801. + vfwmsac.vv v2, v3, v4 # vd overlap vs1
  2802. + vfwmsac.vv v4, v2, v4 # vd overlap vs2
  2803. + vfwmsac.vv v4, v2, v5 # vd overlap vs2
  2804. + vfwmsac.vv v0, v2, v4, v0.t # vd overlap vm
  2805. +
  2806. + vfwnmsac.vv v0, v2, v4 # OK
  2807. + vfwnmsac.vv v1, v2, v4 # vd should be multiple of 2
  2808. + vfwnmsac.vv v2, v2, v4 # vd overlap vs1
  2809. + vfwnmsac.vv v2, v3, v4 # vd overlap vs1
  2810. + vfwnmsac.vv v4, v2, v4 # vd overlap vs2
  2811. + vfwnmsac.vv v4, v2, v5 # vd overlap vs2
  2812. + vfwnmsac.vv v0, v2, v4, v0.t # vd overlap vm
  2813. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.d b/gas/testsuite/gas/riscv/vector-insns-fail-03.d
  2814. new file mode 100644
  2815. index 0000000000..1bfe441872
  2816. --- /dev/null
  2817. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-03.d
  2818. @@ -0,0 +1,3 @@
  2819. +#as: -march=rv32ifv_zvqmac -mcheck-constraints
  2820. +#source: vector-insns-fail-03.s
  2821. +#error_output: vector-insns-fail-03.l
  2822. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.l b/gas/testsuite/gas/riscv/vector-insns-fail-03.l
  2823. new file mode 100644
  2824. index 0000000000..128e22726d
  2825. --- /dev/null
  2826. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-03.l
  2827. @@ -0,0 +1,125 @@
  2828. +.*: Assembler messages:
  2829. +.*Error: illegal operands `vwcvt.x.x.v v1,v2'
  2830. +.*Error: illegal operands `vwcvt.x.x.v v2,v2'
  2831. +.*Error: illegal operands `vwcvt.x.x.v v2,v3'
  2832. +.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
  2833. +.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
  2834. +.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
  2835. +.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
  2836. +.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
  2837. +.*Error: illegal operands `vwaddu.vx v1,v2,a1'
  2838. +.*Error: illegal operands `vwaddu.vx v2,v2,a1'
  2839. +.*Error: illegal operands `vwaddu.vx v2,v3,a1'
  2840. +.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
  2841. +.*Error: illegal operands `vwsubu.vx v1,v2,a1'
  2842. +.*Error: illegal operands `vwsubu.vx v2,v2,a1'
  2843. +.*Error: illegal operands `vwsubu.vx v2,v3,a1'
  2844. +.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
  2845. +.*Error: illegal operands `vwadd.vx v1,v2,a1'
  2846. +.*Error: illegal operands `vwadd.vx v2,v2,a1'
  2847. +.*Error: illegal operands `vwadd.vx v2,v3,a1'
  2848. +.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
  2849. +.*Error: illegal operands `vwsub.vx v1,v2,a1'
  2850. +.*Error: illegal operands `vwsub.vx v2,v2,a1'
  2851. +.*Error: illegal operands `vwsub.vx v2,v3,a1'
  2852. +.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
  2853. +.*Error: illegal operands `vwmul.vx v1,v2,a1'
  2854. +.*Error: illegal operands `vwmul.vx v2,v2,a1'
  2855. +.*Error: illegal operands `vwmul.vx v2,v3,a1'
  2856. +.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
  2857. +.*Error: illegal operands `vwmulu.vx v1,v2,a1'
  2858. +.*Error: illegal operands `vwmulu.vx v2,v2,a1'
  2859. +.*Error: illegal operands `vwmulu.vx v2,v3,a1'
  2860. +.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
  2861. +.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
  2862. +.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
  2863. +.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
  2864. +.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
  2865. +.*Error: illegal operands `vwmaccu.vx v1,a1,v4'
  2866. +.*Error: illegal operands `vwmaccu.vx v4,a1,v4'
  2867. +.*Error: illegal operands `vwmaccu.vx v4,a1,v5'
  2868. +.*Error: illegal operands `vwmaccu.vx v0,a1,v4,v0.t'
  2869. +.*Error: illegal operands `vwmacc.vx v1,a1,v4'
  2870. +.*Error: illegal operands `vwmacc.vx v4,a1,v4'
  2871. +.*Error: illegal operands `vwmacc.vx v4,a1,v5'
  2872. +.*Error: illegal operands `vwmacc.vx v0,a1,v4,v0.t'
  2873. +.*Error: illegal operands `vwmaccsu.vx v1,a1,v4'
  2874. +.*Error: illegal operands `vwmaccsu.vx v4,a1,v4'
  2875. +.*Error: illegal operands `vwmaccsu.vx v4,a1,v5'
  2876. +.*Error: illegal operands `vwmaccsu.vx v0,a1,v4,v0.t'
  2877. +.*Error: illegal operands `vwmaccus.vx v1,a1,v4'
  2878. +.*Error: illegal operands `vwmaccus.vx v4,a1,v4'
  2879. +.*Error: illegal operands `vwmaccus.vx v4,a1,v5'
  2880. +.*Error: illegal operands `vwmaccus.vx v0,a1,v4,v0.t'
  2881. +.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
  2882. +.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
  2883. +.*Error: illegal operands `vqmaccu.vx v4,a1,v6'
  2884. +.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
  2885. +.*Error: illegal operands `vqmacc.vx v2,a1,v4'
  2886. +.*Error: illegal operands `vqmacc.vx v4,a1,v4'
  2887. +.*Error: illegal operands `vqmacc.vx v4,a1,v6'
  2888. +.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
  2889. +.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
  2890. +.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
  2891. +.*Error: illegal operands `vqmaccsu.vx v4,a1,v6'
  2892. +.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
  2893. +.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
  2894. +.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
  2895. +.*Error: illegal operands `vqmaccus.vx v4,a1,v6'
  2896. +.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
  2897. +.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
  2898. +.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
  2899. +.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
  2900. +.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
  2901. +.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
  2902. +.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
  2903. +.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
  2904. +.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
  2905. +.*Error: illegal operands `vfwmul.vf v1,v2,fa1'
  2906. +.*Error: illegal operands `vfwmul.vf v2,v2,fa1'
  2907. +.*Error: illegal operands `vfwmul.vf v2,v3,fa1'
  2908. +.*Error: illegal operands `vfwmul.vf v0,v2,fa1,v0.t'
  2909. +.*Error: illegal operands `vfwmacc.vf v1,fa1,v4'
  2910. +.*Error: illegal operands `vfwmacc.vf v4,fa1,v4'
  2911. +.*Error: illegal operands `vfwmacc.vf v4,fa1,v5'
  2912. +.*Error: illegal operands `vfwmacc.vf v0,fa1,v4,v0.t'
  2913. +.*Error: illegal operands `vfwnmacc.vf v1,fa1,v4'
  2914. +.*Error: illegal operands `vfwnmacc.vf v4,fa1,v4'
  2915. +.*Error: illegal operands `vfwnmacc.vf v4,fa1,v5'
  2916. +.*Error: illegal operands `vfwnmacc.vf v0,fa1,v4,v0.t'
  2917. +.*Error: illegal operands `vfwmsac.vf v1,fa1,v4'
  2918. +.*Error: illegal operands `vfwmsac.vf v4,fa1,v4'
  2919. +.*Error: illegal operands `vfwmsac.vf v4,fa1,v5'
  2920. +.*Error: illegal operands `vfwmsac.vf v0,fa1,v4,v0.t'
  2921. +.*Error: illegal operands `vfwnmsac.vf v1,fa1,v4'
  2922. +.*Error: illegal operands `vfwnmsac.vf v4,fa1,v4'
  2923. +.*Error: illegal operands `vfwnmsac.vf v4,fa1,v5'
  2924. +.*Error: illegal operands `vfwnmsac.vf v0,fa1,v4,v0.t'
  2925. +.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
  2926. +.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
  2927. +.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
  2928. +.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
  2929. +.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
  2930. +.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
  2931. +.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
  2932. +.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
  2933. +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
  2934. +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
  2935. +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
  2936. +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
  2937. +.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
  2938. +.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
  2939. +.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
  2940. +.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
  2941. +.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
  2942. +.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
  2943. +.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
  2944. +.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
  2945. +.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
  2946. +.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
  2947. +.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
  2948. +.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
  2949. +.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
  2950. +.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
  2951. +.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
  2952. +.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
  2953. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.s b/gas/testsuite/gas/riscv/vector-insns-fail-03.s
  2954. new file mode 100644
  2955. index 0000000000..9450b9ceb0
  2956. --- /dev/null
  2957. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-03.s
  2958. @@ -0,0 +1,187 @@
  2959. +# Widening Vector Arithmetic Instructions (V[X|F])
  2960. +
  2961. + vwcvt.x.x.v v0, v2 # OK
  2962. + vwcvt.x.x.v v1, v2 # vd should be multiple of 2
  2963. + vwcvt.x.x.v v2, v2 # vd overlap vs2
  2964. + vwcvt.x.x.v v2, v3 # vd overlap vs2
  2965. + vwcvt.x.x.v v0, v2, v0.t # vd overlap vm
  2966. +
  2967. + vwcvtu.x.x.v v0, v2 # OK
  2968. + vwcvtu.x.x.v v1, v2 # vd should be multiple of 2
  2969. + vwcvtu.x.x.v v2, v2 # vd overlap vs2
  2970. + vwcvtu.x.x.v v2, v3 # vd overlap vs2
  2971. + vwcvtu.x.x.v v0, v2, v0.t # vd overlap vm
  2972. +
  2973. + vwaddu.vx v0, v2, a1 # OK
  2974. + vwaddu.vx v1, v2, a1 # vd should be multiple of 2
  2975. + vwaddu.vx v2, v2, a1 # vd overlap vs2
  2976. + vwaddu.vx v2, v3, a1 # vd overlap vs2
  2977. + vwaddu.vx v0, v2, a1, v0.t # vd overlap vm
  2978. +
  2979. + vwsubu.vx v0, v2, a1 # OK
  2980. + vwsubu.vx v1, v2, a1 # vd should be multiple of 2
  2981. + vwsubu.vx v2, v2, a1 # vd overlap vs2
  2982. + vwsubu.vx v2, v3, a1 # vd overlap vs2
  2983. + vwsubu.vx v0, v2, a1, v0.t # vd overlap vm
  2984. +
  2985. + vwadd.vx v0, v2, a1 # OK
  2986. + vwadd.vx v1, v2, a1 # vd should be multiple of 2
  2987. + vwadd.vx v2, v2, a1 # vd overlap vs2
  2988. + vwadd.vx v2, v3, a1 # vd overlap vs2
  2989. + vwadd.vx v0, v2, a1, v0.t # vd overlap vm
  2990. +
  2991. + vwsub.vx v0, v2, a1 # OK
  2992. + vwsub.vx v1, v2, a1 # vd should be multiple of 2
  2993. + vwsub.vx v2, v2, a1 # vd overlap vs2
  2994. + vwsub.vx v2, v3, a1 # vd overlap vs2
  2995. + vwsub.vx v0, v2, a1, v0.t # vd overlap vm
  2996. +
  2997. + vwmul.vx v0, v2, a1 # OK
  2998. + vwmul.vx v1, v2, a1 # vd should be multiple of 2
  2999. + vwmul.vx v2, v2, a1 # vd overlap vs2
  3000. + vwmul.vx v2, v3, a1 # vd overlap vs2
  3001. + vwmul.vx v0, v2, a1, v0.t # vd overlap vm
  3002. +
  3003. + vwmulu.vx v0, v2, a1 # OK
  3004. + vwmulu.vx v1, v2, a1 # vd should be multiple of 2
  3005. + vwmulu.vx v2, v2, a1 # vd overlap vs2
  3006. + vwmulu.vx v2, v3, a1 # vd overlap vs2
  3007. + vwmulu.vx v0, v2, a1, v0.t # vd overlap vm
  3008. +
  3009. + vwmulsu.vx v0, v2, a1 # OK
  3010. + vwmulsu.vx v1, v2, a1 # vd should be multiple of 2
  3011. + vwmulsu.vx v2, v2, a1 # vd overlap vs2
  3012. + vwmulsu.vx v2, v3, a1 # vd overlap vs2
  3013. + vwmulsu.vx v0, v2, a1, v0.t # vd overlap vm
  3014. +
  3015. + vwmaccu.vx v0, a1, v4 # OK
  3016. + vwmaccu.vx v1, a1, v4 # vd should be multiple of 2
  3017. + vwmaccu.vx v4, a1, v4 # vd overlap vs2
  3018. + vwmaccu.vx v4, a1, v5 # vd overlap vs2
  3019. + vwmaccu.vx v0, a1, v4, v0.t # vd overlap vm
  3020. +
  3021. + vwmacc.vx v0, a1, v4 # OK
  3022. + vwmacc.vx v1, a1, v4 # vd should be multiple of 2
  3023. + vwmacc.vx v4, a1, v4 # vd overlap vs2
  3024. + vwmacc.vx v4, a1, v5 # vd overlap vs2
  3025. + vwmacc.vx v0, a1, v4, v0.t # vd overlap vm
  3026. +
  3027. + vwmaccsu.vx v0, a1, v4 # OK
  3028. + vwmaccsu.vx v1, a1, v4 # vd should be multiple of 2
  3029. + vwmaccsu.vx v4, a1, v4 # vd overlap vs2
  3030. + vwmaccsu.vx v4, a1, v5 # vd overlap vs2
  3031. + vwmaccsu.vx v0, a1, v4, v0.t # vd overlap vm
  3032. +
  3033. + vwmaccus.vx v0, a1, v4 # OK
  3034. + vwmaccus.vx v1, a1, v4 # vd should be multiple of 2
  3035. + vwmaccus.vx v4, a1, v4 # vd overlap vs2
  3036. + vwmaccus.vx v4, a1, v5 # vd overlap vs2
  3037. + vwmaccus.vx v0, a1, v4, v0.t # vd overlap vm
  3038. +
  3039. + vqmaccu.vx v0, a1, v4 # OK
  3040. + vqmaccu.vx v2, a1, v4 # vd should be multiple of 4
  3041. + vqmaccu.vx v4, a1, v4 # vd overlap vs2
  3042. + vqmaccu.vx v4, a1, v6 # vd overlap vs2
  3043. + vqmaccu.vx v0, a1, v4, v0.t # vd overlap vm
  3044. +
  3045. + vqmacc.vx v0, a1, v4 # OK
  3046. + vqmacc.vx v2, a1, v4 # vd should be multiple of 4
  3047. + vqmacc.vx v4, a1, v4 # vd overlap vs2
  3048. + vqmacc.vx v4, a1, v6 # vd overlap vs2
  3049. + vqmacc.vx v0, a1, v4, v0.t # vd overlap vm
  3050. +
  3051. + vqmaccsu.vx v0, a1, v4 # OK
  3052. + vqmaccsu.vx v2, a1, v4 # vd should be multiple of 4
  3053. + vqmaccsu.vx v4, a1, v4 # vd overlap vs2
  3054. + vqmaccsu.vx v4, a1, v6 # vd overlap vs2
  3055. + vqmaccsu.vx v0, a1, v4, v0.t # vd overlap vm
  3056. +
  3057. + vqmaccus.vx v0, a1, v4 # OK
  3058. + vqmaccus.vx v2, a1, v4 # vd should be multiple of 4
  3059. + vqmaccus.vx v4, a1, v4 # vd overlap vs2
  3060. + vqmaccus.vx v4, a1, v6 # vd overlap vs2
  3061. + vqmaccus.vx v0, a1, v4, v0.t # vd overlap vm
  3062. +
  3063. + vfwadd.vf v0, v2, fa1 # OK
  3064. + vfwadd.vf v1, v2, fa1 # vd should be multiple of 2
  3065. + vfwadd.vf v2, v2, fa1 # vd overlap vs2
  3066. + vfwadd.vf v2, v3, fa1 # vd overlap vs2
  3067. + vfwadd.vf v0, v2, fa1, v0.t # vd overlap vm
  3068. +
  3069. + vfwsub.vf v0, v2, fa1 # OK
  3070. + vfwsub.vf v1, v2, fa1 # vd should be multiple of 2
  3071. + vfwsub.vf v2, v2, fa1 # vd overlap vs2
  3072. + vfwsub.vf v2, v3, fa1 # vd overlap vs2
  3073. + vfwsub.vf v0, v2, fa1, v0.t # vd overlap vm
  3074. +
  3075. + vfwmul.vf v0, v2, fa1 # OK
  3076. + vfwmul.vf v1, v2, fa1 # vd should be multiple of 2
  3077. + vfwmul.vf v2, v2, fa1 # vd overlap vs2
  3078. + vfwmul.vf v2, v3, fa1 # vd overlap vs2
  3079. + vfwmul.vf v0, v2, fa1, v0.t # vd overlap vm
  3080. +
  3081. + vfwmacc.vf v0, fa1, v4 # OK
  3082. + vfwmacc.vf v1, fa1, v4 # vd should be multiple of 2
  3083. + vfwmacc.vf v4, fa1, v4 # vd overlap vs2
  3084. + vfwmacc.vf v4, fa1, v5 # vd overlap vs2
  3085. + vfwmacc.vf v0, fa1, v4, v0.t # vd overlap vm
  3086. +
  3087. + vfwnmacc.vf v0, fa1, v4 # OK
  3088. + vfwnmacc.vf v1, fa1, v4 # vd should be multiple of 2
  3089. + vfwnmacc.vf v4, fa1, v4 # vd overlap vs2
  3090. + vfwnmacc.vf v4, fa1, v5 # vd overlap vs2
  3091. + vfwnmacc.vf v0, fa1, v4, v0.t # vd overlap vm
  3092. +
  3093. + vfwmsac.vf v0, fa1, v4 # OK
  3094. + vfwmsac.vf v1, fa1, v4 # vd should be multiple of 2
  3095. + vfwmsac.vf v4, fa1, v4 # vd overlap vs2
  3096. + vfwmsac.vf v4, fa1, v5 # vd overlap vs2
  3097. + vfwmsac.vf v0, fa1, v4, v0.t # vd overlap vm
  3098. +
  3099. + vfwnmsac.vf v0, fa1, v4 # OK
  3100. + vfwnmsac.vf v1, fa1, v4 # vd should be multiple of 2
  3101. + vfwnmsac.vf v4, fa1, v4 # vd overlap vs2
  3102. + vfwnmsac.vf v4, fa1, v5 # vd overlap vs2
  3103. + vfwnmsac.vf v0, fa1, v4, v0.t # vd overlap vm
  3104. +
  3105. + vfwcvt.xu.f.v v0, v2 # OK
  3106. + vfwcvt.xu.f.v v1, v2 # vd should be multiple of 2
  3107. + vfwcvt.xu.f.v v2, v2 # vd overlap vs2
  3108. + vfwcvt.xu.f.v v2, v3 # vd overlap vs2
  3109. + vfwcvt.xu.f.v v0, v2, v0.t # vd overlap vm
  3110. +
  3111. + vfwcvt.x.f.v v0, v2 # OK
  3112. + vfwcvt.x.f.v v1, v2 # vd should be multiple of 2
  3113. + vfwcvt.x.f.v v2, v2 # vd overlap vs2
  3114. + vfwcvt.x.f.v v2, v3 # vd overlap vs2
  3115. + vfwcvt.x.f.v v0, v2, v0.t # vd overlap vm
  3116. +
  3117. + vfwcvt.rtz.xu.f.v v0, v2 # OK
  3118. + vfwcvt.rtz.xu.f.v v1, v2 # vd should be multiple of 2
  3119. + vfwcvt.rtz.xu.f.v v2, v2 # vd overlap vs2
  3120. + vfwcvt.rtz.xu.f.v v2, v3 # vd overlap vs2
  3121. + vfwcvt.rtz.xu.f.v v0, v2, v0.t # vd overlap vm
  3122. +
  3123. + vfwcvt.rtz.x.f.v v0, v2 # OK
  3124. + vfwcvt.rtz.x.f.v v1, v2 # vd should be multiple of 2
  3125. + vfwcvt.rtz.x.f.v v2, v2 # vd overlap vs2
  3126. + vfwcvt.rtz.x.f.v v2, v3 # vd overlap vs2
  3127. + vfwcvt.rtz.x.f.v v0, v2, v0.t # vd overlap vm
  3128. +
  3129. + vfwcvt.f.xu.v v0, v2 # OK
  3130. + vfwcvt.f.xu.v v1, v2 # vd should be multiple of 2
  3131. + vfwcvt.f.xu.v v2, v2 # vd overlap vs2
  3132. + vfwcvt.f.xu.v v2, v3 # vd overlap vs2
  3133. + vfwcvt.f.xu.v v0, v2, v0.t # vd overlap vm
  3134. +
  3135. + vfwcvt.f.x.v v0, v2 # OK
  3136. + vfwcvt.f.x.v v1, v2 # vd should be multiple of 2
  3137. + vfwcvt.f.x.v v2, v2 # vd overlap vs2
  3138. + vfwcvt.f.x.v v2, v3 # vd overlap vs2
  3139. + vfwcvt.f.x.v v0, v2, v0.t # vd overlap vm
  3140. +
  3141. + vfwcvt.f.f.v v0, v2 # OK
  3142. + vfwcvt.f.f.v v1, v2 # vd should be multiple of 2
  3143. + vfwcvt.f.f.v v2, v2 # vd overlap vs2
  3144. + vfwcvt.f.f.v v2, v3 # vd overlap vs2
  3145. + vfwcvt.f.f.v v0, v2, v0.t # vd overlap vm
  3146. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.d b/gas/testsuite/gas/riscv/vector-insns-fail-04.d
  3147. new file mode 100644
  3148. index 0000000000..d483884544
  3149. --- /dev/null
  3150. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-04.d
  3151. @@ -0,0 +1,3 @@
  3152. +#as: -march=rv32ifv -mcheck-constraints
  3153. +#source: vector-insns-fail-04.s
  3154. +#error_output: vector-insns-fail-04.l
  3155. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.l b/gas/testsuite/gas/riscv/vector-insns-fail-04.l
  3156. new file mode 100644
  3157. index 0000000000..9a9c76c19d
  3158. --- /dev/null
  3159. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-04.l
  3160. @@ -0,0 +1,49 @@
  3161. +.*: Assembler messages:
  3162. +.*Error: illegal operands `vwaddu.wv v1,v2,v4'
  3163. +.*Error: illegal operands `vwaddu.wv v2,v3,v4'
  3164. +.*Error: illegal operands `vwaddu.wv v4,v2,v4'
  3165. +.*Error: illegal operands `vwaddu.wv v4,v2,v5'
  3166. +.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
  3167. +.*Error: illegal operands `vwsubu.wv v1,v2,v4'
  3168. +.*Error: illegal operands `vwsubu.wv v2,v3,v4'
  3169. +.*Error: illegal operands `vwsubu.wv v4,v2,v4'
  3170. +.*Error: illegal operands `vwsubu.wv v4,v2,v5'
  3171. +.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
  3172. +.*Error: illegal operands `vwadd.wv v1,v2,v4'
  3173. +.*Error: illegal operands `vwadd.wv v2,v3,v4'
  3174. +.*Error: illegal operands `vwadd.wv v4,v2,v4'
  3175. +.*Error: illegal operands `vwadd.wv v4,v2,v5'
  3176. +.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
  3177. +.*Error: illegal operands `vwsub.wv v1,v2,v4'
  3178. +.*Error: illegal operands `vwsub.wv v2,v3,v4'
  3179. +.*Error: illegal operands `vwsub.wv v4,v2,v4'
  3180. +.*Error: illegal operands `vwsub.wv v4,v2,v5'
  3181. +.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
  3182. +.*Error: illegal operands `vfwadd.wv v1,v2,v4'
  3183. +.*Error: illegal operands `vfwadd.wv v2,v3,v4'
  3184. +.*Error: illegal operands `vfwadd.wv v4,v2,v4'
  3185. +.*Error: illegal operands `vfwadd.wv v4,v2,v5'
  3186. +.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
  3187. +.*Error: illegal operands `vfwsub.wv v1,v2,v4'
  3188. +.*Error: illegal operands `vfwsub.wv v2,v3,v4'
  3189. +.*Error: illegal operands `vfwsub.wv v4,v2,v4'
  3190. +.*Error: illegal operands `vfwsub.wv v4,v2,v5'
  3191. +.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
  3192. +.*Error: illegal operands `vwaddu.wx v1,v2,a1'
  3193. +.*Error: illegal operands `vwaddu.wx v2,v3,a1'
  3194. +.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
  3195. +.*Error: illegal operands `vwsubu.wx v1,v2,a1'
  3196. +.*Error: illegal operands `vwsubu.wx v2,v3,a1'
  3197. +.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
  3198. +.*Error: illegal operands `vwadd.wx v1,v2,a1'
  3199. +.*Error: illegal operands `vwadd.wx v2,v3,a1'
  3200. +.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
  3201. +.*Error: illegal operands `vwsub.wx v1,v2,a1'
  3202. +.*Error: illegal operands `vwsub.wx v2,v3,a1'
  3203. +.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
  3204. +.*Error: illegal operands `vfwadd.wf v1,v2,fa1'
  3205. +.*Error: illegal operands `vfwadd.wf v2,v3,fa1'
  3206. +.*Error: illegal operands `vfwadd.wf v0,v2,fa1,v0.t'
  3207. +.*Error: illegal operands `vfwsub.wf v1,v2,fa1'
  3208. +.*Error: illegal operands `vfwsub.wf v2,v3,fa1'
  3209. +.*Error: illegal operands `vfwsub.wf v0,v2,fa1,v0.t'
  3210. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.s b/gas/testsuite/gas/riscv/vector-insns-fail-04.s
  3211. new file mode 100644
  3212. index 0000000000..e1db16d53b
  3213. --- /dev/null
  3214. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-04.s
  3215. @@ -0,0 +1,85 @@
  3216. +# Widening Vector Arithmetic Instructions (W[V|X])
  3217. +
  3218. + vwaddu.wv v0, v2, v4 # OK
  3219. + vwaddu.wv v1, v2, v4 # vd should be multiple of 2
  3220. + vwaddu.wv v2, v2, v4 # OK
  3221. + vwaddu.wv v2, v3, v4 # vs2 should be multiple of 2
  3222. + vwaddu.wv v4, v2, v4 # vd overlap vs1
  3223. + vwaddu.wv v4, v2, v5 # vd overlap vs1
  3224. + vwaddu.wv v0, v2, v4, v0.t # vd overlap vm
  3225. +
  3226. + vwsubu.wv v0, v2, v4 # OK
  3227. + vwsubu.wv v1, v2, v4 # vd should be multiple of 2
  3228. + vwsubu.wv v2, v2, v4 # OK
  3229. + vwsubu.wv v2, v3, v4 # vs2 should be multiple of 2
  3230. + vwsubu.wv v4, v2, v4 # vd overlap vs1
  3231. + vwsubu.wv v4, v2, v5 # vd overlap vs1
  3232. + vwsubu.wv v0, v2, v4, v0.t # vd overlap vm
  3233. +
  3234. + vwadd.wv v0, v2, v4 # OK
  3235. + vwadd.wv v1, v2, v4 # vd should be multiple of 2
  3236. + vwadd.wv v2, v2, v4 # OK
  3237. + vwadd.wv v2, v3, v4 # vs2 should be multiple of 2
  3238. + vwadd.wv v4, v2, v4 # vd overlap vs1
  3239. + vwadd.wv v4, v2, v5 # vd overlap vs1
  3240. + vwadd.wv v0, v2, v4, v0.t # vd overlap vm
  3241. +
  3242. + vwsub.wv v0, v2, v4 # OK
  3243. + vwsub.wv v1, v2, v4 # vd should be multiple of 2
  3244. + vwsub.wv v2, v2, v4 # OK
  3245. + vwsub.wv v2, v3, v4 # vs2 should be multiple of 2
  3246. + vwsub.wv v4, v2, v4 # vd overlap vs1
  3247. + vwsub.wv v4, v2, v5 # vd overlap vs1
  3248. + vwsub.wv v0, v2, v4, v0.t # vd overlap vm
  3249. +
  3250. + vfwadd.wv v0, v2, v4 # OK
  3251. + vfwadd.wv v1, v2, v4 # vd should be multiple of 2
  3252. + vfwadd.wv v2, v2, v4 # OK
  3253. + vfwadd.wv v2, v3, v4 # vs2 should be multiple of 2
  3254. + vfwadd.wv v4, v2, v4 # vd overlap vs1
  3255. + vfwadd.wv v4, v2, v5 # vd overlap vs1
  3256. + vfwadd.wv v0, v2, v4, v0.t # vd overlap vm
  3257. +
  3258. + vfwsub.wv v0, v2, v4 # OK
  3259. + vfwsub.wv v1, v2, v4 # vd should be multiple of 2
  3260. + vfwsub.wv v2, v2, v4 # OK
  3261. + vfwsub.wv v2, v3, v4 # vs2 should be multiple of 2
  3262. + vfwsub.wv v4, v2, v4 # vd overlap vs1
  3263. + vfwsub.wv v4, v2, v5 # vd overlap vs1
  3264. + vfwsub.wv v0, v2, v4, v0.t # vd overlap vm
  3265. +
  3266. + vwaddu.wx v0, v2, a1 # OK
  3267. + vwaddu.wx v1, v2, a1 # vd should be multiple of 2
  3268. + vwaddu.wx v2, v2, a1 # OK
  3269. + vwaddu.wx v2, v3, a1 # vs2 should be multiple of 2
  3270. + vwaddu.wx v0, v2, a1, v0.t # vd overlap vm
  3271. +
  3272. + vwsubu.wx v0, v2, a1 # OK
  3273. + vwsubu.wx v1, v2, a1 # vd should be multiple of 2
  3274. + vwsubu.wx v2, v2, a1 # OK
  3275. + vwsubu.wx v2, v3, a1 # vs2 should be multiple of 2
  3276. + vwsubu.wx v0, v2, a1, v0.t # vd overlap vm
  3277. +
  3278. + vwadd.wx v0, v2, a1 # OK
  3279. + vwadd.wx v1, v2, a1 # vd should be multiple of 2
  3280. + vwadd.wx v2, v2, a1 # OK
  3281. + vwadd.wx v2, v3, a1 # vs2 should be multiple of 2
  3282. + vwadd.wx v0, v2, a1, v0.t # vd overlap vm
  3283. +
  3284. + vwsub.wx v0, v2, a1 # OK
  3285. + vwsub.wx v1, v2, a1 # vd should be multiple of 2
  3286. + vwsub.wx v2, v2, a1 # OK
  3287. + vwsub.wx v2, v3, a1 # vs2 should be multiple of 2
  3288. + vwsub.wx v0, v2, a1, v0.t # vd overlap vm
  3289. +
  3290. + vfwadd.wf v0, v2, fa1 # OK
  3291. + vfwadd.wf v1, v2, fa1 # vd should be multiple of 2
  3292. + vfwadd.wf v2, v2, fa1 # OK
  3293. + vfwadd.wf v2, v3, fa1 # vs2 should be multiple of 2
  3294. + vfwadd.wf v0, v2, fa1, v0.t # vd overlap vm
  3295. +
  3296. + vfwsub.wf v0, v2, fa1 # OK
  3297. + vfwsub.wf v1, v2, fa1 # vd should be multiple of 2
  3298. + vfwsub.wf v2, v2, fa1 # OK
  3299. + vfwsub.wf v2, v3, fa1 # vs2 should be multiple of 2
  3300. + vfwsub.wf v0, v2, fa1, v0.t # vd overlap vm
  3301. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.d b/gas/testsuite/gas/riscv/vector-insns-fail-05.d
  3302. new file mode 100644
  3303. index 0000000000..b13053ab06
  3304. --- /dev/null
  3305. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.d
  3306. @@ -0,0 +1,3 @@
  3307. +#as: -march=rv32ifv -mcheck-constraints
  3308. +#source: vector-insns-fail-05.s
  3309. +#error_output: vector-insns-fail-05.l
  3310. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.l b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
  3311. new file mode 100644
  3312. index 0000000000..fa519ffcf9
  3313. --- /dev/null
  3314. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
  3315. @@ -0,0 +1,61 @@
  3316. +.*: Assembler messages:
  3317. +.*Error: illegal operands `vnsrl.wv v2,v2,v4'
  3318. +.*Error: illegal operands `vnsrl.wv v2,v3,v4'
  3319. +.*Error: illegal operands `vnsrl.wv v3,v2,v4'
  3320. +.*Error: illegal operands `vnsrl.wx v2,v2,a1'
  3321. +.*Error: illegal operands `vnsrl.wx v2,v3,a1'
  3322. +.*Error: illegal operands `vnsrl.wx v3,v2,a1'
  3323. +.*Error: illegal operands `vnsrl.wi v2,v2,1'
  3324. +.*Error: illegal operands `vnsrl.wi v2,v3,1'
  3325. +.*Error: illegal operands `vnsrl.wi v3,v2,1'
  3326. +.*Error: illegal operands `vnsra.wv v2,v2,v4'
  3327. +.*Error: illegal operands `vnsra.wv v2,v3,v4'
  3328. +.*Error: illegal operands `vnsra.wv v3,v2,v4'
  3329. +.*Error: illegal operands `vnsra.wx v2,v2,a1'
  3330. +.*Error: illegal operands `vnsra.wx v2,v3,a1'
  3331. +.*Error: illegal operands `vnsra.wx v3,v2,a1'
  3332. +.*Error: illegal operands `vnsra.wi v2,v2,1'
  3333. +.*Error: illegal operands `vnsra.wi v2,v3,1'
  3334. +.*Error: illegal operands `vnsra.wi v3,v2,1'
  3335. +.*Error: illegal operands `vnclipu.wv v2,v2,v4'
  3336. +.*Error: illegal operands `vnclipu.wv v2,v3,v4'
  3337. +.*Error: illegal operands `vnclipu.wv v3,v2,v4'
  3338. +.*Error: illegal operands `vnclipu.wx v2,v2,a1'
  3339. +.*Error: illegal operands `vnclipu.wx v2,v3,a1'
  3340. +.*Error: illegal operands `vnclipu.wx v3,v2,a1'
  3341. +.*Error: illegal operands `vnclipu.wi v2,v2,1'
  3342. +.*Error: illegal operands `vnclipu.wi v2,v3,1'
  3343. +.*Error: illegal operands `vnclipu.wi v3,v2,1'
  3344. +.*Error: illegal operands `vnclip.wv v2,v2,v4'
  3345. +.*Error: illegal operands `vnclip.wv v2,v3,v4'
  3346. +.*Error: illegal operands `vnclip.wv v3,v2,v4'
  3347. +.*Error: illegal operands `vnclip.wx v2,v2,a1'
  3348. +.*Error: illegal operands `vnclip.wx v2,v3,a1'
  3349. +.*Error: illegal operands `vnclip.wx v3,v2,a1'
  3350. +.*Error: illegal operands `vnclip.wi v2,v2,1'
  3351. +.*Error: illegal operands `vnclip.wi v2,v3,1'
  3352. +.*Error: illegal operands `vnclip.wi v3,v2,1'
  3353. +.*Error: illegal operands `vfncvt.xu.f.w v2,v2'
  3354. +.*Error: illegal operands `vfncvt.xu.f.w v2,v3'
  3355. +.*Error: illegal operands `vfncvt.xu.f.w v3,v2'
  3356. +.*Error: illegal operands `vfncvt.x.f.w v2,v2'
  3357. +.*Error: illegal operands `vfncvt.x.f.w v2,v3'
  3358. +.*Error: illegal operands `vfncvt.x.f.w v3,v2'
  3359. +.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v2'
  3360. +.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v3'
  3361. +.*Error: illegal operands `vfncvt.rtz.xu.f.w v3,v2'
  3362. +.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v2'
  3363. +.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v3'
  3364. +.*Error: illegal operands `vfncvt.rtz.x.f.w v3,v2'
  3365. +.*Error: illegal operands `vfncvt.f.xu.w v2,v2'
  3366. +.*Error: illegal operands `vfncvt.f.xu.w v2,v3'
  3367. +.*Error: illegal operands `vfncvt.f.xu.w v3,v2'
  3368. +.*Error: illegal operands `vfncvt.f.x.w v2,v2'
  3369. +.*Error: illegal operands `vfncvt.f.x.w v2,v3'
  3370. +.*Error: illegal operands `vfncvt.f.x.w v3,v2'
  3371. +.*Error: illegal operands `vfncvt.f.f.w v2,v2'
  3372. +.*Error: illegal operands `vfncvt.f.f.w v2,v3'
  3373. +.*Error: illegal operands `vfncvt.f.f.w v3,v2'
  3374. +.*Error: illegal operands `vfncvt.rod.f.f.w v2,v2'
  3375. +.*Error: illegal operands `vfncvt.rod.f.f.w v2,v3'
  3376. +.*Error: illegal operands `vfncvt.rod.f.f.w v3,v2'
  3377. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.s b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
  3378. new file mode 100644
  3379. index 0000000000..2ec027299c
  3380. --- /dev/null
  3381. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
  3382. @@ -0,0 +1,133 @@
  3383. +# Narrowing Vector Arithmetic Instructions
  3384. +
  3385. + vnsrl.wv v0, v2, v4 # OK
  3386. + vnsrl.wv v2, v2, v4 # vd overlap vs2
  3387. + vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
  3388. + vnsrl.wv v3, v2, v4 # vd overlap vs2
  3389. + vnsrl.wv v4, v2, v4 # OK
  3390. + vnsrl.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
  3391. +
  3392. + vnsrl.wx v0, v2, a1 # OK
  3393. + vnsrl.wx v2, v2, a1 # vd overlap vs2
  3394. + vnsrl.wx v2, v3, a1 # vs2 should be multiple of 2
  3395. + vnsrl.wx v3, v2, a1 # vd overlap vs2
  3396. + vnsrl.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
  3397. +
  3398. + vnsrl.wi v0, v2, 1 # OK
  3399. + vnsrl.wi v2, v2, 1 # vd overlap vs2
  3400. + vnsrl.wi v2, v3, 1 # vs2 should be multiple of 2
  3401. + vnsrl.wi v3, v2, 1 # vd overlap vs2
  3402. + vnsrl.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
  3403. +
  3404. + vnsra.wv v0, v2, v4 # OK
  3405. + vnsra.wv v2, v2, v4 # vd overlap vs2
  3406. + vnsra.wv v2, v3, v4 # vs2 should be multiple of 2
  3407. + vnsra.wv v3, v2, v4 # vd overlap vs2
  3408. + vnsra.wv v4, v2, v4 # OK
  3409. + vnsra.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
  3410. +
  3411. + vnsra.wx v0, v2, a1 # OK
  3412. + vnsra.wx v2, v2, a1 # vd overlap vs2
  3413. + vnsra.wx v2, v3, a1 # vs2 should be multiple of 2
  3414. + vnsra.wx v3, v2, a1 # vd overlap vs2
  3415. + vnsra.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
  3416. +
  3417. + vnsra.wi v0, v2, 1 # OK
  3418. + vnsra.wi v2, v2, 1 # vd overlap vs2
  3419. + vnsra.wi v2, v3, 1 # vs2 should be multiple of 2
  3420. + vnsra.wi v3, v2, 1 # vd overlap vs2
  3421. + vnsra.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
  3422. +
  3423. + vnclipu.wv v0, v2, v4 # OK
  3424. + vnclipu.wv v2, v2, v4 # vd overlap vs2
  3425. + vnclipu.wv v2, v3, v4 # vs2 should be multiple of 2
  3426. + vnclipu.wv v3, v2, v4 # vd overlap vs2
  3427. + vnclipu.wv v4, v2, v4 # OK
  3428. + vnclipu.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
  3429. +
  3430. + vnclipu.wx v0, v2, a1 # OK
  3431. + vnclipu.wx v2, v2, a1 # vd overlap vs2
  3432. + vnclipu.wx v2, v3, a1 # vs2 should be multiple of 2
  3433. + vnclipu.wx v3, v2, a1 # vd overlap vs2
  3434. + vnclipu.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
  3435. +
  3436. + vnclipu.wi v0, v2, 1 # OK
  3437. + vnclipu.wi v2, v2, 1 # vd overlap vs2
  3438. + vnclipu.wi v2, v3, 1 # vs2 should be multiple of 2
  3439. + vnclipu.wi v3, v2, 1 # vd overlap vs2
  3440. + vnclipu.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
  3441. +
  3442. + vnclip.wv v0, v2, v4 # OK
  3443. + vnclip.wv v2, v2, v4 # vd overlap vs2
  3444. + vnclip.wv v2, v3, v4 # vs2 should be multiple of 2
  3445. + vnclip.wv v3, v2, v4 # vd overlap vs2
  3446. + vnclip.wv v4, v2, v4 # OK
  3447. + vnclip.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
  3448. +
  3449. + vnclip.wx v0, v2, a1 # OK
  3450. + vnclip.wx v2, v2, a1 # vd overlap vs2
  3451. + vnclip.wx v2, v3, a1 # vs2 should be multiple of 2
  3452. + vnclip.wx v3, v2, a1 # vd overlap vs2
  3453. + vnclip.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
  3454. +
  3455. + vnclip.wi v0, v2, 1 # OK
  3456. + vnclip.wi v2, v2, 1 # vd overlap vs2
  3457. + vnclip.wi v2, v3, 1 # vs2 should be multiple of 2
  3458. + vnclip.wi v3, v2, 1 # vd overlap vs2
  3459. + vnclip.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
  3460. +
  3461. + vfncvt.xu.f.w v0, v2 # OK
  3462. + vfncvt.xu.f.w v2, v2 # vd overlap vs2
  3463. + vfncvt.xu.f.w v2, v3 # vs2 should be multiple of 2
  3464. + vfncvt.xu.f.w v3, v2 # vd overlap vs2
  3465. + vfncvt.xu.f.w v4, v2 # OK
  3466. + vfncvt.xu.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  3467. +
  3468. + vfncvt.x.f.w v0, v2 # OK
  3469. + vfncvt.x.f.w v2, v2 # vd overlap vs2
  3470. + vfncvt.x.f.w v2, v3 # vs2 should be multiple of 2
  3471. + vfncvt.x.f.w v3, v2 # vd overlap vs2
  3472. + vfncvt.x.f.w v4, v2 # OK
  3473. + vfncvt.x.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  3474. +
  3475. + vfncvt.rtz.xu.f.w v0, v2 # OK
  3476. + vfncvt.rtz.xu.f.w v2, v2 # vd overlap vs2
  3477. + vfncvt.rtz.xu.f.w v2, v3 # vs2 should be multiple of 2
  3478. + vfncvt.rtz.xu.f.w v3, v2 # vd overlap vs2
  3479. + vfncvt.rtz.xu.f.w v4, v2 # OK
  3480. + vfncvt.rtz.xu.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  3481. +
  3482. + vfncvt.rtz.x.f.w v0, v2 # OK
  3483. + vfncvt.rtz.x.f.w v2, v2 # vd overlap vs2
  3484. + vfncvt.rtz.x.f.w v2, v3 # vs2 should be multiple of 2
  3485. + vfncvt.rtz.x.f.w v3, v2 # vd overlap vs2
  3486. + vfncvt.rtz.x.f.w v4, v2 # OK
  3487. + vfncvt.rtz.x.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  3488. +
  3489. + vfncvt.f.xu.w v0, v2 # OK
  3490. + vfncvt.f.xu.w v2, v2 # vd overlap vs2
  3491. + vfncvt.f.xu.w v2, v3 # vs2 should be multiple of 2
  3492. + vfncvt.f.xu.w v3, v2 # vd overlap vs2
  3493. + vfncvt.f.xu.w v4, v2 # OK
  3494. + vfncvt.f.xu.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  3495. +
  3496. + vfncvt.f.x.w v0, v2 # OK
  3497. + vfncvt.f.x.w v2, v2 # vd overlap vs2
  3498. + vfncvt.f.x.w v2, v3 # vs2 should be multiple of 2
  3499. + vfncvt.f.x.w v3, v2 # vd overlap vs2
  3500. + vfncvt.f.x.w v4, v2 # OK
  3501. + vfncvt.f.x.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  3502. +
  3503. + vfncvt.f.f.w v0, v2 # OK
  3504. + vfncvt.f.f.w v2, v2 # vd overlap vs2
  3505. + vfncvt.f.f.w v2, v3 # vs2 should be multiple of 2
  3506. + vfncvt.f.f.w v3, v2 # vd overlap vs2
  3507. + vfncvt.f.f.w v4, v2 # OK
  3508. + vfncvt.f.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  3509. +
  3510. + vfncvt.rod.f.f.w v0, v2 # OK
  3511. + vfncvt.rod.f.f.w v2, v2 # vd overlap vs2
  3512. + vfncvt.rod.f.f.w v2, v3 # vs2 should be multiple of 2
  3513. + vfncvt.rod.f.f.w v3, v2 # vd overlap vs2
  3514. + vfncvt.rod.f.f.w v4, v2 # OK
  3515. + vfncvt.rod.f.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  3516. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.d b/gas/testsuite/gas/riscv/vector-insns-fail-06.d
  3517. new file mode 100644
  3518. index 0000000000..a2a2220d68
  3519. --- /dev/null
  3520. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.d
  3521. @@ -0,0 +1,3 @@
  3522. +#as: -march=rv32ifv -mcheck-constraints
  3523. +#source: vector-insns-fail-06.s
  3524. +#error_output: vector-insns-fail-06.l
  3525. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.l b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
  3526. new file mode 100644
  3527. index 0000000000..9a86dd37b5
  3528. --- /dev/null
  3529. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
  3530. @@ -0,0 +1,22 @@
  3531. +.*: Assembler messages:
  3532. +.*Error: illegal operands `viota.m v2,v2'
  3533. +.*Error: illegal operands `viota.m v0,v2,v0.t'
  3534. +.*Error: illegal operands `vslideup.vx v2,v2,a4'
  3535. +.*Error: illegal operands `vslideup.vi v2,v2,1'
  3536. +.*Error: illegal operands `vslide1up.vx v2,v2,a4'
  3537. +.*Error: illegal operands `vfslide1up.vf v2,v2,fa4'
  3538. +.*Error: illegal operands `vrgather.vv v2,v2,v4'
  3539. +.*Error: illegal operands `vrgather.vv v4,v2,v4'
  3540. +.*Error: illegal operands `vrgather.vv v0,v2,v4,v0.t'
  3541. +.*Error: illegal operands `vrgather.vx v2,v2,a4'
  3542. +.*Error: illegal operands `vrgather.vx v0,v2,a4,v0.t'
  3543. +.*Error: illegal operands `vrgather.vi v2,v2,1'
  3544. +.*Error: illegal operands `vrgather.vi v0,v2,1,v0.t'
  3545. +.*Error: illegal operands `vcompress.vm v2,v2,v4'
  3546. +.*Error: illegal operands `vcompress.vm v4,v2,v4'
  3547. +.*Error: illegal operands `vmv2r.v v1,v2'
  3548. +.*Error: illegal operands `vmv2r.v v2,v3'
  3549. +.*Error: illegal operands `vmv4r.v v2,v4'
  3550. +.*Error: illegal operands `vmv4r.v v4,v7'
  3551. +.*Error: illegal operands `vmv8r.v v6,v8'
  3552. +.*Error: illegal operands `vmv8r.v v8,v12'
  3553. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.s b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
  3554. new file mode 100644
  3555. index 0000000000..df0edd44c9
  3556. --- /dev/null
  3557. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
  3558. @@ -0,0 +1,67 @@
  3559. +# Vector Iota Instruction
  3560. +# Vector Slideup Instructions
  3561. +# Vector Slide1up
  3562. +# Vector Register Gather Instruction
  3563. +# Vector Compress Instruction
  3564. +# Vector Load/Store Whole Register Instructions
  3565. +# Whole Vector Register Move
  3566. +
  3567. + viota.m v0, v2 # OK
  3568. + viota.m v2, v2 # vd overlap vs2
  3569. + viota.m v0, v2, v0.t # vd overlap vm
  3570. +
  3571. + vslideup.vx v0, v2, a4 # OK
  3572. + vslideup.vx v1, v2, a4 # OK
  3573. + vslideup.vx v2, v2, a4 # vd overlap vs2
  3574. + vslideup.vx v0, v2, a4, v0.t # vd overlap vm
  3575. +
  3576. + vslideup.vi v0, v2, 1 # OK
  3577. + vslideup.vi v1, v2, 1 # OK
  3578. + vslideup.vi v2, v2, 1 # vd overlap vs2
  3579. + vslideup.vi v0, v2, 1, v0.t # vd overlap vm
  3580. +
  3581. + vslide1up.vx v0, v2, a4 # OK
  3582. + vslide1up.vx v1, v2, a4 # OK
  3583. + vslide1up.vx v2, v2, a4 # vd overlap vs2
  3584. + vslide1up.vx v0, v2, a4, v0.t # vd overlap vm
  3585. +
  3586. + vfslide1up.vf v0, v2, fa4 # OK
  3587. + vfslide1up.vf v1, v2, fa4 # OK
  3588. + vfslide1up.vf v2, v2, fa4 # vd overlap vs2
  3589. + vfslide1up.vf v0, v2, fa4, v0.t # vd overlap vm
  3590. +
  3591. + vrgather.vv v0, v2, v4 # OK
  3592. + vrgather.vv v1, v2, v4 # OK
  3593. + vrgather.vv v2, v2, v4 # vd overlap vs2
  3594. + vrgather.vv v4, v2, v4 # vd overlap vs1
  3595. + vrgather.vv v0, v2, v4, v0.t # vd overlap vm
  3596. +
  3597. + vrgather.vx v0, v2, a4 # OK
  3598. + vrgather.vx v1, v2, a4 # OK
  3599. + vrgather.vx v2, v2, a4 # vd overlap vs2
  3600. + vrgather.vx v0, v2, a4, v0.t # vd overlap vm
  3601. +
  3602. + vrgather.vi v0, v2, 1 # OK
  3603. + vrgather.vi v1, v2, 1 # OK
  3604. + vrgather.vi v2, v2, 1 # vd overlap vs2
  3605. + vrgather.vi v0, v2, 1, v0.t # vd overlap vm
  3606. +
  3607. + vcompress.vm v0, v2, v4 # OK
  3608. + vcompress.vm v1, v2, v4 # OK
  3609. + vcompress.vm v2, v2, v4 # vd overlap vs2
  3610. + vcompress.vm v4, v2, v4 # vd overlap vs1
  3611. +
  3612. + vmv1r.v v0, v1 # OK
  3613. + vmv1r.v v2, v3 # OK
  3614. +
  3615. + vmv2r.v v0, v2 # OK
  3616. + vmv2r.v v1, v2 # vd must be aligned to 2
  3617. + vmv2r.v v2, v3 # vs2 must be aligned to 2
  3618. +
  3619. + vmv4r.v v0, v4 # OK
  3620. + vmv4r.v v2, v4 # vd must be aligned to 4
  3621. + vmv4r.v v4, v7 # vs2 must be aligned to 4
  3622. +
  3623. + vmv8r.v v0, v8 # OK
  3624. + vmv8r.v v6, v8 # vd must be aligned to 8
  3625. + vmv8r.v v8, v12 # vs2 must be aligned to 8
  3626. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d
  3627. new file mode 100644
  3628. index 0000000000..a730a2e941
  3629. --- /dev/null
  3630. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d
  3631. @@ -0,0 +1,20 @@
  3632. +#as: -march=rv32iv
  3633. +#source: vector-insns-fail-zvediv.s
  3634. +#warning_output: vector-insns-fail-zvediv.l
  3635. +#objdump: -dr
  3636. +
  3637. +.*:[ ]+file format .*
  3638. +
  3639. +
  3640. +Disassembly of section .text:
  3641. +
  3642. +0+000 <.text>:
  3643. +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d1
  3644. +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
  3645. +[ ]+[0-9a-f]+:[ ]+3005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d8
  3646. +[ ]+[0-9a-f]+:[ ]+4ff5f557[ ]+vsetvli[ ]+a0,a1,1279
  3647. +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d1
  3648. +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d1
  3649. +[ ]+[0-9a-f]+:[ ]+1005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d2
  3650. +[ ]+[0-9a-f]+:[ ]+2005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d4
  3651. +[ ]+[0-9a-f]+:[ ]+3005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d8
  3652. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l
  3653. new file mode 100644
  3654. index 0000000000..2b0b73bc64
  3655. --- /dev/null
  3656. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l
  3657. @@ -0,0 +1,6 @@
  3658. +.*Assembler messages:
  3659. +.*2: Warning: vediv is set but Zvediv extension isn't enabled
  3660. +.*3: Warning: vediv is set but Zvediv extension isn't enabled
  3661. +.*7: Warning: vediv is set but Zvediv extension isn't enabled
  3662. +.*8: Warning: vediv is set but Zvediv extension isn't enabled
  3663. +.*9: Warning: vediv is set but Zvediv extension isn't enabled
  3664. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s
  3665. new file mode 100644
  3666. index 0000000000..834cc17c4a
  3667. --- /dev/null
  3668. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s
  3669. @@ -0,0 +1,9 @@
  3670. + vsetvli a0, a1, 0
  3671. + vsetvli a0, a1, 0x7ff
  3672. + vsetvli a0, a1, 0x300
  3673. + vsetvli a0, a1, 0x4ff
  3674. + vsetvli a0, a1, e8, m1
  3675. + vsetvli a0, a1, e8, m1, d1
  3676. + vsetvli a0, a1, e8, m1, d2
  3677. + vsetvli a0, a1, e8, m1, d4
  3678. + vsetvli a0, a1, e8, m1, d8
  3679. diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
  3680. new file mode 100644
  3681. index 0000000000..4d33fe7d59
  3682. --- /dev/null
  3683. +++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
  3684. @@ -0,0 +1,29 @@
  3685. +#as: -march=rv32iv
  3686. +#objdump: -dr
  3687. +
  3688. +.*:[ ]+file format .*
  3689. +
  3690. +
  3691. +Disassembly of section .text:
  3692. +
  3693. +0+000 <.text>:
  3694. +[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+vmslt.vx[ ]+v4,v8,a1
  3695. +[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
  3696. +[ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t
  3697. +[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
  3698. +[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
  3699. +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
  3700. +[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
  3701. +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
  3702. +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
  3703. +[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
  3704. +[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1
  3705. +[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
  3706. +[ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t
  3707. +[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
  3708. +[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
  3709. +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
  3710. +[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
  3711. +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
  3712. +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
  3713. +[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
  3714. diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
  3715. new file mode 100644
  3716. index 0000000000..afbb7ccb36
  3717. --- /dev/null
  3718. +++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
  3719. @@ -0,0 +1,9 @@
  3720. + vmsge.vx v4, v8, a1 # unmasked va >= x
  3721. + vmsge.vx v8, v12, a2, v0.t # masked va >= x, vd != v0
  3722. + vmsge.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0
  3723. + vmsge.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd
  3724. +
  3725. + vmsgeu.vx v4, v8, a1 # unmasked va >= x
  3726. + vmsgeu.vx v8, v12, a2, v0.t # masked va >= x, vd != v0
  3727. + vmsgeu.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0
  3728. + vmsgeu.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd
  3729. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
  3730. new file mode 100644
  3731. index 0000000000..5e7267c3f8
  3732. --- /dev/null
  3733. +++ b/gas/testsuite/gas/riscv/vector-insns.d
  3734. @@ -0,0 +1,2384 @@
  3735. +#as: -march=rv32iafv_zvediv_zvqmac
  3736. +#objdump: -dr
  3737. +
  3738. +.*:[ ]+file format .*
  3739. +
  3740. +
  3741. +Disassembly of section .text:
  3742. +
  3743. +0+000 <.text>:
  3744. +[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2
  3745. +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d1
  3746. +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
  3747. +[ ]+[0-9a-f]+:[ ]+2055f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu,d4
  3748. +[ ]+[0-9a-f]+:[ ]+3175f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu,d8
  3749. +[ ]+[0-9a-f]+:[ ]+31b5f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu,d8
  3750. +[ ]+[0-9a-f]+:[ ]+31f5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu,d8
  3751. +[ ]+[0-9a-f]+:[ ]+31c5f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu,d8
  3752. +[ ]+[0-9a-f]+:[ ]+33f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu,d8
  3753. +[ ]+[0-9a-f]+:[ ]+13a5f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu,d2
  3754. +[ ]+[0-9a-f]+:[ ]+2355f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu,d4
  3755. +[ ]+[0-9a-f]+:[ ]+2555f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu,d4
  3756. +[ ]+[0-9a-f]+:[ ]+2955f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma,d4
  3757. +[ ]+[0-9a-f]+:[ ]+2155f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
  3758. +[ ]+[0-9a-f]+:[ ]+2155f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
  3759. +[ ]+[0-9a-f]+:[ ]+2d55f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma,d4
  3760. +[ ]+[0-9a-f]+:[ ]+2955f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma,d4
  3761. +[ ]+[0-9a-f]+:[ ]+2555f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu,d4
  3762. +[ ]+[0-9a-f]+:[ ]+2155f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
  3763. +[ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
  3764. +[ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
  3765. +[ ]+[0-9a-f]+:[ ]+00050207[ ]+vle8.v[ ]+v4,\(a0\),v0.t
  3766. +[ ]+[0-9a-f]+:[ ]+02050227[ ]+vse8.v[ ]+v4,\(a0\)
  3767. +[ ]+[0-9a-f]+:[ ]+02050227[ ]+vse8.v[ ]+v4,\(a0\)
  3768. +[ ]+[0-9a-f]+:[ ]+00050227[ ]+vse8.v[ ]+v4,\(a0\),v0.t
  3769. +[ ]+[0-9a-f]+:[ ]+02055207[ ]+vle16.v[ ]+v4,\(a0\)
  3770. +[ ]+[0-9a-f]+:[ ]+02055207[ ]+vle16.v[ ]+v4,\(a0\)
  3771. +[ ]+[0-9a-f]+:[ ]+00055207[ ]+vle16.v[ ]+v4,\(a0\),v0.t
  3772. +[ ]+[0-9a-f]+:[ ]+02055227[ ]+vse16.v[ ]+v4,\(a0\)
  3773. +[ ]+[0-9a-f]+:[ ]+02055227[ ]+vse16.v[ ]+v4,\(a0\)
  3774. +[ ]+[0-9a-f]+:[ ]+00055227[ ]+vse16.v[ ]+v4,\(a0\),v0.t
  3775. +[ ]+[0-9a-f]+:[ ]+02056207[ ]+vle32.v[ ]+v4,\(a0\)
  3776. +[ ]+[0-9a-f]+:[ ]+02056207[ ]+vle32.v[ ]+v4,\(a0\)
  3777. +[ ]+[0-9a-f]+:[ ]+00056207[ ]+vle32.v[ ]+v4,\(a0\),v0.t
  3778. +[ ]+[0-9a-f]+:[ ]+02056227[ ]+vse32.v[ ]+v4,\(a0\)
  3779. +[ ]+[0-9a-f]+:[ ]+02056227[ ]+vse32.v[ ]+v4,\(a0\)
  3780. +[ ]+[0-9a-f]+:[ ]+00056227[ ]+vse32.v[ ]+v4,\(a0\),v0.t
  3781. +[ ]+[0-9a-f]+:[ ]+02057207[ ]+vle64.v[ ]+v4,\(a0\)
  3782. +[ ]+[0-9a-f]+:[ ]+02057207[ ]+vle64.v[ ]+v4,\(a0\)
  3783. +[ ]+[0-9a-f]+:[ ]+00057207[ ]+vle64.v[ ]+v4,\(a0\),v0.t
  3784. +[ ]+[0-9a-f]+:[ ]+02057227[ ]+vse64.v[ ]+v4,\(a0\)
  3785. +[ ]+[0-9a-f]+:[ ]+02057227[ ]+vse64.v[ ]+v4,\(a0\)
  3786. +[ ]+[0-9a-f]+:[ ]+00057227[ ]+vse64.v[ ]+v4,\(a0\),v0.t
  3787. +[ ]+[0-9a-f]+:[ ]+12050207[ ]+vle128.v[ ]+v4,\(a0\)
  3788. +[ ]+[0-9a-f]+:[ ]+12050207[ ]+vle128.v[ ]+v4,\(a0\)
  3789. +[ ]+[0-9a-f]+:[ ]+10050207[ ]+vle128.v[ ]+v4,\(a0\),v0.t
  3790. +[ ]+[0-9a-f]+:[ ]+12050227[ ]+vse128.v[ ]+v4,\(a0\)
  3791. +[ ]+[0-9a-f]+:[ ]+12050227[ ]+vse128.v[ ]+v4,\(a0\)
  3792. +[ ]+[0-9a-f]+:[ ]+10050227[ ]+vse128.v[ ]+v4,\(a0\),v0.t
  3793. +[ ]+[0-9a-f]+:[ ]+12055207[ ]+vle256.v[ ]+v4,\(a0\)
  3794. +[ ]+[0-9a-f]+:[ ]+12055207[ ]+vle256.v[ ]+v4,\(a0\)
  3795. +[ ]+[0-9a-f]+:[ ]+10055207[ ]+vle256.v[ ]+v4,\(a0\),v0.t
  3796. +[ ]+[0-9a-f]+:[ ]+12055227[ ]+vse256.v[ ]+v4,\(a0\)
  3797. +[ ]+[0-9a-f]+:[ ]+12055227[ ]+vse256.v[ ]+v4,\(a0\)
  3798. +[ ]+[0-9a-f]+:[ ]+10055227[ ]+vse256.v[ ]+v4,\(a0\),v0.t
  3799. +[ ]+[0-9a-f]+:[ ]+12056207[ ]+vle512.v[ ]+v4,\(a0\)
  3800. +[ ]+[0-9a-f]+:[ ]+12056207[ ]+vle512.v[ ]+v4,\(a0\)
  3801. +[ ]+[0-9a-f]+:[ ]+10056207[ ]+vle512.v[ ]+v4,\(a0\),v0.t
  3802. +[ ]+[0-9a-f]+:[ ]+12056227[ ]+vse512.v[ ]+v4,\(a0\)
  3803. +[ ]+[0-9a-f]+:[ ]+12056227[ ]+vse512.v[ ]+v4,\(a0\)
  3804. +[ ]+[0-9a-f]+:[ ]+10056227[ ]+vse512.v[ ]+v4,\(a0\),v0.t
  3805. +[ ]+[0-9a-f]+:[ ]+12057207[ ]+vle1024.v[ ]+v4,\(a0\)
  3806. +[ ]+[0-9a-f]+:[ ]+12057207[ ]+vle1024.v[ ]+v4,\(a0\)
  3807. +[ ]+[0-9a-f]+:[ ]+10057207[ ]+vle1024.v[ ]+v4,\(a0\),v0.t
  3808. +[ ]+[0-9a-f]+:[ ]+12057227[ ]+vse1024.v[ ]+v4,\(a0\)
  3809. +[ ]+[0-9a-f]+:[ ]+12057227[ ]+vse1024.v[ ]+v4,\(a0\)
  3810. +[ ]+[0-9a-f]+:[ ]+10057227[ ]+vse1024.v[ ]+v4,\(a0\),v0.t
  3811. +[ ]+[0-9a-f]+:[ ]+0ab50207[ ]+vlse8.v[ ]+v4,\(a0\),a1
  3812. +[ ]+[0-9a-f]+:[ ]+0ab50207[ ]+vlse8.v[ ]+v4,\(a0\),a1
  3813. +[ ]+[0-9a-f]+:[ ]+08b50207[ ]+vlse8.v[ ]+v4,\(a0\),a1,v0.t
  3814. +[ ]+[0-9a-f]+:[ ]+0ab50227[ ]+vsse8.v[ ]+v4,\(a0\),a1
  3815. +[ ]+[0-9a-f]+:[ ]+0ab50227[ ]+vsse8.v[ ]+v4,\(a0\),a1
  3816. +[ ]+[0-9a-f]+:[ ]+08b50227[ ]+vsse8.v[ ]+v4,\(a0\),a1,v0.t
  3817. +[ ]+[0-9a-f]+:[ ]+0ab55207[ ]+vlse16.v[ ]+v4,\(a0\),a1
  3818. +[ ]+[0-9a-f]+:[ ]+0ab55207[ ]+vlse16.v[ ]+v4,\(a0\),a1
  3819. +[ ]+[0-9a-f]+:[ ]+08b55207[ ]+vlse16.v[ ]+v4,\(a0\),a1,v0.t
  3820. +[ ]+[0-9a-f]+:[ ]+0ab55227[ ]+vsse16.v[ ]+v4,\(a0\),a1
  3821. +[ ]+[0-9a-f]+:[ ]+0ab55227[ ]+vsse16.v[ ]+v4,\(a0\),a1
  3822. +[ ]+[0-9a-f]+:[ ]+08b55227[ ]+vsse16.v[ ]+v4,\(a0\),a1,v0.t
  3823. +[ ]+[0-9a-f]+:[ ]+0ab56207[ ]+vlse32.v[ ]+v4,\(a0\),a1
  3824. +[ ]+[0-9a-f]+:[ ]+0ab56207[ ]+vlse32.v[ ]+v4,\(a0\),a1
  3825. +[ ]+[0-9a-f]+:[ ]+08b56207[ ]+vlse32.v[ ]+v4,\(a0\),a1,v0.t
  3826. +[ ]+[0-9a-f]+:[ ]+0ab56227[ ]+vsse32.v[ ]+v4,\(a0\),a1
  3827. +[ ]+[0-9a-f]+:[ ]+0ab56227[ ]+vsse32.v[ ]+v4,\(a0\),a1
  3828. +[ ]+[0-9a-f]+:[ ]+08b56227[ ]+vsse32.v[ ]+v4,\(a0\),a1,v0.t
  3829. +[ ]+[0-9a-f]+:[ ]+0ab57207[ ]+vlse64.v[ ]+v4,\(a0\),a1
  3830. +[ ]+[0-9a-f]+:[ ]+0ab57207[ ]+vlse64.v[ ]+v4,\(a0\),a1
  3831. +[ ]+[0-9a-f]+:[ ]+08b57207[ ]+vlse64.v[ ]+v4,\(a0\),a1,v0.t
  3832. +[ ]+[0-9a-f]+:[ ]+0ab57227[ ]+vsse64.v[ ]+v4,\(a0\),a1
  3833. +[ ]+[0-9a-f]+:[ ]+0ab57227[ ]+vsse64.v[ ]+v4,\(a0\),a1
  3834. +[ ]+[0-9a-f]+:[ ]+08b57227[ ]+vsse64.v[ ]+v4,\(a0\),a1,v0.t
  3835. +[ ]+[0-9a-f]+:[ ]+1ab50207[ ]+vlse128.v[ ]+v4,\(a0\),a1
  3836. +[ ]+[0-9a-f]+:[ ]+1ab50207[ ]+vlse128.v[ ]+v4,\(a0\),a1
  3837. +[ ]+[0-9a-f]+:[ ]+18b50207[ ]+vlse128.v[ ]+v4,\(a0\),a1,v0.t
  3838. +[ ]+[0-9a-f]+:[ ]+1ab50227[ ]+vsse128.v[ ]+v4,\(a0\),a1
  3839. +[ ]+[0-9a-f]+:[ ]+1ab50227[ ]+vsse128.v[ ]+v4,\(a0\),a1
  3840. +[ ]+[0-9a-f]+:[ ]+18b50227[ ]+vsse128.v[ ]+v4,\(a0\),a1,v0.t
  3841. +[ ]+[0-9a-f]+:[ ]+1ab55207[ ]+vlse256.v[ ]+v4,\(a0\),a1
  3842. +[ ]+[0-9a-f]+:[ ]+1ab55207[ ]+vlse256.v[ ]+v4,\(a0\),a1
  3843. +[ ]+[0-9a-f]+:[ ]+18b55207[ ]+vlse256.v[ ]+v4,\(a0\),a1,v0.t
  3844. +[ ]+[0-9a-f]+:[ ]+1ab55227[ ]+vsse256.v[ ]+v4,\(a0\),a1
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  3846. +[ ]+[0-9a-f]+:[ ]+18b55227[ ]+vsse256.v[ ]+v4,\(a0\),a1,v0.t
  3847. +[ ]+[0-9a-f]+:[ ]+1ab56207[ ]+vlse512.v[ ]+v4,\(a0\),a1
  3848. +[ ]+[0-9a-f]+:[ ]+1ab56207[ ]+vlse512.v[ ]+v4,\(a0\),a1
  3849. +[ ]+[0-9a-f]+:[ ]+18b56207[ ]+vlse512.v[ ]+v4,\(a0\),a1,v0.t
  3850. +[ ]+[0-9a-f]+:[ ]+1ab56227[ ]+vsse512.v[ ]+v4,\(a0\),a1
  3851. +[ ]+[0-9a-f]+:[ ]+1ab56227[ ]+vsse512.v[ ]+v4,\(a0\),a1
  3852. +[ ]+[0-9a-f]+:[ ]+18b56227[ ]+vsse512.v[ ]+v4,\(a0\),a1,v0.t
  3853. +[ ]+[0-9a-f]+:[ ]+1ab57207[ ]+vlse1024.v[ ]+v4,\(a0\),a1
  3854. +[ ]+[0-9a-f]+:[ ]+1ab57207[ ]+vlse1024.v[ ]+v4,\(a0\),a1
  3855. +[ ]+[0-9a-f]+:[ ]+18b57207[ ]+vlse1024.v[ ]+v4,\(a0\),a1,v0.t
  3856. +[ ]+[0-9a-f]+:[ ]+1ab57227[ ]+vsse1024.v[ ]+v4,\(a0\),a1
  3857. +[ ]+[0-9a-f]+:[ ]+1ab57227[ ]+vsse1024.v[ ]+v4,\(a0\),a1
  3858. +[ ]+[0-9a-f]+:[ ]+18b57227[ ]+vsse1024.v[ ]+v4,\(a0\),a1,v0.t
  3859. +[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vlxei8.v[ ]+v4,\(a0\),v12
  3860. +[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vlxei8.v[ ]+v4,\(a0\),v12
  3861. +[ ]+[0-9a-f]+:[ ]+0cc50207[ ]+vlxei8.v[ ]+v4,\(a0\),v12,v0.t
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  3865. +[ ]+[0-9a-f]+:[ ]+06c50227[ ]+vsuxei8.v[ ]+v4,\(a0\),v12
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  3867. +[ ]+[0-9a-f]+:[ ]+04c50227[ ]+vsuxei8.v[ ]+v4,\(a0\),v12,v0.t
  3868. +[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+vlxei16.v[ ]+v4,\(a0\),v12
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  3870. +[ ]+[0-9a-f]+:[ ]+0cc55207[ ]+vlxei16.v[ ]+v4,\(a0\),v12,v0.t
  3871. +[ ]+[0-9a-f]+:[ ]+0ec55227[ ]+vsxei16.v[ ]+v4,\(a0\),v12
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  3873. +[ ]+[0-9a-f]+:[ ]+0cc55227[ ]+vsxei16.v[ ]+v4,\(a0\),v12,v0.t
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  3876. +[ ]+[0-9a-f]+:[ ]+04c55227[ ]+vsuxei16.v[ ]+v4,\(a0\),v12,v0.t
  3877. +[ ]+[0-9a-f]+:[ ]+0ec56207[ ]+vlxei32.v[ ]+v4,\(a0\),v12
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  3879. +[ ]+[0-9a-f]+:[ ]+0cc56207[ ]+vlxei32.v[ ]+v4,\(a0\),v12,v0.t
  3880. +[ ]+[0-9a-f]+:[ ]+0ec56227[ ]+vsxei32.v[ ]+v4,\(a0\),v12
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  3886. +[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+vlxei64.v[ ]+v4,\(a0\),v12
  3887. +[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+vlxei64.v[ ]+v4,\(a0\),v12
  3888. +[ ]+[0-9a-f]+:[ ]+0cc57207[ ]+vlxei64.v[ ]+v4,\(a0\),v12,v0.t
  3889. +[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsxei64.v[ ]+v4,\(a0\),v12
  3890. +[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+vsxei64.v[ ]+v4,\(a0\),v12
  3891. +[ ]+[0-9a-f]+:[ ]+0cc57227[ ]+vsxei64.v[ ]+v4,\(a0\),v12,v0.t
  3892. +[ ]+[0-9a-f]+:[ ]+06c57227[ ]+vsuxei64.v[ ]+v4,\(a0\),v12
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  3896. +[ ]+[0-9a-f]+:[ ]+1ec50207[ ]+vlxei128.v[ ]+v4,\(a0\),v12
  3897. +[ ]+[0-9a-f]+:[ ]+1cc50207[ ]+vlxei128.v[ ]+v4,\(a0\),v12,v0.t
  3898. +[ ]+[0-9a-f]+:[ ]+1ec50227[ ]+vsxei128.v[ ]+v4,\(a0\),v12
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  3900. +[ ]+[0-9a-f]+:[ ]+1cc50227[ ]+vsxei128.v[ ]+v4,\(a0\),v12,v0.t
  3901. +[ ]+[0-9a-f]+:[ ]+16c50227[ ]+vsuxei128.v[ ]+v4,\(a0\),v12
  3902. +[ ]+[0-9a-f]+:[ ]+16c50227[ ]+vsuxei128.v[ ]+v4,\(a0\),v12
  3903. +[ ]+[0-9a-f]+:[ ]+14c50227[ ]+vsuxei128.v[ ]+v4,\(a0\),v12,v0.t
  3904. +[ ]+[0-9a-f]+:[ ]+1ec55207[ ]+vlxei256.v[ ]+v4,\(a0\),v12
  3905. +[ ]+[0-9a-f]+:[ ]+1ec55207[ ]+vlxei256.v[ ]+v4,\(a0\),v12
  3906. +[ ]+[0-9a-f]+:[ ]+1cc55207[ ]+vlxei256.v[ ]+v4,\(a0\),v12,v0.t
  3907. +[ ]+[0-9a-f]+:[ ]+1ec55227[ ]+vsxei256.v[ ]+v4,\(a0\),v12
  3908. +[ ]+[0-9a-f]+:[ ]+1ec55227[ ]+vsxei256.v[ ]+v4,\(a0\),v12
  3909. +[ ]+[0-9a-f]+:[ ]+1cc55227[ ]+vsxei256.v[ ]+v4,\(a0\),v12,v0.t
  3910. +[ ]+[0-9a-f]+:[ ]+16c55227[ ]+vsuxei256.v[ ]+v4,\(a0\),v12
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  5371. +[ ]+[0-9a-f]+:[ ]+8685f22f[ ]+vamominei64.v[ ]+v4,\(a1\),v8,v4
  5372. +[ ]+[0-9a-f]+:[ ]+8285f22f[ ]+vamominei64.v[ ]+zero,\(a1\),v8,v4
  5373. +[ ]+[0-9a-f]+:[ ]+8485f22f[ ]+vamominei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5374. +[ ]+[0-9a-f]+:[ ]+8085f22f[ ]+vamominei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5375. +[ ]+[0-9a-f]+:[ ]+a685f22f[ ]+vamomaxei64.v[ ]+v4,\(a1\),v8,v4
  5376. +[ ]+[0-9a-f]+:[ ]+a285f22f[ ]+vamomaxei64.v[ ]+zero,\(a1\),v8,v4
  5377. +[ ]+[0-9a-f]+:[ ]+a485f22f[ ]+vamomaxei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5378. +[ ]+[0-9a-f]+:[ ]+a085f22f[ ]+vamomaxei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5379. +[ ]+[0-9a-f]+:[ ]+c685f22f[ ]+vamominuei64.v[ ]+v4,\(a1\),v8,v4
  5380. +[ ]+[0-9a-f]+:[ ]+c285f22f[ ]+vamominuei64.v[ ]+zero,\(a1\),v8,v4
  5381. +[ ]+[0-9a-f]+:[ ]+c485f22f[ ]+vamominuei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5382. +[ ]+[0-9a-f]+:[ ]+c085f22f[ ]+vamominuei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5383. +[ ]+[0-9a-f]+:[ ]+e685f22f[ ]+vamomaxuei64.v[ ]+v4,\(a1\),v8,v4
  5384. +[ ]+[0-9a-f]+:[ ]+e285f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4
  5385. +[ ]+[0-9a-f]+:[ ]+e485f22f[ ]+vamomaxuei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5386. +[ ]+[0-9a-f]+:[ ]+e085f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5387. +[ ]+[0-9a-f]+:[ ]+0685f22f[ ]+vamoaddei64.v[ ]+v4,\(a1\),v8,v4
  5388. +[ ]+[0-9a-f]+:[ ]+0285f22f[ ]+vamoaddei64.v[ ]+zero,\(a1\),v8,v4
  5389. +[ ]+[0-9a-f]+:[ ]+0485f22f[ ]+vamoaddei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5390. +[ ]+[0-9a-f]+:[ ]+0085f22f[ ]+vamoaddei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5391. +[ ]+[0-9a-f]+:[ ]+0e85f22f[ ]+vamoswapei64.v[ ]+v4,\(a1\),v8,v4
  5392. +[ ]+[0-9a-f]+:[ ]+0a85f22f[ ]+vamoswapei64.v[ ]+zero,\(a1\),v8,v4
  5393. +[ ]+[0-9a-f]+:[ ]+0c85f22f[ ]+vamoswapei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5394. +[ ]+[0-9a-f]+:[ ]+0885f22f[ ]+vamoswapei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5395. +[ ]+[0-9a-f]+:[ ]+2685f22f[ ]+vamoxorei64.v[ ]+v4,\(a1\),v8,v4
  5396. +[ ]+[0-9a-f]+:[ ]+2285f22f[ ]+vamoxorei64.v[ ]+zero,\(a1\),v8,v4
  5397. +[ ]+[0-9a-f]+:[ ]+2485f22f[ ]+vamoxorei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5398. +[ ]+[0-9a-f]+:[ ]+2085f22f[ ]+vamoxorei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5399. +[ ]+[0-9a-f]+:[ ]+6685f22f[ ]+vamoandei64.v[ ]+v4,\(a1\),v8,v4
  5400. +[ ]+[0-9a-f]+:[ ]+6285f22f[ ]+vamoandei64.v[ ]+zero,\(a1\),v8,v4
  5401. +[ ]+[0-9a-f]+:[ ]+6485f22f[ ]+vamoandei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5402. +[ ]+[0-9a-f]+:[ ]+6085f22f[ ]+vamoandei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5403. +[ ]+[0-9a-f]+:[ ]+4685f22f[ ]+vamoorei64.v[ ]+v4,\(a1\),v8,v4
  5404. +[ ]+[0-9a-f]+:[ ]+4285f22f[ ]+vamoorei64.v[ ]+zero,\(a1\),v8,v4
  5405. +[ ]+[0-9a-f]+:[ ]+4485f22f[ ]+vamoorei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5406. +[ ]+[0-9a-f]+:[ ]+4085f22f[ ]+vamoorei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5407. +[ ]+[0-9a-f]+:[ ]+8685f22f[ ]+vamominei64.v[ ]+v4,\(a1\),v8,v4
  5408. +[ ]+[0-9a-f]+:[ ]+8285f22f[ ]+vamominei64.v[ ]+zero,\(a1\),v8,v4
  5409. +[ ]+[0-9a-f]+:[ ]+8485f22f[ ]+vamominei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5410. +[ ]+[0-9a-f]+:[ ]+8085f22f[ ]+vamominei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5411. +[ ]+[0-9a-f]+:[ ]+a685f22f[ ]+vamomaxei64.v[ ]+v4,\(a1\),v8,v4
  5412. +[ ]+[0-9a-f]+:[ ]+a285f22f[ ]+vamomaxei64.v[ ]+zero,\(a1\),v8,v4
  5413. +[ ]+[0-9a-f]+:[ ]+a485f22f[ ]+vamomaxei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5414. +[ ]+[0-9a-f]+:[ ]+a085f22f[ ]+vamomaxei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5415. +[ ]+[0-9a-f]+:[ ]+c685f22f[ ]+vamominuei64.v[ ]+v4,\(a1\),v8,v4
  5416. +[ ]+[0-9a-f]+:[ ]+c285f22f[ ]+vamominuei64.v[ ]+zero,\(a1\),v8,v4
  5417. +[ ]+[0-9a-f]+:[ ]+c485f22f[ ]+vamominuei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5418. +[ ]+[0-9a-f]+:[ ]+c085f22f[ ]+vamominuei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5419. +[ ]+[0-9a-f]+:[ ]+e685f22f[ ]+vamomaxuei64.v[ ]+v4,\(a1\),v8,v4
  5420. +[ ]+[0-9a-f]+:[ ]+e285f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4
  5421. +[ ]+[0-9a-f]+:[ ]+e485f22f[ ]+vamomaxuei64.v[ ]+v4,\(a1\),v8,v4,v0.t
  5422. +[ ]+[0-9a-f]+:[ ]+e085f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4,v0.t
  5423. +[ ]+[0-9a-f]+:[ ]+02860257[ ]+vadd.vv[ ]+v4,v8,v12
  5424. +[ ]+[0-9a-f]+:[ ]+0285c257[ ]+vadd.vx[ ]+v4,v8,a1
  5425. +[ ]+[0-9a-f]+:[ ]+0287b257[ ]+vadd.vi[ ]+v4,v8,15
  5426. +[ ]+[0-9a-f]+:[ ]+02883257[ ]+vadd.vi[ ]+v4,v8,-16
  5427. +[ ]+[0-9a-f]+:[ ]+00860257[ ]+vadd.vv[ ]+v4,v8,v12,v0.t
  5428. +[ ]+[0-9a-f]+:[ ]+0085c257[ ]+vadd.vx[ ]+v4,v8,a1,v0.t
  5429. +[ ]+[0-9a-f]+:[ ]+0087b257[ ]+vadd.vi[ ]+v4,v8,15,v0.t
  5430. +[ ]+[0-9a-f]+:[ ]+00883257[ ]+vadd.vi[ ]+v4,v8,-16,v0.t
  5431. +[ ]+[0-9a-f]+:[ ]+0a860257[ ]+vsub.vv[ ]+v4,v8,v12
  5432. +[ ]+[0-9a-f]+:[ ]+0a85c257[ ]+vsub.vx[ ]+v4,v8,a1
  5433. +[ ]+[0-9a-f]+:[ ]+0e85c257[ ]+vrsub.vx[ ]+v4,v8,a1
  5434. +[ ]+[0-9a-f]+:[ ]+0e87b257[ ]+vrsub.vi[ ]+v4,v8,15
  5435. +[ ]+[0-9a-f]+:[ ]+0e883257[ ]+vrsub.vi[ ]+v4,v8,-16
  5436. +[ ]+[0-9a-f]+:[ ]+08860257[ ]+vsub.vv[ ]+v4,v8,v12,v0.t
  5437. +[ ]+[0-9a-f]+:[ ]+0885c257[ ]+vsub.vx[ ]+v4,v8,a1,v0.t
  5438. +[ ]+[0-9a-f]+:[ ]+0c85c257[ ]+vrsub.vx[ ]+v4,v8,a1,v0.t
  5439. +[ ]+[0-9a-f]+:[ ]+0c87b257[ ]+vrsub.vi[ ]+v4,v8,15,v0.t
  5440. +[ ]+[0-9a-f]+:[ ]+0c883257[ ]+vrsub.vi[ ]+v4,v8,-16,v0.t
  5441. +[ ]+[0-9a-f]+:[ ]+c6806257[ ]+vwcvt.x.x.v[ ]+v4,v8
  5442. +[ ]+[0-9a-f]+:[ ]+c2806257[ ]+vwcvtu.x.x.v[ ]+v4,v8
  5443. +[ ]+[0-9a-f]+:[ ]+c4806257[ ]+vwcvt.x.x.v[ ]+v4,v8,v0.t
  5444. +[ ]+[0-9a-f]+:[ ]+c0806257[ ]+vwcvtu.x.x.v[ ]+v4,v8,v0.t
  5445. +[ ]+[0-9a-f]+:[ ]+c2862257[ ]+vwaddu.vv[ ]+v4,v8,v12
  5446. +[ ]+[0-9a-f]+:[ ]+c285e257[ ]+vwaddu.vx[ ]+v4,v8,a1
  5447. +[ ]+[0-9a-f]+:[ ]+c0862257[ ]+vwaddu.vv[ ]+v4,v8,v12,v0.t
  5448. +[ ]+[0-9a-f]+:[ ]+c085e257[ ]+vwaddu.vx[ ]+v4,v8,a1,v0.t
  5449. +[ ]+[0-9a-f]+:[ ]+ca862257[ ]+vwsubu.vv[ ]+v4,v8,v12
  5450. +[ ]+[0-9a-f]+:[ ]+ca85e257[ ]+vwsubu.vx[ ]+v4,v8,a1
  5451. +[ ]+[0-9a-f]+:[ ]+c8862257[ ]+vwsubu.vv[ ]+v4,v8,v12,v0.t
  5452. +[ ]+[0-9a-f]+:[ ]+c885e257[ ]+vwsubu.vx[ ]+v4,v8,a1,v0.t
  5453. +[ ]+[0-9a-f]+:[ ]+c6862257[ ]+vwadd.vv[ ]+v4,v8,v12
  5454. +[ ]+[0-9a-f]+:[ ]+c685e257[ ]+vwadd.vx[ ]+v4,v8,a1
  5455. +[ ]+[0-9a-f]+:[ ]+c4862257[ ]+vwadd.vv[ ]+v4,v8,v12,v0.t
  5456. +[ ]+[0-9a-f]+:[ ]+c485e257[ ]+vwadd.vx[ ]+v4,v8,a1,v0.t
  5457. +[ ]+[0-9a-f]+:[ ]+ce862257[ ]+vwsub.vv[ ]+v4,v8,v12
  5458. +[ ]+[0-9a-f]+:[ ]+ce85e257[ ]+vwsub.vx[ ]+v4,v8,a1
  5459. +[ ]+[0-9a-f]+:[ ]+cc862257[ ]+vwsub.vv[ ]+v4,v8,v12,v0.t
  5460. +[ ]+[0-9a-f]+:[ ]+cc85e257[ ]+vwsub.vx[ ]+v4,v8,a1,v0.t
  5461. +[ ]+[0-9a-f]+:[ ]+d2862257[ ]+vwaddu.wv[ ]+v4,v8,v12
  5462. +[ ]+[0-9a-f]+:[ ]+d285e257[ ]+vwaddu.wx[ ]+v4,v8,a1
  5463. +[ ]+[0-9a-f]+:[ ]+d0862257[ ]+vwaddu.wv[ ]+v4,v8,v12,v0.t
  5464. +[ ]+[0-9a-f]+:[ ]+d085e257[ ]+vwaddu.wx[ ]+v4,v8,a1,v0.t
  5465. +[ ]+[0-9a-f]+:[ ]+da862257[ ]+vwsubu.wv[ ]+v4,v8,v12
  5466. +[ ]+[0-9a-f]+:[ ]+da85e257[ ]+vwsubu.wx[ ]+v4,v8,a1
  5467. +[ ]+[0-9a-f]+:[ ]+d8862257[ ]+vwsubu.wv[ ]+v4,v8,v12,v0.t
  5468. +[ ]+[0-9a-f]+:[ ]+d885e257[ ]+vwsubu.wx[ ]+v4,v8,a1,v0.t
  5469. +[ ]+[0-9a-f]+:[ ]+d6862257[ ]+vwadd.wv[ ]+v4,v8,v12
  5470. +[ ]+[0-9a-f]+:[ ]+d685e257[ ]+vwadd.wx[ ]+v4,v8,a1
  5471. +[ ]+[0-9a-f]+:[ ]+d4862257[ ]+vwadd.wv[ ]+v4,v8,v12,v0.t
  5472. +[ ]+[0-9a-f]+:[ ]+d485e257[ ]+vwadd.wx[ ]+v4,v8,a1,v0.t
  5473. +[ ]+[0-9a-f]+:[ ]+de862257[ ]+vwsub.wv[ ]+v4,v8,v12
  5474. +[ ]+[0-9a-f]+:[ ]+de85e257[ ]+vwsub.wx[ ]+v4,v8,a1
  5475. +[ ]+[0-9a-f]+:[ ]+dc862257[ ]+vwsub.wv[ ]+v4,v8,v12,v0.t
  5476. +[ ]+[0-9a-f]+:[ ]+dc85e257[ ]+vwsub.wx[ ]+v4,v8,a1,v0.t
  5477. +[ ]+[0-9a-f]+:[ ]+4a832257[ ]+vzext.vf2[ ]+v4,v8
  5478. +[ ]+[0-9a-f]+:[ ]+48832257[ ]+vzext.vf2[ ]+v4,v8,v0.t
  5479. +[ ]+[0-9a-f]+:[ ]+4a83a257[ ]+vsext.vf2[ ]+v4,v8
  5480. +[ ]+[0-9a-f]+:[ ]+4883a257[ ]+vsext.vf2[ ]+v4,v8,v0.t
  5481. +[ ]+[0-9a-f]+:[ ]+4a822257[ ]+vzext.vf4[ ]+v4,v8
  5482. +[ ]+[0-9a-f]+:[ ]+48822257[ ]+vzext.vf4[ ]+v4,v8,v0.t
  5483. +[ ]+[0-9a-f]+:[ ]+4a82a257[ ]+vsext.vf4[ ]+v4,v8
  5484. +[ ]+[0-9a-f]+:[ ]+4882a257[ ]+vsext.vf4[ ]+v4,v8,v0.t
  5485. +[ ]+[0-9a-f]+:[ ]+4a812257[ ]+vzext.vf8[ ]+v4,v8
  5486. +[ ]+[0-9a-f]+:[ ]+48812257[ ]+vzext.vf8[ ]+v4,v8,v0.t
  5487. +[ ]+[0-9a-f]+:[ ]+4a81a257[ ]+vsext.vf8[ ]+v4,v8
  5488. +[ ]+[0-9a-f]+:[ ]+4881a257[ ]+vsext.vf8[ ]+v4,v8,v0.t
  5489. +[ ]+[0-9a-f]+:[ ]+40860257[ ]+vadc.vvm[ ]+v4,v8,v12,v0
  5490. +[ ]+[0-9a-f]+:[ ]+4085c257[ ]+vadc.vxm[ ]+v4,v8,a1,v0
  5491. +[ ]+[0-9a-f]+:[ ]+4087b257[ ]+vadc.vim[ ]+v4,v8,15,v0
  5492. +[ ]+[0-9a-f]+:[ ]+40883257[ ]+vadc.vim[ ]+v4,v8,-16,v0
  5493. +[ ]+[0-9a-f]+:[ ]+44860257[ ]+vmadc.vvm[ ]+v4,v8,v12,v0
  5494. +[ ]+[0-9a-f]+:[ ]+4485c257[ ]+vmadc.vxm[ ]+v4,v8,a1,v0
  5495. +[ ]+[0-9a-f]+:[ ]+4487b257[ ]+vmadc.vim[ ]+v4,v8,15,v0
  5496. +[ ]+[0-9a-f]+:[ ]+44883257[ ]+vmadc.vim[ ]+v4,v8,-16,v0
  5497. +[ ]+[0-9a-f]+:[ ]+46860257[ ]+vmadc.vv[ ]+v4,v8,v12
  5498. +[ ]+[0-9a-f]+:[ ]+4685c257[ ]+vmadc.vx[ ]+v4,v8,a1
  5499. +[ ]+[0-9a-f]+:[ ]+4687b257[ ]+vmadc.vi[ ]+v4,v8,15
  5500. +[ ]+[0-9a-f]+:[ ]+46883257[ ]+vmadc.vi[ ]+v4,v8,-16
  5501. +[ ]+[0-9a-f]+:[ ]+48860257[ ]+vsbc.vvm[ ]+v4,v8,v12,v0
  5502. +[ ]+[0-9a-f]+:[ ]+4885c257[ ]+vsbc.vxm[ ]+v4,v8,a1,v0
  5503. +[ ]+[0-9a-f]+:[ ]+4c860257[ ]+vmsbc.vvm[ ]+v4,v8,v12,v0
  5504. +[ ]+[0-9a-f]+:[ ]+4c85c257[ ]+vmsbc.vxm[ ]+v4,v8,a1,v0
  5505. +[ ]+[0-9a-f]+:[ ]+4e860257[ ]+vmsbc.vv[ ]+v4,v8,v12
  5506. +[ ]+[0-9a-f]+:[ ]+4e85c257[ ]+vmsbc.vx[ ]+v4,v8,a1
  5507. +[ ]+[0-9a-f]+:[ ]+2e8fb257[ ]+vnot.v[ ]+v4,v8
  5508. +[ ]+[0-9a-f]+:[ ]+2c8fb257[ ]+vnot.v[ ]+v4,v8,v0.t
  5509. +[ ]+[0-9a-f]+:[ ]+26860257[ ]+vand.vv[ ]+v4,v8,v12
  5510. +[ ]+[0-9a-f]+:[ ]+2685c257[ ]+vand.vx[ ]+v4,v8,a1
  5511. +[ ]+[0-9a-f]+:[ ]+2687b257[ ]+vand.vi[ ]+v4,v8,15
  5512. +[ ]+[0-9a-f]+:[ ]+26883257[ ]+vand.vi[ ]+v4,v8,-16
  5513. +[ ]+[0-9a-f]+:[ ]+24860257[ ]+vand.vv[ ]+v4,v8,v12,v0.t
  5514. +[ ]+[0-9a-f]+:[ ]+2485c257[ ]+vand.vx[ ]+v4,v8,a1,v0.t
  5515. +[ ]+[0-9a-f]+:[ ]+2487b257[ ]+vand.vi[ ]+v4,v8,15,v0.t
  5516. +[ ]+[0-9a-f]+:[ ]+24883257[ ]+vand.vi[ ]+v4,v8,-16,v0.t
  5517. +[ ]+[0-9a-f]+:[ ]+2a860257[ ]+vor.vv[ ]+v4,v8,v12
  5518. +[ ]+[0-9a-f]+:[ ]+2a85c257[ ]+vor.vx[ ]+v4,v8,a1
  5519. +[ ]+[0-9a-f]+:[ ]+2a87b257[ ]+vor.vi[ ]+v4,v8,15
  5520. +[ ]+[0-9a-f]+:[ ]+2a883257[ ]+vor.vi[ ]+v4,v8,-16
  5521. +[ ]+[0-9a-f]+:[ ]+28860257[ ]+vor.vv[ ]+v4,v8,v12,v0.t
  5522. +[ ]+[0-9a-f]+:[ ]+2885c257[ ]+vor.vx[ ]+v4,v8,a1,v0.t
  5523. +[ ]+[0-9a-f]+:[ ]+2887b257[ ]+vor.vi[ ]+v4,v8,15,v0.t
  5524. +[ ]+[0-9a-f]+:[ ]+28883257[ ]+vor.vi[ ]+v4,v8,-16,v0.t
  5525. +[ ]+[0-9a-f]+:[ ]+2e860257[ ]+vxor.vv[ ]+v4,v8,v12
  5526. +[ ]+[0-9a-f]+:[ ]+2e85c257[ ]+vxor.vx[ ]+v4,v8,a1
  5527. +[ ]+[0-9a-f]+:[ ]+2e87b257[ ]+vxor.vi[ ]+v4,v8,15
  5528. +[ ]+[0-9a-f]+:[ ]+2e883257[ ]+vxor.vi[ ]+v4,v8,-16
  5529. +[ ]+[0-9a-f]+:[ ]+2c860257[ ]+vxor.vv[ ]+v4,v8,v12,v0.t
  5530. +[ ]+[0-9a-f]+:[ ]+2c85c257[ ]+vxor.vx[ ]+v4,v8,a1,v0.t
  5531. +[ ]+[0-9a-f]+:[ ]+2c87b257[ ]+vxor.vi[ ]+v4,v8,15,v0.t
  5532. +[ ]+[0-9a-f]+:[ ]+2c883257[ ]+vxor.vi[ ]+v4,v8,-16,v0.t
  5533. +[ ]+[0-9a-f]+:[ ]+96860257[ ]+vsll.vv[ ]+v4,v8,v12
  5534. +[ ]+[0-9a-f]+:[ ]+9685c257[ ]+vsll.vx[ ]+v4,v8,a1
  5535. +[ ]+[0-9a-f]+:[ ]+9680b257[ ]+vsll.vi[ ]+v4,v8,1
  5536. +[ ]+[0-9a-f]+:[ ]+968fb257[ ]+vsll.vi[ ]+v4,v8,31
  5537. +[ ]+[0-9a-f]+:[ ]+94860257[ ]+vsll.vv[ ]+v4,v8,v12,v0.t
  5538. +[ ]+[0-9a-f]+:[ ]+9485c257[ ]+vsll.vx[ ]+v4,v8,a1,v0.t
  5539. +[ ]+[0-9a-f]+:[ ]+9480b257[ ]+vsll.vi[ ]+v4,v8,1,v0.t
  5540. +[ ]+[0-9a-f]+:[ ]+948fb257[ ]+vsll.vi[ ]+v4,v8,31,v0.t
  5541. +[ ]+[0-9a-f]+:[ ]+a2860257[ ]+vsrl.vv[ ]+v4,v8,v12
  5542. +[ ]+[0-9a-f]+:[ ]+a285c257[ ]+vsrl.vx[ ]+v4,v8,a1
  5543. +[ ]+[0-9a-f]+:[ ]+a280b257[ ]+vsrl.vi[ ]+v4,v8,1
  5544. +[ ]+[0-9a-f]+:[ ]+a28fb257[ ]+vsrl.vi[ ]+v4,v8,31
  5545. +[ ]+[0-9a-f]+:[ ]+a0860257[ ]+vsrl.vv[ ]+v4,v8,v12,v0.t
  5546. +[ ]+[0-9a-f]+:[ ]+a085c257[ ]+vsrl.vx[ ]+v4,v8,a1,v0.t
  5547. +[ ]+[0-9a-f]+:[ ]+a080b257[ ]+vsrl.vi[ ]+v4,v8,1,v0.t
  5548. +[ ]+[0-9a-f]+:[ ]+a08fb257[ ]+vsrl.vi[ ]+v4,v8,31,v0.t
  5549. +[ ]+[0-9a-f]+:[ ]+a6860257[ ]+vsra.vv[ ]+v4,v8,v12
  5550. +[ ]+[0-9a-f]+:[ ]+a685c257[ ]+vsra.vx[ ]+v4,v8,a1
  5551. +[ ]+[0-9a-f]+:[ ]+a680b257[ ]+vsra.vi[ ]+v4,v8,1
  5552. +[ ]+[0-9a-f]+:[ ]+a68fb257[ ]+vsra.vi[ ]+v4,v8,31
  5553. +[ ]+[0-9a-f]+:[ ]+a4860257[ ]+vsra.vv[ ]+v4,v8,v12,v0.t
  5554. +[ ]+[0-9a-f]+:[ ]+a485c257[ ]+vsra.vx[ ]+v4,v8,a1,v0.t
  5555. +[ ]+[0-9a-f]+:[ ]+a480b257[ ]+vsra.vi[ ]+v4,v8,1,v0.t
  5556. +[ ]+[0-9a-f]+:[ ]+a48fb257[ ]+vsra.vi[ ]+v4,v8,31,v0.t
  5557. +[ ]+[0-9a-f]+:[ ]+b2860257[ ]+vnsrl.wv[ ]+v4,v8,v12
  5558. +[ ]+[0-9a-f]+:[ ]+b285c257[ ]+vnsrl.wx[ ]+v4,v8,a1
  5559. +[ ]+[0-9a-f]+:[ ]+b280b257[ ]+vnsrl.wi[ ]+v4,v8,1
  5560. +[ ]+[0-9a-f]+:[ ]+b28fb257[ ]+vnsrl.wi[ ]+v4,v8,31
  5561. +[ ]+[0-9a-f]+:[ ]+b0860257[ ]+vnsrl.wv[ ]+v4,v8,v12,v0.t
  5562. +[ ]+[0-9a-f]+:[ ]+b085c257[ ]+vnsrl.wx[ ]+v4,v8,a1,v0.t
  5563. +[ ]+[0-9a-f]+:[ ]+b080b257[ ]+vnsrl.wi[ ]+v4,v8,1,v0.t
  5564. +[ ]+[0-9a-f]+:[ ]+b08fb257[ ]+vnsrl.wi[ ]+v4,v8,31,v0.t
  5565. +[ ]+[0-9a-f]+:[ ]+b6860257[ ]+vnsra.wv[ ]+v4,v8,v12
  5566. +[ ]+[0-9a-f]+:[ ]+b685c257[ ]+vnsra.wx[ ]+v4,v8,a1
  5567. +[ ]+[0-9a-f]+:[ ]+b680b257[ ]+vnsra.wi[ ]+v4,v8,1
  5568. +[ ]+[0-9a-f]+:[ ]+b68fb257[ ]+vnsra.wi[ ]+v4,v8,31
  5569. +[ ]+[0-9a-f]+:[ ]+b4860257[ ]+vnsra.wv[ ]+v4,v8,v12,v0.t
  5570. +[ ]+[0-9a-f]+:[ ]+b485c257[ ]+vnsra.wx[ ]+v4,v8,a1,v0.t
  5571. +[ ]+[0-9a-f]+:[ ]+b480b257[ ]+vnsra.wi[ ]+v4,v8,1,v0.t
  5572. +[ ]+[0-9a-f]+:[ ]+b48fb257[ ]+vnsra.wi[ ]+v4,v8,31,v0.t
  5573. +[ ]+[0-9a-f]+:[ ]+6ec40257[ ]+vmslt.vv[ ]+v4,v12,v8
  5574. +[ ]+[0-9a-f]+:[ ]+6ac40257[ ]+vmsltu.vv[ ]+v4,v12,v8
  5575. +[ ]+[0-9a-f]+:[ ]+76c40257[ ]+vmsle.vv[ ]+v4,v12,v8
  5576. +[ ]+[0-9a-f]+:[ ]+72c40257[ ]+vmsleu.vv[ ]+v4,v12,v8
  5577. +[ ]+[0-9a-f]+:[ ]+6cc40257[ ]+vmslt.vv[ ]+v4,v12,v8,v0.t
  5578. +[ ]+[0-9a-f]+:[ ]+68c40257[ ]+vmsltu.vv[ ]+v4,v12,v8,v0.t
  5579. +[ ]+[0-9a-f]+:[ ]+74c40257[ ]+vmsle.vv[ ]+v4,v12,v8,v0.t
  5580. +[ ]+[0-9a-f]+:[ ]+70c40257[ ]+vmsleu.vv[ ]+v4,v12,v8,v0.t
  5581. +[ ]+[0-9a-f]+:[ ]+7687b257[ ]+vmsle.vi[ ]+v4,v8,15
  5582. +[ ]+[0-9a-f]+:[ ]+76883257[ ]+vmsle.vi[ ]+v4,v8,-16
  5583. +[ ]+[0-9a-f]+:[ ]+7287b257[ ]+vmsleu.vi[ ]+v4,v8,15
  5584. +[ ]+[0-9a-f]+:[ ]+72883257[ ]+vmsleu.vi[ ]+v4,v8,-16
  5585. +[ ]+[0-9a-f]+:[ ]+7e87b257[ ]+vmsgt.vi[ ]+v4,v8,15
  5586. +[ ]+[0-9a-f]+:[ ]+7e883257[ ]+vmsgt.vi[ ]+v4,v8,-16
  5587. +[ ]+[0-9a-f]+:[ ]+7a87b257[ ]+vmsgtu.vi[ ]+v4,v8,15
  5588. +[ ]+[0-9a-f]+:[ ]+7a883257[ ]+vmsgtu.vi[ ]+v4,v8,-16
  5589. +[ ]+[0-9a-f]+:[ ]+7487b257[ ]+vmsle.vi[ ]+v4,v8,15,v0.t
  5590. +[ ]+[0-9a-f]+:[ ]+74883257[ ]+vmsle.vi[ ]+v4,v8,-16,v0.t
  5591. +[ ]+[0-9a-f]+:[ ]+7087b257[ ]+vmsleu.vi[ ]+v4,v8,15,v0.t
  5592. +[ ]+[0-9a-f]+:[ ]+70883257[ ]+vmsleu.vi[ ]+v4,v8,-16,v0.t
  5593. +[ ]+[0-9a-f]+:[ ]+7c87b257[ ]+vmsgt.vi[ ]+v4,v8,15,v0.t
  5594. +[ ]+[0-9a-f]+:[ ]+7c883257[ ]+vmsgt.vi[ ]+v4,v8,-16,v0.t
  5595. +[ ]+[0-9a-f]+:[ ]+7887b257[ ]+vmsgtu.vi[ ]+v4,v8,15,v0.t
  5596. +[ ]+[0-9a-f]+:[ ]+78883257[ ]+vmsgtu.vi[ ]+v4,v8,-16,v0.t
  5597. +[ ]+[0-9a-f]+:[ ]+62860257[ ]+vmseq.vv[ ]+v4,v8,v12
  5598. +[ ]+[0-9a-f]+:[ ]+6285c257[ ]+vmseq.vx[ ]+v4,v8,a1
  5599. +[ ]+[0-9a-f]+:[ ]+6287b257[ ]+vmseq.vi[ ]+v4,v8,15
  5600. +[ ]+[0-9a-f]+:[ ]+62883257[ ]+vmseq.vi[ ]+v4,v8,-16
  5601. +[ ]+[0-9a-f]+:[ ]+60860257[ ]+vmseq.vv[ ]+v4,v8,v12,v0.t
  5602. +[ ]+[0-9a-f]+:[ ]+6085c257[ ]+vmseq.vx[ ]+v4,v8,a1,v0.t
  5603. +[ ]+[0-9a-f]+:[ ]+6087b257[ ]+vmseq.vi[ ]+v4,v8,15,v0.t
  5604. +[ ]+[0-9a-f]+:[ ]+60883257[ ]+vmseq.vi[ ]+v4,v8,-16,v0.t
  5605. +[ ]+[0-9a-f]+:[ ]+66860257[ ]+vmsne.vv[ ]+v4,v8,v12
  5606. +[ ]+[0-9a-f]+:[ ]+6685c257[ ]+vmsne.vx[ ]+v4,v8,a1
  5607. +[ ]+[0-9a-f]+:[ ]+6687b257[ ]+vmsne.vi[ ]+v4,v8,15
  5608. +[ ]+[0-9a-f]+:[ ]+66883257[ ]+vmsne.vi[ ]+v4,v8,-16
  5609. +[ ]+[0-9a-f]+:[ ]+64860257[ ]+vmsne.vv[ ]+v4,v8,v12,v0.t
  5610. +[ ]+[0-9a-f]+:[ ]+6485c257[ ]+vmsne.vx[ ]+v4,v8,a1,v0.t
  5611. +[ ]+[0-9a-f]+:[ ]+6487b257[ ]+vmsne.vi[ ]+v4,v8,15,v0.t
  5612. +[ ]+[0-9a-f]+:[ ]+64883257[ ]+vmsne.vi[ ]+v4,v8,-16,v0.t
  5613. +[ ]+[0-9a-f]+:[ ]+6a860257[ ]+vmsltu.vv[ ]+v4,v8,v12
  5614. +[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1
  5615. +[ ]+[0-9a-f]+:[ ]+68860257[ ]+vmsltu.vv[ ]+v4,v8,v12,v0.t
  5616. +[ ]+[0-9a-f]+:[ ]+6885c257[ ]+vmsltu.vx[ ]+v4,v8,a1,v0.t
  5617. +[ ]+[0-9a-f]+:[ ]+6e860257[ ]+vmslt.vv[ ]+v4,v8,v12
  5618. +[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+vmslt.vx[ ]+v4,v8,a1
  5619. +[ ]+[0-9a-f]+:[ ]+6c860257[ ]+vmslt.vv[ ]+v4,v8,v12,v0.t
  5620. +[ ]+[0-9a-f]+:[ ]+6c85c257[ ]+vmslt.vx[ ]+v4,v8,a1,v0.t
  5621. +[ ]+[0-9a-f]+:[ ]+72860257[ ]+vmsleu.vv[ ]+v4,v8,v12
  5622. +[ ]+[0-9a-f]+:[ ]+7285c257[ ]+vmsleu.vx[ ]+v4,v8,a1
  5623. +[ ]+[0-9a-f]+:[ ]+7287b257[ ]+vmsleu.vi[ ]+v4,v8,15
  5624. +[ ]+[0-9a-f]+:[ ]+72883257[ ]+vmsleu.vi[ ]+v4,v8,-16
  5625. +[ ]+[0-9a-f]+:[ ]+70860257[ ]+vmsleu.vv[ ]+v4,v8,v12,v0.t
  5626. +[ ]+[0-9a-f]+:[ ]+7085c257[ ]+vmsleu.vx[ ]+v4,v8,a1,v0.t
  5627. +[ ]+[0-9a-f]+:[ ]+7087b257[ ]+vmsleu.vi[ ]+v4,v8,15,v0.t
  5628. +[ ]+[0-9a-f]+:[ ]+70883257[ ]+vmsleu.vi[ ]+v4,v8,-16,v0.t
  5629. +[ ]+[0-9a-f]+:[ ]+76860257[ ]+vmsle.vv[ ]+v4,v8,v12
  5630. +[ ]+[0-9a-f]+:[ ]+7685c257[ ]+vmsle.vx[ ]+v4,v8,a1
  5631. +[ ]+[0-9a-f]+:[ ]+7687b257[ ]+vmsle.vi[ ]+v4,v8,15
  5632. +[ ]+[0-9a-f]+:[ ]+76883257[ ]+vmsle.vi[ ]+v4,v8,-16
  5633. +[ ]+[0-9a-f]+:[ ]+74860257[ ]+vmsle.vv[ ]+v4,v8,v12,v0.t
  5634. +[ ]+[0-9a-f]+:[ ]+7485c257[ ]+vmsle.vx[ ]+v4,v8,a1,v0.t
  5635. +[ ]+[0-9a-f]+:[ ]+7487b257[ ]+vmsle.vi[ ]+v4,v8,15,v0.t
  5636. +[ ]+[0-9a-f]+:[ ]+74883257[ ]+vmsle.vi[ ]+v4,v8,-16,v0.t
  5637. +[ ]+[0-9a-f]+:[ ]+7a85c257[ ]+vmsgtu.vx[ ]+v4,v8,a1
  5638. +[ ]+[0-9a-f]+:[ ]+7a87b257[ ]+vmsgtu.vi[ ]+v4,v8,15
  5639. +[ ]+[0-9a-f]+:[ ]+7a883257[ ]+vmsgtu.vi[ ]+v4,v8,-16
  5640. +[ ]+[0-9a-f]+:[ ]+7885c257[ ]+vmsgtu.vx[ ]+v4,v8,a1,v0.t
  5641. +[ ]+[0-9a-f]+:[ ]+7887b257[ ]+vmsgtu.vi[ ]+v4,v8,15,v0.t
  5642. +[ ]+[0-9a-f]+:[ ]+78883257[ ]+vmsgtu.vi[ ]+v4,v8,-16,v0.t
  5643. +[ ]+[0-9a-f]+:[ ]+7e85c257[ ]+vmsgt.vx[ ]+v4,v8,a1
  5644. +[ ]+[0-9a-f]+:[ ]+7e87b257[ ]+vmsgt.vi[ ]+v4,v8,15
  5645. +[ ]+[0-9a-f]+:[ ]+7e883257[ ]+vmsgt.vi[ ]+v4,v8,-16
  5646. +[ ]+[0-9a-f]+:[ ]+7c85c257[ ]+vmsgt.vx[ ]+v4,v8,a1,v0.t
  5647. +[ ]+[0-9a-f]+:[ ]+7c87b257[ ]+vmsgt.vi[ ]+v4,v8,15,v0.t
  5648. +[ ]+[0-9a-f]+:[ ]+7c883257[ ]+vmsgt.vi[ ]+v4,v8,-16,v0.t
  5649. +[ ]+[0-9a-f]+:[ ]+12860257[ ]+vminu.vv[ ]+v4,v8,v12
  5650. +[ ]+[0-9a-f]+:[ ]+1285c257[ ]+vminu.vx[ ]+v4,v8,a1
  5651. +[ ]+[0-9a-f]+:[ ]+10860257[ ]+vminu.vv[ ]+v4,v8,v12,v0.t
  5652. +[ ]+[0-9a-f]+:[ ]+1085c257[ ]+vminu.vx[ ]+v4,v8,a1,v0.t
  5653. +[ ]+[0-9a-f]+:[ ]+16860257[ ]+vmin.vv[ ]+v4,v8,v12
  5654. +[ ]+[0-9a-f]+:[ ]+1685c257[ ]+vmin.vx[ ]+v4,v8,a1
  5655. +[ ]+[0-9a-f]+:[ ]+14860257[ ]+vmin.vv[ ]+v4,v8,v12,v0.t
  5656. +[ ]+[0-9a-f]+:[ ]+1485c257[ ]+vmin.vx[ ]+v4,v8,a1,v0.t
  5657. +[ ]+[0-9a-f]+:[ ]+1a860257[ ]+vmaxu.vv[ ]+v4,v8,v12
  5658. +[ ]+[0-9a-f]+:[ ]+1a85c257[ ]+vmaxu.vx[ ]+v4,v8,a1
  5659. +[ ]+[0-9a-f]+:[ ]+18860257[ ]+vmaxu.vv[ ]+v4,v8,v12,v0.t
  5660. +[ ]+[0-9a-f]+:[ ]+1885c257[ ]+vmaxu.vx[ ]+v4,v8,a1,v0.t
  5661. +[ ]+[0-9a-f]+:[ ]+1e860257[ ]+vmax.vv[ ]+v4,v8,v12
  5662. +[ ]+[0-9a-f]+:[ ]+1e85c257[ ]+vmax.vx[ ]+v4,v8,a1
  5663. +[ ]+[0-9a-f]+:[ ]+1c860257[ ]+vmax.vv[ ]+v4,v8,v12,v0.t
  5664. +[ ]+[0-9a-f]+:[ ]+1c85c257[ ]+vmax.vx[ ]+v4,v8,a1,v0.t
  5665. +[ ]+[0-9a-f]+:[ ]+96862257[ ]+vmul.vv[ ]+v4,v8,v12
  5666. +[ ]+[0-9a-f]+:[ ]+9685e257[ ]+vmul.vx[ ]+v4,v8,a1
  5667. +[ ]+[0-9a-f]+:[ ]+94862257[ ]+vmul.vv[ ]+v4,v8,v12,v0.t
  5668. +[ ]+[0-9a-f]+:[ ]+9485e257[ ]+vmul.vx[ ]+v4,v8,a1,v0.t
  5669. +[ ]+[0-9a-f]+:[ ]+9e862257[ ]+vmulh.vv[ ]+v4,v8,v12
  5670. +[ ]+[0-9a-f]+:[ ]+9e85e257[ ]+vmulh.vx[ ]+v4,v8,a1
  5671. +[ ]+[0-9a-f]+:[ ]+9c862257[ ]+vmulh.vv[ ]+v4,v8,v12,v0.t
  5672. +[ ]+[0-9a-f]+:[ ]+9c85e257[ ]+vmulh.vx[ ]+v4,v8,a1,v0.t
  5673. +[ ]+[0-9a-f]+:[ ]+92862257[ ]+vmulhu.vv[ ]+v4,v8,v12
  5674. +[ ]+[0-9a-f]+:[ ]+9285e257[ ]+vmulhu.vx[ ]+v4,v8,a1
  5675. +[ ]+[0-9a-f]+:[ ]+90862257[ ]+vmulhu.vv[ ]+v4,v8,v12,v0.t
  5676. +[ ]+[0-9a-f]+:[ ]+9085e257[ ]+vmulhu.vx[ ]+v4,v8,a1,v0.t
  5677. +[ ]+[0-9a-f]+:[ ]+9a862257[ ]+vmulhsu.vv[ ]+v4,v8,v12
  5678. +[ ]+[0-9a-f]+:[ ]+9a85e257[ ]+vmulhsu.vx[ ]+v4,v8,a1
  5679. +[ ]+[0-9a-f]+:[ ]+98862257[ ]+vmulhsu.vv[ ]+v4,v8,v12,v0.t
  5680. +[ ]+[0-9a-f]+:[ ]+9885e257[ ]+vmulhsu.vx[ ]+v4,v8,a1,v0.t
  5681. +[ ]+[0-9a-f]+:[ ]+ee862257[ ]+vwmul.vv[ ]+v4,v8,v12
  5682. +[ ]+[0-9a-f]+:[ ]+ee85e257[ ]+vwmul.vx[ ]+v4,v8,a1
  5683. +[ ]+[0-9a-f]+:[ ]+ec862257[ ]+vwmul.vv[ ]+v4,v8,v12,v0.t
  5684. +[ ]+[0-9a-f]+:[ ]+ec85e257[ ]+vwmul.vx[ ]+v4,v8,a1,v0.t
  5685. +[ ]+[0-9a-f]+:[ ]+e2862257[ ]+vwmulu.vv[ ]+v4,v8,v12
  5686. +[ ]+[0-9a-f]+:[ ]+e285e257[ ]+vwmulu.vx[ ]+v4,v8,a1
  5687. +[ ]+[0-9a-f]+:[ ]+e0862257[ ]+vwmulu.vv[ ]+v4,v8,v12,v0.t
  5688. +[ ]+[0-9a-f]+:[ ]+e085e257[ ]+vwmulu.vx[ ]+v4,v8,a1,v0.t
  5689. +[ ]+[0-9a-f]+:[ ]+ea862257[ ]+vwmulsu.vv[ ]+v4,v8,v12
  5690. +[ ]+[0-9a-f]+:[ ]+ea85e257[ ]+vwmulsu.vx[ ]+v4,v8,a1
  5691. +[ ]+[0-9a-f]+:[ ]+e8862257[ ]+vwmulsu.vv[ ]+v4,v8,v12,v0.t
  5692. +[ ]+[0-9a-f]+:[ ]+e885e257[ ]+vwmulsu.vx[ ]+v4,v8,a1,v0.t
  5693. +[ ]+[0-9a-f]+:[ ]+b6862257[ ]+vmacc.vv[ ]+v4,v12,v8
  5694. +[ ]+[0-9a-f]+:[ ]+b685e257[ ]+vmacc.vx[ ]+v4,a1,v8
  5695. +[ ]+[0-9a-f]+:[ ]+b4862257[ ]+vmacc.vv[ ]+v4,v12,v8,v0.t
  5696. +[ ]+[0-9a-f]+:[ ]+b485e257[ ]+vmacc.vx[ ]+v4,a1,v8,v0.t
  5697. +[ ]+[0-9a-f]+:[ ]+be862257[ ]+vnmsac.vv[ ]+v4,v12,v8
  5698. +[ ]+[0-9a-f]+:[ ]+be85e257[ ]+vnmsac.vx[ ]+v4,a1,v8
  5699. +[ ]+[0-9a-f]+:[ ]+bc862257[ ]+vnmsac.vv[ ]+v4,v12,v8,v0.t
  5700. +[ ]+[0-9a-f]+:[ ]+bc85e257[ ]+vnmsac.vx[ ]+v4,a1,v8,v0.t
  5701. +[ ]+[0-9a-f]+:[ ]+a6862257[ ]+vmadd.vv[ ]+v4,v12,v8
  5702. +[ ]+[0-9a-f]+:[ ]+a685e257[ ]+vmadd.vx[ ]+v4,a1,v8
  5703. +[ ]+[0-9a-f]+:[ ]+a4862257[ ]+vmadd.vv[ ]+v4,v12,v8,v0.t
  5704. +[ ]+[0-9a-f]+:[ ]+a485e257[ ]+vmadd.vx[ ]+v4,a1,v8,v0.t
  5705. +[ ]+[0-9a-f]+:[ ]+ae862257[ ]+vnmsub.vv[ ]+v4,v12,v8
  5706. +[ ]+[0-9a-f]+:[ ]+ae85e257[ ]+vnmsub.vx[ ]+v4,a1,v8
  5707. +[ ]+[0-9a-f]+:[ ]+ac862257[ ]+vnmsub.vv[ ]+v4,v12,v8,v0.t
  5708. +[ ]+[0-9a-f]+:[ ]+ac85e257[ ]+vnmsub.vx[ ]+v4,a1,v8,v0.t
  5709. +[ ]+[0-9a-f]+:[ ]+f2862257[ ]+vwmaccu.vv[ ]+v4,v12,v8
  5710. +[ ]+[0-9a-f]+:[ ]+f285e257[ ]+vwmaccu.vx[ ]+v4,a1,v8
  5711. +[ ]+[0-9a-f]+:[ ]+f0862257[ ]+vwmaccu.vv[ ]+v4,v12,v8,v0.t
  5712. +[ ]+[0-9a-f]+:[ ]+f085e257[ ]+vwmaccu.vx[ ]+v4,a1,v8,v0.t
  5713. +[ ]+[0-9a-f]+:[ ]+f6862257[ ]+vwmacc.vv[ ]+v4,v12,v8
  5714. +[ ]+[0-9a-f]+:[ ]+f685e257[ ]+vwmacc.vx[ ]+v4,a1,v8
  5715. +[ ]+[0-9a-f]+:[ ]+f4862257[ ]+vwmacc.vv[ ]+v4,v12,v8,v0.t
  5716. +[ ]+[0-9a-f]+:[ ]+f485e257[ ]+vwmacc.vx[ ]+v4,a1,v8,v0.t
  5717. +[ ]+[0-9a-f]+:[ ]+fe862257[ ]+vwmaccsu.vv[ ]+v4,v12,v8
  5718. +[ ]+[0-9a-f]+:[ ]+fe85e257[ ]+vwmaccsu.vx[ ]+v4,a1,v8
  5719. +[ ]+[0-9a-f]+:[ ]+fc862257[ ]+vwmaccsu.vv[ ]+v4,v12,v8,v0.t
  5720. +[ ]+[0-9a-f]+:[ ]+fc85e257[ ]+vwmaccsu.vx[ ]+v4,a1,v8,v0.t
  5721. +[ ]+[0-9a-f]+:[ ]+fa85e257[ ]+vwmaccus.vx[ ]+v4,a1,v8
  5722. +[ ]+[0-9a-f]+:[ ]+f885e257[ ]+vwmaccus.vx[ ]+v4,a1,v8,v0.t
  5723. +[ ]+[0-9a-f]+:[ ]+f2860257[ ]+vqmaccu.vv[ ]+v4,v12,v8
  5724. +[ ]+[0-9a-f]+:[ ]+f285c257[ ]+vqmaccu.vx[ ]+v4,a1,v8
  5725. +[ ]+[0-9a-f]+:[ ]+f0860257[ ]+vqmaccu.vv[ ]+v4,v12,v8,v0.t
  5726. +[ ]+[0-9a-f]+:[ ]+f085c257[ ]+vqmaccu.vx[ ]+v4,a1,v8,v0.t
  5727. +[ ]+[0-9a-f]+:[ ]+f6860257[ ]+vqmacc.vv[ ]+v4,v12,v8
  5728. +[ ]+[0-9a-f]+:[ ]+f685c257[ ]+vqmacc.vx[ ]+v4,a1,v8
  5729. +[ ]+[0-9a-f]+:[ ]+f4860257[ ]+vqmacc.vv[ ]+v4,v12,v8,v0.t
  5730. +[ ]+[0-9a-f]+:[ ]+f485c257[ ]+vqmacc.vx[ ]+v4,a1,v8,v0.t
  5731. +[ ]+[0-9a-f]+:[ ]+fe860257[ ]+vqmaccsu.vv[ ]+v4,v12,v8
  5732. +[ ]+[0-9a-f]+:[ ]+fe85c257[ ]+vqmaccsu.vx[ ]+v4,a1,v8
  5733. +[ ]+[0-9a-f]+:[ ]+fc860257[ ]+vqmaccsu.vv[ ]+v4,v12,v8,v0.t
  5734. +[ ]+[0-9a-f]+:[ ]+fc85c257[ ]+vqmaccsu.vx[ ]+v4,a1,v8,v0.t
  5735. +[ ]+[0-9a-f]+:[ ]+fa85c257[ ]+vqmaccus.vx[ ]+v4,a1,v8
  5736. +[ ]+[0-9a-f]+:[ ]+f885c257[ ]+vqmaccus.vx[ ]+v4,a1,v8,v0.t
  5737. +[ ]+[0-9a-f]+:[ ]+82862257[ ]+vdivu.vv[ ]+v4,v8,v12
  5738. +[ ]+[0-9a-f]+:[ ]+8285e257[ ]+vdivu.vx[ ]+v4,v8,a1
  5739. +[ ]+[0-9a-f]+:[ ]+80862257[ ]+vdivu.vv[ ]+v4,v8,v12,v0.t
  5740. +[ ]+[0-9a-f]+:[ ]+8085e257[ ]+vdivu.vx[ ]+v4,v8,a1,v0.t
  5741. +[ ]+[0-9a-f]+:[ ]+86862257[ ]+vdiv.vv[ ]+v4,v8,v12
  5742. +[ ]+[0-9a-f]+:[ ]+8685e257[ ]+vdiv.vx[ ]+v4,v8,a1
  5743. +[ ]+[0-9a-f]+:[ ]+84862257[ ]+vdiv.vv[ ]+v4,v8,v12,v0.t
  5744. +[ ]+[0-9a-f]+:[ ]+8485e257[ ]+vdiv.vx[ ]+v4,v8,a1,v0.t
  5745. +[ ]+[0-9a-f]+:[ ]+8a862257[ ]+vremu.vv[ ]+v4,v8,v12
  5746. +[ ]+[0-9a-f]+:[ ]+8a85e257[ ]+vremu.vx[ ]+v4,v8,a1
  5747. +[ ]+[0-9a-f]+:[ ]+88862257[ ]+vremu.vv[ ]+v4,v8,v12,v0.t
  5748. +[ ]+[0-9a-f]+:[ ]+8885e257[ ]+vremu.vx[ ]+v4,v8,a1,v0.t
  5749. +[ ]+[0-9a-f]+:[ ]+8e862257[ ]+vrem.vv[ ]+v4,v8,v12
  5750. +[ ]+[0-9a-f]+:[ ]+8e85e257[ ]+vrem.vx[ ]+v4,v8,a1
  5751. +[ ]+[0-9a-f]+:[ ]+8c862257[ ]+vrem.vv[ ]+v4,v8,v12,v0.t
  5752. +[ ]+[0-9a-f]+:[ ]+8c85e257[ ]+vrem.vx[ ]+v4,v8,a1,v0.t
  5753. +[ ]+[0-9a-f]+:[ ]+5c860257[ ]+vmerge.vvm[ ]+v4,v8,v12,v0
  5754. +[ ]+[0-9a-f]+:[ ]+5c85c257[ ]+vmerge.vxm[ ]+v4,v8,a1,v0
  5755. +[ ]+[0-9a-f]+:[ ]+5c87b257[ ]+vmerge.vim[ ]+v4,v8,15,v0
  5756. +[ ]+[0-9a-f]+:[ ]+5c883257[ ]+vmerge.vim[ ]+v4,v8,-16,v0
  5757. +[ ]+[0-9a-f]+:[ ]+5e060457[ ]+vmv.v.v[ ]+v8,v12
  5758. +[ ]+[0-9a-f]+:[ ]+5e05c457[ ]+vmv.v.x[ ]+v8,a1
  5759. +[ ]+[0-9a-f]+:[ ]+5e07b457[ ]+vmv.v.i[ ]+v8,15
  5760. +[ ]+[0-9a-f]+:[ ]+5e083457[ ]+vmv.v.i[ ]+v8,-16
  5761. +[ ]+[0-9a-f]+:[ ]+82860257[ ]+vsaddu.vv[ ]+v4,v8,v12
  5762. +[ ]+[0-9a-f]+:[ ]+8285c257[ ]+vsaddu.vx[ ]+v4,v8,a1
  5763. +[ ]+[0-9a-f]+:[ ]+8287b257[ ]+vsaddu.vi[ ]+v4,v8,15
  5764. +[ ]+[0-9a-f]+:[ ]+82883257[ ]+vsaddu.vi[ ]+v4,v8,-16
  5765. +[ ]+[0-9a-f]+:[ ]+80860257[ ]+vsaddu.vv[ ]+v4,v8,v12,v0.t
  5766. +[ ]+[0-9a-f]+:[ ]+8085c257[ ]+vsaddu.vx[ ]+v4,v8,a1,v0.t
  5767. +[ ]+[0-9a-f]+:[ ]+8087b257[ ]+vsaddu.vi[ ]+v4,v8,15,v0.t
  5768. +[ ]+[0-9a-f]+:[ ]+80883257[ ]+vsaddu.vi[ ]+v4,v8,-16,v0.t
  5769. +[ ]+[0-9a-f]+:[ ]+86860257[ ]+vsadd.vv[ ]+v4,v8,v12
  5770. +[ ]+[0-9a-f]+:[ ]+8685c257[ ]+vsadd.vx[ ]+v4,v8,a1
  5771. +[ ]+[0-9a-f]+:[ ]+8687b257[ ]+vsadd.vi[ ]+v4,v8,15
  5772. +[ ]+[0-9a-f]+:[ ]+86883257[ ]+vsadd.vi[ ]+v4,v8,-16
  5773. +[ ]+[0-9a-f]+:[ ]+84860257[ ]+vsadd.vv[ ]+v4,v8,v12,v0.t
  5774. +[ ]+[0-9a-f]+:[ ]+8485c257[ ]+vsadd.vx[ ]+v4,v8,a1,v0.t
  5775. +[ ]+[0-9a-f]+:[ ]+8487b257[ ]+vsadd.vi[ ]+v4,v8,15,v0.t
  5776. +[ ]+[0-9a-f]+:[ ]+84883257[ ]+vsadd.vi[ ]+v4,v8,-16,v0.t
  5777. +[ ]+[0-9a-f]+:[ ]+8a860257[ ]+vssubu.vv[ ]+v4,v8,v12
  5778. +[ ]+[0-9a-f]+:[ ]+8a85c257[ ]+vssubu.vx[ ]+v4,v8,a1
  5779. +[ ]+[0-9a-f]+:[ ]+88860257[ ]+vssubu.vv[ ]+v4,v8,v12,v0.t
  5780. +[ ]+[0-9a-f]+:[ ]+8885c257[ ]+vssubu.vx[ ]+v4,v8,a1,v0.t
  5781. +[ ]+[0-9a-f]+:[ ]+8e860257[ ]+vssub.vv[ ]+v4,v8,v12
  5782. +[ ]+[0-9a-f]+:[ ]+8e85c257[ ]+vssub.vx[ ]+v4,v8,a1
  5783. +[ ]+[0-9a-f]+:[ ]+8c860257[ ]+vssub.vv[ ]+v4,v8,v12,v0.t
  5784. +[ ]+[0-9a-f]+:[ ]+8c85c257[ ]+vssub.vx[ ]+v4,v8,a1,v0.t
  5785. +[ ]+[0-9a-f]+:[ ]+22862257[ ]+vaaddu.vv[ ]+v4,v8,v12
  5786. +[ ]+[0-9a-f]+:[ ]+2285e257[ ]+vaaddu.vx[ ]+v4,v8,a1
  5787. +[ ]+[0-9a-f]+:[ ]+20862257[ ]+vaaddu.vv[ ]+v4,v8,v12,v0.t
  5788. +[ ]+[0-9a-f]+:[ ]+2085e257[ ]+vaaddu.vx[ ]+v4,v8,a1,v0.t
  5789. +[ ]+[0-9a-f]+:[ ]+26862257[ ]+vaadd.vv[ ]+v4,v8,v12
  5790. +[ ]+[0-9a-f]+:[ ]+2685e257[ ]+vaadd.vx[ ]+v4,v8,a1
  5791. +[ ]+[0-9a-f]+:[ ]+24862257[ ]+vaadd.vv[ ]+v4,v8,v12,v0.t
  5792. +[ ]+[0-9a-f]+:[ ]+2485e257[ ]+vaadd.vx[ ]+v4,v8,a1,v0.t
  5793. +[ ]+[0-9a-f]+:[ ]+2a862257[ ]+vasubu.vv[ ]+v4,v8,v12
  5794. +[ ]+[0-9a-f]+:[ ]+2a85e257[ ]+vasubu.vx[ ]+v4,v8,a1
  5795. +[ ]+[0-9a-f]+:[ ]+28862257[ ]+vasubu.vv[ ]+v4,v8,v12,v0.t
  5796. +[ ]+[0-9a-f]+:[ ]+2885e257[ ]+vasubu.vx[ ]+v4,v8,a1,v0.t
  5797. +[ ]+[0-9a-f]+:[ ]+2e862257[ ]+vasub.vv[ ]+v4,v8,v12
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  5799. +[ ]+[0-9a-f]+:[ ]+2c862257[ ]+vasub.vv[ ]+v4,v8,v12,v0.t
  5800. +[ ]+[0-9a-f]+:[ ]+2c85e257[ ]+vasub.vx[ ]+v4,v8,a1,v0.t
  5801. +[ ]+[0-9a-f]+:[ ]+9e860257[ ]+vsmul.vv[ ]+v4,v8,v12
  5802. +[ ]+[0-9a-f]+:[ ]+9e85c257[ ]+vsmul.vx[ ]+v4,v8,a1
  5803. +[ ]+[0-9a-f]+:[ ]+9c860257[ ]+vsmul.vv[ ]+v4,v8,v12,v0.t
  5804. +[ ]+[0-9a-f]+:[ ]+9c85c257[ ]+vsmul.vx[ ]+v4,v8,a1,v0.t
  5805. +[ ]+[0-9a-f]+:[ ]+aa860257[ ]+vssrl.vv[ ]+v4,v8,v12
  5806. +[ ]+[0-9a-f]+:[ ]+aa85c257[ ]+vssrl.vx[ ]+v4,v8,a1
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  5808. +[ ]+[0-9a-f]+:[ ]+aa8fb257[ ]+vssrl.vi[ ]+v4,v8,31
  5809. +[ ]+[0-9a-f]+:[ ]+a8860257[ ]+vssrl.vv[ ]+v4,v8,v12,v0.t
  5810. +[ ]+[0-9a-f]+:[ ]+a885c257[ ]+vssrl.vx[ ]+v4,v8,a1,v0.t
  5811. +[ ]+[0-9a-f]+:[ ]+a880b257[ ]+vssrl.vi[ ]+v4,v8,1,v0.t
  5812. +[ ]+[0-9a-f]+:[ ]+a88fb257[ ]+vssrl.vi[ ]+v4,v8,31,v0.t
  5813. +[ ]+[0-9a-f]+:[ ]+ae860257[ ]+vssra.vv[ ]+v4,v8,v12
  5814. +[ ]+[0-9a-f]+:[ ]+ae85c257[ ]+vssra.vx[ ]+v4,v8,a1
  5815. +[ ]+[0-9a-f]+:[ ]+ae80b257[ ]+vssra.vi[ ]+v4,v8,1
  5816. +[ ]+[0-9a-f]+:[ ]+ae8fb257[ ]+vssra.vi[ ]+v4,v8,31
  5817. +[ ]+[0-9a-f]+:[ ]+ac860257[ ]+vssra.vv[ ]+v4,v8,v12,v0.t
  5818. +[ ]+[0-9a-f]+:[ ]+ac85c257[ ]+vssra.vx[ ]+v4,v8,a1,v0.t
  5819. +[ ]+[0-9a-f]+:[ ]+ac80b257[ ]+vssra.vi[ ]+v4,v8,1,v0.t
  5820. +[ ]+[0-9a-f]+:[ ]+ac8fb257[ ]+vssra.vi[ ]+v4,v8,31,v0.t
  5821. +[ ]+[0-9a-f]+:[ ]+ba860257[ ]+vnclipu.wv[ ]+v4,v8,v12
  5822. +[ ]+[0-9a-f]+:[ ]+ba85c257[ ]+vnclipu.wx[ ]+v4,v8,a1
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  5824. +[ ]+[0-9a-f]+:[ ]+ba8fb257[ ]+vnclipu.wi[ ]+v4,v8,31
  5825. +[ ]+[0-9a-f]+:[ ]+b8860257[ ]+vnclipu.wv[ ]+v4,v8,v12,v0.t
  5826. +[ ]+[0-9a-f]+:[ ]+b885c257[ ]+vnclipu.wx[ ]+v4,v8,a1,v0.t
  5827. +[ ]+[0-9a-f]+:[ ]+b880b257[ ]+vnclipu.wi[ ]+v4,v8,1,v0.t
  5828. +[ ]+[0-9a-f]+:[ ]+b88fb257[ ]+vnclipu.wi[ ]+v4,v8,31,v0.t
  5829. +[ ]+[0-9a-f]+:[ ]+be860257[ ]+vnclip.wv[ ]+v4,v8,v12
  5830. +[ ]+[0-9a-f]+:[ ]+be85c257[ ]+vnclip.wx[ ]+v4,v8,a1
  5831. +[ ]+[0-9a-f]+:[ ]+be80b257[ ]+vnclip.wi[ ]+v4,v8,1
  5832. +[ ]+[0-9a-f]+:[ ]+be8fb257[ ]+vnclip.wi[ ]+v4,v8,31
  5833. +[ ]+[0-9a-f]+:[ ]+bc860257[ ]+vnclip.wv[ ]+v4,v8,v12,v0.t
  5834. +[ ]+[0-9a-f]+:[ ]+bc85c257[ ]+vnclip.wx[ ]+v4,v8,a1,v0.t
  5835. +[ ]+[0-9a-f]+:[ ]+bc80b257[ ]+vnclip.wi[ ]+v4,v8,1,v0.t
  5836. +[ ]+[0-9a-f]+:[ ]+bc8fb257[ ]+vnclip.wi[ ]+v4,v8,31,v0.t
  5837. +[ ]+[0-9a-f]+:[ ]+02861257[ ]+vfadd.vv[ ]+v4,v8,v12
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  5840. +[ ]+[0-9a-f]+:[ ]+00865257[ ]+vfadd.vf[ ]+v4,v8,fa2,v0.t
  5841. +[ ]+[0-9a-f]+:[ ]+0a861257[ ]+vfsub.vv[ ]+v4,v8,v12
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  5844. +[ ]+[0-9a-f]+:[ ]+08865257[ ]+vfsub.vf[ ]+v4,v8,fa2,v0.t
  5845. +[ ]+[0-9a-f]+:[ ]+9e865257[ ]+vfrsub.vf[ ]+v4,v8,fa2
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  5847. +[ ]+[0-9a-f]+:[ ]+c2861257[ ]+vfwadd.vv[ ]+v4,v8,v12
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  5850. +[ ]+[0-9a-f]+:[ ]+c0865257[ ]+vfwadd.vf[ ]+v4,v8,fa2,v0.t
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  5861. +[ ]+[0-9a-f]+:[ ]+d8861257[ ]+vfwsub.wv[ ]+v4,v8,v12,v0.t
  5862. +[ ]+[0-9a-f]+:[ ]+d8865257[ ]+vfwsub.wf[ ]+v4,v8,fa2,v0.t
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  5870. +[ ]+[0-9a-f]+:[ ]+80865257[ ]+vfdiv.vf[ ]+v4,v8,fa2,v0.t
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  5875. +[ ]+[0-9a-f]+:[ ]+e0861257[ ]+vfwmul.vv[ ]+v4,v8,v12,v0.t
  5876. +[ ]+[0-9a-f]+:[ ]+e0865257[ ]+vfwmul.vf[ ]+v4,v8,fa2,v0.t
  5877. +[ ]+[0-9a-f]+:[ ]+a2861257[ ]+vfmadd.vv[ ]+v4,v12,v8
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  6058. +[ ]+[0-9a-f]+:[ ]+6a862257[ ]+vmor.mm[ ]+v4,v8,v12
  6059. +[ ]+[0-9a-f]+:[ ]+7a862257[ ]+vmnor.mm[ ]+v4,v8,v12
  6060. +[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmornot.mm[ ]+v4,v8,v12
  6061. +[ ]+[0-9a-f]+:[ ]+7e862257[ ]+vmxnor.mm[ ]+v4,v8,v12
  6062. +[ ]+[0-9a-f]+:[ ]+42c82557[ ]+vpopc.m[ ]+a0,v12
  6063. +[ ]+[0-9a-f]+:[ ]+42c8a557[ ]+vfirst.m[ ]+a0,v12
  6064. +[ ]+[0-9a-f]+:[ ]+5280a257[ ]+vmsbf.m[ ]+v4,v8
  6065. +[ ]+[0-9a-f]+:[ ]+5281a257[ ]+vmsif.m[ ]+v4,v8
  6066. +[ ]+[0-9a-f]+:[ ]+52812257[ ]+vmsof.m[ ]+v4,v8
  6067. +[ ]+[0-9a-f]+:[ ]+52882257[ ]+viota.m[ ]+v4,v8
  6068. +[ ]+[0-9a-f]+:[ ]+5208a257[ ]+vid.v[ ]+v4
  6069. +[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vpopc.m[ ]+a0,v12,v0.t
  6070. +[ ]+[0-9a-f]+:[ ]+40c8a557[ ]+vfirst.m[ ]+a0,v12,v0.t
  6071. +[ ]+[0-9a-f]+:[ ]+5080a257[ ]+vmsbf.m[ ]+v4,v8,v0.t
  6072. +[ ]+[0-9a-f]+:[ ]+5081a257[ ]+vmsif.m[ ]+v4,v8,v0.t
  6073. +[ ]+[0-9a-f]+:[ ]+50812257[ ]+vmsof.m[ ]+v4,v8,v0.t
  6074. +[ ]+[0-9a-f]+:[ ]+50882257[ ]+viota.m[ ]+v4,v8,v0.t
  6075. +[ ]+[0-9a-f]+:[ ]+5008a257[ ]+vid.v[ ]+v4,v0.t
  6076. +[ ]+[0-9a-f]+:[ ]+42c02557[ ]+vmv.x.s[ ]+a0,v12
  6077. +[ ]+[0-9a-f]+:[ ]+42056257[ ]+vmv.s.x[ ]+v4,a0
  6078. +[ ]+[0-9a-f]+:[ ]+42801557[ ]+vfmv.f.s[ ]+fa0,v8
  6079. +[ ]+[0-9a-f]+:[ ]+4205d257[ ]+vfmv.s.f[ ]+v4,fa1
  6080. +[ ]+[0-9a-f]+:[ ]+3a85c257[ ]+vslideup.vx[ ]+v4,v8,a1
  6081. +[ ]+[0-9a-f]+:[ ]+3a803257[ ]+vslideup.vi[ ]+v4,v8,0
  6082. +[ ]+[0-9a-f]+:[ ]+3a8fb257[ ]+vslideup.vi[ ]+v4,v8,31
  6083. +[ ]+[0-9a-f]+:[ ]+3e85c257[ ]+vslidedown.vx[ ]+v4,v8,a1
  6084. +[ ]+[0-9a-f]+:[ ]+3e803257[ ]+vslidedown.vi[ ]+v4,v8,0
  6085. +[ ]+[0-9a-f]+:[ ]+3e8fb257[ ]+vslidedown.vi[ ]+v4,v8,31
  6086. +[ ]+[0-9a-f]+:[ ]+3885c257[ ]+vslideup.vx[ ]+v4,v8,a1,v0.t
  6087. +[ ]+[0-9a-f]+:[ ]+38803257[ ]+vslideup.vi[ ]+v4,v8,0,v0.t
  6088. +[ ]+[0-9a-f]+:[ ]+388fb257[ ]+vslideup.vi[ ]+v4,v8,31,v0.t
  6089. +[ ]+[0-9a-f]+:[ ]+3c85c257[ ]+vslidedown.vx[ ]+v4,v8,a1,v0.t
  6090. +[ ]+[0-9a-f]+:[ ]+3c803257[ ]+vslidedown.vi[ ]+v4,v8,0,v0.t
  6091. +[ ]+[0-9a-f]+:[ ]+3c8fb257[ ]+vslidedown.vi[ ]+v4,v8,31,v0.t
  6092. +[ ]+[0-9a-f]+:[ ]+3a85e257[ ]+vslide1up.vx[ ]+v4,v8,a1
  6093. +[ ]+[0-9a-f]+:[ ]+3e85e257[ ]+vslide1down.vx[ ]+v4,v8,a1
  6094. +[ ]+[0-9a-f]+:[ ]+3885e257[ ]+vslide1up.vx[ ]+v4,v8,a1,v0.t
  6095. +[ ]+[0-9a-f]+:[ ]+3c85e257[ ]+vslide1down.vx[ ]+v4,v8,a1,v0.t
  6096. +[ ]+[0-9a-f]+:[ ]+3a85d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1
  6097. +[ ]+[0-9a-f]+:[ ]+3e85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1
  6098. +[ ]+[0-9a-f]+:[ ]+3885d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1,v0.t
  6099. +[ ]+[0-9a-f]+:[ ]+3c85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1,v0.t
  6100. +[ ]+[0-9a-f]+:[ ]+32860257[ ]+vrgather.vv[ ]+v4,v8,v12
  6101. +[ ]+[0-9a-f]+:[ ]+3285c257[ ]+vrgather.vx[ ]+v4,v8,a1
  6102. +[ ]+[0-9a-f]+:[ ]+32803257[ ]+vrgather.vi[ ]+v4,v8,0
  6103. +[ ]+[0-9a-f]+:[ ]+328fb257[ ]+vrgather.vi[ ]+v4,v8,31
  6104. +[ ]+[0-9a-f]+:[ ]+30860257[ ]+vrgather.vv[ ]+v4,v8,v12,v0.t
  6105. +[ ]+[0-9a-f]+:[ ]+3085c257[ ]+vrgather.vx[ ]+v4,v8,a1,v0.t
  6106. +[ ]+[0-9a-f]+:[ ]+30803257[ ]+vrgather.vi[ ]+v4,v8,0,v0.t
  6107. +[ ]+[0-9a-f]+:[ ]+308fb257[ ]+vrgather.vi[ ]+v4,v8,31,v0.t
  6108. +[ ]+[0-9a-f]+:[ ]+5e862257[ ]+vcompress.vm[ ]+v4,v8,v12
  6109. +[ ]+[0-9a-f]+:[ ]+9e2030d7[ ]+vmv1r.v[ ]+v1,v2
  6110. +[ ]+[0-9a-f]+:[ ]+9e40b157[ ]+vmv2r.v[ ]+v2,v4
  6111. +[ ]+[0-9a-f]+:[ ]+9e81b257[ ]+vmv4r.v[ ]+v4,v8
  6112. +[ ]+[0-9a-f]+:[ ]+9e83b057[ ]+vmv8r.v[ ]+v0,v8
  6113. +[ ]+[0-9a-f]+:[ ]+e6860257[ ]+vdot.vv[ ]+v4,v8,v12
  6114. +[ ]+[0-9a-f]+:[ ]+e2860257[ ]+vdotu.vv[ ]+v4,v8,v12
  6115. +[ ]+[0-9a-f]+:[ ]+e6861257[ ]+vfdot.vv[ ]+v4,v8,v12
  6116. +[ ]+[0-9a-f]+:[ ]+e4860257[ ]+vdot.vv[ ]+v4,v8,v12,v0.t
  6117. +[ ]+[0-9a-f]+:[ ]+e0860257[ ]+vdotu.vv[ ]+v4,v8,v12,v0.t
  6118. +[ ]+[0-9a-f]+:[ ]+e4861257[ ]+vfdot.vv[ ]+v4,v8,v12,v0.t
  6119. diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
  6120. new file mode 100644
  6121. index 0000000000..8b9a894418
  6122. --- /dev/null
  6123. +++ b/gas/testsuite/gas/riscv/vector-insns.s
  6124. @@ -0,0 +1,2718 @@
  6125. + vsetvl a0, a1, a2
  6126. + vsetvli a0, a1, 0
  6127. + vsetvli a0, a1, 0x7ff
  6128. + vsetvli a0, a1, e16,m2,d4
  6129. + vsetvli a0, a1, e256, m8, d8
  6130. + vsetvli a0, a1, e512, m8, d8
  6131. + vsetvli a0, a1, e1024, m8, d8
  6132. + vsetvli a0, a1, e1024, m1, d8
  6133. + vsetvli a0, a1, e1024, mf2, d8
  6134. + vsetvli a0, a1, e512, mf4, d2
  6135. + vsetvli a0, a1, e256, mf8, d4
  6136. + vsetvli a0, a1, e256, m2, ta, d4
  6137. + vsetvli a0, a1, e256, m2, ma, d4
  6138. + vsetvli a0, a1, e256, m2, tu, d4
  6139. + vsetvli a0, a1, e256, m2, mu, d4
  6140. + vsetvli a0, a1, e256, m2, ta,ma, d4
  6141. + vsetvli a0, a1, e256, m2, tu,ma, d4
  6142. + vsetvli a0, a1, e256, m2, ta,mu, d4
  6143. + vsetvli a0, a1, e256, m2, tu,mu, d4
  6144. +
  6145. + vle8.v v4, (a0)
  6146. + vle8.v v4, 0(a0)
  6147. + vle8.v v4, (a0), v0.t
  6148. + vse8.v v4, (a0)
  6149. + vse8.v v4, 0(a0)
  6150. + vse8.v v4, (a0), v0.t
  6151. +
  6152. + vle16.v v4, (a0)
  6153. + vle16.v v4, 0(a0)
  6154. + vle16.v v4, (a0), v0.t
  6155. + vse16.v v4, (a0)
  6156. + vse16.v v4, 0(a0)
  6157. + vse16.v v4, (a0), v0.t
  6158. +
  6159. + vle32.v v4, (a0)
  6160. + vle32.v v4, 0(a0)
  6161. + vle32.v v4, (a0), v0.t
  6162. + vse32.v v4, (a0)
  6163. + vse32.v v4, 0(a0)
  6164. + vse32.v v4, (a0), v0.t
  6165. +
  6166. + vle64.v v4, (a0)
  6167. + vle64.v v4, 0(a0)
  6168. + vle64.v v4, (a0), v0.t
  6169. + vse64.v v4, (a0)
  6170. + vse64.v v4, 0(a0)
  6171. + vse64.v v4, (a0), v0.t
  6172. +
  6173. + vle128.v v4, (a0)
  6174. + vle128.v v4, 0(a0)
  6175. + vle128.v v4, (a0), v0.t
  6176. + vse128.v v4, (a0)
  6177. + vse128.v v4, 0(a0)
  6178. + vse128.v v4, (a0), v0.t
  6179. +
  6180. + vle256.v v4, (a0)
  6181. + vle256.v v4, 0(a0)
  6182. + vle256.v v4, (a0), v0.t
  6183. + vse256.v v4, (a0)
  6184. + vse256.v v4, 0(a0)
  6185. + vse256.v v4, (a0), v0.t
  6186. +
  6187. + vle512.v v4, (a0)
  6188. + vle512.v v4, 0(a0)
  6189. + vle512.v v4, (a0), v0.t
  6190. + vse512.v v4, (a0)
  6191. + vse512.v v4, 0(a0)
  6192. + vse512.v v4, (a0), v0.t
  6193. +
  6194. + vle1024.v v4, (a0)
  6195. + vle1024.v v4, 0(a0)
  6196. + vle1024.v v4, (a0), v0.t
  6197. + vse1024.v v4, (a0)
  6198. + vse1024.v v4, 0(a0)
  6199. + vse1024.v v4, (a0), v0.t
  6200. +
  6201. + vlse8.v v4, (a0), a1
  6202. + vlse8.v v4, 0(a0), a1
  6203. + vlse8.v v4, (a0), a1, v0.t
  6204. + vsse8.v v4, (a0), a1
  6205. + vsse8.v v4, 0(a0), a1
  6206. + vsse8.v v4, (a0), a1, v0.t
  6207. +
  6208. + vlse16.v v4, (a0), a1
  6209. + vlse16.v v4, 0(a0), a1
  6210. + vlse16.v v4, (a0), a1, v0.t
  6211. + vsse16.v v4, (a0), a1
  6212. + vsse16.v v4, 0(a0), a1
  6213. + vsse16.v v4, (a0), a1, v0.t
  6214. +
  6215. + vlse32.v v4, (a0), a1
  6216. + vlse32.v v4, 0(a0), a1
  6217. + vlse32.v v4, (a0), a1, v0.t
  6218. + vsse32.v v4, (a0), a1
  6219. + vsse32.v v4, 0(a0), a1
  6220. + vsse32.v v4, (a0), a1, v0.t
  6221. +
  6222. + vlse64.v v4, (a0), a1
  6223. + vlse64.v v4, 0(a0), a1
  6224. + vlse64.v v4, (a0), a1, v0.t
  6225. + vsse64.v v4, (a0), a1
  6226. + vsse64.v v4, 0(a0), a1
  6227. + vsse64.v v4, (a0), a1, v0.t
  6228. +
  6229. + vlse128.v v4, (a0), a1
  6230. + vlse128.v v4, 0(a0), a1
  6231. + vlse128.v v4, (a0), a1, v0.t
  6232. + vsse128.v v4, (a0), a1
  6233. + vsse128.v v4, 0(a0), a1
  6234. + vsse128.v v4, (a0), a1, v0.t
  6235. +
  6236. + vlse256.v v4, (a0), a1
  6237. + vlse256.v v4, 0(a0), a1
  6238. + vlse256.v v4, (a0), a1, v0.t
  6239. + vsse256.v v4, (a0), a1
  6240. + vsse256.v v4, 0(a0), a1
  6241. + vsse256.v v4, (a0), a1, v0.t
  6242. +
  6243. + vlse512.v v4, (a0), a1
  6244. + vlse512.v v4, 0(a0), a1
  6245. + vlse512.v v4, (a0), a1, v0.t
  6246. + vsse512.v v4, (a0), a1
  6247. + vsse512.v v4, 0(a0), a1
  6248. + vsse512.v v4, (a0), a1, v0.t
  6249. +
  6250. + vlse1024.v v4, (a0), a1
  6251. + vlse1024.v v4, 0(a0), a1
  6252. + vlse1024.v v4, (a0), a1, v0.t
  6253. + vsse1024.v v4, (a0), a1
  6254. + vsse1024.v v4, 0(a0), a1
  6255. + vsse1024.v v4, (a0), a1, v0.t
  6256. +
  6257. + vlxei8.v v4, (a0), v12
  6258. + vlxei8.v v4, 0(a0), v12
  6259. + vlxei8.v v4, (a0), v12, v0.t
  6260. + vsxei8.v v4, (a0), v12
  6261. + vsxei8.v v4, 0(a0), v12
  6262. + vsxei8.v v4, (a0), v12, v0.t
  6263. + vsuxei8.v v4, (a0), v12
  6264. + vsuxei8.v v4, 0(a0), v12
  6265. + vsuxei8.v v4, (a0), v12, v0.t
  6266. +
  6267. + vlxei16.v v4, (a0), v12
  6268. + vlxei16.v v4, 0(a0), v12
  6269. + vlxei16.v v4, (a0), v12, v0.t
  6270. + vsxei16.v v4, (a0), v12
  6271. + vsxei16.v v4, 0(a0), v12
  6272. + vsxei16.v v4, (a0), v12, v0.t
  6273. + vsuxei16.v v4, (a0), v12
  6274. + vsuxei16.v v4, 0(a0), v12
  6275. + vsuxei16.v v4, (a0), v12, v0.t
  6276. +
  6277. + vlxei32.v v4, (a0), v12
  6278. + vlxei32.v v4, 0(a0), v12
  6279. + vlxei32.v v4, (a0), v12, v0.t
  6280. + vsxei32.v v4, (a0), v12
  6281. + vsxei32.v v4, 0(a0), v12
  6282. + vsxei32.v v4, (a0), v12, v0.t
  6283. + vsuxei32.v v4, (a0), v12
  6284. + vsuxei32.v v4, 0(a0), v12
  6285. + vsuxei32.v v4, (a0), v12, v0.t
  6286. +
  6287. + vlxei64.v v4, (a0), v12
  6288. + vlxei64.v v4, 0(a0), v12
  6289. + vlxei64.v v4, (a0), v12, v0.t
  6290. + vsxei64.v v4, (a0), v12
  6291. + vsxei64.v v4, 0(a0), v12
  6292. + vsxei64.v v4, (a0), v12, v0.t
  6293. + vsuxei64.v v4, (a0), v12
  6294. + vsuxei64.v v4, 0(a0), v12
  6295. + vsuxei64.v v4, (a0), v12, v0.t
  6296. +
  6297. + vlxei128.v v4, (a0), v12
  6298. + vlxei128.v v4, 0(a0), v12
  6299. + vlxei128.v v4, (a0), v12, v0.t
  6300. + vsxei128.v v4, (a0), v12
  6301. + vsxei128.v v4, 0(a0), v12
  6302. + vsxei128.v v4, (a0), v12, v0.t
  6303. + vsuxei128.v v4, (a0), v12
  6304. + vsuxei128.v v4, 0(a0), v12
  6305. + vsuxei128.v v4, (a0), v12, v0.t
  6306. +
  6307. + vlxei256.v v4, (a0), v12
  6308. + vlxei256.v v4, 0(a0), v12
  6309. + vlxei256.v v4, (a0), v12, v0.t
  6310. + vsxei256.v v4, (a0), v12
  6311. + vsxei256.v v4, 0(a0), v12
  6312. + vsxei256.v v4, (a0), v12, v0.t
  6313. + vsuxei256.v v4, (a0), v12
  6314. + vsuxei256.v v4, 0(a0), v12
  6315. + vsuxei256.v v4, (a0), v12, v0.t
  6316. +
  6317. + vlxei512.v v4, (a0), v12
  6318. + vlxei512.v v4, 0(a0), v12
  6319. + vlxei512.v v4, (a0), v12, v0.t
  6320. + vsxei512.v v4, (a0), v12
  6321. + vsxei512.v v4, 0(a0), v12
  6322. + vsxei512.v v4, (a0), v12, v0.t
  6323. + vsuxei512.v v4, (a0), v12
  6324. + vsuxei512.v v4, 0(a0), v12
  6325. + vsuxei512.v v4, (a0), v12, v0.t
  6326. +
  6327. + vlxei1024.v v4, (a0), v12
  6328. + vlxei1024.v v4, 0(a0), v12
  6329. + vlxei1024.v v4, (a0), v12, v0.t
  6330. + vsxei1024.v v4, (a0), v12
  6331. + vsxei1024.v v4, 0(a0), v12
  6332. + vsxei1024.v v4, (a0), v12, v0.t
  6333. + vsuxei1024.v v4, (a0), v12
  6334. + vsuxei1024.v v4, 0(a0), v12
  6335. + vsuxei1024.v v4, (a0), v12, v0.t
  6336. +
  6337. + vle8ff.v v4, (a0)
  6338. + vle8ff.v v4, 0(a0)
  6339. + vle8ff.v v4, (a0), v0.t
  6340. +
  6341. + vle16ff.v v4, (a0)
  6342. + vle16ff.v v4, 0(a0)
  6343. + vle16ff.v v4, (a0), v0.t
  6344. +
  6345. + vle32ff.v v4, (a0)
  6346. + vle32ff.v v4, 0(a0)
  6347. + vle32ff.v v4, (a0), v0.t
  6348. +
  6349. + vle64ff.v v4, (a0)
  6350. + vle64ff.v v4, 0(a0)
  6351. + vle64ff.v v4, (a0), v0.t
  6352. +
  6353. + vle128ff.v v4, (a0)
  6354. + vle128ff.v v4, 0(a0)
  6355. + vle128ff.v v4, (a0), v0.t
  6356. +
  6357. + vle256ff.v v4, (a0)
  6358. + vle256ff.v v4, 0(a0)
  6359. + vle256ff.v v4, (a0), v0.t
  6360. +
  6361. + vle512ff.v v4, (a0)
  6362. + vle512ff.v v4, 0(a0)
  6363. + vle512ff.v v4, (a0), v0.t
  6364. +
  6365. + vle1024ff.v v4, (a0)
  6366. + vle1024ff.v v4, 0(a0)
  6367. + vle1024ff.v v4, (a0), v0.t
  6368. +
  6369. + vlseg2e8.v v4, (a0)
  6370. + vlseg2e8.v v4, 0(a0)
  6371. + vlseg2e8.v v4, (a0), v0.t
  6372. + vsseg2e8.v v4, (a0)
  6373. + vsseg2e8.v v4, 0(a0)
  6374. + vsseg2e8.v v4, (a0), v0.t
  6375. +
  6376. + vlseg3e8.v v4, (a0)
  6377. + vlseg3e8.v v4, 0(a0)
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  7397. +
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  7404. +
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  7410. + vsxseg3ei256.v v4, (a0), v12, v0.t
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  7417. + vsxseg4ei256.v v4, (a0), v12, v0.t
  7418. +
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  7422. + vsxseg5ei256.v v4, (a0), v12
  7423. + vsxseg5ei256.v v4, 0(a0), v12
  7424. + vsxseg5ei256.v v4, (a0), v12, v0.t
  7425. +
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  7428. + vlxseg6ei256.v v4, (a0), v12, v0.t
  7429. + vsxseg6ei256.v v4, (a0), v12
  7430. + vsxseg6ei256.v v4, 0(a0), v12
  7431. + vsxseg6ei256.v v4, (a0), v12, v0.t
  7432. +
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  7436. + vsxseg7ei256.v v4, (a0), v12
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  7438. + vsxseg7ei256.v v4, (a0), v12, v0.t
  7439. +
  7440. + vlxseg8ei256.v v4, (a0), v12
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  7445. + vsxseg8ei256.v v4, (a0), v12, v0.t
  7446. +
  7447. + vlxseg2ei512.v v4, (a0), v12
  7448. + vlxseg2ei512.v v4, 0(a0), v12
  7449. + vlxseg2ei512.v v4, (a0), v12, v0.t
  7450. + vsxseg2ei512.v v4, (a0), v12
  7451. + vsxseg2ei512.v v4, 0(a0), v12
  7452. + vsxseg2ei512.v v4, (a0), v12, v0.t
  7453. +
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  7456. + vlxseg3ei512.v v4, (a0), v12, v0.t
  7457. + vsxseg3ei512.v v4, (a0), v12
  7458. + vsxseg3ei512.v v4, 0(a0), v12
  7459. + vsxseg3ei512.v v4, (a0), v12, v0.t
  7460. +
  7461. + vlxseg4ei512.v v4, (a0), v12
  7462. + vlxseg4ei512.v v4, 0(a0), v12
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  7780. + vamoswapei8.v v4, (a1), v8, v4, v0.t
  7781. + vamoswapei8.v x0, (a1), v8, v4, v0.t
  7782. +
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  7785. + vamoxorei8.v v4, (a1), v8, v4, v0.t
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  7788. + vamoandei8.v x0, (a1), v8, v4
  7789. + vamoandei8.v v4, (a1), v8, v4, v0.t
  7790. + vamoandei8.v x0, (a1), v8, v4, v0.t
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  7792. + vamoorei8.v x0, (a1), v8, v4
  7793. + vamoorei8.v v4, (a1), v8, v4, v0.t
  7794. + vamoorei8.v x0, (a1), v8, v4, v0.t
  7795. +
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  7799. + vamominei8.v x0, (a1), v8, v4, v0.t
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  7802. + vamomaxei8.v v4, (a1), v8, v4, v0.t
  7803. + vamomaxei8.v x0, (a1), v8, v4, v0.t
  7804. + vamominuei8.v v4, (a1), v8, v4
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  7806. + vamominuei8.v v4, (a1), v8, v4, v0.t
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  7811. + vamomaxuei8.v x0, (a1), v8, v4, v0.t
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  7816. + vamoaddei8.v x0, 0(a1), v8, v4, v0.t
  7817. + vamoswapei8.v v4, 0(a1), v8, v4
  7818. + vamoswapei8.v x0, 0(a1), v8, v4
  7819. + vamoswapei8.v v4, 0(a1), v8, v4, v0.t
  7820. + vamoswapei8.v x0, 0(a1), v8, v4, v0.t
  7821. +
  7822. + vamoxorei8.v v4, 0(a1), v8, v4
  7823. + vamoxorei8.v x0, 0(a1), v8, v4
  7824. + vamoxorei8.v v4, 0(a1), v8, v4, v0.t
  7825. + vamoxorei8.v x0, 0(a1), v8, v4, v0.t
  7826. + vamoandei8.v v4, 0(a1), v8, v4
  7827. + vamoandei8.v x0, 0(a1), v8, v4
  7828. + vamoandei8.v v4, 0(a1), v8, v4, v0.t
  7829. + vamoandei8.v x0, 0(a1), v8, v4, v0.t
  7830. + vamoorei8.v v4, 0(a1), v8, v4
  7831. + vamoorei8.v x0, 0(a1), v8, v4
  7832. + vamoorei8.v v4, 0(a1), v8, v4, v0.t
  7833. + vamoorei8.v x0, 0(a1), v8, v4, v0.t
  7834. +
  7835. + vamominei8.v v4, 0(a1), v8, v4
  7836. + vamominei8.v x0, 0(a1), v8, v4
  7837. + vamominei8.v v4, 0(a1), v8, v4, v0.t
  7838. + vamominei8.v x0, 0(a1), v8, v4, v0.t
  7839. + vamomaxei8.v v4, 0(a1), v8, v4
  7840. + vamomaxei8.v x0, 0(a1), v8, v4
  7841. + vamomaxei8.v v4, 0(a1), v8, v4, v0.t
  7842. + vamomaxei8.v x0, 0(a1), v8, v4, v0.t
  7843. + vamominuei8.v v4, 0(a1), v8, v4
  7844. + vamominuei8.v x0, 0(a1), v8, v4
  7845. + vamominuei8.v v4, 0(a1), v8, v4, v0.t
  7846. + vamominuei8.v x0, 0(a1), v8, v4, v0.t
  7847. + vamomaxuei8.v v4, 0(a1), v8, v4
  7848. + vamomaxuei8.v x0, 0(a1), v8, v4
  7849. + vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
  7850. + vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
  7851. +
  7852. + vamoaddei16.v v4, (a1), v8, v4
  7853. + vamoaddei16.v x0, (a1), v8, v4
  7854. + vamoaddei16.v v4, (a1), v8, v4, v0.t
  7855. + vamoaddei16.v x0, (a1), v8, v4, v0.t
  7856. + vamoswapei16.v v4, (a1), v8, v4
  7857. + vamoswapei16.v x0, (a1), v8, v4
  7858. + vamoswapei16.v v4, (a1), v8, v4, v0.t
  7859. + vamoswapei16.v x0, (a1), v8, v4, v0.t
  7860. +
  7861. + vamoxorei16.v v4, (a1), v8, v4
  7862. + vamoxorei16.v x0, (a1), v8, v4
  7863. + vamoxorei16.v v4, (a1), v8, v4, v0.t
  7864. + vamoxorei16.v x0, (a1), v8, v4, v0.t
  7865. + vamoandei16.v v4, (a1), v8, v4
  7866. + vamoandei16.v x0, (a1), v8, v4
  7867. + vamoandei16.v v4, (a1), v8, v4, v0.t
  7868. + vamoandei16.v x0, (a1), v8, v4, v0.t
  7869. + vamoorei16.v v4, (a1), v8, v4
  7870. + vamoorei16.v x0, (a1), v8, v4
  7871. + vamoorei16.v v4, (a1), v8, v4, v0.t
  7872. + vamoorei16.v x0, (a1), v8, v4, v0.t
  7873. +
  7874. + vamominei16.v v4, (a1), v8, v4
  7875. + vamominei16.v x0, (a1), v8, v4
  7876. + vamominei16.v v4, (a1), v8, v4, v0.t
  7877. + vamominei16.v x0, (a1), v8, v4, v0.t
  7878. + vamomaxei16.v v4, (a1), v8, v4
  7879. + vamomaxei16.v x0, (a1), v8, v4
  7880. + vamomaxei16.v v4, (a1), v8, v4, v0.t
  7881. + vamomaxei16.v x0, (a1), v8, v4, v0.t
  7882. + vamominuei16.v v4, (a1), v8, v4
  7883. + vamominuei16.v x0, (a1), v8, v4
  7884. + vamominuei16.v v4, (a1), v8, v4, v0.t
  7885. + vamominuei16.v x0, (a1), v8, v4, v0.t
  7886. + vamomaxuei16.v v4, (a1), v8, v4
  7887. + vamomaxuei16.v x0, (a1), v8, v4
  7888. + vamomaxuei16.v v4, (a1), v8, v4, v0.t
  7889. + vamomaxuei16.v x0, (a1), v8, v4, v0.t
  7890. +
  7891. + vamoaddei16.v v4, 0(a1), v8, v4
  7892. + vamoaddei16.v x0, 0(a1), v8, v4
  7893. + vamoaddei16.v v4, 0(a1), v8, v4, v0.t
  7894. + vamoaddei16.v x0, 0(a1), v8, v4, v0.t
  7895. + vamoswapei16.v v4, 0(a1), v8, v4
  7896. + vamoswapei16.v x0, 0(a1), v8, v4
  7897. + vamoswapei16.v v4, 0(a1), v8, v4, v0.t
  7898. + vamoswapei16.v x0, 0(a1), v8, v4, v0.t
  7899. +
  7900. + vamoxorei16.v v4, 0(a1), v8, v4
  7901. + vamoxorei16.v x0, 0(a1), v8, v4
  7902. + vamoxorei16.v v4, 0(a1), v8, v4, v0.t
  7903. + vamoxorei16.v x0, 0(a1), v8, v4, v0.t
  7904. + vamoandei16.v v4, 0(a1), v8, v4
  7905. + vamoandei16.v x0, 0(a1), v8, v4
  7906. + vamoandei16.v v4, 0(a1), v8, v4, v0.t
  7907. + vamoandei16.v x0, 0(a1), v8, v4, v0.t
  7908. + vamoorei16.v v4, 0(a1), v8, v4
  7909. + vamoorei16.v x0, 0(a1), v8, v4
  7910. + vamoorei16.v v4, 0(a1), v8, v4, v0.t
  7911. + vamoorei16.v x0, 0(a1), v8, v4, v0.t
  7912. +
  7913. + vamominei16.v v4, 0(a1), v8, v4
  7914. + vamominei16.v x0, 0(a1), v8, v4
  7915. + vamominei16.v v4, 0(a1), v8, v4, v0.t
  7916. + vamominei16.v x0, 0(a1), v8, v4, v0.t
  7917. + vamomaxei16.v v4, 0(a1), v8, v4
  7918. + vamomaxei16.v x0, 0(a1), v8, v4
  7919. + vamomaxei16.v v4, 0(a1), v8, v4, v0.t
  7920. + vamomaxei16.v x0, 0(a1), v8, v4, v0.t
  7921. + vamominuei16.v v4, 0(a1), v8, v4
  7922. + vamominuei16.v x0, 0(a1), v8, v4
  7923. + vamominuei16.v v4, 0(a1), v8, v4, v0.t
  7924. + vamominuei16.v x0, 0(a1), v8, v4, v0.t
  7925. + vamomaxuei16.v v4, 0(a1), v8, v4
  7926. + vamomaxuei16.v x0, 0(a1), v8, v4
  7927. + vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
  7928. + vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
  7929. +
  7930. + vamoaddei32.v v4, (a1), v8, v4
  7931. + vamoaddei32.v x0, (a1), v8, v4
  7932. + vamoaddei32.v v4, (a1), v8, v4, v0.t
  7933. + vamoaddei32.v x0, (a1), v8, v4, v0.t
  7934. + vamoswapei32.v v4, (a1), v8, v4
  7935. + vamoswapei32.v x0, (a1), v8, v4
  7936. + vamoswapei32.v v4, (a1), v8, v4, v0.t
  7937. + vamoswapei32.v x0, (a1), v8, v4, v0.t
  7938. +
  7939. + vamoxorei32.v v4, (a1), v8, v4
  7940. + vamoxorei32.v x0, (a1), v8, v4
  7941. + vamoxorei32.v v4, (a1), v8, v4, v0.t
  7942. + vamoxorei32.v x0, (a1), v8, v4, v0.t
  7943. + vamoandei32.v v4, (a1), v8, v4
  7944. + vamoandei32.v x0, (a1), v8, v4
  7945. + vamoandei32.v v4, (a1), v8, v4, v0.t
  7946. + vamoandei32.v x0, (a1), v8, v4, v0.t
  7947. + vamoorei32.v v4, (a1), v8, v4
  7948. + vamoorei32.v x0, (a1), v8, v4
  7949. + vamoorei32.v v4, (a1), v8, v4, v0.t
  7950. + vamoorei32.v x0, (a1), v8, v4, v0.t
  7951. +
  7952. + vamominei32.v v4, (a1), v8, v4
  7953. + vamominei32.v x0, (a1), v8, v4
  7954. + vamominei32.v v4, (a1), v8, v4, v0.t
  7955. + vamominei32.v x0, (a1), v8, v4, v0.t
  7956. + vamomaxei32.v v4, (a1), v8, v4
  7957. + vamomaxei32.v x0, (a1), v8, v4
  7958. + vamomaxei32.v v4, (a1), v8, v4, v0.t
  7959. + vamomaxei32.v x0, (a1), v8, v4, v0.t
  7960. + vamominuei32.v v4, (a1), v8, v4
  7961. + vamominuei32.v x0, (a1), v8, v4
  7962. + vamominuei32.v v4, (a1), v8, v4, v0.t
  7963. + vamominuei32.v x0, (a1), v8, v4, v0.t
  7964. + vamomaxuei32.v v4, (a1), v8, v4
  7965. + vamomaxuei32.v x0, (a1), v8, v4
  7966. + vamomaxuei32.v v4, (a1), v8, v4, v0.t
  7967. + vamomaxuei32.v x0, (a1), v8, v4, v0.t
  7968. +
  7969. + vamoaddei32.v v4, 0(a1), v8, v4
  7970. + vamoaddei32.v x0, 0(a1), v8, v4
  7971. + vamoaddei32.v v4, 0(a1), v8, v4, v0.t
  7972. + vamoaddei32.v x0, 0(a1), v8, v4, v0.t
  7973. + vamoswapei32.v v4, 0(a1), v8, v4
  7974. + vamoswapei32.v x0, 0(a1), v8, v4
  7975. + vamoswapei32.v v4, 0(a1), v8, v4, v0.t
  7976. + vamoswapei32.v x0, 0(a1), v8, v4, v0.t
  7977. +
  7978. + vamoxorei32.v v4, 0(a1), v8, v4
  7979. + vamoxorei32.v x0, 0(a1), v8, v4
  7980. + vamoxorei32.v v4, 0(a1), v8, v4, v0.t
  7981. + vamoxorei32.v x0, 0(a1), v8, v4, v0.t
  7982. + vamoandei32.v v4, 0(a1), v8, v4
  7983. + vamoandei32.v x0, 0(a1), v8, v4
  7984. + vamoandei32.v v4, 0(a1), v8, v4, v0.t
  7985. + vamoandei32.v x0, 0(a1), v8, v4, v0.t
  7986. + vamoorei32.v v4, 0(a1), v8, v4
  7987. + vamoorei32.v x0, 0(a1), v8, v4
  7988. + vamoorei32.v v4, 0(a1), v8, v4, v0.t
  7989. + vamoorei32.v x0, 0(a1), v8, v4, v0.t
  7990. +
  7991. + vamominei32.v v4, 0(a1), v8, v4
  7992. + vamominei32.v x0, 0(a1), v8, v4
  7993. + vamominei32.v v4, 0(a1), v8, v4, v0.t
  7994. + vamominei32.v x0, 0(a1), v8, v4, v0.t
  7995. + vamomaxei32.v v4, 0(a1), v8, v4
  7996. + vamomaxei32.v x0, 0(a1), v8, v4
  7997. + vamomaxei32.v v4, 0(a1), v8, v4, v0.t
  7998. + vamomaxei32.v x0, 0(a1), v8, v4, v0.t
  7999. + vamominuei32.v v4, 0(a1), v8, v4
  8000. + vamominuei32.v x0, 0(a1), v8, v4
  8001. + vamominuei32.v v4, 0(a1), v8, v4, v0.t
  8002. + vamominuei32.v x0, 0(a1), v8, v4, v0.t
  8003. + vamomaxuei32.v v4, 0(a1), v8, v4
  8004. + vamomaxuei32.v x0, 0(a1), v8, v4
  8005. + vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
  8006. + vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
  8007. +
  8008. + vamoaddei64.v v4, (a1), v8, v4
  8009. + vamoaddei64.v x0, (a1), v8, v4
  8010. + vamoaddei64.v v4, (a1), v8, v4, v0.t
  8011. + vamoaddei64.v x0, (a1), v8, v4, v0.t
  8012. + vamoswapei64.v v4, (a1), v8, v4
  8013. + vamoswapei64.v x0, (a1), v8, v4
  8014. + vamoswapei64.v v4, (a1), v8, v4, v0.t
  8015. + vamoswapei64.v x0, (a1), v8, v4, v0.t
  8016. +
  8017. + vamoxorei64.v v4, (a1), v8, v4
  8018. + vamoxorei64.v x0, (a1), v8, v4
  8019. + vamoxorei64.v v4, (a1), v8, v4, v0.t
  8020. + vamoxorei64.v x0, (a1), v8, v4, v0.t
  8021. + vamoandei64.v v4, (a1), v8, v4
  8022. + vamoandei64.v x0, (a1), v8, v4
  8023. + vamoandei64.v v4, (a1), v8, v4, v0.t
  8024. + vamoandei64.v x0, (a1), v8, v4, v0.t
  8025. + vamoorei64.v v4, (a1), v8, v4
  8026. + vamoorei64.v x0, (a1), v8, v4
  8027. + vamoorei64.v v4, (a1), v8, v4, v0.t
  8028. + vamoorei64.v x0, (a1), v8, v4, v0.t
  8029. +
  8030. + vamominei64.v v4, (a1), v8, v4
  8031. + vamominei64.v x0, (a1), v8, v4
  8032. + vamominei64.v v4, (a1), v8, v4, v0.t
  8033. + vamominei64.v x0, (a1), v8, v4, v0.t
  8034. + vamomaxei64.v v4, (a1), v8, v4
  8035. + vamomaxei64.v x0, (a1), v8, v4
  8036. + vamomaxei64.v v4, (a1), v8, v4, v0.t
  8037. + vamomaxei64.v x0, (a1), v8, v4, v0.t
  8038. + vamominuei64.v v4, (a1), v8, v4
  8039. + vamominuei64.v x0, (a1), v8, v4
  8040. + vamominuei64.v v4, (a1), v8, v4, v0.t
  8041. + vamominuei64.v x0, (a1), v8, v4, v0.t
  8042. + vamomaxuei64.v v4, (a1), v8, v4
  8043. + vamomaxuei64.v x0, (a1), v8, v4
  8044. + vamomaxuei64.v v4, (a1), v8, v4, v0.t
  8045. + vamomaxuei64.v x0, (a1), v8, v4, v0.t
  8046. +
  8047. + vamoaddei64.v v4, 0(a1), v8, v4
  8048. + vamoaddei64.v x0, 0(a1), v8, v4
  8049. + vamoaddei64.v v4, 0(a1), v8, v4, v0.t
  8050. + vamoaddei64.v x0, 0(a1), v8, v4, v0.t
  8051. + vamoswapei64.v v4, 0(a1), v8, v4
  8052. + vamoswapei64.v x0, 0(a1), v8, v4
  8053. + vamoswapei64.v v4, 0(a1), v8, v4, v0.t
  8054. + vamoswapei64.v x0, 0(a1), v8, v4, v0.t
  8055. +
  8056. + vamoxorei64.v v4, 0(a1), v8, v4
  8057. + vamoxorei64.v x0, 0(a1), v8, v4
  8058. + vamoxorei64.v v4, 0(a1), v8, v4, v0.t
  8059. + vamoxorei64.v x0, 0(a1), v8, v4, v0.t
  8060. + vamoandei64.v v4, 0(a1), v8, v4
  8061. + vamoandei64.v x0, 0(a1), v8, v4
  8062. + vamoandei64.v v4, 0(a1), v8, v4, v0.t
  8063. + vamoandei64.v x0, 0(a1), v8, v4, v0.t
  8064. + vamoorei64.v v4, 0(a1), v8, v4
  8065. + vamoorei64.v x0, 0(a1), v8, v4
  8066. + vamoorei64.v v4, 0(a1), v8, v4, v0.t
  8067. + vamoorei64.v x0, 0(a1), v8, v4, v0.t
  8068. +
  8069. + vamominei64.v v4, 0(a1), v8, v4
  8070. + vamominei64.v x0, 0(a1), v8, v4
  8071. + vamominei64.v v4, 0(a1), v8, v4, v0.t
  8072. + vamominei64.v x0, 0(a1), v8, v4, v0.t
  8073. + vamomaxei64.v v4, 0(a1), v8, v4
  8074. + vamomaxei64.v x0, 0(a1), v8, v4
  8075. + vamomaxei64.v v4, 0(a1), v8, v4, v0.t
  8076. + vamomaxei64.v x0, 0(a1), v8, v4, v0.t
  8077. + vamominuei64.v v4, 0(a1), v8, v4
  8078. + vamominuei64.v x0, 0(a1), v8, v4
  8079. + vamominuei64.v v4, 0(a1), v8, v4, v0.t
  8080. + vamominuei64.v x0, 0(a1), v8, v4, v0.t
  8081. + vamomaxuei64.v v4, 0(a1), v8, v4
  8082. + vamomaxuei64.v x0, 0(a1), v8, v4
  8083. + vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
  8084. + vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
  8085. +
  8086. + vadd.vv v4, v8, v12
  8087. + vadd.vx v4, v8, a1
  8088. + vadd.vi v4, v8, 15
  8089. + vadd.vi v4, v8, -16
  8090. + vadd.vv v4, v8, v12, v0.t
  8091. + vadd.vx v4, v8, a1, v0.t
  8092. + vadd.vi v4, v8, 15, v0.t
  8093. + vadd.vi v4, v8, -16, v0.t
  8094. + vsub.vv v4, v8, v12
  8095. + vsub.vx v4, v8, a1
  8096. + vrsub.vx v4, v8, a1
  8097. + vrsub.vi v4, v8, 15
  8098. + vrsub.vi v4, v8, -16
  8099. + vsub.vv v4, v8, v12, v0.t
  8100. + vsub.vx v4, v8, a1, v0.t
  8101. + vrsub.vx v4, v8, a1, v0.t
  8102. + vrsub.vi v4, v8, 15, v0.t
  8103. + vrsub.vi v4, v8, -16, v0.t
  8104. +
  8105. + # Aliases
  8106. + vwcvt.x.x.v v4, v8
  8107. + vwcvtu.x.x.v v4, v8
  8108. + vwcvt.x.x.v v4, v8, v0.t
  8109. + vwcvtu.x.x.v v4, v8, v0.t
  8110. +
  8111. + vwaddu.vv v4, v8, v12
  8112. + vwaddu.vx v4, v8, a1
  8113. + vwaddu.vv v4, v8, v12, v0.t
  8114. + vwaddu.vx v4, v8, a1, v0.t
  8115. + vwsubu.vv v4, v8, v12
  8116. + vwsubu.vx v4, v8, a1
  8117. + vwsubu.vv v4, v8, v12, v0.t
  8118. + vwsubu.vx v4, v8, a1, v0.t
  8119. + vwadd.vv v4, v8, v12
  8120. + vwadd.vx v4, v8, a1
  8121. + vwadd.vv v4, v8, v12, v0.t
  8122. + vwadd.vx v4, v8, a1, v0.t
  8123. + vwsub.vv v4, v8, v12
  8124. + vwsub.vx v4, v8, a1
  8125. + vwsub.vv v4, v8, v12, v0.t
  8126. + vwsub.vx v4, v8, a1, v0.t
  8127. + vwaddu.wv v4, v8, v12
  8128. + vwaddu.wx v4, v8, a1
  8129. + vwaddu.wv v4, v8, v12, v0.t
  8130. + vwaddu.wx v4, v8, a1, v0.t
  8131. + vwsubu.wv v4, v8, v12
  8132. + vwsubu.wx v4, v8, a1
  8133. + vwsubu.wv v4, v8, v12, v0.t
  8134. + vwsubu.wx v4, v8, a1, v0.t
  8135. + vwadd.wv v4, v8, v12
  8136. + vwadd.wx v4, v8, a1
  8137. + vwadd.wv v4, v8, v12, v0.t
  8138. + vwadd.wx v4, v8, a1, v0.t
  8139. + vwsub.wv v4, v8, v12
  8140. + vwsub.wx v4, v8, a1
  8141. + vwsub.wv v4, v8, v12, v0.t
  8142. + vwsub.wx v4, v8, a1, v0.t
  8143. +
  8144. + vzext.vf2 v4, v8
  8145. + vzext.vf2 v4, v8, v0.t
  8146. + vsext.vf2 v4, v8
  8147. + vsext.vf2 v4, v8, v0.t
  8148. + vzext.vf4 v4, v8
  8149. + vzext.vf4 v4, v8, v0.t
  8150. + vsext.vf4 v4, v8
  8151. + vsext.vf4 v4, v8, v0.t
  8152. + vzext.vf8 v4, v8
  8153. + vzext.vf8 v4, v8, v0.t
  8154. + vsext.vf8 v4, v8
  8155. + vsext.vf8 v4, v8, v0.t
  8156. +
  8157. + vadc.vvm v4, v8, v12, v0
  8158. + vadc.vxm v4, v8, a1, v0
  8159. + vadc.vim v4, v8, 15, v0
  8160. + vadc.vim v4, v8, -16, v0
  8161. + vmadc.vvm v4, v8, v12, v0
  8162. + vmadc.vxm v4, v8, a1, v0
  8163. + vmadc.vim v4, v8, 15, v0
  8164. + vmadc.vim v4, v8, -16, v0
  8165. + vmadc.vv v4, v8, v12
  8166. + vmadc.vx v4, v8, a1
  8167. + vmadc.vi v4, v8, 15
  8168. + vmadc.vi v4, v8, -16
  8169. + vsbc.vvm v4, v8, v12, v0
  8170. + vsbc.vxm v4, v8, a1, v0
  8171. + vmsbc.vvm v4, v8, v12, v0
  8172. + vmsbc.vxm v4, v8, a1, v0
  8173. + vmsbc.vv v4, v8, v12
  8174. + vmsbc.vx v4, v8, a1
  8175. +
  8176. + # Aliases
  8177. + vnot.v v4, v8
  8178. + vnot.v v4, v8, v0.t
  8179. +
  8180. + vand.vv v4, v8, v12
  8181. + vand.vx v4, v8, a1
  8182. + vand.vi v4, v8, 15
  8183. + vand.vi v4, v8, -16
  8184. + vand.vv v4, v8, v12, v0.t
  8185. + vand.vx v4, v8, a1, v0.t
  8186. + vand.vi v4, v8, 15, v0.t
  8187. + vand.vi v4, v8, -16, v0.t
  8188. + vor.vv v4, v8, v12
  8189. + vor.vx v4, v8, a1
  8190. + vor.vi v4, v8, 15
  8191. + vor.vi v4, v8, -16
  8192. + vor.vv v4, v8, v12, v0.t
  8193. + vor.vx v4, v8, a1, v0.t
  8194. + vor.vi v4, v8, 15, v0.t
  8195. + vor.vi v4, v8, -16, v0.t
  8196. + vxor.vv v4, v8, v12
  8197. + vxor.vx v4, v8, a1
  8198. + vxor.vi v4, v8, 15
  8199. + vxor.vi v4, v8, -16
  8200. + vxor.vv v4, v8, v12, v0.t
  8201. + vxor.vx v4, v8, a1, v0.t
  8202. + vxor.vi v4, v8, 15, v0.t
  8203. + vxor.vi v4, v8, -16, v0.t
  8204. +
  8205. + vsll.vv v4, v8, v12
  8206. + vsll.vx v4, v8, a1
  8207. + vsll.vi v4, v8, 1
  8208. + vsll.vi v4, v8, 31
  8209. + vsll.vv v4, v8, v12, v0.t
  8210. + vsll.vx v4, v8, a1, v0.t
  8211. + vsll.vi v4, v8, 1, v0.t
  8212. + vsll.vi v4, v8, 31, v0.t
  8213. + vsrl.vv v4, v8, v12
  8214. + vsrl.vx v4, v8, a1
  8215. + vsrl.vi v4, v8, 1
  8216. + vsrl.vi v4, v8, 31
  8217. + vsrl.vv v4, v8, v12, v0.t
  8218. + vsrl.vx v4, v8, a1, v0.t
  8219. + vsrl.vi v4, v8, 1, v0.t
  8220. + vsrl.vi v4, v8, 31, v0.t
  8221. + vsra.vv v4, v8, v12
  8222. + vsra.vx v4, v8, a1
  8223. + vsra.vi v4, v8, 1
  8224. + vsra.vi v4, v8, 31
  8225. + vsra.vv v4, v8, v12, v0.t
  8226. + vsra.vx v4, v8, a1, v0.t
  8227. + vsra.vi v4, v8, 1, v0.t
  8228. + vsra.vi v4, v8, 31, v0.t
  8229. +
  8230. + vnsrl.wv v4, v8, v12
  8231. + vnsrl.wx v4, v8, a1
  8232. + vnsrl.wi v4, v8, 1
  8233. + vnsrl.wi v4, v8, 31
  8234. + vnsrl.wv v4, v8, v12, v0.t
  8235. + vnsrl.wx v4, v8, a1, v0.t
  8236. + vnsrl.wi v4, v8, 1, v0.t
  8237. + vnsrl.wi v4, v8, 31, v0.t
  8238. + vnsra.wv v4, v8, v12
  8239. + vnsra.wx v4, v8, a1
  8240. + vnsra.wi v4, v8, 1
  8241. + vnsra.wi v4, v8, 31
  8242. + vnsra.wv v4, v8, v12, v0.t
  8243. + vnsra.wx v4, v8, a1, v0.t
  8244. + vnsra.wi v4, v8, 1, v0.t
  8245. + vnsra.wi v4, v8, 31, v0.t
  8246. +
  8247. + # Aliases
  8248. + vmsgt.vv v4, v8, v12
  8249. + vmsgtu.vv v4, v8, v12
  8250. + vmsge.vv v4, v8, v12
  8251. + vmsgeu.vv v4, v8, v12
  8252. + vmsgt.vv v4, v8, v12, v0.t
  8253. + vmsgtu.vv v4, v8, v12, v0.t
  8254. + vmsge.vv v4, v8, v12, v0.t
  8255. + vmsgeu.vv v4, v8, v12, v0.t
  8256. + vmslt.vi v4, v8, 16
  8257. + vmslt.vi v4, v8, -15
  8258. + vmsltu.vi v4, v8, 16
  8259. + vmsltu.vi v4, v8, -15
  8260. + vmsge.vi v4, v8, 16
  8261. + vmsge.vi v4, v8, -15
  8262. + vmsgeu.vi v4, v8, 16
  8263. + vmsgeu.vi v4, v8, -15
  8264. + vmslt.vi v4, v8, 16, v0.t
  8265. + vmslt.vi v4, v8, -15, v0.t
  8266. + vmsltu.vi v4, v8, 16, v0.t
  8267. + vmsltu.vi v4, v8, -15, v0.t
  8268. + vmsge.vi v4, v8, 16, v0.t
  8269. + vmsge.vi v4, v8, -15, v0.t
  8270. + vmsgeu.vi v4, v8, 16, v0.t
  8271. + vmsgeu.vi v4, v8, -15, v0.t
  8272. +
  8273. + vmseq.vv v4, v8, v12
  8274. + vmseq.vx v4, v8, a1
  8275. + vmseq.vi v4, v8, 15
  8276. + vmseq.vi v4, v8, -16
  8277. + vmseq.vv v4, v8, v12, v0.t
  8278. + vmseq.vx v4, v8, a1, v0.t
  8279. + vmseq.vi v4, v8, 15, v0.t
  8280. + vmseq.vi v4, v8, -16, v0.t
  8281. + vmsne.vv v4, v8, v12
  8282. + vmsne.vx v4, v8, a1
  8283. + vmsne.vi v4, v8, 15
  8284. + vmsne.vi v4, v8, -16
  8285. + vmsne.vv v4, v8, v12, v0.t
  8286. + vmsne.vx v4, v8, a1, v0.t
  8287. + vmsne.vi v4, v8, 15, v0.t
  8288. + vmsne.vi v4, v8, -16, v0.t
  8289. + vmsltu.vv v4, v8, v12
  8290. + vmsltu.vx v4, v8, a1
  8291. + vmsltu.vv v4, v8, v12, v0.t
  8292. + vmsltu.vx v4, v8, a1, v0.t
  8293. + vmslt.vv v4, v8, v12
  8294. + vmslt.vx v4, v8, a1
  8295. + vmslt.vv v4, v8, v12, v0.t
  8296. + vmslt.vx v4, v8, a1, v0.t
  8297. + vmsleu.vv v4, v8, v12
  8298. + vmsleu.vx v4, v8, a1
  8299. + vmsleu.vi v4, v8, 15
  8300. + vmsleu.vi v4, v8, -16
  8301. + vmsleu.vv v4, v8, v12, v0.t
  8302. + vmsleu.vx v4, v8, a1, v0.t
  8303. + vmsleu.vi v4, v8, 15, v0.t
  8304. + vmsleu.vi v4, v8, -16, v0.t
  8305. + vmsle.vv v4, v8, v12
  8306. + vmsle.vx v4, v8, a1
  8307. + vmsle.vi v4, v8, 15
  8308. + vmsle.vi v4, v8, -16
  8309. + vmsle.vv v4, v8, v12, v0.t
  8310. + vmsle.vx v4, v8, a1, v0.t
  8311. + vmsle.vi v4, v8, 15, v0.t
  8312. + vmsle.vi v4, v8, -16, v0.t
  8313. + vmsgtu.vx v4, v8, a1
  8314. + vmsgtu.vi v4, v8, 15
  8315. + vmsgtu.vi v4, v8, -16
  8316. + vmsgtu.vx v4, v8, a1, v0.t
  8317. + vmsgtu.vi v4, v8, 15, v0.t
  8318. + vmsgtu.vi v4, v8, -16, v0.t
  8319. + vmsgt.vx v4, v8, a1
  8320. + vmsgt.vi v4, v8, 15
  8321. + vmsgt.vi v4, v8, -16
  8322. + vmsgt.vx v4, v8, a1, v0.t
  8323. + vmsgt.vi v4, v8, 15, v0.t
  8324. + vmsgt.vi v4, v8, -16, v0.t
  8325. +
  8326. + vminu.vv v4, v8, v12
  8327. + vminu.vx v4, v8, a1
  8328. + vminu.vv v4, v8, v12, v0.t
  8329. + vminu.vx v4, v8, a1, v0.t
  8330. + vmin.vv v4, v8, v12
  8331. + vmin.vx v4, v8, a1
  8332. + vmin.vv v4, v8, v12, v0.t
  8333. + vmin.vx v4, v8, a1, v0.t
  8334. + vmaxu.vv v4, v8, v12
  8335. + vmaxu.vx v4, v8, a1
  8336. + vmaxu.vv v4, v8, v12, v0.t
  8337. + vmaxu.vx v4, v8, a1, v0.t
  8338. + vmax.vv v4, v8, v12
  8339. + vmax.vx v4, v8, a1
  8340. + vmax.vv v4, v8, v12, v0.t
  8341. + vmax.vx v4, v8, a1, v0.t
  8342. +
  8343. + vmul.vv v4, v8, v12
  8344. + vmul.vx v4, v8, a1
  8345. + vmul.vv v4, v8, v12, v0.t
  8346. + vmul.vx v4, v8, a1, v0.t
  8347. + vmulh.vv v4, v8, v12
  8348. + vmulh.vx v4, v8, a1
  8349. + vmulh.vv v4, v8, v12, v0.t
  8350. + vmulh.vx v4, v8, a1, v0.t
  8351. + vmulhu.vv v4, v8, v12
  8352. + vmulhu.vx v4, v8, a1
  8353. + vmulhu.vv v4, v8, v12, v0.t
  8354. + vmulhu.vx v4, v8, a1, v0.t
  8355. + vmulhsu.vv v4, v8, v12
  8356. + vmulhsu.vx v4, v8, a1
  8357. + vmulhsu.vv v4, v8, v12, v0.t
  8358. + vmulhsu.vx v4, v8, a1, v0.t
  8359. +
  8360. + vwmul.vv v4, v8, v12
  8361. + vwmul.vx v4, v8, a1
  8362. + vwmul.vv v4, v8, v12, v0.t
  8363. + vwmul.vx v4, v8, a1, v0.t
  8364. + vwmulu.vv v4, v8, v12
  8365. + vwmulu.vx v4, v8, a1
  8366. + vwmulu.vv v4, v8, v12, v0.t
  8367. + vwmulu.vx v4, v8, a1, v0.t
  8368. + vwmulsu.vv v4, v8, v12
  8369. + vwmulsu.vx v4, v8, a1
  8370. + vwmulsu.vv v4, v8, v12, v0.t
  8371. + vwmulsu.vx v4, v8, a1, v0.t
  8372. +
  8373. + vmacc.vv v4, v12, v8
  8374. + vmacc.vx v4, a1, v8
  8375. + vmacc.vv v4, v12, v8, v0.t
  8376. + vmacc.vx v4, a1, v8, v0.t
  8377. + vnmsac.vv v4, v12, v8
  8378. + vnmsac.vx v4, a1, v8
  8379. + vnmsac.vv v4, v12, v8, v0.t
  8380. + vnmsac.vx v4, a1, v8, v0.t
  8381. + vmadd.vv v4, v12, v8
  8382. + vmadd.vx v4, a1, v8
  8383. + vmadd.vv v4, v12, v8, v0.t
  8384. + vmadd.vx v4, a1, v8, v0.t
  8385. + vnmsub.vv v4, v12, v8
  8386. + vnmsub.vx v4, a1, v8
  8387. + vnmsub.vv v4, v12, v8, v0.t
  8388. + vnmsub.vx v4, a1, v8, v0.t
  8389. +
  8390. + vwmaccu.vv v4, v12, v8
  8391. + vwmaccu.vx v4, a1, v8
  8392. + vwmaccu.vv v4, v12, v8, v0.t
  8393. + vwmaccu.vx v4, a1, v8, v0.t
  8394. + vwmacc.vv v4, v12, v8
  8395. + vwmacc.vx v4, a1, v8
  8396. + vwmacc.vv v4, v12, v8, v0.t
  8397. + vwmacc.vx v4, a1, v8, v0.t
  8398. + vwmaccsu.vv v4, v12, v8
  8399. + vwmaccsu.vx v4, a1, v8
  8400. + vwmaccsu.vv v4, v12, v8, v0.t
  8401. + vwmaccsu.vx v4, a1, v8, v0.t
  8402. + vwmaccus.vx v4, a1, v8
  8403. + vwmaccus.vx v4, a1, v8, v0.t
  8404. +
  8405. + vqmaccu.vv v4, v12, v8
  8406. + vqmaccu.vx v4, a1, v8
  8407. + vqmaccu.vv v4, v12, v8, v0.t
  8408. + vqmaccu.vx v4, a1, v8, v0.t
  8409. + vqmacc.vv v4, v12, v8
  8410. + vqmacc.vx v4, a1, v8
  8411. + vqmacc.vv v4, v12, v8, v0.t
  8412. + vqmacc.vx v4, a1, v8, v0.t
  8413. + vqmaccsu.vv v4, v12, v8
  8414. + vqmaccsu.vx v4, a1, v8
  8415. + vqmaccsu.vv v4, v12, v8, v0.t
  8416. + vqmaccsu.vx v4, a1, v8, v0.t
  8417. + vqmaccus.vx v4, a1, v8
  8418. + vqmaccus.vx v4, a1, v8, v0.t
  8419. +
  8420. + vdivu.vv v4, v8, v12
  8421. + vdivu.vx v4, v8, a1
  8422. + vdivu.vv v4, v8, v12, v0.t
  8423. + vdivu.vx v4, v8, a1, v0.t
  8424. + vdiv.vv v4, v8, v12
  8425. + vdiv.vx v4, v8, a1
  8426. + vdiv.vv v4, v8, v12, v0.t
  8427. + vdiv.vx v4, v8, a1, v0.t
  8428. + vremu.vv v4, v8, v12
  8429. + vremu.vx v4, v8, a1
  8430. + vremu.vv v4, v8, v12, v0.t
  8431. + vremu.vx v4, v8, a1, v0.t
  8432. + vrem.vv v4, v8, v12
  8433. + vrem.vx v4, v8, a1
  8434. + vrem.vv v4, v8, v12, v0.t
  8435. + vrem.vx v4, v8, a1, v0.t
  8436. +
  8437. + vmerge.vvm v4, v8, v12, v0
  8438. + vmerge.vxm v4, v8, a1, v0
  8439. + vmerge.vim v4, v8, 15, v0
  8440. + vmerge.vim v4, v8, -16, v0
  8441. +
  8442. + vmv.v.v v8, v12
  8443. + vmv.v.x v8, a1
  8444. + vmv.v.i v8, 15
  8445. + vmv.v.i v8, -16
  8446. +
  8447. + vsaddu.vv v4, v8, v12
  8448. + vsaddu.vx v4, v8, a1
  8449. + vsaddu.vi v4, v8, 15
  8450. + vsaddu.vi v4, v8, -16
  8451. + vsaddu.vv v4, v8, v12, v0.t
  8452. + vsaddu.vx v4, v8, a1, v0.t
  8453. + vsaddu.vi v4, v8, 15, v0.t
  8454. + vsaddu.vi v4, v8, -16, v0.t
  8455. + vsadd.vv v4, v8, v12
  8456. + vsadd.vx v4, v8, a1
  8457. + vsadd.vi v4, v8, 15
  8458. + vsadd.vi v4, v8, -16
  8459. + vsadd.vv v4, v8, v12, v0.t
  8460. + vsadd.vx v4, v8, a1, v0.t
  8461. + vsadd.vi v4, v8, 15, v0.t
  8462. + vsadd.vi v4, v8, -16, v0.t
  8463. + vssubu.vv v4, v8, v12
  8464. + vssubu.vx v4, v8, a1
  8465. + vssubu.vv v4, v8, v12, v0.t
  8466. + vssubu.vx v4, v8, a1, v0.t
  8467. + vssub.vv v4, v8, v12
  8468. + vssub.vx v4, v8, a1
  8469. + vssub.vv v4, v8, v12, v0.t
  8470. + vssub.vx v4, v8, a1, v0.t
  8471. +
  8472. + vaaddu.vv v4, v8, v12
  8473. + vaaddu.vx v4, v8, a1
  8474. + vaaddu.vv v4, v8, v12, v0.t
  8475. + vaaddu.vx v4, v8, a1, v0.t
  8476. + vaadd.vv v4, v8, v12
  8477. + vaadd.vx v4, v8, a1
  8478. + vaadd.vv v4, v8, v12, v0.t
  8479. + vaadd.vx v4, v8, a1, v0.t
  8480. + vasubu.vv v4, v8, v12
  8481. + vasubu.vx v4, v8, a1
  8482. + vasubu.vv v4, v8, v12, v0.t
  8483. + vasubu.vx v4, v8, a1, v0.t
  8484. + vasub.vv v4, v8, v12
  8485. + vasub.vx v4, v8, a1
  8486. + vasub.vv v4, v8, v12, v0.t
  8487. + vasub.vx v4, v8, a1, v0.t
  8488. +
  8489. + vsmul.vv v4, v8, v12
  8490. + vsmul.vx v4, v8, a1
  8491. + vsmul.vv v4, v8, v12, v0.t
  8492. + vsmul.vx v4, v8, a1, v0.t
  8493. +
  8494. + vssrl.vv v4, v8, v12
  8495. + vssrl.vx v4, v8, a1
  8496. + vssrl.vi v4, v8, 1
  8497. + vssrl.vi v4, v8, 31
  8498. + vssrl.vv v4, v8, v12, v0.t
  8499. + vssrl.vx v4, v8, a1, v0.t
  8500. + vssrl.vi v4, v8, 1, v0.t
  8501. + vssrl.vi v4, v8, 31, v0.t
  8502. + vssra.vv v4, v8, v12
  8503. + vssra.vx v4, v8, a1
  8504. + vssra.vi v4, v8, 1
  8505. + vssra.vi v4, v8, 31
  8506. + vssra.vv v4, v8, v12, v0.t
  8507. + vssra.vx v4, v8, a1, v0.t
  8508. + vssra.vi v4, v8, 1, v0.t
  8509. + vssra.vi v4, v8, 31, v0.t
  8510. +
  8511. + vnclipu.wv v4, v8, v12
  8512. + vnclipu.wx v4, v8, a1
  8513. + vnclipu.wi v4, v8, 1
  8514. + vnclipu.wi v4, v8, 31
  8515. + vnclipu.wv v4, v8, v12, v0.t
  8516. + vnclipu.wx v4, v8, a1, v0.t
  8517. + vnclipu.wi v4, v8, 1, v0.t
  8518. + vnclipu.wi v4, v8, 31, v0.t
  8519. + vnclip.wv v4, v8, v12
  8520. + vnclip.wx v4, v8, a1
  8521. + vnclip.wi v4, v8, 1
  8522. + vnclip.wi v4, v8, 31
  8523. + vnclip.wv v4, v8, v12, v0.t
  8524. + vnclip.wx v4, v8, a1, v0.t
  8525. + vnclip.wi v4, v8, 1, v0.t
  8526. + vnclip.wi v4, v8, 31, v0.t
  8527. +
  8528. + vfadd.vv v4, v8, v12
  8529. + vfadd.vf v4, v8, fa2
  8530. + vfadd.vv v4, v8, v12, v0.t
  8531. + vfadd.vf v4, v8, fa2, v0.t
  8532. + vfsub.vv v4, v8, v12
  8533. + vfsub.vf v4, v8, fa2
  8534. + vfsub.vv v4, v8, v12, v0.t
  8535. + vfsub.vf v4, v8, fa2, v0.t
  8536. + vfrsub.vf v4, v8, fa2
  8537. + vfrsub.vf v4, v8, fa2, v0.t
  8538. +
  8539. + vfwadd.vv v4, v8, v12
  8540. + vfwadd.vf v4, v8, fa2
  8541. + vfwadd.vv v4, v8, v12, v0.t
  8542. + vfwadd.vf v4, v8, fa2, v0.t
  8543. + vfwsub.vv v4, v8, v12
  8544. + vfwsub.vf v4, v8, fa2
  8545. + vfwsub.vv v4, v8, v12, v0.t
  8546. + vfwsub.vf v4, v8, fa2, v0.t
  8547. + vfwadd.wv v4, v8, v12
  8548. + vfwadd.wf v4, v8, fa2
  8549. + vfwadd.wv v4, v8, v12, v0.t
  8550. + vfwadd.wf v4, v8, fa2, v0.t
  8551. + vfwsub.wv v4, v8, v12
  8552. + vfwsub.wf v4, v8, fa2
  8553. + vfwsub.wv v4, v8, v12, v0.t
  8554. + vfwsub.wf v4, v8, fa2, v0.t
  8555. +
  8556. + vfmul.vv v4, v8, v12
  8557. + vfmul.vf v4, v8, fa2
  8558. + vfmul.vv v4, v8, v12, v0.t
  8559. + vfmul.vf v4, v8, fa2, v0.t
  8560. + vfdiv.vv v4, v8, v12
  8561. + vfdiv.vf v4, v8, fa2
  8562. + vfdiv.vv v4, v8, v12, v0.t
  8563. + vfdiv.vf v4, v8, fa2, v0.t
  8564. + vfrdiv.vf v4, v8, fa2
  8565. + vfrdiv.vf v4, v8, fa2, v0.t
  8566. +
  8567. + vfwmul.vv v4, v8, v12
  8568. + vfwmul.vf v4, v8, fa2
  8569. + vfwmul.vv v4, v8, v12, v0.t
  8570. + vfwmul.vf v4, v8, fa2, v0.t
  8571. +
  8572. + vfmadd.vv v4, v12, v8
  8573. + vfmadd.vf v4, fa2, v8
  8574. + vfnmadd.vv v4, v12, v8
  8575. + vfnmadd.vf v4, fa2, v8
  8576. + vfmsub.vv v4, v12, v8
  8577. + vfmsub.vf v4, fa2, v8
  8578. + vfnmsub.vv v4, v12, v8
  8579. + vfnmsub.vf v4, fa2, v8
  8580. + vfmadd.vv v4, v12, v8, v0.t
  8581. + vfmadd.vf v4, fa2, v8, v0.t
  8582. + vfnmadd.vv v4, v12, v8, v0.t
  8583. + vfnmadd.vf v4, fa2, v8, v0.t
  8584. + vfmsub.vv v4, v12, v8, v0.t
  8585. + vfmsub.vf v4, fa2, v8, v0.t
  8586. + vfnmsub.vv v4, v12, v8, v0.t
  8587. + vfnmsub.vf v4, fa2, v8, v0.t
  8588. + vfmacc.vv v4, v12, v8
  8589. + vfmacc.vf v4, fa2, v8
  8590. + vfnmacc.vv v4, v12, v8
  8591. + vfnmacc.vf v4, fa2, v8
  8592. + vfmsac.vv v4, v12, v8
  8593. + vfmsac.vf v4, fa2, v8
  8594. + vfnmsac.vv v4, v12, v8
  8595. + vfnmsac.vf v4, fa2, v8
  8596. + vfmacc.vv v4, v12, v8, v0.t
  8597. + vfmacc.vf v4, fa2, v8, v0.t
  8598. + vfnmacc.vv v4, v12, v8, v0.t
  8599. + vfnmacc.vf v4, fa2, v8, v0.t
  8600. + vfmsac.vv v4, v12, v8, v0.t
  8601. + vfmsac.vf v4, fa2, v8, v0.t
  8602. + vfnmsac.vv v4, v12, v8, v0.t
  8603. + vfnmsac.vf v4, fa2, v8, v0.t
  8604. +
  8605. + vfwmacc.vv v4, v12, v8
  8606. + vfwmacc.vf v4, fa2, v8
  8607. + vfwnmacc.vv v4, v12, v8
  8608. + vfwnmacc.vf v4, fa2, v8
  8609. + vfwmsac.vv v4, v12, v8
  8610. + vfwmsac.vf v4, fa2, v8
  8611. + vfwnmsac.vv v4, v12, v8
  8612. + vfwnmsac.vf v4, fa2, v8
  8613. + vfwmacc.vv v4, v12, v8, v0.t
  8614. + vfwmacc.vf v4, fa2, v8, v0.t
  8615. + vfwnmacc.vv v4, v12, v8, v0.t
  8616. + vfwnmacc.vf v4, fa2, v8, v0.t
  8617. + vfwmsac.vv v4, v12, v8, v0.t
  8618. + vfwmsac.vf v4, fa2, v8, v0.t
  8619. + vfwnmsac.vv v4, v12, v8, v0.t
  8620. + vfwnmsac.vf v4, fa2, v8, v0.t
  8621. +
  8622. + vfsqrt.v v4, v8
  8623. + vfsqrt.v v4, v8, v0.t
  8624. +
  8625. + vfmin.vv v4, v8, v12
  8626. + vfmin.vf v4, v8, fa2
  8627. + vfmax.vv v4, v8, v12
  8628. + vfmax.vf v4, v8, fa2
  8629. + vfmin.vv v4, v8, v12, v0.t
  8630. + vfmin.vf v4, v8, fa2, v0.t
  8631. + vfmax.vv v4, v8, v12, v0.t
  8632. + vfmax.vf v4, v8, fa2, v0.t
  8633. +
  8634. + vfsgnj.vv v4, v8, v12
  8635. + vfsgnj.vf v4, v8, fa2
  8636. + vfsgnjn.vv v4, v8, v12
  8637. + vfsgnjn.vf v4, v8, fa2
  8638. + vfsgnjx.vv v4, v8, v12
  8639. + vfsgnjx.vf v4, v8, fa2
  8640. + vfsgnj.vv v4, v8, v12, v0.t
  8641. + vfsgnj.vf v4, v8, fa2, v0.t
  8642. + vfsgnjn.vv v4, v8, v12, v0.t
  8643. + vfsgnjn.vf v4, v8, fa2, v0.t
  8644. + vfsgnjx.vv v4, v8, v12, v0.t
  8645. + vfsgnjx.vf v4, v8, fa2, v0.t
  8646. +
  8647. + # Aliases
  8648. + vmfgt.vv v4, v8, v12
  8649. + vmfge.vv v4, v8, v12
  8650. + vmfgt.vv v4, v8, v12, v0.t
  8651. + vmfge.vv v4, v8, v12, v0.t
  8652. +
  8653. + vmfeq.vv v4, v8, v12
  8654. + vmfeq.vf v4, v8, fa2
  8655. + vmfne.vv v4, v8, v12
  8656. + vmfne.vf v4, v8, fa2
  8657. + vmflt.vv v4, v8, v12
  8658. + vmflt.vf v4, v8, fa2
  8659. + vmfle.vv v4, v8, v12
  8660. + vmfle.vf v4, v8, fa2
  8661. + vmfgt.vf v4, v8, fa2
  8662. + vmfge.vf v4, v8, fa2
  8663. + vmfeq.vv v4, v8, v12, v0.t
  8664. + vmfeq.vf v4, v8, fa2, v0.t
  8665. + vmfne.vv v4, v8, v12, v0.t
  8666. + vmfne.vf v4, v8, fa2, v0.t
  8667. + vmflt.vv v4, v8, v12, v0.t
  8668. + vmflt.vf v4, v8, fa2, v0.t
  8669. + vmfle.vv v4, v8, v12, v0.t
  8670. + vmfle.vf v4, v8, fa2, v0.t
  8671. + vmfgt.vf v4, v8, fa2, v0.t
  8672. + vmfge.vf v4, v8, fa2, v0.t
  8673. +
  8674. + vfclass.v v4, v8
  8675. + vfclass.v v4, v8, v0.t
  8676. +
  8677. + vfmerge.vfm v4, v8, fa2, v0
  8678. + vfmv.v.f v4, fa1
  8679. +
  8680. + vfcvt.xu.f.v v4, v8
  8681. + vfcvt.x.f.v v4, v8
  8682. + vfcvt.rtz.xu.f.v v4, v8
  8683. + vfcvt.rtz.x.f.v v4, v8
  8684. + vfcvt.f.xu.v v4, v8
  8685. + vfcvt.f.x.v v4, v8
  8686. + vfcvt.xu.f.v v4, v8, v0.t
  8687. + vfcvt.x.f.v v4, v8, v0.t
  8688. + vfcvt.rtz.xu.f.v v4, v8, v0.t
  8689. + vfcvt.rtz.x.f.v v4, v8, v0.t
  8690. + vfcvt.f.xu.v v4, v8, v0.t
  8691. + vfcvt.f.x.v v4, v8, v0.t
  8692. +
  8693. + vfwcvt.xu.f.v v4, v8
  8694. + vfwcvt.x.f.v v4, v8
  8695. + vfwcvt.rtz.xu.f.v v4, v8
  8696. + vfwcvt.rtz.x.f.v v4, v8
  8697. + vfwcvt.f.xu.v v4, v8
  8698. + vfwcvt.f.x.v v4, v8
  8699. + vfwcvt.f.f.v v4, v8
  8700. + vfwcvt.xu.f.v v4, v8, v0.t
  8701. + vfwcvt.x.f.v v4, v8, v0.t
  8702. + vfwcvt.rtz.xu.f.v v4, v8, v0.t
  8703. + vfwcvt.rtz.x.f.v v4, v8, v0.t
  8704. + vfwcvt.f.xu.v v4, v8, v0.t
  8705. + vfwcvt.f.x.v v4, v8, v0.t
  8706. + vfwcvt.f.f.v v4, v8, v0.t
  8707. +
  8708. + vfncvt.xu.f.w v4, v8
  8709. + vfncvt.x.f.w v4, v8
  8710. + vfncvt.rtz.xu.f.w v4, v8
  8711. + vfncvt.rtz.x.f.w v4, v8
  8712. + vfncvt.f.xu.w v4, v8
  8713. + vfncvt.f.x.w v4, v8
  8714. + vfncvt.f.f.w v4, v8
  8715. + vfncvt.rod.f.f.w v4, v8
  8716. + vfncvt.xu.f.w v4, v8, v0.t
  8717. + vfncvt.x.f.w v4, v8, v0.t
  8718. + vfncvt.rtz.xu.f.w v4, v8, v0.t
  8719. + vfncvt.rtz.x.f.w v4, v8, v0.t
  8720. + vfncvt.f.xu.w v4, v8, v0.t
  8721. + vfncvt.f.x.w v4, v8, v0.t
  8722. + vfncvt.f.f.w v4, v8, v0.t
  8723. + vfncvt.rod.f.f.w v4, v8, v0.t
  8724. +
  8725. + vredsum.vs v4, v8, v12
  8726. + vredmaxu.vs v4, v8, v8
  8727. + vredmax.vs v4, v8, v8
  8728. + vredminu.vs v4, v8, v8
  8729. + vredmin.vs v4, v8, v8
  8730. + vredand.vs v4, v8, v12
  8731. + vredor.vs v4, v8, v12
  8732. + vredxor.vs v4, v8, v12
  8733. + vredsum.vs v4, v8, v12, v0.t
  8734. + vredmaxu.vs v4, v8, v8, v0.t
  8735. + vredmax.vs v4, v8, v8, v0.t
  8736. + vredminu.vs v4, v8, v8, v0.t
  8737. + vredmin.vs v4, v8, v8, v0.t
  8738. + vredand.vs v4, v8, v12, v0.t
  8739. + vredor.vs v4, v8, v12, v0.t
  8740. + vredxor.vs v4, v8, v12, v0.t
  8741. +
  8742. + vwredsumu.vs v4, v8, v12
  8743. + vwredsum.vs v4, v8, v12
  8744. + vwredsumu.vs v4, v8, v12, v0.t
  8745. + vwredsum.vs v4, v8, v12, v0.t
  8746. +
  8747. + vfredosum.vs v4, v8, v12
  8748. + vfredsum.vs v4, v8, v12
  8749. + vfredmax.vs v4, v8, v12
  8750. + vfredmin.vs v4, v8, v12
  8751. + vfredosum.vs v4, v8, v12, v0.t
  8752. + vfredsum.vs v4, v8, v12, v0.t
  8753. + vfredmax.vs v4, v8, v12, v0.t
  8754. + vfredmin.vs v4, v8, v12, v0.t
  8755. +
  8756. + vfwredosum.vs v4, v8, v12
  8757. + vfwredsum.vs v4, v8, v12
  8758. + vfwredosum.vs v4, v8, v12, v0.t
  8759. + vfwredsum.vs v4, v8, v12, v0.t
  8760. +
  8761. + # Aliases
  8762. + vmcpy.m v4, v8
  8763. + vmmv.m v4, v8
  8764. + vmclr.m v4
  8765. + vmset.m v4
  8766. + vmnot.m v4, v8
  8767. +
  8768. + vmand.mm v4, v8, v12
  8769. + vmnand.mm v4, v8, v12
  8770. + vmandnot.mm v4, v8, v12
  8771. + vmxor.mm v4, v8, v12
  8772. + vmor.mm v4, v8, v12
  8773. + vmnor.mm v4, v8, v12
  8774. + vmornot.mm v4, v8, v12
  8775. + vmxnor.mm v4, v8, v12
  8776. +
  8777. + vpopc.m a0, v12
  8778. + vfirst.m a0, v12
  8779. + vmsbf.m v4, v8
  8780. + vmsif.m v4, v8
  8781. + vmsof.m v4, v8
  8782. + viota.m v4, v8
  8783. + vid.v v4
  8784. + vpopc.m a0, v12, v0.t
  8785. + vfirst.m a0, v12, v0.t
  8786. + vmsbf.m v4, v8, v0.t
  8787. + vmsif.m v4, v8, v0.t
  8788. + vmsof.m v4, v8, v0.t
  8789. + viota.m v4, v8, v0.t
  8790. + vid.v v4, v0.t
  8791. +
  8792. + vmv.x.s a0, v12
  8793. + vmv.s.x v4, a0
  8794. +
  8795. + vfmv.f.s fa0, v8
  8796. + vfmv.s.f v4, fa1
  8797. +
  8798. + vslideup.vx v4, v8, a1
  8799. + vslideup.vi v4, v8, 0
  8800. + vslideup.vi v4, v8, 31
  8801. + vslidedown.vx v4, v8, a1
  8802. + vslidedown.vi v4, v8, 0
  8803. + vslidedown.vi v4, v8, 31
  8804. + vslideup.vx v4, v8, a1, v0.t
  8805. + vslideup.vi v4, v8, 0, v0.t
  8806. + vslideup.vi v4, v8, 31, v0.t
  8807. + vslidedown.vx v4, v8, a1, v0.t
  8808. + vslidedown.vi v4, v8, 0, v0.t
  8809. + vslidedown.vi v4, v8, 31, v0.t
  8810. +
  8811. + vslide1up.vx v4, v8, a1
  8812. + vslide1down.vx v4, v8, a1
  8813. + vslide1up.vx v4, v8, a1, v0.t
  8814. + vslide1down.vx v4, v8, a1, v0.t
  8815. +
  8816. + vfslide1up.vf v4, v8, fa1
  8817. + vfslide1down.vf v4, v8, fa1
  8818. + vfslide1up.vf v4, v8, fa1, v0.t
  8819. + vfslide1down.vf v4, v8, fa1, v0.t
  8820. +
  8821. + vrgather.vv v4, v8, v12
  8822. + vrgather.vx v4, v8, a1
  8823. + vrgather.vi v4, v8, 0
  8824. + vrgather.vi v4, v8, 31
  8825. + vrgather.vv v4, v8, v12, v0.t
  8826. + vrgather.vx v4, v8, a1, v0.t
  8827. + vrgather.vi v4, v8, 0, v0.t
  8828. + vrgather.vi v4, v8, 31, v0.t
  8829. +
  8830. + vcompress.vm v4, v8, v12
  8831. +
  8832. + vmv1r.v v1, v2
  8833. + vmv2r.v v2, v4
  8834. + vmv4r.v v4, v8
  8835. + vmv8r.v v0, v8
  8836. +
  8837. + vdot.vv v4, v8, v12
  8838. + vdotu.vv v4, v8, v12
  8839. + vfdot.vv v4, v8, v12
  8840. + vdot.vv v4, v8, v12, v0.t
  8841. + vdotu.vv v4, v8, v12, v0.t
  8842. + vfdot.vv v4, v8, v12, v0.t
  8843. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  8844. index 158de32485..6ec4c2a33a 100644
  8845. --- a/include/opcode/riscv-opc.h
  8846. +++ b/include/opcode/riscv-opc.h
  8847. @@ -547,6 +547,2130 @@
  8848. #define MASK_C_LDSP 0xe003
  8849. #define MATCH_C_SDSP 0xe002
  8850. #define MASK_C_SDSP 0xe003
  8851. +
  8852. +/* RVV */
  8853. +/* Version 1.0-draft-20200516. */
  8854. +
  8855. +#define MATCH_VSETVL 0x80007057
  8856. +#define MASK_VSETVL 0xfe00707f
  8857. +#define MATCH_VSETVLI 0x00007057
  8858. +#define MASK_VSETVLI 0x8000707f
  8859. +
  8860. +/* Temporary Load/store encoding info
  8861. +MOP load
  8862. +00 unit-stride VLE<EEW>, VLE<EEW>FF, VL<nf>RV (nf = 1)
  8863. +01 reserved
  8864. +10 strided VLSE<EEW>
  8865. +11 indexed VLXEI<EEW>
  8866. +
  8867. +MOP store
  8868. +00 unit-stride VSE<EEW>, VS<nf>RV (nf = 1)
  8869. +01 indexed-unordered VSUXEI<EEW>
  8870. +10 strided VSSE<EEW>
  8871. +11 indexed-ordered VSXEI<EEW>
  8872. +
  8873. +VM 0 masked
  8874. +VM 1 unmasked
  8875. +
  8876. +LUMOP
  8877. +00000 unit-stride
  8878. +00xxx reserved, x!=0
  8879. +01000 unit-stride, whole registers
  8880. +01xxx reserved, x!=0
  8881. +10000 unit-stride first-fault
  8882. +1xxxx reserved, x!=0
  8883. +
  8884. +SUMOP
  8885. +00000 unit-stride
  8886. +00xxx reserved, x!=0
  8887. +01000 unit-stride, whole registers
  8888. +01xxx reserved, x!=0
  8889. +1xxxx reserved
  8890. +
  8891. +MEW WIDTH
  8892. +- ---
  8893. +x 001 FLH/FSH
  8894. +x 010 FLW/FSW
  8895. +x 011 FLD/FSW
  8896. +x 100 FLQ/FSQ
  8897. +0 000 VLxE8/VSxE8
  8898. +0 101 VLxE16/VSxE16
  8899. +0 110 VLxE32/VSxE32
  8900. +0 111 VLxE64/VSxE64
  8901. +1 000 VLxE128/VSxE128
  8902. +1 101 VLxE256/VSxE256
  8903. +1 110 VLxE512/VSxE512
  8904. +1 111 VLxE1024/VSxE1024
  8905. +
  8906. +NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
  8907. +000 - 00 x 00000 xxxxx --- xxxxx 0000111 VLE<EEW>
  8908. +000 - 00 x 00000 xxxxx --- xxxxx 0100111 VSE<EEW>
  8909. +000 - 10 x xxxxx xxxxx --- xxxxx 0000111 VLSE<EEW>
  8910. +000 - 10 x xxxxx xxxxx --- xxxxx 0100111 VSSE<EEW>
  8911. +000 - 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
  8912. +000 - 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
  8913. +000 - 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
  8914. +000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
  8915. +000 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1
  8916. +000 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1
  8917. +
  8918. +xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
  8919. +xxx - 00 x 00000 xxxxx --- xxxxx 0100111 VSSEG<nf>E<EEW>
  8920. +xxx - 10 x 00000 xxxxx --- xxxxx 0000111 VLSSEG<nf>E<EEW>
  8921. +xxx - 10 x 00000 xxxxx --- xxxxx 0100111 VSSSEG<nf>E<EEW>
  8922. +xxx - 11 x 00000 xxxxx --- xxxxx 0000111 VLXSEG<nf>E<EEW>I
  8923. +xxx - 11 x 00000 xxxxx --- xxxxx 0100111 VSXSEG<nf>E<EEW>I
  8924. +xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
  8925. +*/
  8926. +
  8927. +#define MATCH_VLE8V 0x00000007
  8928. +#define MASK_VLE8V 0xfdf0707f
  8929. +#define MATCH_VLE16V 0x00005007
  8930. +#define MASK_VLE16V 0xfdf0707f
  8931. +#define MATCH_VLE32V 0x00006007
  8932. +#define MASK_VLE32V 0xfdf0707f
  8933. +#define MATCH_VLE64V 0x00007007
  8934. +#define MASK_VLE64V 0xfdf0707f
  8935. +#define MATCH_VLE128V 0x10000007
  8936. +#define MASK_VLE128V 0xfdf0707f
  8937. +#define MATCH_VLE256V 0x10005007
  8938. +#define MASK_VLE256V 0xfdf0707f
  8939. +#define MATCH_VLE512V 0x10006007
  8940. +#define MASK_VLE512V 0xfdf0707f
  8941. +#define MATCH_VLE1024V 0x10007007
  8942. +#define MASK_VLE1024V 0xfdf0707f
  8943. +
  8944. +#define MATCH_VSE8V 0x00000027
  8945. +#define MASK_VSE8V 0xfdf0707f
  8946. +#define MATCH_VSE16V 0x00005027
  8947. +#define MASK_VSE16V 0xfdf0707f
  8948. +#define MATCH_VSE32V 0x00006027
  8949. +#define MASK_VSE32V 0xfdf0707f
  8950. +#define MATCH_VSE64V 0x00007027
  8951. +#define MASK_VSE64V 0xfdf0707f
  8952. +#define MATCH_VSE128V 0x10000027
  8953. +#define MASK_VSE128V 0xfdf0707f
  8954. +#define MATCH_VSE256V 0x10005027
  8955. +#define MASK_VSE256V 0xfdf0707f
  8956. +#define MATCH_VSE512V 0x10006027
  8957. +#define MASK_VSE512V 0xfdf0707f
  8958. +#define MATCH_VSE1024V 0x10007027
  8959. +#define MASK_VSE1024V 0xfdf0707f
  8960. +
  8961. +#define MATCH_VLSE8V 0x08000007
  8962. +#define MASK_VLSE8V 0xfc00707f
  8963. +#define MATCH_VLSE16V 0x08005007
  8964. +#define MASK_VLSE16V 0xfc00707f
  8965. +#define MATCH_VLSE32V 0x08006007
  8966. +#define MASK_VLSE32V 0xfc00707f
  8967. +#define MATCH_VLSE64V 0x08007007
  8968. +#define MASK_VLSE64V 0xfc00707f
  8969. +#define MATCH_VLSE128V 0x18000007
  8970. +#define MASK_VLSE128V 0xfc00707f
  8971. +#define MATCH_VLSE256V 0x18005007
  8972. +#define MASK_VLSE256V 0xfc00707f
  8973. +#define MATCH_VLSE512V 0x18006007
  8974. +#define MASK_VLSE512V 0xfc00707f
  8975. +#define MATCH_VLSE1024V 0x18007007
  8976. +#define MASK_VLSE1024V 0xfc00707f
  8977. +
  8978. +#define MATCH_VSSE8V 0x08000027
  8979. +#define MASK_VSSE8V 0xfc00707f
  8980. +#define MATCH_VSSE16V 0x08005027
  8981. +#define MASK_VSSE16V 0xfc00707f
  8982. +#define MATCH_VSSE32V 0x08006027
  8983. +#define MASK_VSSE32V 0xfc00707f
  8984. +#define MATCH_VSSE64V 0x08007027
  8985. +#define MASK_VSSE64V 0xfc00707f
  8986. +#define MATCH_VSSE128V 0x18000027
  8987. +#define MASK_VSSE128V 0xfc00707f
  8988. +#define MATCH_VSSE256V 0x18005027
  8989. +#define MASK_VSSE256V 0xfc00707f
  8990. +#define MATCH_VSSE512V 0x18006027
  8991. +#define MASK_VSSE512V 0xfc00707f
  8992. +#define MATCH_VSSE1024V 0x18007027
  8993. +#define MASK_VSSE1024V 0xfc00707f
  8994. +
  8995. +#define MATCH_VLXEI8V 0x0c000007
  8996. +#define MASK_VLXEI8V 0xfc00707f
  8997. +#define MATCH_VLXEI16V 0x0c005007
  8998. +#define MASK_VLXEI16V 0xfc00707f
  8999. +#define MATCH_VLXEI32V 0x0c006007
  9000. +#define MASK_VLXEI32V 0xfc00707f
  9001. +#define MATCH_VLXEI64V 0x0c007007
  9002. +#define MASK_VLXEI64V 0xfc00707f
  9003. +#define MATCH_VLXEI128V 0x1c000007
  9004. +#define MASK_VLXEI128V 0xfc00707f
  9005. +#define MATCH_VLXEI256V 0x1c005007
  9006. +#define MASK_VLXEI256V 0xfc00707f
  9007. +#define MATCH_VLXEI512V 0x1c006007
  9008. +#define MASK_VLXEI512V 0xfc00707f
  9009. +#define MATCH_VLXEI1024V 0x1c007007
  9010. +#define MASK_VLXEI1024V 0xfc00707f
  9011. +
  9012. +#define MATCH_VSXEI8V 0x0c000027
  9013. +#define MASK_VSXEI8V 0xfc00707f
  9014. +#define MATCH_VSXEI16V 0x0c005027
  9015. +#define MASK_VSXEI16V 0xfc00707f
  9016. +#define MATCH_VSXEI32V 0x0c006027
  9017. +#define MASK_VSXEI32V 0xfc00707f
  9018. +#define MATCH_VSXEI64V 0x0c007027
  9019. +#define MASK_VSXEI64V 0xfc00707f
  9020. +#define MATCH_VSXEI128V 0x1c000027
  9021. +#define MASK_VSXEI128V 0xfc00707f
  9022. +#define MATCH_VSXEI256V 0x1c005027
  9023. +#define MASK_VSXEI256V 0xfc00707f
  9024. +#define MATCH_VSXEI512V 0x1c006027
  9025. +#define MASK_VSXEI512V 0xfc00707f
  9026. +#define MATCH_VSXEI1024V 0x1c007027
  9027. +#define MASK_VSXEI1024V 0xfc00707f
  9028. +
  9029. +#define MATCH_VSUXEI8V 0x04000027
  9030. +#define MASK_VSUXEI8V 0xfc00707f
  9031. +#define MATCH_VSUXEI16V 0x04005027
  9032. +#define MASK_VSUXEI16V 0xfc00707f
  9033. +#define MATCH_VSUXEI32V 0x04006027
  9034. +#define MASK_VSUXEI32V 0xfc00707f
  9035. +#define MATCH_VSUXEI64V 0x04007027
  9036. +#define MASK_VSUXEI64V 0xfc00707f
  9037. +#define MATCH_VSUXEI128V 0x14000027
  9038. +#define MASK_VSUXEI128V 0xfc00707f
  9039. +#define MATCH_VSUXEI256V 0x14005027
  9040. +#define MASK_VSUXEI256V 0xfc00707f
  9041. +#define MATCH_VSUXEI512V 0x14006027
  9042. +#define MASK_VSUXEI512V 0xfc00707f
  9043. +#define MATCH_VSUXEI1024V 0x14007027
  9044. +#define MASK_VSUXEI1024V 0xfc00707f
  9045. +
  9046. +#define MATCH_VLE8FFV 0x01000007
  9047. +#define MASK_VLE8FFV 0xfdf0707f
  9048. +#define MATCH_VLE16FFV 0x01005007
  9049. +#define MASK_VLE16FFV 0xfdf0707f
  9050. +#define MATCH_VLE32FFV 0x01006007
  9051. +#define MASK_VLE32FFV 0xfdf0707f
  9052. +#define MATCH_VLE64FFV 0x01007007
  9053. +#define MASK_VLE64FFV 0xfdf0707f
  9054. +#define MATCH_VLE128FFV 0x11000007
  9055. +#define MASK_VLE128FFV 0xfdf0707f
  9056. +#define MATCH_VLE256FFV 0x11005007
  9057. +#define MASK_VLE256FFV 0xfdf0707f
  9058. +#define MATCH_VLE512FFV 0x11006007
  9059. +#define MASK_VLE512FFV 0xfdf0707f
  9060. +#define MATCH_VLE1024FFV 0x11007007
  9061. +#define MASK_VLE1024FFV 0xfdf0707f
  9062. +
  9063. +#define MATCH_VLSEG2E8V 0x20000007
  9064. +#define MASK_VLSEG2E8V 0xfdf0707f
  9065. +#define MATCH_VSSEG2E8V 0x20000027
  9066. +#define MASK_VSSEG2E8V 0xfdf0707f
  9067. +#define MATCH_VLSEG3E8V 0x40000007
  9068. +#define MASK_VLSEG3E8V 0xfdf0707f
  9069. +#define MATCH_VSSEG3E8V 0x40000027
  9070. +#define MASK_VSSEG3E8V 0xfdf0707f
  9071. +#define MATCH_VLSEG4E8V 0x60000007
  9072. +#define MASK_VLSEG4E8V 0xfdf0707f
  9073. +#define MATCH_VSSEG4E8V 0x60000027
  9074. +#define MASK_VSSEG4E8V 0xfdf0707f
  9075. +#define MATCH_VLSEG5E8V 0x80000007
  9076. +#define MASK_VLSEG5E8V 0xfdf0707f
  9077. +#define MATCH_VSSEG5E8V 0x80000027
  9078. +#define MASK_VSSEG5E8V 0xfdf0707f
  9079. +#define MATCH_VLSEG6E8V 0xa0000007
  9080. +#define MASK_VLSEG6E8V 0xfdf0707f
  9081. +#define MATCH_VSSEG6E8V 0xa0000027
  9082. +#define MASK_VSSEG6E8V 0xfdf0707f
  9083. +#define MATCH_VLSEG7E8V 0xc0000007
  9084. +#define MASK_VLSEG7E8V 0xfdf0707f
  9085. +#define MATCH_VSSEG7E8V 0xc0000027
  9086. +#define MASK_VSSEG7E8V 0xfdf0707f
  9087. +#define MATCH_VLSEG8E8V 0xe0000007
  9088. +#define MASK_VLSEG8E8V 0xfdf0707f
  9089. +#define MATCH_VSSEG8E8V 0xe0000027
  9090. +#define MASK_VSSEG8E8V 0xfdf0707f
  9091. +
  9092. +#define MATCH_VLSEG2E16V 0x20005007
  9093. +#define MASK_VLSEG2E16V 0xfdf0707f
  9094. +#define MATCH_VSSEG2E16V 0x20005027
  9095. +#define MASK_VSSEG2E16V 0xfdf0707f
  9096. +#define MATCH_VLSEG3E16V 0x40005007
  9097. +#define MASK_VLSEG3E16V 0xfdf0707f
  9098. +#define MATCH_VSSEG3E16V 0x40005027
  9099. +#define MASK_VSSEG3E16V 0xfdf0707f
  9100. +#define MATCH_VLSEG4E16V 0x60005007
  9101. +#define MASK_VLSEG4E16V 0xfdf0707f
  9102. +#define MATCH_VSSEG4E16V 0x60005027
  9103. +#define MASK_VSSEG4E16V 0xfdf0707f
  9104. +#define MATCH_VLSEG5E16V 0x80005007
  9105. +#define MASK_VLSEG5E16V 0xfdf0707f
  9106. +#define MATCH_VSSEG5E16V 0x80005027
  9107. +#define MASK_VSSEG5E16V 0xfdf0707f
  9108. +#define MATCH_VLSEG6E16V 0xa0005007
  9109. +#define MASK_VLSEG6E16V 0xfdf0707f
  9110. +#define MATCH_VSSEG6E16V 0xa0005027
  9111. +#define MASK_VSSEG6E16V 0xfdf0707f
  9112. +#define MATCH_VLSEG7E16V 0xc0005007
  9113. +#define MASK_VLSEG7E16V 0xfdf0707f
  9114. +#define MATCH_VSSEG7E16V 0xc0005027
  9115. +#define MASK_VSSEG7E16V 0xfdf0707f
  9116. +#define MATCH_VLSEG8E16V 0xe0005007
  9117. +#define MASK_VLSEG8E16V 0xfdf0707f
  9118. +#define MATCH_VSSEG8E16V 0xe0005027
  9119. +#define MASK_VSSEG8E16V 0xfdf0707f
  9120. +
  9121. +#define MATCH_VLSEG2E32V 0x20006007
  9122. +#define MASK_VLSEG2E32V 0xfdf0707f
  9123. +#define MATCH_VSSEG2E32V 0x20006027
  9124. +#define MASK_VSSEG2E32V 0xfdf0707f
  9125. +#define MATCH_VLSEG3E32V 0x40006007
  9126. +#define MASK_VLSEG3E32V 0xfdf0707f
  9127. +#define MATCH_VSSEG3E32V 0x40006027
  9128. +#define MASK_VSSEG3E32V 0xfdf0707f
  9129. +#define MATCH_VLSEG4E32V 0x60006007
  9130. +#define MASK_VLSEG4E32V 0xfdf0707f
  9131. +#define MATCH_VSSEG4E32V 0x60006027
  9132. +#define MASK_VSSEG4E32V 0xfdf0707f
  9133. +#define MATCH_VLSEG5E32V 0x80006007
  9134. +#define MASK_VLSEG5E32V 0xfdf0707f
  9135. +#define MATCH_VSSEG5E32V 0x80006027
  9136. +#define MASK_VSSEG5E32V 0xfdf0707f
  9137. +#define MATCH_VLSEG6E32V 0xa0006007
  9138. +#define MASK_VLSEG6E32V 0xfdf0707f
  9139. +#define MATCH_VSSEG6E32V 0xa0006027
  9140. +#define MASK_VSSEG6E32V 0xfdf0707f
  9141. +#define MATCH_VLSEG7E32V 0xc0006007
  9142. +#define MASK_VLSEG7E32V 0xfdf0707f
  9143. +#define MATCH_VSSEG7E32V 0xc0006027
  9144. +#define MASK_VSSEG7E32V 0xfdf0707f
  9145. +#define MATCH_VLSEG8E32V 0xe0006007
  9146. +#define MASK_VLSEG8E32V 0xfdf0707f
  9147. +#define MATCH_VSSEG8E32V 0xe0006027
  9148. +#define MASK_VSSEG8E32V 0xfdf0707f
  9149. +
  9150. +#define MATCH_VLSEG2E64V 0x20007007
  9151. +#define MASK_VLSEG2E64V 0xfdf0707f
  9152. +#define MATCH_VSSEG2E64V 0x20007027
  9153. +#define MASK_VSSEG2E64V 0xfdf0707f
  9154. +#define MATCH_VLSEG3E64V 0x40007007
  9155. +#define MASK_VLSEG3E64V 0xfdf0707f
  9156. +#define MATCH_VSSEG3E64V 0x40007027
  9157. +#define MASK_VSSEG3E64V 0xfdf0707f
  9158. +#define MATCH_VLSEG4E64V 0x60007007
  9159. +#define MASK_VLSEG4E64V 0xfdf0707f
  9160. +#define MATCH_VSSEG4E64V 0x60007027
  9161. +#define MASK_VSSEG4E64V 0xfdf0707f
  9162. +#define MATCH_VLSEG5E64V 0x80007007
  9163. +#define MASK_VLSEG5E64V 0xfdf0707f
  9164. +#define MATCH_VSSEG5E64V 0x80007027
  9165. +#define MASK_VSSEG5E64V 0xfdf0707f
  9166. +#define MATCH_VLSEG6E64V 0xa0007007
  9167. +#define MASK_VLSEG6E64V 0xfdf0707f
  9168. +#define MATCH_VSSEG6E64V 0xa0007027
  9169. +#define MASK_VSSEG6E64V 0xfdf0707f
  9170. +#define MATCH_VLSEG7E64V 0xc0007007
  9171. +#define MASK_VLSEG7E64V 0xfdf0707f
  9172. +#define MATCH_VSSEG7E64V 0xc0007027
  9173. +#define MASK_VSSEG7E64V 0xfdf0707f
  9174. +#define MATCH_VLSEG8E64V 0xe0007007
  9175. +#define MASK_VLSEG8E64V 0xfdf0707f
  9176. +#define MATCH_VSSEG8E64V 0xe0007027
  9177. +#define MASK_VSSEG8E64V 0xfdf0707f
  9178. +
  9179. +#define MATCH_VLSEG2E128V 0x30000007
  9180. +#define MASK_VLSEG2E128V 0xfdf0707f
  9181. +#define MATCH_VSSEG2E128V 0x30000027
  9182. +#define MASK_VSSEG2E128V 0xfdf0707f
  9183. +#define MATCH_VLSEG3E128V 0x50000007
  9184. +#define MASK_VLSEG3E128V 0xfdf0707f
  9185. +#define MATCH_VSSEG3E128V 0x50000027
  9186. +#define MASK_VSSEG3E128V 0xfdf0707f
  9187. +#define MATCH_VLSEG4E128V 0x70000007
  9188. +#define MASK_VLSEG4E128V 0xfdf0707f
  9189. +#define MATCH_VSSEG4E128V 0x70000027
  9190. +#define MASK_VSSEG4E128V 0xfdf0707f
  9191. +#define MATCH_VLSEG5E128V 0x90000007
  9192. +#define MASK_VLSEG5E128V 0xfdf0707f
  9193. +#define MATCH_VSSEG5E128V 0x90000027
  9194. +#define MASK_VSSEG5E128V 0xfdf0707f
  9195. +#define MATCH_VLSEG6E128V 0xb0000007
  9196. +#define MASK_VLSEG6E128V 0xfdf0707f
  9197. +#define MATCH_VSSEG6E128V 0xb0000027
  9198. +#define MASK_VSSEG6E128V 0xfdf0707f
  9199. +#define MATCH_VLSEG7E128V 0xd0000007
  9200. +#define MASK_VLSEG7E128V 0xfdf0707f
  9201. +#define MATCH_VSSEG7E128V 0xd0000027
  9202. +#define MASK_VSSEG7E128V 0xfdf0707f
  9203. +#define MATCH_VLSEG8E128V 0xf0000007
  9204. +#define MASK_VLSEG8E128V 0xfdf0707f
  9205. +#define MATCH_VSSEG8E128V 0xf0000027
  9206. +#define MASK_VSSEG8E128V 0xfdf0707f
  9207. +
  9208. +#define MATCH_VLSEG2E256V 0x30005007
  9209. +#define MASK_VLSEG2E256V 0xfdf0707f
  9210. +#define MATCH_VSSEG2E256V 0x30005027
  9211. +#define MASK_VSSEG2E256V 0xfdf0707f
  9212. +#define MATCH_VLSEG3E256V 0x50005007
  9213. +#define MASK_VLSEG3E256V 0xfdf0707f
  9214. +#define MATCH_VSSEG3E256V 0x50005027
  9215. +#define MASK_VSSEG3E256V 0xfdf0707f
  9216. +#define MATCH_VLSEG4E256V 0x70005007
  9217. +#define MASK_VLSEG4E256V 0xfdf0707f
  9218. +#define MATCH_VSSEG4E256V 0x70005027
  9219. +#define MASK_VSSEG4E256V 0xfdf0707f
  9220. +#define MATCH_VLSEG5E256V 0x90005007
  9221. +#define MASK_VLSEG5E256V 0xfdf0707f
  9222. +#define MATCH_VSSEG5E256V 0x90005027
  9223. +#define MASK_VSSEG5E256V 0xfdf0707f
  9224. +#define MATCH_VLSEG6E256V 0xb0005007
  9225. +#define MASK_VLSEG6E256V 0xfdf0707f
  9226. +#define MATCH_VSSEG6E256V 0xb0005027
  9227. +#define MASK_VSSEG6E256V 0xfdf0707f
  9228. +#define MATCH_VLSEG7E256V 0xd0005007
  9229. +#define MASK_VLSEG7E256V 0xfdf0707f
  9230. +#define MATCH_VSSEG7E256V 0xd0005027
  9231. +#define MASK_VSSEG7E256V 0xfdf0707f
  9232. +#define MATCH_VLSEG8E256V 0xf0005007
  9233. +#define MASK_VLSEG8E256V 0xfdf0707f
  9234. +#define MATCH_VSSEG8E256V 0xf0005027
  9235. +#define MASK_VSSEG8E256V 0xfdf0707f
  9236. +
  9237. +#define MATCH_VLSEG2E512V 0x30006007
  9238. +#define MASK_VLSEG2E512V 0xfdf0707f
  9239. +#define MATCH_VSSEG2E512V 0x30006027
  9240. +#define MASK_VSSEG2E512V 0xfdf0707f
  9241. +#define MATCH_VLSEG3E512V 0x50006007
  9242. +#define MASK_VLSEG3E512V 0xfdf0707f
  9243. +#define MATCH_VSSEG3E512V 0x50006027
  9244. +#define MASK_VSSEG3E512V 0xfdf0707f
  9245. +#define MATCH_VLSEG4E512V 0x70006007
  9246. +#define MASK_VLSEG4E512V 0xfdf0707f
  9247. +#define MATCH_VSSEG4E512V 0x70006027
  9248. +#define MASK_VSSEG4E512V 0xfdf0707f
  9249. +#define MATCH_VLSEG5E512V 0x90006007
  9250. +#define MASK_VLSEG5E512V 0xfdf0707f
  9251. +#define MATCH_VSSEG5E512V 0x90006027
  9252. +#define MASK_VSSEG5E512V 0xfdf0707f
  9253. +#define MATCH_VLSEG6E512V 0xb0006007
  9254. +#define MASK_VLSEG6E512V 0xfdf0707f
  9255. +#define MATCH_VSSEG6E512V 0xb0006027
  9256. +#define MASK_VSSEG6E512V 0xfdf0707f
  9257. +#define MATCH_VLSEG7E512V 0xd0006007
  9258. +#define MASK_VLSEG7E512V 0xfdf0707f
  9259. +#define MATCH_VSSEG7E512V 0xd0006027
  9260. +#define MASK_VSSEG7E512V 0xfdf0707f
  9261. +#define MATCH_VLSEG8E512V 0xf0006007
  9262. +#define MASK_VLSEG8E512V 0xfdf0707f
  9263. +#define MATCH_VSSEG8E512V 0xf0006027
  9264. +#define MASK_VSSEG8E512V 0xfdf0707f
  9265. +
  9266. +#define MATCH_VLSEG2E1024V 0x30007007
  9267. +#define MASK_VLSEG2E1024V 0xfdf0707f
  9268. +#define MATCH_VSSEG2E1024V 0x30007027
  9269. +#define MASK_VSSEG2E1024V 0xfdf0707f
  9270. +#define MATCH_VLSEG3E1024V 0x50007007
  9271. +#define MASK_VLSEG3E1024V 0xfdf0707f
  9272. +#define MATCH_VSSEG3E1024V 0x50007027
  9273. +#define MASK_VSSEG3E1024V 0xfdf0707f
  9274. +#define MATCH_VLSEG4E1024V 0x70007007
  9275. +#define MASK_VLSEG4E1024V 0xfdf0707f
  9276. +#define MATCH_VSSEG4E1024V 0x70007027
  9277. +#define MASK_VSSEG4E1024V 0xfdf0707f
  9278. +#define MATCH_VLSEG5E1024V 0x90007007
  9279. +#define MASK_VLSEG5E1024V 0xfdf0707f
  9280. +#define MATCH_VSSEG5E1024V 0x90007027
  9281. +#define MASK_VSSEG5E1024V 0xfdf0707f
  9282. +#define MATCH_VLSEG6E1024V 0xb0007007
  9283. +#define MASK_VLSEG6E1024V 0xfdf0707f
  9284. +#define MATCH_VSSEG6E1024V 0xb0007027
  9285. +#define MASK_VSSEG6E1024V 0xfdf0707f
  9286. +#define MATCH_VLSEG7E1024V 0xd0007007
  9287. +#define MASK_VLSEG7E1024V 0xfdf0707f
  9288. +#define MATCH_VSSEG7E1024V 0xd0007027
  9289. +#define MASK_VSSEG7E1024V 0xfdf0707f
  9290. +#define MATCH_VLSEG8E1024V 0xf0007007
  9291. +#define MASK_VLSEG8E1024V 0xfdf0707f
  9292. +#define MATCH_VSSEG8E1024V 0xf0007027
  9293. +#define MASK_VSSEG8E1024V 0xfdf0707f
  9294. +
  9295. +#define MATCH_VLSSEG2E8V 0x28000007
  9296. +#define MASK_VLSSEG2E8V 0xfc00707f
  9297. +#define MATCH_VSSSEG2E8V 0x28000027
  9298. +#define MASK_VSSSEG2E8V 0xfc00707f
  9299. +#define MATCH_VLSSEG3E8V 0x48000007
  9300. +#define MASK_VLSSEG3E8V 0xfc00707f
  9301. +#define MATCH_VSSSEG3E8V 0x48000027
  9302. +#define MASK_VSSSEG3E8V 0xfc00707f
  9303. +#define MATCH_VLSSEG4E8V 0x68000007
  9304. +#define MASK_VLSSEG4E8V 0xfc00707f
  9305. +#define MATCH_VSSSEG4E8V 0x68000027
  9306. +#define MASK_VSSSEG4E8V 0xfc00707f
  9307. +#define MATCH_VLSSEG5E8V 0x88000007
  9308. +#define MASK_VLSSEG5E8V 0xfc00707f
  9309. +#define MATCH_VSSSEG5E8V 0x88000027
  9310. +#define MASK_VSSSEG5E8V 0xfc00707f
  9311. +#define MATCH_VLSSEG6E8V 0xa8000007
  9312. +#define MASK_VLSSEG6E8V 0xfc00707f
  9313. +#define MATCH_VSSSEG6E8V 0xa8000027
  9314. +#define MASK_VSSSEG6E8V 0xfc00707f
  9315. +#define MATCH_VLSSEG7E8V 0xc8000007
  9316. +#define MASK_VLSSEG7E8V 0xfc00707f
  9317. +#define MATCH_VSSSEG7E8V 0xc8000027
  9318. +#define MASK_VSSSEG7E8V 0xfc00707f
  9319. +#define MATCH_VLSSEG8E8V 0xe8000007
  9320. +#define MASK_VLSSEG8E8V 0xfc00707f
  9321. +#define MATCH_VSSSEG8E8V 0xe8000027
  9322. +#define MASK_VSSSEG8E8V 0xfc00707f
  9323. +
  9324. +#define MATCH_VLSSEG2E16V 0x28005007
  9325. +#define MASK_VLSSEG2E16V 0xfc00707f
  9326. +#define MATCH_VSSSEG2E16V 0x28005027
  9327. +#define MASK_VSSSEG2E16V 0xfc00707f
  9328. +#define MATCH_VLSSEG3E16V 0x48005007
  9329. +#define MASK_VLSSEG3E16V 0xfc00707f
  9330. +#define MATCH_VSSSEG3E16V 0x48005027
  9331. +#define MASK_VSSSEG3E16V 0xfc00707f
  9332. +#define MATCH_VLSSEG4E16V 0x68005007
  9333. +#define MASK_VLSSEG4E16V 0xfc00707f
  9334. +#define MATCH_VSSSEG4E16V 0x68005027
  9335. +#define MASK_VSSSEG4E16V 0xfc00707f
  9336. +#define MATCH_VLSSEG5E16V 0x88005007
  9337. +#define MASK_VLSSEG5E16V 0xfc00707f
  9338. +#define MATCH_VSSSEG5E16V 0x88005027
  9339. +#define MASK_VSSSEG5E16V 0xfc00707f
  9340. +#define MATCH_VLSSEG6E16V 0xa8005007
  9341. +#define MASK_VLSSEG6E16V 0xfc00707f
  9342. +#define MATCH_VSSSEG6E16V 0xa8005027
  9343. +#define MASK_VSSSEG6E16V 0xfc00707f
  9344. +#define MATCH_VLSSEG7E16V 0xc8005007
  9345. +#define MASK_VLSSEG7E16V 0xfc00707f
  9346. +#define MATCH_VSSSEG7E16V 0xc8005027
  9347. +#define MASK_VSSSEG7E16V 0xfc00707f
  9348. +#define MATCH_VLSSEG8E16V 0xe8005007
  9349. +#define MASK_VLSSEG8E16V 0xfc00707f
  9350. +#define MATCH_VSSSEG8E16V 0xe8005027
  9351. +#define MASK_VSSSEG8E16V 0xfc00707f
  9352. +
  9353. +#define MATCH_VLSSEG2E32V 0x28006007
  9354. +#define MASK_VLSSEG2E32V 0xfc00707f
  9355. +#define MATCH_VSSSEG2E32V 0x28006027
  9356. +#define MASK_VSSSEG2E32V 0xfc00707f
  9357. +#define MATCH_VLSSEG3E32V 0x48006007
  9358. +#define MASK_VLSSEG3E32V 0xfc00707f
  9359. +#define MATCH_VSSSEG3E32V 0x48006027
  9360. +#define MASK_VSSSEG3E32V 0xfc00707f
  9361. +#define MATCH_VLSSEG4E32V 0x68006007
  9362. +#define MASK_VLSSEG4E32V 0xfc00707f
  9363. +#define MATCH_VSSSEG4E32V 0x68006027
  9364. +#define MASK_VSSSEG4E32V 0xfc00707f
  9365. +#define MATCH_VLSSEG5E32V 0x88006007
  9366. +#define MASK_VLSSEG5E32V 0xfc00707f
  9367. +#define MATCH_VSSSEG5E32V 0x88006027
  9368. +#define MASK_VSSSEG5E32V 0xfc00707f
  9369. +#define MATCH_VLSSEG6E32V 0xa8006007
  9370. +#define MASK_VLSSEG6E32V 0xfc00707f
  9371. +#define MATCH_VSSSEG6E32V 0xa8006027
  9372. +#define MASK_VSSSEG6E32V 0xfc00707f
  9373. +#define MATCH_VLSSEG7E32V 0xc8006007
  9374. +#define MASK_VLSSEG7E32V 0xfc00707f
  9375. +#define MATCH_VSSSEG7E32V 0xc8006027
  9376. +#define MASK_VSSSEG7E32V 0xfc00707f
  9377. +#define MATCH_VLSSEG8E32V 0xe8006007
  9378. +#define MASK_VLSSEG8E32V 0xfc00707f
  9379. +#define MATCH_VSSSEG8E32V 0xe8006027
  9380. +#define MASK_VSSSEG8E32V 0xfc00707f
  9381. +
  9382. +#define MATCH_VLSSEG2E64V 0x28007007
  9383. +#define MASK_VLSSEG2E64V 0xfc00707f
  9384. +#define MATCH_VSSSEG2E64V 0x28007027
  9385. +#define MASK_VSSSEG2E64V 0xfc00707f
  9386. +#define MATCH_VLSSEG3E64V 0x48007007
  9387. +#define MASK_VLSSEG3E64V 0xfc00707f
  9388. +#define MATCH_VSSSEG3E64V 0x48007027
  9389. +#define MASK_VSSSEG3E64V 0xfc00707f
  9390. +#define MATCH_VLSSEG4E64V 0x68007007
  9391. +#define MASK_VLSSEG4E64V 0xfc00707f
  9392. +#define MATCH_VSSSEG4E64V 0x68007027
  9393. +#define MASK_VSSSEG4E64V 0xfc00707f
  9394. +#define MATCH_VLSSEG5E64V 0x88007007
  9395. +#define MASK_VLSSEG5E64V 0xfc00707f
  9396. +#define MATCH_VSSSEG5E64V 0x88007027
  9397. +#define MASK_VSSSEG5E64V 0xfc00707f
  9398. +#define MATCH_VLSSEG6E64V 0xa8007007
  9399. +#define MASK_VLSSEG6E64V 0xfc00707f
  9400. +#define MATCH_VSSSEG6E64V 0xa8007027
  9401. +#define MASK_VSSSEG6E64V 0xfc00707f
  9402. +#define MATCH_VLSSEG7E64V 0xc8007007
  9403. +#define MASK_VLSSEG7E64V 0xfc00707f
  9404. +#define MATCH_VSSSEG7E64V 0xc8007027
  9405. +#define MASK_VSSSEG7E64V 0xfc00707f
  9406. +#define MATCH_VLSSEG8E64V 0xe8007007
  9407. +#define MASK_VLSSEG8E64V 0xfc00707f
  9408. +#define MATCH_VSSSEG8E64V 0xe8007027
  9409. +#define MASK_VSSSEG8E64V 0xfc00707f
  9410. +
  9411. +#define MATCH_VLSSEG2E128V 0x38000007
  9412. +#define MASK_VLSSEG2E128V 0xfc00707f
  9413. +#define MATCH_VSSSEG2E128V 0x38000027
  9414. +#define MASK_VSSSEG2E128V 0xfc00707f
  9415. +#define MATCH_VLSSEG3E128V 0x58000007
  9416. +#define MASK_VLSSEG3E128V 0xfc00707f
  9417. +#define MATCH_VSSSEG3E128V 0x58000027
  9418. +#define MASK_VSSSEG3E128V 0xfc00707f
  9419. +#define MATCH_VLSSEG4E128V 0x78000007
  9420. +#define MASK_VLSSEG4E128V 0xfc00707f
  9421. +#define MATCH_VSSSEG4E128V 0x78000027
  9422. +#define MASK_VSSSEG4E128V 0xfc00707f
  9423. +#define MATCH_VLSSEG5E128V 0x98000007
  9424. +#define MASK_VLSSEG5E128V 0xfc00707f
  9425. +#define MATCH_VSSSEG5E128V 0x98000027
  9426. +#define MASK_VSSSEG5E128V 0xfc00707f
  9427. +#define MATCH_VLSSEG6E128V 0xb8000007
  9428. +#define MASK_VLSSEG6E128V 0xfc00707f
  9429. +#define MATCH_VSSSEG6E128V 0xb8000027
  9430. +#define MASK_VSSSEG6E128V 0xfc00707f
  9431. +#define MATCH_VLSSEG7E128V 0xd8000007
  9432. +#define MASK_VLSSEG7E128V 0xfc00707f
  9433. +#define MATCH_VSSSEG7E128V 0xd8000027
  9434. +#define MASK_VSSSEG7E128V 0xfc00707f
  9435. +#define MATCH_VLSSEG8E128V 0xf8000007
  9436. +#define MASK_VLSSEG8E128V 0xfc00707f
  9437. +#define MATCH_VSSSEG8E128V 0xf8000027
  9438. +#define MASK_VSSSEG8E128V 0xfc00707f
  9439. +
  9440. +#define MATCH_VLSSEG2E256V 0x38005007
  9441. +#define MASK_VLSSEG2E256V 0xfc00707f
  9442. +#define MATCH_VSSSEG2E256V 0x38005027
  9443. +#define MASK_VSSSEG2E256V 0xfc00707f
  9444. +#define MATCH_VLSSEG3E256V 0x58005007
  9445. +#define MASK_VLSSEG3E256V 0xfc00707f
  9446. +#define MATCH_VSSSEG3E256V 0x58005027
  9447. +#define MASK_VSSSEG3E256V 0xfc00707f
  9448. +#define MATCH_VLSSEG4E256V 0x78005007
  9449. +#define MASK_VLSSEG4E256V 0xfc00707f
  9450. +#define MATCH_VSSSEG4E256V 0x78005027
  9451. +#define MASK_VSSSEG4E256V 0xfc00707f
  9452. +#define MATCH_VLSSEG5E256V 0x98005007
  9453. +#define MASK_VLSSEG5E256V 0xfc00707f
  9454. +#define MATCH_VSSSEG5E256V 0x98005027
  9455. +#define MASK_VSSSEG5E256V 0xfc00707f
  9456. +#define MATCH_VLSSEG6E256V 0xb8005007
  9457. +#define MASK_VLSSEG6E256V 0xfc00707f
  9458. +#define MATCH_VSSSEG6E256V 0xb8005027
  9459. +#define MASK_VSSSEG6E256V 0xfc00707f
  9460. +#define MATCH_VLSSEG7E256V 0xd8005007
  9461. +#define MASK_VLSSEG7E256V 0xfc00707f
  9462. +#define MATCH_VSSSEG7E256V 0xd8005027
  9463. +#define MASK_VSSSEG7E256V 0xfc00707f
  9464. +#define MATCH_VLSSEG8E256V 0xf8005007
  9465. +#define MASK_VLSSEG8E256V 0xfc00707f
  9466. +#define MATCH_VSSSEG8E256V 0xf8005027
  9467. +#define MASK_VSSSEG8E256V 0xfc00707f
  9468. +
  9469. +#define MATCH_VLSSEG2E512V 0x38006007
  9470. +#define MASK_VLSSEG2E512V 0xfc00707f
  9471. +#define MATCH_VSSSEG2E512V 0x38006027
  9472. +#define MASK_VSSSEG2E512V 0xfc00707f
  9473. +#define MATCH_VLSSEG3E512V 0x58006007
  9474. +#define MASK_VLSSEG3E512V 0xfc00707f
  9475. +#define MATCH_VSSSEG3E512V 0x58006027
  9476. +#define MASK_VSSSEG3E512V 0xfc00707f
  9477. +#define MATCH_VLSSEG4E512V 0x78006007
  9478. +#define MASK_VLSSEG4E512V 0xfc00707f
  9479. +#define MATCH_VSSSEG4E512V 0x78006027
  9480. +#define MASK_VSSSEG4E512V 0xfc00707f
  9481. +#define MATCH_VLSSEG5E512V 0x98006007
  9482. +#define MASK_VLSSEG5E512V 0xfc00707f
  9483. +#define MATCH_VSSSEG5E512V 0x98006027
  9484. +#define MASK_VSSSEG5E512V 0xfc00707f
  9485. +#define MATCH_VLSSEG6E512V 0xb8006007
  9486. +#define MASK_VLSSEG6E512V 0xfc00707f
  9487. +#define MATCH_VSSSEG6E512V 0xb8006027
  9488. +#define MASK_VSSSEG6E512V 0xfc00707f
  9489. +#define MATCH_VLSSEG7E512V 0xd8006007
  9490. +#define MASK_VLSSEG7E512V 0xfc00707f
  9491. +#define MATCH_VSSSEG7E512V 0xd8006027
  9492. +#define MASK_VSSSEG7E512V 0xfc00707f
  9493. +#define MATCH_VLSSEG8E512V 0xf8006007
  9494. +#define MASK_VLSSEG8E512V 0xfc00707f
  9495. +#define MATCH_VSSSEG8E512V 0xf8006027
  9496. +#define MASK_VSSSEG8E512V 0xfc00707f
  9497. +
  9498. +#define MATCH_VLSSEG2E1024V 0x38007007
  9499. +#define MASK_VLSSEG2E1024V 0xfc00707f
  9500. +#define MATCH_VSSSEG2E1024V 0x38007027
  9501. +#define MASK_VSSSEG2E1024V 0xfc00707f
  9502. +#define MATCH_VLSSEG3E1024V 0x58007007
  9503. +#define MASK_VLSSEG3E1024V 0xfc00707f
  9504. +#define MATCH_VSSSEG3E1024V 0x58007027
  9505. +#define MASK_VSSSEG3E1024V 0xfc00707f
  9506. +#define MATCH_VLSSEG4E1024V 0x78007007
  9507. +#define MASK_VLSSEG4E1024V 0xfc00707f
  9508. +#define MATCH_VSSSEG4E1024V 0x78007027
  9509. +#define MASK_VSSSEG4E1024V 0xfc00707f
  9510. +#define MATCH_VLSSEG5E1024V 0x98007007
  9511. +#define MASK_VLSSEG5E1024V 0xfc00707f
  9512. +#define MATCH_VSSSEG5E1024V 0x98007027
  9513. +#define MASK_VSSSEG5E1024V 0xfc00707f
  9514. +#define MATCH_VLSSEG6E1024V 0xb8007007
  9515. +#define MASK_VLSSEG6E1024V 0xfc00707f
  9516. +#define MATCH_VSSSEG6E1024V 0xb8007027
  9517. +#define MASK_VSSSEG6E1024V 0xfc00707f
  9518. +#define MATCH_VLSSEG7E1024V 0xd8007007
  9519. +#define MASK_VLSSEG7E1024V 0xfc00707f
  9520. +#define MATCH_VSSSEG7E1024V 0xd8007027
  9521. +#define MASK_VSSSEG7E1024V 0xfc00707f
  9522. +#define MATCH_VLSSEG8E1024V 0xf8007007
  9523. +#define MASK_VLSSEG8E1024V 0xfc00707f
  9524. +#define MATCH_VSSSEG8E1024V 0xf8007027
  9525. +#define MASK_VSSSEG8E1024V 0xfc00707f
  9526. +
  9527. +#define MATCH_VLXSEG2EI8V 0x2c000007
  9528. +#define MASK_VLXSEG2EI8V 0xfc00707f
  9529. +#define MATCH_VSXSEG2EI8V 0x2c000027
  9530. +#define MASK_VSXSEG2EI8V 0xfc00707f
  9531. +#define MATCH_VLXSEG3EI8V 0x4c000007
  9532. +#define MASK_VLXSEG3EI8V 0xfc00707f
  9533. +#define MATCH_VSXSEG3EI8V 0x4c000027
  9534. +#define MASK_VSXSEG3EI8V 0xfc00707f
  9535. +#define MATCH_VLXSEG4EI8V 0x6c000007
  9536. +#define MASK_VLXSEG4EI8V 0xfc00707f
  9537. +#define MATCH_VSXSEG4EI8V 0x6c000027
  9538. +#define MASK_VSXSEG4EI8V 0xfc00707f
  9539. +#define MATCH_VLXSEG5EI8V 0x8c000007
  9540. +#define MASK_VLXSEG5EI8V 0xfc00707f
  9541. +#define MATCH_VSXSEG5EI8V 0x8c000027
  9542. +#define MASK_VSXSEG5EI8V 0xfc00707f
  9543. +#define MATCH_VLXSEG6EI8V 0xac000007
  9544. +#define MASK_VLXSEG6EI8V 0xfc00707f
  9545. +#define MATCH_VSXSEG6EI8V 0xac000027
  9546. +#define MASK_VSXSEG6EI8V 0xfc00707f
  9547. +#define MATCH_VLXSEG7EI8V 0xcc000007
  9548. +#define MASK_VLXSEG7EI8V 0xfc00707f
  9549. +#define MATCH_VSXSEG7EI8V 0xcc000027
  9550. +#define MASK_VSXSEG7EI8V 0xfc00707f
  9551. +#define MATCH_VLXSEG8EI8V 0xec000007
  9552. +#define MASK_VLXSEG8EI8V 0xfc00707f
  9553. +#define MATCH_VSXSEG8EI8V 0xec000027
  9554. +#define MASK_VSXSEG8EI8V 0xfc00707f
  9555. +
  9556. +#define MATCH_VLXSEG2EI16V 0x2c005007
  9557. +#define MASK_VLXSEG2EI16V 0xfc00707f
  9558. +#define MATCH_VSXSEG2EI16V 0x2c005027
  9559. +#define MASK_VSXSEG2EI16V 0xfc00707f
  9560. +#define MATCH_VLXSEG3EI16V 0x4c005007
  9561. +#define MASK_VLXSEG3EI16V 0xfc00707f
  9562. +#define MATCH_VSXSEG3EI16V 0x4c005027
  9563. +#define MASK_VSXSEG3EI16V 0xfc00707f
  9564. +#define MATCH_VLXSEG4EI16V 0x6c005007
  9565. +#define MASK_VLXSEG4EI16V 0xfc00707f
  9566. +#define MATCH_VSXSEG4EI16V 0x6c005027
  9567. +#define MASK_VSXSEG4EI16V 0xfc00707f
  9568. +#define MATCH_VLXSEG5EI16V 0x8c005007
  9569. +#define MASK_VLXSEG5EI16V 0xfc00707f
  9570. +#define MATCH_VSXSEG5EI16V 0x8c005027
  9571. +#define MASK_VSXSEG5EI16V 0xfc00707f
  9572. +#define MATCH_VLXSEG6EI16V 0xac005007
  9573. +#define MASK_VLXSEG6EI16V 0xfc00707f
  9574. +#define MATCH_VSXSEG6EI16V 0xac005027
  9575. +#define MASK_VSXSEG6EI16V 0xfc00707f
  9576. +#define MATCH_VLXSEG7EI16V 0xcc005007
  9577. +#define MASK_VLXSEG7EI16V 0xfc00707f
  9578. +#define MATCH_VSXSEG7EI16V 0xcc005027
  9579. +#define MASK_VSXSEG7EI16V 0xfc00707f
  9580. +#define MATCH_VLXSEG8EI16V 0xec005007
  9581. +#define MASK_VLXSEG8EI16V 0xfc00707f
  9582. +#define MATCH_VSXSEG8EI16V 0xec005027
  9583. +#define MASK_VSXSEG8EI16V 0xfc00707f
  9584. +
  9585. +#define MATCH_VLXSEG2EI32V 0x2c006007
  9586. +#define MASK_VLXSEG2EI32V 0xfc00707f
  9587. +#define MATCH_VSXSEG2EI32V 0x2c006027
  9588. +#define MASK_VSXSEG2EI32V 0xfc00707f
  9589. +#define MATCH_VLXSEG3EI32V 0x4c006007
  9590. +#define MASK_VLXSEG3EI32V 0xfc00707f
  9591. +#define MATCH_VSXSEG3EI32V 0x4c006027
  9592. +#define MASK_VSXSEG3EI32V 0xfc00707f
  9593. +#define MATCH_VLXSEG4EI32V 0x6c006007
  9594. +#define MASK_VLXSEG4EI32V 0xfc00707f
  9595. +#define MATCH_VSXSEG4EI32V 0x6c006027
  9596. +#define MASK_VSXSEG4EI32V 0xfc00707f
  9597. +#define MATCH_VLXSEG5EI32V 0x8c006007
  9598. +#define MASK_VLXSEG5EI32V 0xfc00707f
  9599. +#define MATCH_VSXSEG5EI32V 0x8c006027
  9600. +#define MASK_VSXSEG5EI32V 0xfc00707f
  9601. +#define MATCH_VLXSEG6EI32V 0xac006007
  9602. +#define MASK_VLXSEG6EI32V 0xfc00707f
  9603. +#define MATCH_VSXSEG6EI32V 0xac006027
  9604. +#define MASK_VSXSEG6EI32V 0xfc00707f
  9605. +#define MATCH_VLXSEG7EI32V 0xcc006007
  9606. +#define MASK_VLXSEG7EI32V 0xfc00707f
  9607. +#define MATCH_VSXSEG7EI32V 0xcc006027
  9608. +#define MASK_VSXSEG7EI32V 0xfc00707f
  9609. +#define MATCH_VLXSEG8EI32V 0xec006007
  9610. +#define MASK_VLXSEG8EI32V 0xfc00707f
  9611. +#define MATCH_VSXSEG8EI32V 0xec006027
  9612. +#define MASK_VSXSEG8EI32V 0xfc00707f
  9613. +
  9614. +#define MATCH_VLXSEG2EI64V 0x2c007007
  9615. +#define MASK_VLXSEG2EI64V 0xfc00707f
  9616. +#define MATCH_VSXSEG2EI64V 0x2c007027
  9617. +#define MASK_VSXSEG2EI64V 0xfc00707f
  9618. +#define MATCH_VLXSEG3EI64V 0x4c007007
  9619. +#define MASK_VLXSEG3EI64V 0xfc00707f
  9620. +#define MATCH_VSXSEG3EI64V 0x4c007027
  9621. +#define MASK_VSXSEG3EI64V 0xfc00707f
  9622. +#define MATCH_VLXSEG4EI64V 0x6c007007
  9623. +#define MASK_VLXSEG4EI64V 0xfc00707f
  9624. +#define MATCH_VSXSEG4EI64V 0x6c007027
  9625. +#define MASK_VSXSEG4EI64V 0xfc00707f
  9626. +#define MATCH_VLXSEG5EI64V 0x8c007007
  9627. +#define MASK_VLXSEG5EI64V 0xfc00707f
  9628. +#define MATCH_VSXSEG5EI64V 0x8c007027
  9629. +#define MASK_VSXSEG5EI64V 0xfc00707f
  9630. +#define MATCH_VLXSEG6EI64V 0xac007007
  9631. +#define MASK_VLXSEG6EI64V 0xfc00707f
  9632. +#define MATCH_VSXSEG6EI64V 0xac007027
  9633. +#define MASK_VSXSEG6EI64V 0xfc00707f
  9634. +#define MATCH_VLXSEG7EI64V 0xcc007007
  9635. +#define MASK_VLXSEG7EI64V 0xfc00707f
  9636. +#define MATCH_VSXSEG7EI64V 0xcc007027
  9637. +#define MASK_VSXSEG7EI64V 0xfc00707f
  9638. +#define MATCH_VLXSEG8EI64V 0xec007007
  9639. +#define MASK_VLXSEG8EI64V 0xfc00707f
  9640. +#define MATCH_VSXSEG8EI64V 0xec007027
  9641. +#define MASK_VSXSEG8EI64V 0xfc00707f
  9642. +
  9643. +#define MATCH_VLXSEG2EI128V 0x3c000007
  9644. +#define MASK_VLXSEG2EI128V 0xfc00707f
  9645. +#define MATCH_VSXSEG2EI128V 0x3c000027
  9646. +#define MASK_VSXSEG2EI128V 0xfc00707f
  9647. +#define MATCH_VLXSEG3EI128V 0x5c000007
  9648. +#define MASK_VLXSEG3EI128V 0xfc00707f
  9649. +#define MATCH_VSXSEG3EI128V 0x5c000027
  9650. +#define MASK_VSXSEG3EI128V 0xfc00707f
  9651. +#define MATCH_VLXSEG4EI128V 0x7c000007
  9652. +#define MASK_VLXSEG4EI128V 0xfc00707f
  9653. +#define MATCH_VSXSEG4EI128V 0x7c000027
  9654. +#define MASK_VSXSEG4EI128V 0xfc00707f
  9655. +#define MATCH_VLXSEG5EI128V 0x9c000007
  9656. +#define MASK_VLXSEG5EI128V 0xfc00707f
  9657. +#define MATCH_VSXSEG5EI128V 0x9c000027
  9658. +#define MASK_VSXSEG5EI128V 0xfc00707f
  9659. +#define MATCH_VLXSEG6EI128V 0xbc000007
  9660. +#define MASK_VLXSEG6EI128V 0xfc00707f
  9661. +#define MATCH_VSXSEG6EI128V 0xbc000027
  9662. +#define MASK_VSXSEG6EI128V 0xfc00707f
  9663. +#define MATCH_VLXSEG7EI128V 0xdc000007
  9664. +#define MASK_VLXSEG7EI128V 0xfc00707f
  9665. +#define MATCH_VSXSEG7EI128V 0xdc000027
  9666. +#define MASK_VSXSEG7EI128V 0xfc00707f
  9667. +#define MATCH_VLXSEG8EI128V 0xfc000007
  9668. +#define MASK_VLXSEG8EI128V 0xfc00707f
  9669. +#define MATCH_VSXSEG8EI128V 0xfc000027
  9670. +#define MASK_VSXSEG8EI128V 0xfc00707f
  9671. +
  9672. +#define MATCH_VLXSEG2EI256V 0x3c005007
  9673. +#define MASK_VLXSEG2EI256V 0xfc00707f
  9674. +#define MATCH_VSXSEG2EI256V 0x3c005027
  9675. +#define MASK_VSXSEG2EI256V 0xfc00707f
  9676. +#define MATCH_VLXSEG3EI256V 0x5c005007
  9677. +#define MASK_VLXSEG3EI256V 0xfc00707f
  9678. +#define MATCH_VSXSEG3EI256V 0x5c005027
  9679. +#define MASK_VSXSEG3EI256V 0xfc00707f
  9680. +#define MATCH_VLXSEG4EI256V 0x7c005007
  9681. +#define MASK_VLXSEG4EI256V 0xfc00707f
  9682. +#define MATCH_VSXSEG4EI256V 0x7c005027
  9683. +#define MASK_VSXSEG4EI256V 0xfc00707f
  9684. +#define MATCH_VLXSEG5EI256V 0x9c005007
  9685. +#define MASK_VLXSEG5EI256V 0xfc00707f
  9686. +#define MATCH_VSXSEG5EI256V 0x9c005027
  9687. +#define MASK_VSXSEG5EI256V 0xfc00707f
  9688. +#define MATCH_VLXSEG6EI256V 0xbc005007
  9689. +#define MASK_VLXSEG6EI256V 0xfc00707f
  9690. +#define MATCH_VSXSEG6EI256V 0xbc005027
  9691. +#define MASK_VSXSEG6EI256V 0xfc00707f
  9692. +#define MATCH_VLXSEG7EI256V 0xdc005007
  9693. +#define MASK_VLXSEG7EI256V 0xfc00707f
  9694. +#define MATCH_VSXSEG7EI256V 0xdc005027
  9695. +#define MASK_VSXSEG7EI256V 0xfc00707f
  9696. +#define MATCH_VLXSEG8EI256V 0xfc005007
  9697. +#define MASK_VLXSEG8EI256V 0xfc00707f
  9698. +#define MATCH_VSXSEG8EI256V 0xfc005027
  9699. +#define MASK_VSXSEG8EI256V 0xfc00707f
  9700. +
  9701. +#define MATCH_VLXSEG2EI512V 0x3c006007
  9702. +#define MASK_VLXSEG2EI512V 0xfc00707f
  9703. +#define MATCH_VSXSEG2EI512V 0x3c006027
  9704. +#define MASK_VSXSEG2EI512V 0xfc00707f
  9705. +#define MATCH_VLXSEG3EI512V 0x5c006007
  9706. +#define MASK_VLXSEG3EI512V 0xfc00707f
  9707. +#define MATCH_VSXSEG3EI512V 0x5c006027
  9708. +#define MASK_VSXSEG3EI512V 0xfc00707f
  9709. +#define MATCH_VLXSEG4EI512V 0x7c006007
  9710. +#define MASK_VLXSEG4EI512V 0xfc00707f
  9711. +#define MATCH_VSXSEG4EI512V 0x7c006027
  9712. +#define MASK_VSXSEG4EI512V 0xfc00707f
  9713. +#define MATCH_VLXSEG5EI512V 0x9c006007
  9714. +#define MASK_VLXSEG5EI512V 0xfc00707f
  9715. +#define MATCH_VSXSEG5EI512V 0x9c006027
  9716. +#define MASK_VSXSEG5EI512V 0xfc00707f
  9717. +#define MATCH_VLXSEG6EI512V 0xbc006007
  9718. +#define MASK_VLXSEG6EI512V 0xfc00707f
  9719. +#define MATCH_VSXSEG6EI512V 0xbc006027
  9720. +#define MASK_VSXSEG6EI512V 0xfc00707f
  9721. +#define MATCH_VLXSEG7EI512V 0xdc006007
  9722. +#define MASK_VLXSEG7EI512V 0xfc00707f
  9723. +#define MATCH_VSXSEG7EI512V 0xdc006027
  9724. +#define MASK_VSXSEG7EI512V 0xfc00707f
  9725. +#define MATCH_VLXSEG8EI512V 0xfc006007
  9726. +#define MASK_VLXSEG8EI512V 0xfc00707f
  9727. +#define MATCH_VSXSEG8EI512V 0xfc006027
  9728. +#define MASK_VSXSEG8EI512V 0xfc00707f
  9729. +
  9730. +#define MATCH_VLXSEG2EI1024V 0x3c007007
  9731. +#define MASK_VLXSEG2EI1024V 0xfc00707f
  9732. +#define MATCH_VSXSEG2EI1024V 0x3c007027
  9733. +#define MASK_VSXSEG2EI1024V 0xfc00707f
  9734. +#define MATCH_VLXSEG3EI1024V 0x5c007007
  9735. +#define MASK_VLXSEG3EI1024V 0xfc00707f
  9736. +#define MATCH_VSXSEG3EI1024V 0x5c007027
  9737. +#define MASK_VSXSEG3EI1024V 0xfc00707f
  9738. +#define MATCH_VLXSEG4EI1024V 0x7c007007
  9739. +#define MASK_VLXSEG4EI1024V 0xfc00707f
  9740. +#define MATCH_VSXSEG4EI1024V 0x7c007027
  9741. +#define MASK_VSXSEG4EI1024V 0xfc00707f
  9742. +#define MATCH_VLXSEG5EI1024V 0x9c007007
  9743. +#define MASK_VLXSEG5EI1024V 0xfc00707f
  9744. +#define MATCH_VSXSEG5EI1024V 0x9c007027
  9745. +#define MASK_VSXSEG5EI1024V 0xfc00707f
  9746. +#define MATCH_VLXSEG6EI1024V 0xbc007007
  9747. +#define MASK_VLXSEG6EI1024V 0xfc00707f
  9748. +#define MATCH_VSXSEG6EI1024V 0xbc007027
  9749. +#define MASK_VSXSEG6EI1024V 0xfc00707f
  9750. +#define MATCH_VLXSEG7EI1024V 0xdc007007
  9751. +#define MASK_VLXSEG7EI1024V 0xfc00707f
  9752. +#define MATCH_VSXSEG7EI1024V 0xdc007027
  9753. +#define MASK_VSXSEG7EI1024V 0xfc00707f
  9754. +#define MATCH_VLXSEG8EI1024V 0xfc007007
  9755. +#define MASK_VLXSEG8EI1024V 0xfc00707f
  9756. +#define MATCH_VSXSEG8EI1024V 0xfc007027
  9757. +#define MASK_VSXSEG8EI1024V 0xfc00707f
  9758. +
  9759. +#define MATCH_VLSEG2E8FFV 0x21000007
  9760. +#define MASK_VLSEG2E8FFV 0xfdf0707f
  9761. +#define MATCH_VLSEG3E8FFV 0x41000007
  9762. +#define MASK_VLSEG3E8FFV 0xfdf0707f
  9763. +#define MATCH_VLSEG4E8FFV 0x61000007
  9764. +#define MASK_VLSEG4E8FFV 0xfdf0707f
  9765. +#define MATCH_VLSEG5E8FFV 0x81000007
  9766. +#define MASK_VLSEG5E8FFV 0xfdf0707f
  9767. +#define MATCH_VLSEG6E8FFV 0xa1000007
  9768. +#define MASK_VLSEG6E8FFV 0xfdf0707f
  9769. +#define MATCH_VLSEG7E8FFV 0xc1000007
  9770. +#define MASK_VLSEG7E8FFV 0xfdf0707f
  9771. +#define MATCH_VLSEG8E8FFV 0xe1000007
  9772. +#define MASK_VLSEG8E8FFV 0xfdf0707f
  9773. +
  9774. +#define MATCH_VLSEG2E16FFV 0x21005007
  9775. +#define MASK_VLSEG2E16FFV 0xfdf0707f
  9776. +#define MATCH_VLSEG3E16FFV 0x41005007
  9777. +#define MASK_VLSEG3E16FFV 0xfdf0707f
  9778. +#define MATCH_VLSEG4E16FFV 0x61005007
  9779. +#define MASK_VLSEG4E16FFV 0xfdf0707f
  9780. +#define MATCH_VLSEG5E16FFV 0x81005007
  9781. +#define MASK_VLSEG5E16FFV 0xfdf0707f
  9782. +#define MATCH_VLSEG6E16FFV 0xa1005007
  9783. +#define MASK_VLSEG6E16FFV 0xfdf0707f
  9784. +#define MATCH_VLSEG7E16FFV 0xc1005007
  9785. +#define MASK_VLSEG7E16FFV 0xfdf0707f
  9786. +#define MATCH_VLSEG8E16FFV 0xe1005007
  9787. +#define MASK_VLSEG8E16FFV 0xfdf0707f
  9788. +
  9789. +#define MATCH_VLSEG2E32FFV 0x21006007
  9790. +#define MASK_VLSEG2E32FFV 0xfdf0707f
  9791. +#define MATCH_VLSEG3E32FFV 0x41006007
  9792. +#define MASK_VLSEG3E32FFV 0xfdf0707f
  9793. +#define MATCH_VLSEG4E32FFV 0x61006007
  9794. +#define MASK_VLSEG4E32FFV 0xfdf0707f
  9795. +#define MATCH_VLSEG5E32FFV 0x81006007
  9796. +#define MASK_VLSEG5E32FFV 0xfdf0707f
  9797. +#define MATCH_VLSEG6E32FFV 0xa1006007
  9798. +#define MASK_VLSEG6E32FFV 0xfdf0707f
  9799. +#define MATCH_VLSEG7E32FFV 0xc1006007
  9800. +#define MASK_VLSEG7E32FFV 0xfdf0707f
  9801. +#define MATCH_VLSEG8E32FFV 0xe1006007
  9802. +#define MASK_VLSEG8E32FFV 0xfdf0707f
  9803. +
  9804. +#define MATCH_VLSEG2E64FFV 0x21007007
  9805. +#define MASK_VLSEG2E64FFV 0xfdf0707f
  9806. +#define MATCH_VLSEG3E64FFV 0x41007007
  9807. +#define MASK_VLSEG3E64FFV 0xfdf0707f
  9808. +#define MATCH_VLSEG4E64FFV 0x61007007
  9809. +#define MASK_VLSEG4E64FFV 0xfdf0707f
  9810. +#define MATCH_VLSEG5E64FFV 0x81007007
  9811. +#define MASK_VLSEG5E64FFV 0xfdf0707f
  9812. +#define MATCH_VLSEG6E64FFV 0xa1007007
  9813. +#define MASK_VLSEG6E64FFV 0xfdf0707f
  9814. +#define MATCH_VLSEG7E64FFV 0xc1007007
  9815. +#define MASK_VLSEG7E64FFV 0xfdf0707f
  9816. +#define MATCH_VLSEG8E64FFV 0xe1007007
  9817. +#define MASK_VLSEG8E64FFV 0xfdf0707f
  9818. +
  9819. +#define MATCH_VLSEG2E128FFV 0x31000007
  9820. +#define MASK_VLSEG2E128FFV 0xfdf0707f
  9821. +#define MATCH_VLSEG3E128FFV 0x51000007
  9822. +#define MASK_VLSEG3E128FFV 0xfdf0707f
  9823. +#define MATCH_VLSEG4E128FFV 0x71000007
  9824. +#define MASK_VLSEG4E128FFV 0xfdf0707f
  9825. +#define MATCH_VLSEG5E128FFV 0x91000007
  9826. +#define MASK_VLSEG5E128FFV 0xfdf0707f
  9827. +#define MATCH_VLSEG6E128FFV 0xb1000007
  9828. +#define MASK_VLSEG6E128FFV 0xfdf0707f
  9829. +#define MATCH_VLSEG7E128FFV 0xd1000007
  9830. +#define MASK_VLSEG7E128FFV 0xfdf0707f
  9831. +#define MATCH_VLSEG8E128FFV 0xf1000007
  9832. +#define MASK_VLSEG8E128FFV 0xfdf0707f
  9833. +
  9834. +#define MATCH_VLSEG2E256FFV 0x31005007
  9835. +#define MASK_VLSEG2E256FFV 0xfdf0707f
  9836. +#define MATCH_VLSEG3E256FFV 0x51005007
  9837. +#define MASK_VLSEG3E256FFV 0xfdf0707f
  9838. +#define MATCH_VLSEG4E256FFV 0x71005007
  9839. +#define MASK_VLSEG4E256FFV 0xfdf0707f
  9840. +#define MATCH_VLSEG5E256FFV 0x91005007
  9841. +#define MASK_VLSEG5E256FFV 0xfdf0707f
  9842. +#define MATCH_VLSEG6E256FFV 0xb1005007
  9843. +#define MASK_VLSEG6E256FFV 0xfdf0707f
  9844. +#define MATCH_VLSEG7E256FFV 0xd1005007
  9845. +#define MASK_VLSEG7E256FFV 0xfdf0707f
  9846. +#define MATCH_VLSEG8E256FFV 0xf1005007
  9847. +#define MASK_VLSEG8E256FFV 0xfdf0707f
  9848. +
  9849. +#define MATCH_VLSEG2E512FFV 0x31006007
  9850. +#define MASK_VLSEG2E512FFV 0xfdf0707f
  9851. +#define MATCH_VLSEG3E512FFV 0x51006007
  9852. +#define MASK_VLSEG3E512FFV 0xfdf0707f
  9853. +#define MATCH_VLSEG4E512FFV 0x71006007
  9854. +#define MASK_VLSEG4E512FFV 0xfdf0707f
  9855. +#define MATCH_VLSEG5E512FFV 0x91006007
  9856. +#define MASK_VLSEG5E512FFV 0xfdf0707f
  9857. +#define MATCH_VLSEG6E512FFV 0xb1006007
  9858. +#define MASK_VLSEG6E512FFV 0xfdf0707f
  9859. +#define MATCH_VLSEG7E512FFV 0xd1006007
  9860. +#define MASK_VLSEG7E512FFV 0xfdf0707f
  9861. +#define MATCH_VLSEG8E512FFV 0xf1006007
  9862. +#define MASK_VLSEG8E512FFV 0xfdf0707f
  9863. +
  9864. +#define MATCH_VLSEG2E1024FFV 0x31007007
  9865. +#define MASK_VLSEG2E1024FFV 0xfdf0707f
  9866. +#define MATCH_VLSEG3E1024FFV 0x51007007
  9867. +#define MASK_VLSEG3E1024FFV 0xfdf0707f
  9868. +#define MATCH_VLSEG4E1024FFV 0x71007007
  9869. +#define MASK_VLSEG4E1024FFV 0xfdf0707f
  9870. +#define MATCH_VLSEG5E1024FFV 0x91007007
  9871. +#define MASK_VLSEG5E1024FFV 0xfdf0707f
  9872. +#define MATCH_VLSEG6E1024FFV 0xb1007007
  9873. +#define MASK_VLSEG6E1024FFV 0xfdf0707f
  9874. +#define MATCH_VLSEG7E1024FFV 0xd1007007
  9875. +#define MASK_VLSEG7E1024FFV 0xfdf0707f
  9876. +#define MATCH_VLSEG8E1024FFV 0xf1007007
  9877. +#define MASK_VLSEG8E1024FFV 0xfdf0707f
  9878. +
  9879. +#define MATCH_VL1RV 0x02800007
  9880. +#define MASK_VL1RV 0xfff0707f
  9881. +#define MATCH_VS1RV 0x02800027
  9882. +#define MASK_VS1RV 0xfff0707f
  9883. +
  9884. +/* Temporary AMO encoding info
  9885. +
  9886. +width
  9887. +010 AMO*.W
  9888. +011 AMO*.D
  9889. +100 AMO*.Q
  9890. +000 VAMO*EI8.V
  9891. +101 VAMO*EI16.V
  9892. +110 VAMO*EI32.V
  9893. +111 VAMO*EI64.V
  9894. +
  9895. +amoop
  9896. +00001 vamoswap
  9897. +00000 vamoadd
  9898. +00100 vamoxor
  9899. +01100 vamoand
  9900. +01000 vamoor
  9901. +10000 vamomin
  9902. +10100 vamomax
  9903. +11000 vamominu
  9904. +11100 vamomaxu
  9905. +
  9906. + 31-27 26 25 24-20 19-15 14-12 11-7 6-0
  9907. + amoop wd vm vs2 rs1 width vs3/vd opcode
  9908. + 00001 x 1 xxxxx xxxxx 110 xxxxx 0101111
  9909. + 0000 1x1x xxxx xxxx x110 xxxx x010 1111
  9910. + 1111 1010 0000 0000 0111 0000 0111 1111 */
  9911. +
  9912. +#define MATCH_VAMOADDEI8V 0x0000002f
  9913. +#define MASK_VAMOADDEI8V 0xf800707f
  9914. +#define MATCH_VAMOSWAPEI8V 0x0800002f
  9915. +#define MASK_VAMOSWAPEI8V 0xf800707f
  9916. +#define MATCH_VAMOXOREI8V 0x2000002f
  9917. +#define MASK_VAMOXOREI8V 0xf800707f
  9918. +#define MATCH_VAMOANDEI8V 0x6000002f
  9919. +#define MASK_VAMOANDEI8V 0xf800707f
  9920. +#define MATCH_VAMOOREI8V 0x4000002f
  9921. +#define MASK_VAMOOREI8V 0xf800707f
  9922. +#define MATCH_VAMOMINEI8V 0x8000002f
  9923. +#define MASK_VAMOMINEI8V 0xf800707f
  9924. +#define MATCH_VAMOMAXEI8V 0xa000002f
  9925. +#define MASK_VAMOMAXEI8V 0xf800707f
  9926. +#define MATCH_VAMOMINUEI8V 0xc000002f
  9927. +#define MASK_VAMOMINUEI8V 0xf800707f
  9928. +#define MATCH_VAMOMAXUEI8V 0xe000002f
  9929. +#define MASK_VAMOMAXUEI8V 0xf800707f
  9930. +
  9931. +#define MATCH_VAMOADDEI16V 0x0000502f
  9932. +#define MASK_VAMOADDEI16V 0xf800707f
  9933. +#define MATCH_VAMOSWAPEI16V 0x0800502f
  9934. +#define MASK_VAMOSWAPEI16V 0xf800707f
  9935. +#define MATCH_VAMOXOREI16V 0x2000502f
  9936. +#define MASK_VAMOXOREI16V 0xf800707f
  9937. +#define MATCH_VAMOANDEI16V 0x6000502f
  9938. +#define MASK_VAMOANDEI16V 0xf800707f
  9939. +#define MATCH_VAMOOREI16V 0x4000502f
  9940. +#define MASK_VAMOOREI16V 0xf800707f
  9941. +#define MATCH_VAMOMINEI16V 0x8000502f
  9942. +#define MASK_VAMOMINEI16V 0xf800707f
  9943. +#define MATCH_VAMOMAXEI16V 0xa000502f
  9944. +#define MASK_VAMOMAXEI16V 0xf800707f
  9945. +#define MATCH_VAMOMINUEI16V 0xc000502f
  9946. +#define MASK_VAMOMINUEI16V 0xf800707f
  9947. +#define MATCH_VAMOMAXUEI16V 0xe000502f
  9948. +#define MASK_VAMOMAXUEI16V 0xf800707f
  9949. +
  9950. +#define MATCH_VAMOADDEI32V 0x0000602f
  9951. +#define MASK_VAMOADDEI32V 0xf800707f
  9952. +#define MATCH_VAMOSWAPEI32V 0x0800602f
  9953. +#define MASK_VAMOSWAPEI32V 0xf800707f
  9954. +#define MATCH_VAMOXOREI32V 0x2000602f
  9955. +#define MASK_VAMOXOREI32V 0xf800707f
  9956. +#define MATCH_VAMOANDEI32V 0x6000602f
  9957. +#define MASK_VAMOANDEI32V 0xf800707f
  9958. +#define MATCH_VAMOOREI32V 0x4000602f
  9959. +#define MASK_VAMOOREI32V 0xf800707f
  9960. +#define MATCH_VAMOMINEI32V 0x8000602f
  9961. +#define MASK_VAMOMINEI32V 0xf800707f
  9962. +#define MATCH_VAMOMAXEI32V 0xa000602f
  9963. +#define MASK_VAMOMAXEI32V 0xf800707f
  9964. +#define MATCH_VAMOMINUEI32V 0xc000602f
  9965. +#define MASK_VAMOMINUEI32V 0xf800707f
  9966. +#define MATCH_VAMOMAXUEI32V 0xe000602f
  9967. +#define MASK_VAMOMAXUEI32V 0xf800707f
  9968. +
  9969. +#define MATCH_VAMOADDEI64V 0x0000702f
  9970. +#define MASK_VAMOADDEI64V 0xf800707f
  9971. +#define MATCH_VAMOSWAPEI64V 0x0800702f
  9972. +#define MASK_VAMOSWAPEI64V 0xf800707f
  9973. +#define MATCH_VAMOXOREI64V 0x2000702f
  9974. +#define MASK_VAMOXOREI64V 0xf800707f
  9975. +#define MATCH_VAMOANDEI64V 0x6000702f
  9976. +#define MASK_VAMOANDEI64V 0xf800707f
  9977. +#define MATCH_VAMOOREI64V 0x4000702f
  9978. +#define MASK_VAMOOREI64V 0xf800707f
  9979. +#define MATCH_VAMOMINEI64V 0x8000702f
  9980. +#define MASK_VAMOMINEI64V 0xf800707f
  9981. +#define MATCH_VAMOMAXEI64V 0xa000702f
  9982. +#define MASK_VAMOMAXEI64V 0xf800707f
  9983. +#define MATCH_VAMOMINUEI64V 0xc000702f
  9984. +#define MASK_VAMOMINUEI64V 0xf800707f
  9985. +#define MATCH_VAMOMAXUEI64V 0xe000702f
  9986. +#define MASK_VAMOMAXUEI64V 0xf800707f
  9987. +
  9988. +/* Temporary ALU encoding info
  9989. +
  9990. +funct3
  9991. +000 OPIVV vv
  9992. +001 OPFVV vv
  9993. +010 OPMVV vv
  9994. +011 OPIVI vi simm[4:0]
  9995. +100 OPIVX vx GPR x-reg rs1
  9996. +101 OPFVF vf FP f-reg rs1
  9997. +110 OPMVX vx GPR x-reg rs1
  9998. +111 OPCFG si GPR x-reg rs1 & rs2/imm
  9999. +
  10000. +INT OPI
  10001. +funct6
  10002. +000000 vadd
  10003. +000001
  10004. +000010 vsub
  10005. +000011 vrsub
  10006. +000100 vminu
  10007. +000101 vmin
  10008. +000110 vmaxu
  10009. +000111 vmax
  10010. +001000
  10011. +001001 vand
  10012. +001010 vor
  10013. +001011 vxor
  10014. +001100 vrgather
  10015. +001101
  10016. +001110 vslideup
  10017. +001111 vslidedown
  10018. +010000 vadc
  10019. +010001 vmadc
  10020. +010010 vsbc
  10021. +010011 vmsbc
  10022. +010100
  10023. +010101
  10024. +010110
  10025. +010111 vmerge/vmv
  10026. +011000 vmseq
  10027. +011001 vmsne
  10028. +011010 vmsltu
  10029. +011011 vmslt
  10030. +011100 vmsleu
  10031. +011101 vmsle
  10032. +011110 vmsgtu
  10033. +011111 vmsgt
  10034. +100000 vsaddu
  10035. +100001 vsadd
  10036. +100010 vssubu
  10037. +100011 vssub
  10038. +100100
  10039. +100101 vsll
  10040. +100110
  10041. +100111 vmv<nf>r (nf = 1, 2, 4, 8)
  10042. +101000 vsrl
  10043. +101001 vsra
  10044. +101010 vssrl
  10045. +101011 vssra
  10046. +101100 vnsrl
  10047. +101101 vnsra
  10048. +101110 vnclipu
  10049. +101111 vnclip
  10050. +110000 vwredsumu
  10051. +110001 vwredsum
  10052. +110010
  10053. +110011
  10054. +110100
  10055. +110101
  10056. +110110
  10057. +110111
  10058. +111000 vdotu **
  10059. +111001 vdot **
  10060. +111010
  10061. +111011
  10062. +111100 vqmaccu
  10063. +111101 vqmacc
  10064. +111110 vqmaccus
  10065. +111111 vqmaccsu
  10066. +
  10067. +INT OPM
  10068. +funct6
  10069. +000000 vredsum
  10070. +000001 vredand
  10071. +000010 vredor
  10072. +000011 vredxor
  10073. +000100 vredminu
  10074. +000101 vredmin
  10075. +000110 vredmaxu
  10076. +000111 vredmax
  10077. +001000 vaaddu
  10078. +001001 vaadd
  10079. +001010 vasubu
  10080. +001011 vasub
  10081. +001100
  10082. +001101
  10083. +001110 vslide1up
  10084. +001111 vslide1down
  10085. +010000 VRXUNARY0/VWXUNARY0
  10086. +010001
  10087. +010010 VXUNARY0
  10088. +010011
  10089. +010100 VMUNARY0
  10090. +010101
  10091. +010110
  10092. +010111 vcompress
  10093. +011000 vmandnot
  10094. +011001 vmand
  10095. +011010 vmor
  10096. +011011 vmxor
  10097. +011100 vmornot
  10098. +011101 vmnand
  10099. +011110 vmnor
  10100. +011111 vmxnor
  10101. +100000 vdivu
  10102. +100001 vdiv
  10103. +100010 vremu
  10104. +100011 vrem
  10105. +100100 vmulhu
  10106. +100101 vmul
  10107. +100110 vmulhsu
  10108. +100111 vmulh
  10109. +101000
  10110. +101001 vmadd
  10111. +101010
  10112. +101011 vnmsub
  10113. +101100
  10114. +101101 vmacc
  10115. +101110
  10116. +101111 vnmsac
  10117. +110000 vwaddu
  10118. +110001 vwadd
  10119. +110010 vwsubu
  10120. +110011 vwsub
  10121. +110100 vwaddu.w
  10122. +110101 vwadd.w
  10123. +110110 vwsubu.w
  10124. +110111 vwsub.w
  10125. +111000 vwmulu
  10126. +111001
  10127. +111010 vwmulsu
  10128. +111011 vwmul
  10129. +111100 vwmaccu
  10130. +111101 vwmacc
  10131. +111110 vwmaccus
  10132. +111111 vwmaccsu
  10133. +
  10134. +VRXUNARY0
  10135. +vs2, funct3=X
  10136. +00000 vmv.s.x
  10137. +
  10138. +VWXUNARY0
  10139. +vs1, funct3=V
  10140. +00000 vmv.x.s
  10141. +10000 vpopc
  10142. +10001 vfirst
  10143. +
  10144. +VXUNARY0
  10145. +vs1, funct3=V
  10146. +00010 vzext.vf8
  10147. +00011 vsext.vf8
  10148. +00100 vzext.vf4
  10149. +00101 vsext.vf4
  10150. +00110 vzext.vf2
  10151. +00111 vsext.vf2
  10152. +
  10153. +VMUNARY0
  10154. +rs1
  10155. +00001 vmsbf
  10156. +00010 vmsof
  10157. +00011 vmsif
  10158. +10000 viota
  10159. +10001 vid
  10160. +
  10161. +VFLOAT
  10162. +funct6
  10163. +000000 vfadd
  10164. +000001 vfredsum
  10165. +000010 vfsub
  10166. +000011 vfredosum
  10167. +000100 vfmin
  10168. +000101 vfredmin
  10169. +000110 vfmax
  10170. +000111 vfredmax
  10171. +001000 vfsgnj
  10172. +001001 vfsgnn
  10173. +001010 vfsgnx
  10174. +001011
  10175. +001100
  10176. +001101
  10177. +001110 vfslide1up
  10178. +001111 vfslide1down
  10179. +010000 VRFUNARY0/VWFUNARY0
  10180. +010001
  10181. +010010 VFUNARY0
  10182. +010011 VFUNARY1
  10183. +010100
  10184. +010101
  10185. +010110
  10186. +010111 vfmerge/vfmv
  10187. +011000 vmfeq
  10188. +011001 vmfle
  10189. +011010
  10190. +011011 vmflt
  10191. +011100 vmfne
  10192. +011101 vmfgt
  10193. +011110
  10194. +011111 vmfge
  10195. +100000 vfdiv
  10196. +100001 vfrdiv
  10197. +100010
  10198. +100011
  10199. +100100 vfmul
  10200. +100101
  10201. +100110
  10202. +100111 vfrsub
  10203. +101000 vfmadd
  10204. +101001 vfnmadd
  10205. +101010 vfmsub
  10206. +101011 vfnmsub
  10207. +101100 vfmacc
  10208. +101101 vfnmacc
  10209. +101110 vfmsac
  10210. +101111 vfnmsac
  10211. +110000 vfwadd
  10212. +110001 vfwredsum
  10213. +110010 vfwsub
  10214. +110011 vfwredosum
  10215. +110100 vfwadd.w
  10216. +110101
  10217. +110110 vfwsub.w
  10218. +110111
  10219. +111000 vfwmul
  10220. +111001 vfdot
  10221. +111010
  10222. +111011
  10223. +111100 vfwmacc
  10224. +111101 vfwnmacc
  10225. +111110 vfwmsac
  10226. +111111 vfwnmsac
  10227. +
  10228. +VRFUNARY0
  10229. +vs2, funct3=F
  10230. +00000 vfmv.s.f
  10231. +
  10232. +VWFUNARY0
  10233. +vs1, funct3=V
  10234. +00000 vfmv.f.s
  10235. +
  10236. +VFUNARY0
  10237. +vs1
  10238. +00000 vfcvt.xu.f.v
  10239. +00001 vfcvt.x.f.v
  10240. +00010 vfcvt.f.xu.v
  10241. +00011 vfcvt.f.x.v
  10242. +00110 vfcvt.rtz.xu.f.v
  10243. +00111 vfcvt.rtz.x.f.v
  10244. +
  10245. +01000 vfwcvt.xu.f.v
  10246. +01001 vfwcvt.x.f.v
  10247. +01010 vfwcvt.f.xu.v
  10248. +01011 vfwcvt.f.x.v
  10249. +01100 vfwcvt.f.f.v
  10250. +01110 vfwcvt.rtz.xu.f.v
  10251. +01111 vfwcvt.rtz.x.f.v
  10252. +
  10253. +10000 vfncvt.xu.f.w
  10254. +10001 vfncvt.x.f.w
  10255. +10010 vfncvt.f.xu.w
  10256. +10011 vfncvt.f.x.w
  10257. +10100 vfncvt.f.f.w
  10258. +10101 vfncvt.rod.f.f.w
  10259. +10110 vfncvt.rtz.xu.f.v
  10260. +10111 vfncvt.rtz.x.f.v
  10261. +
  10262. +VFUNARY1
  10263. +vs1
  10264. +00000 vfsqrt.v
  10265. +10000 vfclass.v
  10266. +
  10267. +31-26 25 24-20 19-15 14-12 11-7 6-0
  10268. +funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
  10269. +010000 x xxxxx 00000 001 xxxxx 1010111
  10270. +0100 00xx xxxx 0000 0001 xxxx x101 0111
  10271. +*/
  10272. +
  10273. +#define MATCH_VADDVV 0x00000057
  10274. +#define MASK_VADDVV 0xfc00707f
  10275. +#define MATCH_VADDVX 0x00004057
  10276. +#define MASK_VADDVX 0xfc00707f
  10277. +#define MATCH_VADDVI 0x00003057
  10278. +#define MASK_VADDVI 0xfc00707f
  10279. +#define MATCH_VSUBVV 0x08000057
  10280. +#define MASK_VSUBVV 0xfc00707f
  10281. +#define MATCH_VSUBVX 0x08004057
  10282. +#define MASK_VSUBVX 0xfc00707f
  10283. +#define MATCH_VRSUBVX 0x0c004057
  10284. +#define MASK_VRSUBVX 0xfc00707f
  10285. +#define MATCH_VRSUBVI 0x0c003057
  10286. +#define MASK_VRSUBVI 0xfc00707f
  10287. +
  10288. +#define MATCH_VWCVTXXV 0xc4006057
  10289. +#define MASK_VWCVTXXV 0xfc0ff07f
  10290. +#define MATCH_VWCVTUXXV 0xc0006057
  10291. +#define MASK_VWCVTUXXV 0xfc0ff07f
  10292. +
  10293. +#define MATCH_VWADDVV 0xc4002057
  10294. +#define MASK_VWADDVV 0xfc00707f
  10295. +#define MATCH_VWADDVX 0xc4006057
  10296. +#define MASK_VWADDVX 0xfc00707f
  10297. +#define MATCH_VWSUBVV 0xcc002057
  10298. +#define MASK_VWSUBVV 0xfc00707f
  10299. +#define MATCH_VWSUBVX 0xcc006057
  10300. +#define MASK_VWSUBVX 0xfc00707f
  10301. +#define MATCH_VWADDWV 0xd4002057
  10302. +#define MASK_VWADDWV 0xfc00707f
  10303. +#define MATCH_VWADDWX 0xd4006057
  10304. +#define MASK_VWADDWX 0xfc00707f
  10305. +#define MATCH_VWSUBWV 0xdc002057
  10306. +#define MASK_VWSUBWV 0xfc00707f
  10307. +#define MATCH_VWSUBWX 0xdc006057
  10308. +#define MASK_VWSUBWX 0xfc00707f
  10309. +#define MATCH_VWADDUVV 0xc0002057
  10310. +#define MASK_VWADDUVV 0xfc00707f
  10311. +#define MATCH_VWADDUVX 0xc0006057
  10312. +#define MASK_VWADDUVX 0xfc00707f
  10313. +#define MATCH_VWSUBUVV 0xc8002057
  10314. +#define MASK_VWSUBUVV 0xfc00707f
  10315. +#define MATCH_VWSUBUVX 0xc8006057
  10316. +#define MASK_VWSUBUVX 0xfc00707f
  10317. +#define MATCH_VWADDUWV 0xd0002057
  10318. +#define MASK_VWADDUWV 0xfc00707f
  10319. +#define MATCH_VWADDUWX 0xd0006057
  10320. +#define MASK_VWADDUWX 0xfc00707f
  10321. +#define MATCH_VWSUBUWV 0xd8002057
  10322. +#define MASK_VWSUBUWV 0xfc00707f
  10323. +#define MATCH_VWSUBUWX 0xd8006057
  10324. +#define MASK_VWSUBUWX 0xfc00707f
  10325. +
  10326. +#define MATCH_VZEXT_VF8 0x48012057
  10327. +#define MASK_VZEXT_VF8 0xfc0ff07f
  10328. +#define MATCH_VSEXT_VF8 0x4801a057
  10329. +#define MASK_VSEXT_VF8 0xfc0ff07f
  10330. +#define MATCH_VZEXT_VF4 0x48022057
  10331. +#define MASK_VZEXT_VF4 0xfc0ff07f
  10332. +#define MATCH_VSEXT_VF4 0x4802a057
  10333. +#define MASK_VSEXT_VF4 0xfc0ff07f
  10334. +#define MATCH_VZEXT_VF2 0x48032057
  10335. +#define MASK_VZEXT_VF2 0xfc0ff07f
  10336. +#define MATCH_VSEXT_VF2 0x4803a057
  10337. +#define MASK_VSEXT_VF2 0xfc0ff07f
  10338. +
  10339. +#define MATCH_VADCVVM 0x40000057
  10340. +#define MASK_VADCVVM 0xfe00707f
  10341. +#define MATCH_VADCVXM 0x40004057
  10342. +#define MASK_VADCVXM 0xfe00707f
  10343. +#define MATCH_VADCVIM 0x40003057
  10344. +#define MASK_VADCVIM 0xfe00707f
  10345. +#define MATCH_VMADCVVM 0x44000057
  10346. +#define MASK_VMADCVVM 0xfe00707f
  10347. +#define MATCH_VMADCVXM 0x44004057
  10348. +#define MASK_VMADCVXM 0xfe00707f
  10349. +#define MATCH_VMADCVIM 0x44003057
  10350. +#define MASK_VMADCVIM 0xfe00707f
  10351. +#define MATCH_VMADCVV 0x46000057
  10352. +#define MASK_VMADCVV 0xfe00707f
  10353. +#define MATCH_VMADCVX 0x46004057
  10354. +#define MASK_VMADCVX 0xfe00707f
  10355. +#define MATCH_VMADCVI 0x46003057
  10356. +#define MASK_VMADCVI 0xfe00707f
  10357. +#define MATCH_VSBCVVM 0x48000057
  10358. +#define MASK_VSBCVVM 0xfe00707f
  10359. +#define MATCH_VSBCVXM 0x48004057
  10360. +#define MASK_VSBCVXM 0xfe00707f
  10361. +#define MATCH_VMSBCVVM 0x4c000057
  10362. +#define MASK_VMSBCVVM 0xfe00707f
  10363. +#define MATCH_VMSBCVXM 0x4c004057
  10364. +#define MASK_VMSBCVXM 0xfe00707f
  10365. +#define MATCH_VMSBCVV 0x4e000057
  10366. +#define MASK_VMSBCVV 0xfe00707f
  10367. +#define MATCH_VMSBCVX 0x4e004057
  10368. +#define MASK_VMSBCVX 0xfe00707f
  10369. +
  10370. +#define MATCH_VNOTV 0x2c0fb057
  10371. +#define MASK_VNOTV 0xfc0ff07f
  10372. +
  10373. +#define MATCH_VANDVV 0x24000057
  10374. +#define MASK_VANDVV 0xfc00707f
  10375. +#define MATCH_VANDVX 0x24004057
  10376. +#define MASK_VANDVX 0xfc00707f
  10377. +#define MATCH_VANDVI 0x24003057
  10378. +#define MASK_VANDVI 0xfc00707f
  10379. +#define MATCH_VORVV 0x28000057
  10380. +#define MASK_VORVV 0xfc00707f
  10381. +#define MATCH_VORVX 0x28004057
  10382. +#define MASK_VORVX 0xfc00707f
  10383. +#define MATCH_VORVI 0x28003057
  10384. +#define MASK_VORVI 0xfc00707f
  10385. +#define MATCH_VXORVV 0x2c000057
  10386. +#define MASK_VXORVV 0xfc00707f
  10387. +#define MATCH_VXORVX 0x2c004057
  10388. +#define MASK_VXORVX 0xfc00707f
  10389. +#define MATCH_VXORVI 0x2c003057
  10390. +#define MASK_VXORVI 0xfc00707f
  10391. +
  10392. +#define MATCH_VSLLVV 0x94000057
  10393. +#define MASK_VSLLVV 0xfc00707f
  10394. +#define MATCH_VSLLVX 0x94004057
  10395. +#define MASK_VSLLVX 0xfc00707f
  10396. +#define MATCH_VSLLVI 0x94003057
  10397. +#define MASK_VSLLVI 0xfc00707f
  10398. +#define MATCH_VSRLVV 0xa0000057
  10399. +#define MASK_VSRLVV 0xfc00707f
  10400. +#define MATCH_VSRLVX 0xa0004057
  10401. +#define MASK_VSRLVX 0xfc00707f
  10402. +#define MATCH_VSRLVI 0xa0003057
  10403. +#define MASK_VSRLVI 0xfc00707f
  10404. +#define MATCH_VSRAVV 0xa4000057
  10405. +#define MASK_VSRAVV 0xfc00707f
  10406. +#define MATCH_VSRAVX 0xa4004057
  10407. +#define MASK_VSRAVX 0xfc00707f
  10408. +#define MATCH_VSRAVI 0xa4003057
  10409. +#define MASK_VSRAVI 0xfc00707f
  10410. +
  10411. +#define MATCH_VNSRLWV 0xb0000057
  10412. +#define MASK_VNSRLWV 0xfc00707f
  10413. +#define MATCH_VNSRLWX 0xb0004057
  10414. +#define MASK_VNSRLWX 0xfc00707f
  10415. +#define MATCH_VNSRLWI 0xb0003057
  10416. +#define MASK_VNSRLWI 0xfc00707f
  10417. +#define MATCH_VNSRAWV 0xb4000057
  10418. +#define MASK_VNSRAWV 0xfc00707f
  10419. +#define MATCH_VNSRAWX 0xb4004057
  10420. +#define MASK_VNSRAWX 0xfc00707f
  10421. +#define MATCH_VNSRAWI 0xb4003057
  10422. +#define MASK_VNSRAWI 0xfc00707f
  10423. +
  10424. +#define MATCH_VMSEQVV 0x60000057
  10425. +#define MASK_VMSEQVV 0xfc00707f
  10426. +#define MATCH_VMSEQVX 0x60004057
  10427. +#define MASK_VMSEQVX 0xfc00707f
  10428. +#define MATCH_VMSEQVI 0x60003057
  10429. +#define MASK_VMSEQVI 0xfc00707f
  10430. +#define MATCH_VMSNEVV 0x64000057
  10431. +#define MASK_VMSNEVV 0xfc00707f
  10432. +#define MATCH_VMSNEVX 0x64004057
  10433. +#define MASK_VMSNEVX 0xfc00707f
  10434. +#define MATCH_VMSNEVI 0x64003057
  10435. +#define MASK_VMSNEVI 0xfc00707f
  10436. +#define MATCH_VMSLTVV 0x6c000057
  10437. +#define MASK_VMSLTVV 0xfc00707f
  10438. +#define MATCH_VMSLTVX 0x6c004057
  10439. +#define MASK_VMSLTVX 0xfc00707f
  10440. +#define MATCH_VMSLTUVV 0x68000057
  10441. +#define MASK_VMSLTUVV 0xfc00707f
  10442. +#define MATCH_VMSLTUVX 0x68004057
  10443. +#define MASK_VMSLTUVX 0xfc00707f
  10444. +#define MATCH_VMSLEVV 0x74000057
  10445. +#define MASK_VMSLEVV 0xfc00707f
  10446. +#define MATCH_VMSLEVX 0x74004057
  10447. +#define MASK_VMSLEVX 0xfc00707f
  10448. +#define MATCH_VMSLEVI 0x74003057
  10449. +#define MASK_VMSLEVI 0xfc00707f
  10450. +#define MATCH_VMSLEUVV 0x70000057
  10451. +#define MASK_VMSLEUVV 0xfc00707f
  10452. +#define MATCH_VMSLEUVX 0x70004057
  10453. +#define MASK_VMSLEUVX 0xfc00707f
  10454. +#define MATCH_VMSLEUVI 0x70003057
  10455. +#define MASK_VMSLEUVI 0xfc00707f
  10456. +#define MATCH_VMSGTVX 0x7c004057
  10457. +#define MASK_VMSGTVX 0xfc00707f
  10458. +#define MATCH_VMSGTVI 0x7c003057
  10459. +#define MASK_VMSGTVI 0xfc00707f
  10460. +#define MATCH_VMSGTUVX 0x78004057
  10461. +#define MASK_VMSGTUVX 0xfc00707f
  10462. +#define MATCH_VMSGTUVI 0x78003057
  10463. +#define MASK_VMSGTUVI 0xfc00707f
  10464. +
  10465. +#define MATCH_VMINVV 0x14000057
  10466. +#define MASK_VMINVV 0xfc00707f
  10467. +#define MATCH_VMINVX 0x14004057
  10468. +#define MASK_VMINVX 0xfc00707f
  10469. +#define MATCH_VMAXVV 0x1c000057
  10470. +#define MASK_VMAXVV 0xfc00707f
  10471. +#define MATCH_VMAXVX 0x1c004057
  10472. +#define MASK_VMAXVX 0xfc00707f
  10473. +#define MATCH_VMINUVV 0x10000057
  10474. +#define MASK_VMINUVV 0xfc00707f
  10475. +#define MATCH_VMINUVX 0x10004057
  10476. +#define MASK_VMINUVX 0xfc00707f
  10477. +#define MATCH_VMAXUVV 0x18000057
  10478. +#define MASK_VMAXUVV 0xfc00707f
  10479. +#define MATCH_VMAXUVX 0x18004057
  10480. +#define MASK_VMAXUVX 0xfc00707f
  10481. +
  10482. +#define MATCH_VMULVV 0x94002057
  10483. +#define MASK_VMULVV 0xfc00707f
  10484. +#define MATCH_VMULVX 0x94006057
  10485. +#define MASK_VMULVX 0xfc00707f
  10486. +#define MATCH_VMULHVV 0x9c002057
  10487. +#define MASK_VMULHVV 0xfc00707f
  10488. +#define MATCH_VMULHVX 0x9c006057
  10489. +#define MASK_VMULHVX 0xfc00707f
  10490. +#define MATCH_VMULHUVV 0x90002057
  10491. +#define MASK_VMULHUVV 0xfc00707f
  10492. +#define MATCH_VMULHUVX 0x90006057
  10493. +#define MASK_VMULHUVX 0xfc00707f
  10494. +#define MATCH_VMULHSUVV 0x98002057
  10495. +#define MASK_VMULHSUVV 0xfc00707f
  10496. +#define MATCH_VMULHSUVX 0x98006057
  10497. +#define MASK_VMULHSUVX 0xfc00707f
  10498. +
  10499. +#define MATCH_VWMULVV 0xec002057
  10500. +#define MASK_VWMULVV 0xfc00707f
  10501. +#define MATCH_VWMULVX 0xec006057
  10502. +#define MASK_VWMULVX 0xfc00707f
  10503. +#define MATCH_VWMULUVV 0xe0002057
  10504. +#define MASK_VWMULUVV 0xfc00707f
  10505. +#define MATCH_VWMULUVX 0xe0006057
  10506. +#define MASK_VWMULUVX 0xfc00707f
  10507. +#define MATCH_VWMULSUVV 0xe8002057
  10508. +#define MASK_VWMULSUVV 0xfc00707f
  10509. +#define MATCH_VWMULSUVX 0xe8006057
  10510. +#define MASK_VWMULSUVX 0xfc00707f
  10511. +
  10512. +#define MATCH_VMACCVV 0xb4002057
  10513. +#define MASK_VMACCVV 0xfc00707f
  10514. +#define MATCH_VMACCVX 0xb4006057
  10515. +#define MASK_VMACCVX 0xfc00707f
  10516. +#define MATCH_VNMSACVV 0xbc002057
  10517. +#define MASK_VNMSACVV 0xfc00707f
  10518. +#define MATCH_VNMSACVX 0xbc006057
  10519. +#define MASK_VNMSACVX 0xfc00707f
  10520. +#define MATCH_VMADDVV 0xa4002057
  10521. +#define MASK_VMADDVV 0xfc00707f
  10522. +#define MATCH_VMADDVX 0xa4006057
  10523. +#define MASK_VMADDVX 0xfc00707f
  10524. +#define MATCH_VNMSUBVV 0xac002057
  10525. +#define MASK_VNMSUBVV 0xfc00707f
  10526. +#define MATCH_VNMSUBVX 0xac006057
  10527. +#define MASK_VNMSUBVX 0xfc00707f
  10528. +
  10529. +#define MATCH_VWMACCUVV 0xf0002057
  10530. +#define MASK_VWMACCUVV 0xfc00707f
  10531. +#define MATCH_VWMACCUVX 0xf0006057
  10532. +#define MASK_VWMACCUVX 0xfc00707f
  10533. +#define MATCH_VWMACCVV 0xf4002057
  10534. +#define MASK_VWMACCVV 0xfc00707f
  10535. +#define MATCH_VWMACCVX 0xf4006057
  10536. +#define MASK_VWMACCVX 0xfc00707f
  10537. +#define MATCH_VWMACCSUVV 0xfc002057
  10538. +#define MASK_VWMACCSUVV 0xfc00707f
  10539. +#define MATCH_VWMACCSUVX 0xfc006057
  10540. +#define MASK_VWMACCSUVX 0xfc00707f
  10541. +#define MATCH_VWMACCUSVX 0xf8006057
  10542. +#define MASK_VWMACCUSVX 0xfc00707f
  10543. +
  10544. +#define MATCH_VQMACCUVV 0xf0000057
  10545. +#define MASK_VQMACCUVV 0xfc00707f
  10546. +#define MATCH_VQMACCUVX 0xf0004057
  10547. +#define MASK_VQMACCUVX 0xfc00707f
  10548. +#define MATCH_VQMACCVV 0xf4000057
  10549. +#define MASK_VQMACCVV 0xfc00707f
  10550. +#define MATCH_VQMACCVX 0xf4004057
  10551. +#define MASK_VQMACCVX 0xfc00707f
  10552. +#define MATCH_VQMACCSUVV 0xfc000057
  10553. +#define MASK_VQMACCSUVV 0xfc00707f
  10554. +#define MATCH_VQMACCSUVX 0xfc004057
  10555. +#define MASK_VQMACCSUVX 0xfc00707f
  10556. +#define MATCH_VQMACCUSVX 0xf8004057
  10557. +#define MASK_VQMACCUSVX 0xfc00707f
  10558. +
  10559. +#define MATCH_VDIVVV 0x84002057
  10560. +#define MASK_VDIVVV 0xfc00707f
  10561. +#define MATCH_VDIVVX 0x84006057
  10562. +#define MASK_VDIVVX 0xfc00707f
  10563. +#define MATCH_VDIVUVV 0x80002057
  10564. +#define MASK_VDIVUVV 0xfc00707f
  10565. +#define MATCH_VDIVUVX 0x80006057
  10566. +#define MASK_VDIVUVX 0xfc00707f
  10567. +#define MATCH_VREMVV 0x8c002057
  10568. +#define MASK_VREMVV 0xfc00707f
  10569. +#define MATCH_VREMVX 0x8c006057
  10570. +#define MASK_VREMVX 0xfc00707f
  10571. +#define MATCH_VREMUVV 0x88002057
  10572. +#define MASK_VREMUVV 0xfc00707f
  10573. +#define MATCH_VREMUVX 0x88006057
  10574. +#define MASK_VREMUVX 0xfc00707f
  10575. +
  10576. +#define MATCH_VMERGEVVM 0x5c000057
  10577. +#define MASK_VMERGEVVM 0xfe00707f
  10578. +#define MATCH_VMERGEVXM 0x5c004057
  10579. +#define MASK_VMERGEVXM 0xfe00707f
  10580. +#define MATCH_VMERGEVIM 0x5c003057
  10581. +#define MASK_VMERGEVIM 0xfe00707f
  10582. +
  10583. +#define MATCH_VMVVV 0x5e000057
  10584. +#define MASK_VMVVV 0xfff0707f
  10585. +#define MATCH_VMVVX 0x5e004057
  10586. +#define MASK_VMVVX 0xfff0707f
  10587. +#define MATCH_VMVVI 0x5e003057
  10588. +#define MASK_VMVVI 0xfff0707f
  10589. +
  10590. +#define MATCH_VSADDUVV 0x80000057
  10591. +#define MASK_VSADDUVV 0xfc00707f
  10592. +#define MATCH_VSADDUVX 0x80004057
  10593. +#define MASK_VSADDUVX 0xfc00707f
  10594. +#define MATCH_VSADDUVI 0x80003057
  10595. +#define MASK_VSADDUVI 0xfc00707f
  10596. +#define MATCH_VSADDVV 0x84000057
  10597. +#define MASK_VSADDVV 0xfc00707f
  10598. +#define MATCH_VSADDVX 0x84004057
  10599. +#define MASK_VSADDVX 0xfc00707f
  10600. +#define MATCH_VSADDVI 0x84003057
  10601. +#define MASK_VSADDVI 0xfc00707f
  10602. +#define MATCH_VSSUBUVV 0x88000057
  10603. +#define MASK_VSSUBUVV 0xfc00707f
  10604. +#define MATCH_VSSUBUVX 0x88004057
  10605. +#define MASK_VSSUBUVX 0xfc00707f
  10606. +#define MATCH_VSSUBVV 0x8c000057
  10607. +#define MASK_VSSUBVV 0xfc00707f
  10608. +#define MATCH_VSSUBVX 0x8c004057
  10609. +#define MASK_VSSUBVX 0xfc00707f
  10610. +
  10611. +#define MATCH_VAADDUVV 0x20002057
  10612. +#define MASK_VAADDUVV 0xfc00707f
  10613. +#define MATCH_VAADDUVX 0x20006057
  10614. +#define MASK_VAADDUVX 0xfc00707f
  10615. +#define MATCH_VAADDVV 0x24002057
  10616. +#define MASK_VAADDVV 0xfc00707f
  10617. +#define MATCH_VAADDVX 0x24006057
  10618. +#define MASK_VAADDVX 0xfc00707f
  10619. +#define MATCH_VASUBUVV 0x28002057
  10620. +#define MASK_VASUBUVV 0xfc00707f
  10621. +#define MATCH_VASUBUVX 0x28006057
  10622. +#define MASK_VASUBUVX 0xfc00707f
  10623. +#define MATCH_VASUBVV 0x2c002057
  10624. +#define MASK_VASUBVV 0xfc00707f
  10625. +#define MATCH_VASUBVX 0x2c006057
  10626. +#define MASK_VASUBVX 0xfc00707f
  10627. +
  10628. +#define MATCH_VSMULVV 0x9c000057
  10629. +#define MASK_VSMULVV 0xfc00707f
  10630. +#define MATCH_VSMULVX 0x9c004057
  10631. +#define MASK_VSMULVX 0xfc00707f
  10632. +
  10633. +#define MATCH_VSSRLVV 0xa8000057
  10634. +#define MASK_VSSRLVV 0xfc00707f
  10635. +#define MATCH_VSSRLVX 0xa8004057
  10636. +#define MASK_VSSRLVX 0xfc00707f
  10637. +#define MATCH_VSSRLVI 0xa8003057
  10638. +#define MASK_VSSRLVI 0xfc00707f
  10639. +#define MATCH_VSSRAVV 0xac000057
  10640. +#define MASK_VSSRAVV 0xfc00707f
  10641. +#define MATCH_VSSRAVX 0xac004057
  10642. +#define MASK_VSSRAVX 0xfc00707f
  10643. +#define MATCH_VSSRAVI 0xac003057
  10644. +#define MASK_VSSRAVI 0xfc00707f
  10645. +
  10646. +#define MATCH_VNCLIPUWV 0xb8000057
  10647. +#define MASK_VNCLIPUWV 0xfc00707f
  10648. +#define MATCH_VNCLIPUWX 0xb8004057
  10649. +#define MASK_VNCLIPUWX 0xfc00707f
  10650. +#define MATCH_VNCLIPUWI 0xb8003057
  10651. +#define MASK_VNCLIPUWI 0xfc00707f
  10652. +#define MATCH_VNCLIPWV 0xbc000057
  10653. +#define MASK_VNCLIPWV 0xfc00707f
  10654. +#define MATCH_VNCLIPWX 0xbc004057
  10655. +#define MASK_VNCLIPWX 0xfc00707f
  10656. +#define MATCH_VNCLIPWI 0xbc003057
  10657. +#define MASK_VNCLIPWI 0xfc00707f
  10658. +
  10659. +#define MATCH_VFADDVV 0x00001057
  10660. +#define MASK_VFADDVV 0xfc00707f
  10661. +#define MATCH_VFADDVF 0x00005057
  10662. +#define MASK_VFADDVF 0xfc00707f
  10663. +#define MATCH_VFSUBVV 0x08001057
  10664. +#define MASK_VFSUBVV 0xfc00707f
  10665. +#define MATCH_VFSUBVF 0x08005057
  10666. +#define MASK_VFSUBVF 0xfc00707f
  10667. +#define MATCH_VFRSUBVF 0x9c005057
  10668. +#define MASK_VFRSUBVF 0xfc00707f
  10669. +
  10670. +#define MATCH_VFWADDVV 0xc0001057
  10671. +#define MASK_VFWADDVV 0xfc00707f
  10672. +#define MATCH_VFWADDVF 0xc0005057
  10673. +#define MASK_VFWADDVF 0xfc00707f
  10674. +#define MATCH_VFWSUBVV 0xc8001057
  10675. +#define MASK_VFWSUBVV 0xfc00707f
  10676. +#define MATCH_VFWSUBVF 0xc8005057
  10677. +#define MASK_VFWSUBVF 0xfc00707f
  10678. +#define MATCH_VFWADDWV 0xd0001057
  10679. +#define MASK_VFWADDWV 0xfc00707f
  10680. +#define MATCH_VFWADDWF 0xd0005057
  10681. +#define MASK_VFWADDWF 0xfc00707f
  10682. +#define MATCH_VFWSUBWV 0xd8001057
  10683. +#define MASK_VFWSUBWV 0xfc00707f
  10684. +#define MATCH_VFWSUBWF 0xd8005057
  10685. +#define MASK_VFWSUBWF 0xfc00707f
  10686. +
  10687. +#define MATCH_VFMULVV 0x90001057
  10688. +#define MASK_VFMULVV 0xfc00707f
  10689. +#define MATCH_VFMULVF 0x90005057
  10690. +#define MASK_VFMULVF 0xfc00707f
  10691. +#define MATCH_VFDIVVV 0x80001057
  10692. +#define MASK_VFDIVVV 0xfc00707f
  10693. +#define MATCH_VFDIVVF 0x80005057
  10694. +#define MASK_VFDIVVF 0xfc00707f
  10695. +#define MATCH_VFRDIVVF 0x84005057
  10696. +#define MASK_VFRDIVVF 0xfc00707f
  10697. +
  10698. +#define MATCH_VFWMULVV 0xe0001057
  10699. +#define MASK_VFWMULVV 0xfc00707f
  10700. +#define MATCH_VFWMULVF 0xe0005057
  10701. +#define MASK_VFWMULVF 0xfc00707f
  10702. +
  10703. +#define MATCH_VFMADDVV 0xa0001057
  10704. +#define MASK_VFMADDVV 0xfc00707f
  10705. +#define MATCH_VFMADDVF 0xa0005057
  10706. +#define MASK_VFMADDVF 0xfc00707f
  10707. +#define MATCH_VFNMADDVV 0xa4001057
  10708. +#define MASK_VFNMADDVV 0xfc00707f
  10709. +#define MATCH_VFNMADDVF 0xa4005057
  10710. +#define MASK_VFNMADDVF 0xfc00707f
  10711. +#define MATCH_VFMSUBVV 0xa8001057
  10712. +#define MASK_VFMSUBVV 0xfc00707f
  10713. +#define MATCH_VFMSUBVF 0xa8005057
  10714. +#define MASK_VFMSUBVF 0xfc00707f
  10715. +#define MATCH_VFNMSUBVV 0xac001057
  10716. +#define MASK_VFNMSUBVV 0xfc00707f
  10717. +#define MATCH_VFNMSUBVF 0xac005057
  10718. +#define MASK_VFNMSUBVF 0xfc00707f
  10719. +#define MATCH_VFMACCVV 0xb0001057
  10720. +#define MASK_VFMACCVV 0xfc00707f
  10721. +#define MATCH_VFMACCVF 0xb0005057
  10722. +#define MASK_VFMACCVF 0xfc00707f
  10723. +#define MATCH_VFNMACCVV 0xb4001057
  10724. +#define MASK_VFNMACCVV 0xfc00707f
  10725. +#define MATCH_VFNMACCVF 0xb4005057
  10726. +#define MASK_VFNMACCVF 0xfc00707f
  10727. +#define MATCH_VFMSACVV 0xb8001057
  10728. +#define MASK_VFMSACVV 0xfc00707f
  10729. +#define MATCH_VFMSACVF 0xb8005057
  10730. +#define MASK_VFMSACVF 0xfc00707f
  10731. +#define MATCH_VFNMSACVV 0xbc001057
  10732. +#define MASK_VFNMSACVV 0xfc00707f
  10733. +#define MATCH_VFNMSACVF 0xbc005057
  10734. +#define MASK_VFNMSACVF 0xfc00707f
  10735. +
  10736. +#define MATCH_VFWMACCVV 0xf0001057
  10737. +#define MASK_VFWMACCVV 0xfc00707f
  10738. +#define MATCH_VFWMACCVF 0xf0005057
  10739. +#define MASK_VFWMACCVF 0xfc00707f
  10740. +#define MATCH_VFWNMACCVV 0xf4001057
  10741. +#define MASK_VFWNMACCVV 0xfc00707f
  10742. +#define MATCH_VFWNMACCVF 0xf4005057
  10743. +#define MASK_VFWNMACCVF 0xfc00707f
  10744. +#define MATCH_VFWMSACVV 0xf8001057
  10745. +#define MASK_VFWMSACVV 0xfc00707f
  10746. +#define MATCH_VFWMSACVF 0xf8005057
  10747. +#define MASK_VFWMSACVF 0xfc00707f
  10748. +#define MATCH_VFWNMSACVV 0xfc001057
  10749. +#define MASK_VFWNMSACVV 0xfc00707f
  10750. +#define MATCH_VFWNMSACVF 0xfc005057
  10751. +#define MASK_VFWNMSACVF 0xfc00707f
  10752. +
  10753. +#define MATCH_VFSQRTV 0x4c001057
  10754. +#define MASK_VFSQRTV 0xfc0ff07f
  10755. +
  10756. +#define MATCH_VFMINVV 0x10001057
  10757. +#define MASK_VFMINVV 0xfc00707f
  10758. +#define MATCH_VFMINVF 0x10005057
  10759. +#define MASK_VFMINVF 0xfc00707f
  10760. +#define MATCH_VFMAXVV 0x18001057
  10761. +#define MASK_VFMAXVV 0xfc00707f
  10762. +#define MATCH_VFMAXVF 0x18005057
  10763. +#define MASK_VFMAXVF 0xfc00707f
  10764. +
  10765. +#define MATCH_VFSGNJVV 0x20001057
  10766. +#define MASK_VFSGNJVV 0xfc00707f
  10767. +#define MATCH_VFSGNJVF 0x20005057
  10768. +#define MASK_VFSGNJVF 0xfc00707f
  10769. +#define MATCH_VFSGNJNVV 0x24001057
  10770. +#define MASK_VFSGNJNVV 0xfc00707f
  10771. +#define MATCH_VFSGNJNVF 0x24005057
  10772. +#define MASK_VFSGNJNVF 0xfc00707f
  10773. +#define MATCH_VFSGNJXVV 0x28001057
  10774. +#define MASK_VFSGNJXVV 0xfc00707f
  10775. +#define MATCH_VFSGNJXVF 0x28005057
  10776. +#define MASK_VFSGNJXVF 0xfc00707f
  10777. +
  10778. +#define MATCH_VMFEQVV 0x60001057
  10779. +#define MASK_VMFEQVV 0xfc00707f
  10780. +#define MATCH_VMFEQVF 0x60005057
  10781. +#define MASK_VMFEQVF 0xfc00707f
  10782. +#define MATCH_VMFNEVV 0x70001057
  10783. +#define MASK_VMFNEVV 0xfc00707f
  10784. +#define MATCH_VMFNEVF 0x70005057
  10785. +#define MASK_VMFNEVF 0xfc00707f
  10786. +#define MATCH_VMFLTVV 0x6c001057
  10787. +#define MASK_VMFLTVV 0xfc00707f
  10788. +#define MATCH_VMFLTVF 0x6c005057
  10789. +#define MASK_VMFLTVF 0xfc00707f
  10790. +#define MATCH_VMFLEVV 0x64001057
  10791. +#define MASK_VMFLEVV 0xfc00707f
  10792. +#define MATCH_VMFLEVF 0x64005057
  10793. +#define MASK_VMFLEVF 0xfc00707f
  10794. +#define MATCH_VMFGTVF 0x74005057
  10795. +#define MASK_VMFGTVF 0xfc00707f
  10796. +#define MATCH_VMFGEVF 0x7c005057
  10797. +#define MASK_VMFGEVF 0xfc00707f
  10798. +
  10799. +#define MATCH_VFCLASSV 0x4c081057
  10800. +#define MASK_VFCLASSV 0xfc0ff07f
  10801. +
  10802. +#define MATCH_VFMERGEVFM 0x5c005057
  10803. +#define MASK_VFMERGEVFM 0xfe00707f
  10804. +#define MATCH_VFMVVF 0x5e005057
  10805. +#define MASK_VFMVVF 0xfff0707f
  10806. +
  10807. +#define MATCH_VFCVTXUFV 0x48001057
  10808. +#define MASK_VFCVTXUFV 0xfc0ff07f
  10809. +#define MATCH_VFCVTXFV 0x48009057
  10810. +#define MASK_VFCVTXFV 0xfc0ff07f
  10811. +#define MATCH_VFCVTFXUV 0x48011057
  10812. +#define MASK_VFCVTFXUV 0xfc0ff07f
  10813. +#define MATCH_VFCVTFXV 0x48019057
  10814. +#define MASK_VFCVTFXV 0xfc0ff07f
  10815. +#define MATCH_VFCVTRTZXUFV 0x48031057
  10816. +#define MASK_VFCVTRTZXUFV 0xfc0ff07f
  10817. +#define MATCH_VFCVTRTZXFV 0x48039057
  10818. +#define MASK_VFCVTRTZXFV 0xfc0ff07f
  10819. +#define MATCH_VFWCVTXUFV 0x48041057
  10820. +#define MASK_VFWCVTXUFV 0xfc0ff07f
  10821. +#define MATCH_VFWCVTXFV 0x48049057
  10822. +#define MASK_VFWCVTXFV 0xfc0ff07f
  10823. +#define MATCH_VFWCVTFXUV 0x48051057
  10824. +#define MASK_VFWCVTFXUV 0xfc0ff07f
  10825. +#define MATCH_VFWCVTFXV 0x48059057
  10826. +#define MASK_VFWCVTFXV 0xfc0ff07f
  10827. +#define MATCH_VFWCVTFFV 0x48061057
  10828. +#define MASK_VFWCVTFFV 0xfc0ff07f
  10829. +#define MATCH_VFWCVTRTZXUFV 0x48071057
  10830. +#define MASK_VFWCVTRTZXUFV 0xfc0ff07f
  10831. +#define MATCH_VFWCVTRTZXFV 0x48079057
  10832. +#define MASK_VFWCVTRTZXFV 0xfc0ff07f
  10833. +#define MATCH_VFNCVTXUFW 0x48081057
  10834. +#define MASK_VFNCVTXUFW 0xfc0ff07f
  10835. +#define MATCH_VFNCVTXFW 0x48089057
  10836. +#define MASK_VFNCVTXFW 0xfc0ff07f
  10837. +#define MATCH_VFNCVTFXUW 0x48091057
  10838. +#define MASK_VFNCVTFXUW 0xfc0ff07f
  10839. +#define MATCH_VFNCVTFXW 0x48099057
  10840. +#define MASK_VFNCVTFXW 0xfc0ff07f
  10841. +#define MATCH_VFNCVTFFW 0x480a1057
  10842. +#define MASK_VFNCVTFFW 0xfc0ff07f
  10843. +#define MATCH_VFNCVTRODFFW 0x480a9057
  10844. +#define MASK_VFNCVTRODFFW 0xfc0ff07f
  10845. +#define MATCH_VFNCVTRTZXUFW 0x480b1057
  10846. +#define MASK_VFNCVTRTZXUFW 0xfc0ff07f
  10847. +#define MATCH_VFNCVTRTZXFW 0x480b9057
  10848. +#define MASK_VFNCVTRTZXFW 0xfc0ff07f
  10849. +
  10850. +#define MATCH_VREDSUMVS 0x00002057
  10851. +#define MASK_VREDSUMVS 0xfc00707f
  10852. +#define MATCH_VREDMAXVS 0x1c002057
  10853. +#define MASK_VREDMAXVS 0xfc00707f
  10854. +#define MATCH_VREDMAXUVS 0x18002057
  10855. +#define MASK_VREDMAXUVS 0xfc00707f
  10856. +#define MATCH_VREDMINVS 0x14002057
  10857. +#define MASK_VREDMINVS 0xfc00707f
  10858. +#define MATCH_VREDMINUVS 0x10002057
  10859. +#define MASK_VREDMINUVS 0xfc00707f
  10860. +#define MATCH_VREDANDVS 0x04002057
  10861. +#define MASK_VREDANDVS 0xfc00707f
  10862. +#define MATCH_VREDORVS 0x08002057
  10863. +#define MASK_VREDORVS 0xfc00707f
  10864. +#define MATCH_VREDXORVS 0x0c002057
  10865. +#define MASK_VREDXORVS 0xfc00707f
  10866. +
  10867. +#define MATCH_VWREDSUMUVS 0xc0000057
  10868. +#define MASK_VWREDSUMUVS 0xfc00707f
  10869. +#define MATCH_VWREDSUMVS 0xc4000057
  10870. +#define MASK_VWREDSUMVS 0xfc00707f
  10871. +
  10872. +#define MATCH_VFREDOSUMVS 0x0c001057
  10873. +#define MASK_VFREDOSUMVS 0xfc00707f
  10874. +#define MATCH_VFREDSUMVS 0x04001057
  10875. +#define MASK_VFREDSUMVS 0xfc00707f
  10876. +#define MATCH_VFREDMAXVS 0x1c001057
  10877. +#define MASK_VFREDMAXVS 0xfc00707f
  10878. +#define MATCH_VFREDMINVS 0x14001057
  10879. +#define MASK_VFREDMINVS 0xfc00707f
  10880. +
  10881. +#define MATCH_VFWREDOSUMVS 0xcc001057
  10882. +#define MASK_VFWREDOSUMVS 0xfc00707f
  10883. +#define MATCH_VFWREDSUMVS 0xc4001057
  10884. +#define MASK_VFWREDSUMVS 0xfc00707f
  10885. +
  10886. +#define MATCH_VMANDMM 0x66002057
  10887. +#define MASK_VMANDMM 0xfe00707f
  10888. +#define MATCH_VMNANDMM 0x76002057
  10889. +#define MASK_VMNANDMM 0xfe00707f
  10890. +#define MATCH_VMANDNOTMM 0x62002057
  10891. +#define MASK_VMANDNOTMM 0xfe00707f
  10892. +#define MATCH_VMXORMM 0x6e002057
  10893. +#define MASK_VMXORMM 0xfe00707f
  10894. +#define MATCH_VMORMM 0x6a002057
  10895. +#define MASK_VMORMM 0xfe00707f
  10896. +#define MATCH_VMNORMM 0x7a002057
  10897. +#define MASK_VMNORMM 0xfe00707f
  10898. +#define MATCH_VMORNOTMM 0x72002057
  10899. +#define MASK_VMORNOTMM 0xfe00707f
  10900. +#define MATCH_VMXNORMM 0x7e002057
  10901. +#define MASK_VMXNORMM 0xfe00707f
  10902. +
  10903. +#define MATCH_VPOPCM 0x40082057
  10904. +#define MASK_VPOPCM 0xfc0ff07f
  10905. +#define MATCH_VFIRSTM 0x4008a057
  10906. +#define MASK_VFIRSTM 0xfc0ff07f
  10907. +
  10908. +#define MATCH_VMSBFM 0x5000a057
  10909. +#define MASK_VMSBFM 0xfc0ff07f
  10910. +#define MATCH_VMSIFM 0x5001a057
  10911. +#define MASK_VMSIFM 0xfc0ff07f
  10912. +#define MATCH_VMSOFM 0x50012057
  10913. +#define MASK_VMSOFM 0xfc0ff07f
  10914. +#define MATCH_VIOTAM 0x50082057
  10915. +#define MASK_VIOTAM 0xfc0ff07f
  10916. +#define MATCH_VIDV 0x5008a057
  10917. +#define MASK_VIDV 0xfdfff07f
  10918. +
  10919. +#define MATCH_VMVXS 0x42002057
  10920. +#define MASK_VMVXS 0xfe0ff07f
  10921. +#define MATCH_VMVSX 0x42006057
  10922. +#define MASK_VMVSX 0xfff0707f
  10923. +
  10924. +#define MATCH_VFMVFS 0x42001057
  10925. +#define MASK_VFMVFS 0xfe0ff07f
  10926. +#define MATCH_VFMVSF 0x42005057
  10927. +#define MASK_VFMVSF 0xfff0707f
  10928. +
  10929. +#define MATCH_VSLIDEUPVX 0x38004057
  10930. +#define MASK_VSLIDEUPVX 0xfc00707f
  10931. +#define MATCH_VSLIDEUPVI 0x38003057
  10932. +#define MASK_VSLIDEUPVI 0xfc00707f
  10933. +#define MATCH_VSLIDEDOWNVX 0x3c004057
  10934. +#define MASK_VSLIDEDOWNVX 0xfc00707f
  10935. +#define MATCH_VSLIDEDOWNVI 0x3c003057
  10936. +#define MASK_VSLIDEDOWNVI 0xfc00707f
  10937. +
  10938. +#define MATCH_VSLIDE1UPVX 0x38006057
  10939. +#define MASK_VSLIDE1UPVX 0xfc00707f
  10940. +#define MATCH_VSLIDE1DOWNVX 0x3c006057
  10941. +#define MASK_VSLIDE1DOWNVX 0xfc00707f
  10942. +
  10943. +#define MATCH_VFSLIDE1UPVF 0x38005057
  10944. +#define MASK_VFSLIDE1UPVF 0xfc00707f
  10945. +#define MATCH_VFSLIDE1DOWNVF 0x3c005057
  10946. +#define MASK_VFSLIDE1DOWNVF 0xfc00707f
  10947. +
  10948. +#define MATCH_VRGATHERVV 0x30000057
  10949. +#define MASK_VRGATHERVV 0xfc00707f
  10950. +#define MATCH_VRGATHERVX 0x30004057
  10951. +#define MASK_VRGATHERVX 0xfc00707f
  10952. +#define MATCH_VRGATHERVI 0x30003057
  10953. +#define MASK_VRGATHERVI 0xfc00707f
  10954. +
  10955. +#define MATCH_VCOMPRESSVM 0x5e002057
  10956. +#define MASK_VCOMPRESSVM 0xfe00707f
  10957. +
  10958. +#define MATCH_VMV1RV 0x9e003057
  10959. +#define MASK_VMV1RV 0xfe0ff07f
  10960. +#define MATCH_VMV2RV 0x9e00b057
  10961. +#define MASK_VMV2RV 0xfe0ff07f
  10962. +#define MATCH_VMV4RV 0x9e01b057
  10963. +#define MASK_VMV4RV 0xfe0ff07f
  10964. +#define MATCH_VMV8RV 0x9e03b057
  10965. +#define MASK_VMV8RV 0xfe0ff07f
  10966. +
  10967. +#define MATCH_VDOTVV 0xe4000057
  10968. +#define MASK_VDOTVV 0xfc00707f
  10969. +#define MATCH_VDOTUVV 0xe0000057
  10970. +#define MASK_VDOTUVV 0xfc00707f
  10971. +#define MATCH_VFDOTVV 0xe4001057
  10972. +#define MASK_VFDOTVV 0xfc00707f
  10973. +/* END RVV */
  10974. +
  10975. #define MATCH_CUSTOM0 0xb
  10976. #define MASK_CUSTOM0 0x707f
  10977. #define MATCH_CUSTOM0_RS1 0x200b
  10978. @@ -830,6 +2954,13 @@
  10979. #define CSR_FFLAGS 0x1
  10980. #define CSR_FRM 0x2
  10981. #define CSR_FCSR 0x3
  10982. +#define CSR_VSTART 0x008
  10983. +#define CSR_VXSAT 0x009
  10984. +#define CSR_VXRM 0x00a
  10985. +#define CSR_VCSR 0x00f
  10986. +#define CSR_VL 0xc20
  10987. +#define CSR_VTYPE 0xc21
  10988. +#define CSR_VLENB 0xc22
  10989. #define CSR_DCSR 0x7b0
  10990. #define CSR_DPC 0x7b1
  10991. #define CSR_DSCRATCH0 0x7b2
  10992. @@ -1365,6 +3496,13 @@ DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
  10993. DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  10994. DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  10995. DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  10996. +DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  10997. +DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  10998. +DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  10999. +DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  11000. +DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  11001. +DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  11002. +DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  11003. DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  11004. DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  11005. DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
  11006. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  11007. index 680780a664..62049bdd23 100644
  11008. --- a/include/opcode/riscv.h
  11009. +++ b/include/opcode/riscv.h
  11010. @@ -52,6 +52,34 @@ static const char * const riscv_pred_succ[16] =
  11011. "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
  11012. };
  11013. +/* List of vsetvli vsew constants. */
  11014. +static const char * const riscv_vsew[8] =
  11015. +{
  11016. + "e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024"
  11017. +};
  11018. +
  11019. +/* List of vsetvli vlmul constants. */
  11020. +static const char * const riscv_vlmul[8] =
  11021. +{
  11022. + "m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2"
  11023. +};
  11024. +
  11025. +/* List of vsetvli vediv constants. */
  11026. +static const char * const riscv_vediv[4] =
  11027. +{
  11028. + "d1", "d2", "d4", "d8"
  11029. +};
  11030. +
  11031. +static const char * const riscv_vta[2] =
  11032. +{
  11033. + "tu", "ta"
  11034. +};
  11035. +
  11036. +static const char * const riscv_vma[2] =
  11037. +{
  11038. + "mu", "ma"
  11039. +};
  11040. +
  11041. #define RVC_JUMP_BITS 11
  11042. #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
  11043. @@ -99,6 +127,14 @@ static const char * const riscv_pred_succ[16] =
  11044. ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
  11045. #define EXTRACT_RVC_J_IMM(x) \
  11046. ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
  11047. +#define EXTRACT_RVV_VI_IMM(x) \
  11048. + (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
  11049. +#define EXTRACT_RVV_VI_UIMM(x) \
  11050. + (RV_X(x, 15, 5))
  11051. +#define EXTRACT_RVV_OFFSET(x) \
  11052. + (RV_X(x, 29, 3))
  11053. +#define EXTRACT_RVV_VC_IMM(x) \
  11054. + (RV_X(x, 20, 11))
  11055. #define ENCODE_ITYPE_IMM(x) \
  11056. (RV_X(x, 0, 12) << 20)
  11057. @@ -138,6 +174,8 @@ static const char * const riscv_pred_succ[16] =
  11058. ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
  11059. #define ENCODE_RVC_J_IMM(x) \
  11060. ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
  11061. +#define ENCODE_RVV_VC_IMM(x) \
  11062. + (RV_X(x, 0, 11) << 20)
  11063. #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
  11064. #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
  11065. @@ -158,6 +196,7 @@ static const char * const riscv_pred_succ[16] =
  11066. #define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
  11067. #define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
  11068. #define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
  11069. +#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
  11070. #define RISCV_RTYPE(insn, rd, rs1, rs2) \
  11071. ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
  11072. @@ -256,6 +295,37 @@ static const char * const riscv_pred_succ[16] =
  11073. #define OP_MASK_CFUNCT2 0x3
  11074. #define OP_SH_CFUNCT2 5
  11075. +/* RVV fields. */
  11076. +
  11077. +#define OP_MASK_VD 0x1f
  11078. +#define OP_SH_VD 7
  11079. +#define OP_MASK_VS1 0x1f
  11080. +#define OP_SH_VS1 15
  11081. +#define OP_MASK_VS2 0x1f
  11082. +#define OP_SH_VS2 20
  11083. +#define OP_MASK_VIMM 0x1f
  11084. +#define OP_SH_VIMM 15
  11085. +#define OP_MASK_VMASK 0x1
  11086. +#define OP_SH_VMASK 25
  11087. +#define OP_MASK_VFUNCT6 0x3f
  11088. +#define OP_SH_VFUNCT6 26
  11089. +
  11090. +#define OP_MASK_VLMUL 0x23
  11091. +#define OP_SH_VLMUL 0
  11092. +#define OP_MASK_VSEW 0x7
  11093. +#define OP_SH_VSEW 2
  11094. +#define OP_MASK_VEDIV 0x3
  11095. +#define OP_SH_VEDIV 8
  11096. +#define OP_MASK_VTYPE_RES 0x1
  11097. +#define OP_SH_VTYPE_RES 10
  11098. +#define OP_MASK_VTA 0x1
  11099. +#define OP_SH_VTA 6
  11100. +#define OP_MASK_VMA 0x1
  11101. +#define OP_SH_VMA 7
  11102. +
  11103. +#define OP_MASK_VWD 0x1
  11104. +#define OP_SH_VWD 26
  11105. +
  11106. /* ABI names for selected x-registers. */
  11107. #define X_RA 1
  11108. @@ -269,6 +339,8 @@ static const char * const riscv_pred_succ[16] =
  11109. #define NGPR 32
  11110. #define NFPR 32
  11111. +#define NVECR 32
  11112. +#define NVECM 1
  11113. /* These fake label defines are use by both the assembler, and
  11114. libopcodes. The assembler uses this when it needs to generate a fake
  11115. @@ -282,6 +354,10 @@ static const char * const riscv_pred_succ[16] =
  11116. (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
  11117. | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
  11118. +#define INSERT_VLMUL(STRUCT, VALUE) \
  11119. + INSERT_BITS (STRUCT, (VALUE & 0x3), (OP_MASK_VLMUL & 0x3), 0), \
  11120. + INSERT_BITS (STRUCT, (((VALUE & 0x4) >> 2) <<5), (OP_MASK_VLMUL & 0x20), 0)
  11121. +
  11122. /* Extract bits MASK << SHIFT from STRUCT and shift them right
  11123. SHIFT places. */
  11124. #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
  11125. @@ -291,6 +367,11 @@ static const char * const riscv_pred_succ[16] =
  11126. #define EXTRACT_OPERAND(FIELD, INSN) \
  11127. EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
  11128. +/* Extract the vlmul value from vsetvli instrucion. */
  11129. +#define EXTRACT_VLMUL(INSN) \
  11130. + (((EXTRACT_OPERAND (VLMUL, INSN) >> 5) << 2) \
  11131. + | (EXTRACT_OPERAND (VLMUL, INSN) & 0x3))
  11132. +
  11133. /* The maximal number of subset can be required. */
  11134. #define MAX_SUBSET_NUM 4
  11135. @@ -309,6 +390,12 @@ enum riscv_insn_class
  11136. INSN_CLASS_D_AND_C,
  11137. INSN_CLASS_F_AND_C,
  11138. INSN_CLASS_Q,
  11139. + INSN_CLASS_V,
  11140. + INSN_CLASS_V_AND_F,
  11141. + INSN_CLASS_V_OR_ZVAMO,
  11142. + INSN_CLASS_V_AND_ZVEDIV,
  11143. + INSN_CLASS_V_OR_ZVLSSEG,
  11144. + INSN_CLASS_V_AND_ZVQMAC,
  11145. };
  11146. /* This structure holds information for a particular instruction. */
  11147. @@ -335,8 +422,11 @@ struct riscv_opcode
  11148. INSN_MACRO, then this field is the macro identifier. */
  11149. insn_t mask;
  11150. /* A function to determine if a word corresponds to this instruction.
  11151. - Usually, this computes ((word & mask) == match). */
  11152. - int (*match_func) (const struct riscv_opcode *op, insn_t word);
  11153. + Usually, this computes ((word & mask) == match). If the constraints
  11154. + checking is disable, then most of the function should check only the
  11155. + basic encoding for the instruction. */
  11156. + int (*match_func) (const struct riscv_opcode *op, insn_t word,
  11157. + int constraints);
  11158. /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
  11159. of bits describing the instruction, notably any relevant hazard
  11160. information. */
  11161. @@ -375,6 +465,7 @@ enum riscv_csr_class
  11162. CSR_CLASS_I,
  11163. CSR_CLASS_I_32, /* rv32 only */
  11164. CSR_CLASS_F, /* f-ext only */
  11165. + CSR_CLASS_V, /* v-ext only */
  11166. CSR_CLASS_DEBUG /* debug CSR */
  11167. };
  11168. @@ -478,6 +569,8 @@ enum
  11169. M_CALL,
  11170. M_J,
  11171. M_LI,
  11172. + M_VMSGE,
  11173. + M_VMSGEU,
  11174. M_NUM_MACROS
  11175. };
  11176. @@ -486,6 +579,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR];
  11177. extern const char * const riscv_gpr_names_abi[NGPR];
  11178. extern const char * const riscv_fpr_names_numeric[NFPR];
  11179. extern const char * const riscv_fpr_names_abi[NFPR];
  11180. +extern const char * const riscv_vecr_names_numeric[NVECR];
  11181. +extern const char * const riscv_vecm_names_numeric[NVECM];
  11182. extern const struct riscv_opcode riscv_opcodes[];
  11183. extern const struct riscv_opcode riscv_insn_types[];
  11184. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
  11185. index 655ce4ad0b..25e0a93e88 100644
  11186. --- a/opcodes/riscv-dis.c
  11187. +++ b/opcodes/riscv-dis.c
  11188. @@ -43,6 +43,7 @@ struct riscv_private_data
  11189. static const char * const *riscv_gpr_names;
  11190. static const char * const *riscv_fpr_names;
  11191. +static const char * const *riscv_vecr_names;
  11192. /* Other options. */
  11193. static int no_aliases; /* If set disassemble as most general inst. */
  11194. @@ -52,6 +53,7 @@ set_default_riscv_dis_options (void)
  11195. {
  11196. riscv_gpr_names = riscv_gpr_names_abi;
  11197. riscv_fpr_names = riscv_fpr_names_abi;
  11198. + riscv_vecr_names = riscv_vecr_names_numeric;
  11199. no_aliases = 0;
  11200. }
  11201. @@ -401,6 +403,88 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
  11202. print (info->stream, "%d", rs1);
  11203. break;
  11204. + case 'V': /* RVV */
  11205. + switch (*++d)
  11206. + {
  11207. + case 'd':
  11208. + case 'f':
  11209. + print (info->stream, "%s",
  11210. + riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
  11211. + break;
  11212. +
  11213. + case 'e':
  11214. + if (!EXTRACT_OPERAND (VWD, l))
  11215. + print (info->stream, "%s", riscv_gpr_names[0]);
  11216. + else
  11217. + print (info->stream, "%s",
  11218. + riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
  11219. + break;
  11220. +
  11221. + case 's':
  11222. + print (info->stream, "%s",
  11223. + riscv_vecr_names[EXTRACT_OPERAND (VS1, l)]);
  11224. + break;
  11225. +
  11226. + case 't':
  11227. + case 'u': /* VS1 == VS2 already verified at this point. */
  11228. + case 'v': /* VD == VS1 == VS2 already verified at this point. */
  11229. + print (info->stream, "%s",
  11230. + riscv_vecr_names[EXTRACT_OPERAND (VS2, l)]);
  11231. + break;
  11232. +
  11233. + case '0':
  11234. + print (info->stream, "%s", riscv_vecr_names[0]);
  11235. + break;
  11236. +
  11237. + case 'c':
  11238. + {
  11239. + int imm = EXTRACT_RVV_VC_IMM (l);
  11240. + unsigned int imm_vlmul = EXTRACT_VLMUL (imm);
  11241. + unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
  11242. + unsigned int imm_vediv = EXTRACT_OPERAND (VEDIV, imm);
  11243. + unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
  11244. + unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
  11245. + unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm);
  11246. +
  11247. + if (imm_vsew < ARRAY_SIZE (riscv_vsew)
  11248. + && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
  11249. + && imm_vediv < ARRAY_SIZE (riscv_vediv)
  11250. + && imm_vta < ARRAY_SIZE (riscv_vta)
  11251. + && imm_vma < ARRAY_SIZE (riscv_vma)
  11252. + && ! imm_vtype_res)
  11253. + print (info->stream, "%s,%s,%s,%s,%s", riscv_vsew[imm_vsew],
  11254. + riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
  11255. + riscv_vma[imm_vma], riscv_vediv[imm_vediv]);
  11256. + else
  11257. + print (info->stream, "%d", imm);
  11258. + }
  11259. + break;
  11260. +
  11261. + case 'i':
  11262. + print (info->stream, "%d", (int)EXTRACT_RVV_VI_IMM (l));
  11263. + break;
  11264. +
  11265. + case 'j':
  11266. + print (info->stream, "%d", (int)EXTRACT_RVV_VI_UIMM (l));
  11267. + break;
  11268. +
  11269. + case 'k':
  11270. + print (info->stream, "%d", (int)EXTRACT_RVV_OFFSET (l));
  11271. + break;
  11272. +
  11273. + case 'm':
  11274. + if (! EXTRACT_OPERAND (VMASK, l))
  11275. + print (info->stream, ",%s", riscv_vecm_names_numeric[0]);
  11276. + break;
  11277. +
  11278. + default:
  11279. + /* xgettext:c-format */
  11280. + print (info->stream, _("# internal error, undefined modifier (V%c)"),
  11281. + *d);
  11282. + return;
  11283. + }
  11284. + break;
  11285. +
  11286. default:
  11287. /* xgettext:c-format */
  11288. print (info->stream, _("# internal error, undefined modifier (%c)"),
  11289. @@ -488,7 +572,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
  11290. for (; op->name; op++)
  11291. {
  11292. /* Does the opcode match? */
  11293. - if (! (op->match_func) (op, word))
  11294. + if (! (op->match_func) (op, word, 0))
  11295. continue;
  11296. /* Is this a pseudo-instruction and may we print it as such? */
  11297. if (no_aliases && (op->pinfo & INSN_ALIAS))
  11298. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  11299. index 7ca44dc5b8..fcd87e2261 100644
  11300. --- a/opcodes/riscv-opc.c
  11301. +++ b/opcodes/riscv-opc.c
  11302. @@ -56,6 +56,19 @@ const char * const riscv_fpr_names_abi[NFPR] = {
  11303. "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
  11304. };
  11305. +const char * const riscv_vecr_names_numeric[NVECR] =
  11306. +{
  11307. + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
  11308. + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
  11309. + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
  11310. + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
  11311. +};
  11312. +
  11313. +const char * const riscv_vecm_names_numeric[NVECM] =
  11314. +{
  11315. + "v0.t"
  11316. +};
  11317. +
  11318. /* The order of overloaded instructions matters. Label arguments and
  11319. register arguments look the same. Instructions that can have either
  11320. for arguments must apear in the correct order in this table for the
  11321. @@ -79,68 +92,112 @@ const char * const riscv_fpr_names_abi[NFPR] = {
  11322. #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
  11323. #define MASK_RL (OP_MASK_RL << OP_SH_RL)
  11324. #define MASK_AQRL (MASK_AQ | MASK_RL)
  11325. +#define MASK_VD (OP_MASK_VD << OP_SH_VD)
  11326. +#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
  11327. +#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
  11328. +#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
  11329. static int
  11330. -match_opcode (const struct riscv_opcode *op, insn_t insn)
  11331. +match_opcode (const struct riscv_opcode *op,
  11332. + insn_t insn,
  11333. + int constraints ATTRIBUTE_UNUSED)
  11334. {
  11335. return ((insn ^ op->match) & op->mask) == 0;
  11336. }
  11337. static int
  11338. match_never (const struct riscv_opcode *op ATTRIBUTE_UNUSED,
  11339. - insn_t insn ATTRIBUTE_UNUSED)
  11340. + insn_t insn ATTRIBUTE_UNUSED,
  11341. + int constraints ATTRIBUTE_UNUSED)
  11342. {
  11343. return 0;
  11344. }
  11345. static int
  11346. -match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn)
  11347. +match_rs1_eq_rs2 (const struct riscv_opcode *op,
  11348. + insn_t insn,
  11349. + int constraints ATTRIBUTE_UNUSED)
  11350. {
  11351. int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
  11352. int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
  11353. - return match_opcode (op, insn) && rs1 == rs2;
  11354. + return match_opcode (op, insn, 0) && rs1 == rs2;
  11355. +}
  11356. +
  11357. +static int
  11358. +match_vs1_eq_vs2 (const struct riscv_opcode *op,
  11359. + insn_t insn,
  11360. + int constraints ATTRIBUTE_UNUSED)
  11361. +{
  11362. + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
  11363. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11364. +
  11365. + return match_opcode (op, insn, 0) && vs1 == vs2;
  11366. +}
  11367. +
  11368. +static int
  11369. +match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
  11370. + insn_t insn,
  11371. + int constraints ATTRIBUTE_UNUSED)
  11372. +{
  11373. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11374. + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
  11375. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11376. +
  11377. + return match_opcode (op, insn, 0) && vd == vs1 && vs1 == vs2;
  11378. }
  11379. static int
  11380. -match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
  11381. +match_rd_nonzero (const struct riscv_opcode *op,
  11382. + insn_t insn,
  11383. + int constraints ATTRIBUTE_UNUSED)
  11384. {
  11385. - return match_opcode (op, insn) && ((insn & MASK_RD) != 0);
  11386. + return match_opcode (op, insn, 0) && ((insn & MASK_RD) != 0);
  11387. }
  11388. static int
  11389. -match_c_add (const struct riscv_opcode *op, insn_t insn)
  11390. +match_c_add (const struct riscv_opcode *op,
  11391. + insn_t insn,
  11392. + int constraints ATTRIBUTE_UNUSED)
  11393. {
  11394. - return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0);
  11395. + return match_rd_nonzero (op, insn, 0) && ((insn & MASK_CRS2) != 0);
  11396. }
  11397. /* We don't allow mv zero,X to become a c.mv hint, so we need a separate
  11398. matching function for this. */
  11399. static int
  11400. -match_c_add_with_hint (const struct riscv_opcode *op, insn_t insn)
  11401. +match_c_add_with_hint (const struct riscv_opcode *op,
  11402. + insn_t insn,
  11403. + int constraints ATTRIBUTE_UNUSED)
  11404. {
  11405. - return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0);
  11406. + return match_opcode (op, insn, 0) && ((insn & MASK_CRS2) != 0);
  11407. }
  11408. static int
  11409. -match_c_nop (const struct riscv_opcode *op, insn_t insn)
  11410. +match_c_nop (const struct riscv_opcode *op,
  11411. + insn_t insn,
  11412. + int constraints ATTRIBUTE_UNUSED)
  11413. {
  11414. - return (match_opcode (op, insn)
  11415. + return (match_opcode (op, insn, 0)
  11416. && (((insn & MASK_RD) >> OP_SH_RD) == 0));
  11417. }
  11418. static int
  11419. -match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
  11420. +match_c_addi16sp (const struct riscv_opcode *op,
  11421. + insn_t insn,
  11422. + int constraints ATTRIBUTE_UNUSED)
  11423. {
  11424. - return (match_opcode (op, insn)
  11425. + return (match_opcode (op, insn, 0)
  11426. && (((insn & MASK_RD) >> OP_SH_RD) == 2)
  11427. && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0);
  11428. }
  11429. static int
  11430. -match_c_lui (const struct riscv_opcode *op, insn_t insn)
  11431. +match_c_lui (const struct riscv_opcode *op,
  11432. + insn_t insn,
  11433. + int constraints ATTRIBUTE_UNUSED)
  11434. {
  11435. - return (match_rd_nonzero (op, insn)
  11436. + return (match_rd_nonzero (op, insn, 0)
  11437. && (((insn & MASK_RD) >> OP_SH_RD) != 2)
  11438. && EXTRACT_RVC_LUI_IMM (insn) != 0);
  11439. }
  11440. @@ -149,50 +206,275 @@ match_c_lui (const struct riscv_opcode *op, insn_t insn)
  11441. matching function for this. */
  11442. static int
  11443. -match_c_lui_with_hint (const struct riscv_opcode *op, insn_t insn)
  11444. +match_c_lui_with_hint (const struct riscv_opcode *op,
  11445. + insn_t insn,
  11446. + int constraints ATTRIBUTE_UNUSED)
  11447. {
  11448. - return (match_opcode (op, insn)
  11449. + return (match_opcode (op, insn, 0)
  11450. && (((insn & MASK_RD) >> OP_SH_RD) != 2)
  11451. && EXTRACT_RVC_LUI_IMM (insn) != 0);
  11452. }
  11453. static int
  11454. -match_c_addi4spn (const struct riscv_opcode *op, insn_t insn)
  11455. +match_c_addi4spn (const struct riscv_opcode *op,
  11456. + insn_t insn,
  11457. + int constraints ATTRIBUTE_UNUSED)
  11458. {
  11459. - return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
  11460. + return match_opcode (op, insn, 0) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
  11461. }
  11462. /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */
  11463. static int
  11464. -match_c_slli (const struct riscv_opcode *op, insn_t insn)
  11465. +match_c_slli (const struct riscv_opcode *op,
  11466. + insn_t insn,
  11467. + int constraints ATTRIBUTE_UNUSED)
  11468. {
  11469. - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
  11470. + return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
  11471. }
  11472. /* This requires a non-zero rd, and a non-zero shift. */
  11473. static int
  11474. -match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn)
  11475. +match_slli_as_c_slli (const struct riscv_opcode *op,
  11476. + insn_t insn,
  11477. + int constraints ATTRIBUTE_UNUSED)
  11478. {
  11479. - return match_rd_nonzero (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
  11480. + return match_rd_nonzero (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
  11481. }
  11482. /* This requires a zero shift. A zero rd is a hint, so is allowed. */
  11483. static int
  11484. -match_c_slli64 (const struct riscv_opcode *op, insn_t insn)
  11485. +match_c_slli64 (const struct riscv_opcode *op,
  11486. + insn_t insn,
  11487. + int constraints ATTRIBUTE_UNUSED)
  11488. {
  11489. - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) == 0;
  11490. + return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) == 0;
  11491. }
  11492. /* This is used for both srli and srai. This requires a non-zero shift.
  11493. A zero rd is not possible. */
  11494. static int
  11495. -match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
  11496. +match_srxi_as_c_srxi (const struct riscv_opcode *op,
  11497. + insn_t insn,
  11498. + int constraints ATTRIBUTE_UNUSED)
  11499. +{
  11500. + return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
  11501. +}
  11502. +
  11503. +/* These are used to check the vector constraints. */
  11504. +
  11505. +static int
  11506. +match_widen_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
  11507. + insn_t insn,
  11508. + int constraints)
  11509. +{
  11510. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11511. + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
  11512. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11513. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  11514. +
  11515. + if (constraints
  11516. + && ((vd % 2) != 0
  11517. + || (vs1 >= vd && vs1 <= (vd + 1))
  11518. + || (vs2 >= vd && vs2 <= (vd + 1))
  11519. + || (!vm && vm >= vd && vm <= (vd + 1))))
  11520. + return 0;
  11521. +
  11522. + return match_opcode (op, insn, 0);
  11523. +}
  11524. +
  11525. +static int
  11526. +match_widen_vd_neq_vs1_neq_vm (const struct riscv_opcode *op,
  11527. + insn_t insn,
  11528. + int constraints)
  11529. +{
  11530. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11531. + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
  11532. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11533. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  11534. +
  11535. + if (constraints
  11536. + && ((vd % 2) != 0
  11537. + || (vs2 % 2) != 0
  11538. + || (vs1 >= vd && vs1 <= (vd + 1))
  11539. + || (!vm && vm >= vd && vm <= (vd + 1))))
  11540. + return 0;
  11541. +
  11542. + return match_opcode (op, insn, 0);
  11543. +}
  11544. +
  11545. +static int
  11546. +match_widen_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
  11547. + insn_t insn,
  11548. + int constraints)
  11549. +{
  11550. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11551. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11552. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  11553. +
  11554. + if (constraints
  11555. + && ((vd % 2) != 0
  11556. + || (vs2 >= vd && vs2 <= (vd + 1))
  11557. + || (!vm && vm >= vd && vm <= (vd + 1))))
  11558. + return 0;
  11559. +
  11560. + return match_opcode (op, insn, 0);
  11561. +}
  11562. +
  11563. +static int
  11564. +match_widen_vd_neq_vm (const struct riscv_opcode *op,
  11565. + insn_t insn,
  11566. + int constraints)
  11567. +{
  11568. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11569. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11570. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  11571. +
  11572. + if (constraints
  11573. + && ((vd % 2) != 0
  11574. + || (vs2 % 2) != 0
  11575. + || (!vm && vm >= vd && vm <= (vd + 1))))
  11576. + return 0;
  11577. +
  11578. + return match_opcode (op, insn, 0);
  11579. +}
  11580. +
  11581. +static int
  11582. +match_quad_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
  11583. + insn_t insn,
  11584. + int constraints)
  11585. +{
  11586. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11587. + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
  11588. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11589. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  11590. +
  11591. + if (constraints
  11592. + && ((vd % 4) != 0
  11593. + || (vs1 >= vd && vs1 <= (vd + 3))
  11594. + || (vs2 >= vd && vs2 <= (vd + 3))
  11595. + || (!vm && vm >= vd && vm <= (vd + 3))))
  11596. + return 0;
  11597. +
  11598. + return match_opcode (op, insn, 0);
  11599. +}
  11600. +
  11601. +static int
  11602. +match_quad_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
  11603. + insn_t insn,
  11604. + int constraints)
  11605. +{
  11606. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11607. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11608. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  11609. +
  11610. + if (constraints
  11611. + && ((vd % 4) != 0
  11612. + || (vs2 >= vd && vs2 <= (vd + 3))
  11613. + || (!vm && vm >= vd && vm <= (vd + 3))))
  11614. + return 0;
  11615. +
  11616. + return match_opcode (op, insn, 0);
  11617. +}
  11618. +
  11619. +static int
  11620. +match_narrow_vd_neq_vs2 (const struct riscv_opcode *op,
  11621. + insn_t insn,
  11622. + int constraints)
  11623. +{
  11624. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11625. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11626. +
  11627. + if (constraints
  11628. + && ((vs2 % 2) != 0
  11629. + || (vd >= vs2 && vd <= (vs2 + 1))))
  11630. + return 0;
  11631. +
  11632. + return match_opcode (op, insn, 0);
  11633. +}
  11634. +
  11635. +static int
  11636. +match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
  11637. + insn_t insn,
  11638. + int constraints)
  11639. +{
  11640. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11641. + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
  11642. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11643. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  11644. +
  11645. + if (constraints
  11646. + && (vs1 == vd
  11647. + || vs2 == vd
  11648. + || (!vm && vm == vd)))
  11649. + return 0;
  11650. +
  11651. + return match_opcode (op, insn, 0);
  11652. +}
  11653. +
  11654. +static int
  11655. +match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
  11656. + insn_t insn,
  11657. + int constraints)
  11658. +{
  11659. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11660. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11661. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  11662. +
  11663. + if (constraints
  11664. + && (vs2 == vd
  11665. + || (!vm && vm == vd)))
  11666. + return 0;
  11667. +
  11668. + return match_opcode (op, insn, 0);
  11669. +}
  11670. +
  11671. +static int
  11672. +match_vd_neq_vs2 (const struct riscv_opcode *op,
  11673. + insn_t insn,
  11674. + int constraints)
  11675. +{
  11676. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11677. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11678. +
  11679. + if (constraints && vs2 == vd)
  11680. + return 0;
  11681. +
  11682. + return match_opcode (op, insn, 0);
  11683. +}
  11684. +
  11685. +static int
  11686. +match_vd_neq_vm (const struct riscv_opcode *op,
  11687. + insn_t insn,
  11688. + int constraints)
  11689. {
  11690. - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
  11691. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11692. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  11693. +
  11694. + if (constraints && !vm && vm == vd)
  11695. + return 0;
  11696. +
  11697. + return match_opcode (op, insn, 0);
  11698. +}
  11699. +
  11700. +static int
  11701. +match_vmv_nf_rv (const struct riscv_opcode *op,
  11702. + insn_t insn,
  11703. + int constraints)
  11704. +{
  11705. + int vd = (insn & MASK_VD) >> OP_SH_VD;
  11706. + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  11707. + int nf = ((insn & (0x7 << 15) ) >> 15) + 1;
  11708. +
  11709. + if (constraints
  11710. + && ((vd % nf) != 0
  11711. + || (vs2 % nf) != 0))
  11712. + return 0;
  11713. +
  11714. + return match_opcode (op, insn, 0);
  11715. }
  11716. const struct riscv_opcode riscv_opcodes[] =
  11717. @@ -780,6 +1062,954 @@ const struct riscv_opcode riscv_opcodes[] =
  11718. {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
  11719. {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
  11720. +/* RVV */
  11721. +{"vsetvl", 0, INSN_CLASS_V, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
  11722. +{"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
  11723. +
  11724. +{"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
  11725. +{"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
  11726. +{"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
  11727. +{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
  11728. +{"vle128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128V, MASK_VLE128V, match_opcode, INSN_DREF },
  11729. +{"vle256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256V, MASK_VLE256V, match_opcode, INSN_DREF },
  11730. +{"vle512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512V, MASK_VLE512V, match_opcode, INSN_DREF },
  11731. +{"vle1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024V, MASK_VLE1024V, match_opcode, INSN_DREF },
  11732. +
  11733. +{"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
  11734. +{"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
  11735. +{"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
  11736. +{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
  11737. +{"vse128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE128V, MASK_VSE128V, match_opcode, INSN_DREF },
  11738. +{"vse256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE256V, MASK_VSE256V, match_opcode, INSN_DREF },
  11739. +{"vse512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE512V, MASK_VSE512V, match_opcode, INSN_DREF },
  11740. +{"vse1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE1024V, MASK_VSE1024V, match_opcode, INSN_DREF },
  11741. +
  11742. +{"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
  11743. +{"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
  11744. +{"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
  11745. +{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
  11746. +{"vlse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE128V, MASK_VLSE128V, match_opcode, INSN_DREF },
  11747. +{"vlse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE256V, MASK_VLSE256V, match_opcode, INSN_DREF },
  11748. +{"vlse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE512V, MASK_VLSE512V, match_opcode, INSN_DREF },
  11749. +{"vlse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE1024V, MASK_VLSE1024V, match_opcode, INSN_DREF },
  11750. +
  11751. +{"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
  11752. +{"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
  11753. +{"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
  11754. +{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
  11755. +{"vsse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE128V, MASK_VSSE128V, match_opcode, INSN_DREF },
  11756. +{"vsse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE256V, MASK_VSSE256V, match_opcode, INSN_DREF },
  11757. +{"vsse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_opcode, INSN_DREF },
  11758. +{"vsse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_opcode, INSN_DREF },
  11759. +
  11760. +{"vlxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_opcode, INSN_DREF },
  11761. +{"vlxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_opcode, INSN_DREF },
  11762. +{"vlxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_opcode, INSN_DREF },
  11763. +{"vlxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_opcode, INSN_DREF },
  11764. +{"vlxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI128V, MASK_VLXEI128V, match_opcode, INSN_DREF },
  11765. +{"vlxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI256V, MASK_VLXEI256V, match_opcode, INSN_DREF },
  11766. +{"vlxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI512V, MASK_VLXEI512V, match_opcode, INSN_DREF },
  11767. +{"vlxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI1024V, MASK_VLXEI1024V, match_opcode, INSN_DREF },
  11768. +
  11769. +{"vsxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_opcode, INSN_DREF },
  11770. +{"vsxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_opcode, INSN_DREF },
  11771. +{"vsxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_opcode, INSN_DREF },
  11772. +{"vsxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_opcode, INSN_DREF },
  11773. +{"vsxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI128V, MASK_VSXEI128V, match_opcode, INSN_DREF },
  11774. +{"vsxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI256V, MASK_VSXEI256V, match_opcode, INSN_DREF },
  11775. +{"vsxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI512V, MASK_VSXEI512V, match_opcode, INSN_DREF },
  11776. +{"vsxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI1024V, MASK_VSXEI1024V, match_opcode, INSN_DREF },
  11777. +
  11778. +{"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF },
  11779. +{"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF },
  11780. +{"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF },
  11781. +{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF },
  11782. +{"vsuxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI128V, MASK_VSUXEI128V, match_opcode, INSN_DREF },
  11783. +{"vsuxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI256V, MASK_VSUXEI256V, match_opcode, INSN_DREF },
  11784. +{"vsuxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI512V, MASK_VSUXEI512V, match_opcode, INSN_DREF },
  11785. +{"vsuxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI1024V, MASK_VSUXEI1024V, match_opcode, INSN_DREF },
  11786. +
  11787. +{"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
  11788. +{"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
  11789. +{"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
  11790. +{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
  11791. +{"vle128ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128FFV, MASK_VLE128FFV, match_opcode, INSN_DREF },
  11792. +{"vle256ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256FFV, MASK_VLE256FFV, match_opcode, INSN_DREF },
  11793. +{"vle512ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512FFV, MASK_VLE512FFV, match_opcode, INSN_DREF },
  11794. +{"vle1024ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024FFV, MASK_VLE1024FFV, match_opcode, INSN_DREF },
  11795. +
  11796. +{"vlseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
  11797. +{"vsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF },
  11798. +{"vlseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
  11799. +{"vsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF },
  11800. +{"vlseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
  11801. +{"vsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF },
  11802. +{"vlseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
  11803. +{"vsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF },
  11804. +{"vlseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
  11805. +{"vsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF },
  11806. +{"vlseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
  11807. +{"vsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF },
  11808. +{"vlseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
  11809. +{"vsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF },
  11810. +
  11811. +{"vlseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
  11812. +{"vsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF },
  11813. +{"vlseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
  11814. +{"vsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF },
  11815. +{"vlseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
  11816. +{"vsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF },
  11817. +{"vlseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
  11818. +{"vsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF },
  11819. +{"vlseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
  11820. +{"vsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF },
  11821. +{"vlseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
  11822. +{"vsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF },
  11823. +{"vlseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
  11824. +{"vsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF },
  11825. +
  11826. +{"vlseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
  11827. +{"vsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF },
  11828. +{"vlseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
  11829. +{"vsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF },
  11830. +{"vlseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
  11831. +{"vsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF },
  11832. +{"vlseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
  11833. +{"vsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF },
  11834. +{"vlseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
  11835. +{"vsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF },
  11836. +{"vlseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
  11837. +{"vsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF },
  11838. +{"vlseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
  11839. +{"vsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF },
  11840. +
  11841. +{"vlseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
  11842. +{"vsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF },
  11843. +{"vlseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
  11844. +{"vsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF },
  11845. +{"vlseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
  11846. +{"vsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF },
  11847. +{"vlseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
  11848. +{"vsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF },
  11849. +{"vlseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
  11850. +{"vsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF },
  11851. +{"vlseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
  11852. +{"vsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF },
  11853. +{"vlseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
  11854. +{"vsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF },
  11855. +
  11856. +{"vlseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E128V, MASK_VLSEG2E128V, match_vd_neq_vm, INSN_DREF },
  11857. +{"vsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E128V, MASK_VSSEG2E128V, match_opcode, INSN_DREF },
  11858. +{"vlseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E128V, MASK_VLSEG3E128V, match_vd_neq_vm, INSN_DREF },
  11859. +{"vsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E128V, MASK_VSSEG3E128V, match_opcode, INSN_DREF },
  11860. +{"vlseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E128V, MASK_VLSEG4E128V, match_vd_neq_vm, INSN_DREF },
  11861. +{"vsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E128V, MASK_VSSEG4E128V, match_opcode, INSN_DREF },
  11862. +{"vlseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E128V, MASK_VLSEG5E128V, match_vd_neq_vm, INSN_DREF },
  11863. +{"vsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E128V, MASK_VSSEG5E128V, match_opcode, INSN_DREF },
  11864. +{"vlseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E128V, MASK_VLSEG6E128V, match_vd_neq_vm, INSN_DREF },
  11865. +{"vsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E128V, MASK_VSSEG6E128V, match_opcode, INSN_DREF },
  11866. +{"vlseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E128V, MASK_VLSEG7E128V, match_vd_neq_vm, INSN_DREF },
  11867. +{"vsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E128V, MASK_VSSEG7E128V, match_opcode, INSN_DREF },
  11868. +{"vlseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E128V, MASK_VLSEG8E128V, match_vd_neq_vm, INSN_DREF },
  11869. +{"vsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E128V, MASK_VSSEG8E128V, match_opcode, INSN_DREF },
  11870. +
  11871. +{"vlseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E256V, MASK_VLSEG2E256V, match_vd_neq_vm, INSN_DREF },
  11872. +{"vsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E256V, MASK_VSSEG2E256V, match_opcode, INSN_DREF },
  11873. +{"vlseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E256V, MASK_VLSEG3E256V, match_vd_neq_vm, INSN_DREF },
  11874. +{"vsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E256V, MASK_VSSEG3E256V, match_opcode, INSN_DREF },
  11875. +{"vlseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E256V, MASK_VLSEG4E256V, match_vd_neq_vm, INSN_DREF },
  11876. +{"vsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E256V, MASK_VSSEG4E256V, match_opcode, INSN_DREF },
  11877. +{"vlseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E256V, MASK_VLSEG5E256V, match_vd_neq_vm, INSN_DREF },
  11878. +{"vsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E256V, MASK_VSSEG5E256V, match_opcode, INSN_DREF },
  11879. +{"vlseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E256V, MASK_VLSEG6E256V, match_vd_neq_vm, INSN_DREF },
  11880. +{"vsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E256V, MASK_VSSEG6E256V, match_opcode, INSN_DREF },
  11881. +{"vlseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E256V, MASK_VLSEG7E256V, match_vd_neq_vm, INSN_DREF },
  11882. +{"vsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E256V, MASK_VSSEG7E256V, match_opcode, INSN_DREF },
  11883. +{"vlseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E256V, MASK_VLSEG8E256V, match_vd_neq_vm, INSN_DREF },
  11884. +{"vsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E256V, MASK_VSSEG8E256V, match_opcode, INSN_DREF },
  11885. +
  11886. +{"vlseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E512V, MASK_VLSEG2E512V, match_vd_neq_vm, INSN_DREF },
  11887. +{"vsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E512V, MASK_VSSEG2E512V, match_opcode, INSN_DREF },
  11888. +{"vlseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E512V, MASK_VLSEG3E512V, match_vd_neq_vm, INSN_DREF },
  11889. +{"vsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E512V, MASK_VSSEG3E512V, match_opcode, INSN_DREF },
  11890. +{"vlseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E512V, MASK_VLSEG4E512V, match_vd_neq_vm, INSN_DREF },
  11891. +{"vsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E512V, MASK_VSSEG4E512V, match_opcode, INSN_DREF },
  11892. +{"vlseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E512V, MASK_VLSEG5E512V, match_vd_neq_vm, INSN_DREF },
  11893. +{"vsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E512V, MASK_VSSEG5E512V, match_opcode, INSN_DREF },
  11894. +{"vlseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E512V, MASK_VLSEG6E512V, match_vd_neq_vm, INSN_DREF },
  11895. +{"vsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E512V, MASK_VSSEG6E512V, match_opcode, INSN_DREF },
  11896. +{"vlseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E512V, MASK_VLSEG7E512V, match_vd_neq_vm, INSN_DREF },
  11897. +{"vsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E512V, MASK_VSSEG7E512V, match_opcode, INSN_DREF },
  11898. +{"vlseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E512V, MASK_VLSEG8E512V, match_vd_neq_vm, INSN_DREF },
  11899. +{"vsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E512V, MASK_VSSEG8E512V, match_opcode, INSN_DREF },
  11900. +
  11901. +{"vlseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E1024V, MASK_VLSEG2E1024V, match_vd_neq_vm, INSN_DREF },
  11902. +{"vsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E1024V, MASK_VSSEG2E1024V, match_opcode, INSN_DREF },
  11903. +{"vlseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E1024V, MASK_VLSEG3E1024V, match_vd_neq_vm, INSN_DREF },
  11904. +{"vsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E1024V, MASK_VSSEG3E1024V, match_opcode, INSN_DREF },
  11905. +{"vlseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E1024V, MASK_VLSEG4E1024V, match_vd_neq_vm, INSN_DREF },
  11906. +{"vsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E1024V, MASK_VSSEG4E1024V, match_opcode, INSN_DREF },
  11907. +{"vlseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E1024V, MASK_VLSEG5E1024V, match_vd_neq_vm, INSN_DREF },
  11908. +{"vsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E1024V, MASK_VSSEG5E1024V, match_opcode, INSN_DREF },
  11909. +{"vlseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E1024V, MASK_VLSEG6E1024V, match_vd_neq_vm, INSN_DREF },
  11910. +{"vsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E1024V, MASK_VSSEG6E1024V, match_opcode, INSN_DREF },
  11911. +{"vlseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E1024V, MASK_VLSEG7E1024V, match_vd_neq_vm, INSN_DREF },
  11912. +{"vsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E1024V, MASK_VSSEG7E1024V, match_opcode, INSN_DREF },
  11913. +{"vlseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024V, MASK_VLSEG8E1024V, match_vd_neq_vm, INSN_DREF },
  11914. +{"vsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E1024V, MASK_VSSEG8E1024V, match_opcode, INSN_DREF },
  11915. +
  11916. +{"vlsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
  11917. +{"vssseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF },
  11918. +{"vlsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
  11919. +{"vssseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF },
  11920. +{"vlsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
  11921. +{"vssseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF },
  11922. +{"vlsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
  11923. +{"vssseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF },
  11924. +{"vlsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
  11925. +{"vssseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF },
  11926. +{"vlsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
  11927. +{"vssseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF },
  11928. +{"vlsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
  11929. +{"vssseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF },
  11930. +
  11931. +{"vlsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
  11932. +{"vssseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF },
  11933. +{"vlsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
  11934. +{"vssseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF },
  11935. +{"vlsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
  11936. +{"vssseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF },
  11937. +{"vlsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
  11938. +{"vssseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF },
  11939. +{"vlsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
  11940. +{"vssseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF },
  11941. +{"vlsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
  11942. +{"vssseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF },
  11943. +{"vlsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
  11944. +{"vssseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF },
  11945. +
  11946. +{"vlsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
  11947. +{"vssseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF },
  11948. +{"vlsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
  11949. +{"vssseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF },
  11950. +{"vlsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
  11951. +{"vssseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF },
  11952. +{"vlsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
  11953. +{"vssseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF },
  11954. +{"vlsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
  11955. +{"vssseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF },
  11956. +{"vlsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
  11957. +{"vssseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF },
  11958. +{"vlsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
  11959. +{"vssseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF },
  11960. +
  11961. +{"vlsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
  11962. +{"vssseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF },
  11963. +{"vlsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
  11964. +{"vssseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF },
  11965. +{"vlsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
  11966. +{"vssseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF },
  11967. +{"vlsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
  11968. +{"vssseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF },
  11969. +{"vlsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
  11970. +{"vssseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF },
  11971. +{"vlsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
  11972. +{"vssseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF },
  11973. +{"vlsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
  11974. +{"vssseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF },
  11975. +
  11976. +{"vlsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E128V, MASK_VLSSEG2E128V, match_vd_neq_vm, INSN_DREF },
  11977. +{"vssseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E128V, MASK_VSSSEG2E128V, match_opcode, INSN_DREF },
  11978. +{"vlsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E128V, MASK_VLSSEG3E128V, match_vd_neq_vm, INSN_DREF },
  11979. +{"vssseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E128V, MASK_VSSSEG3E128V, match_opcode, INSN_DREF },
  11980. +{"vlsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E128V, MASK_VLSSEG4E128V, match_vd_neq_vm, INSN_DREF },
  11981. +{"vssseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E128V, MASK_VSSSEG4E128V, match_opcode, INSN_DREF },
  11982. +{"vlsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E128V, MASK_VLSSEG5E128V, match_vd_neq_vm, INSN_DREF },
  11983. +{"vssseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E128V, MASK_VSSSEG5E128V, match_opcode, INSN_DREF },
  11984. +{"vlsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E128V, MASK_VLSSEG6E128V, match_vd_neq_vm, INSN_DREF },
  11985. +{"vssseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E128V, MASK_VSSSEG6E128V, match_opcode, INSN_DREF },
  11986. +{"vlsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E128V, MASK_VLSSEG7E128V, match_vd_neq_vm, INSN_DREF },
  11987. +{"vssseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E128V, MASK_VSSSEG7E128V, match_opcode, INSN_DREF },
  11988. +{"vlsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E128V, MASK_VLSSEG8E128V, match_vd_neq_vm, INSN_DREF },
  11989. +{"vssseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E128V, MASK_VSSSEG8E128V, match_opcode, INSN_DREF },
  11990. +
  11991. +{"vlsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E256V, MASK_VLSSEG2E256V, match_vd_neq_vm, INSN_DREF },
  11992. +{"vssseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E256V, MASK_VSSSEG2E256V, match_opcode, INSN_DREF },
  11993. +{"vlsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E256V, MASK_VLSSEG3E256V, match_vd_neq_vm, INSN_DREF },
  11994. +{"vssseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E256V, MASK_VSSSEG3E256V, match_opcode, INSN_DREF },
  11995. +{"vlsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E256V, MASK_VLSSEG4E256V, match_vd_neq_vm, INSN_DREF },
  11996. +{"vssseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E256V, MASK_VSSSEG4E256V, match_opcode, INSN_DREF },
  11997. +{"vlsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E256V, MASK_VLSSEG5E256V, match_vd_neq_vm, INSN_DREF },
  11998. +{"vssseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E256V, MASK_VSSSEG5E256V, match_opcode, INSN_DREF },
  11999. +{"vlsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E256V, MASK_VLSSEG6E256V, match_vd_neq_vm, INSN_DREF },
  12000. +{"vssseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E256V, MASK_VSSSEG6E256V, match_opcode, INSN_DREF },
  12001. +{"vlsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E256V, MASK_VLSSEG7E256V, match_vd_neq_vm, INSN_DREF },
  12002. +{"vssseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E256V, MASK_VSSSEG7E256V, match_opcode, INSN_DREF },
  12003. +{"vlsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E256V, MASK_VLSSEG8E256V, match_vd_neq_vm, INSN_DREF },
  12004. +{"vssseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E256V, MASK_VSSSEG8E256V, match_opcode, INSN_DREF },
  12005. +
  12006. +{"vlsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E512V, MASK_VLSSEG2E512V, match_vd_neq_vm, INSN_DREF },
  12007. +{"vssseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E512V, MASK_VSSSEG2E512V, match_opcode, INSN_DREF },
  12008. +{"vlsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E512V, MASK_VLSSEG3E512V, match_vd_neq_vm, INSN_DREF },
  12009. +{"vssseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E512V, MASK_VSSSEG3E512V, match_opcode, INSN_DREF },
  12010. +{"vlsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E512V, MASK_VLSSEG4E512V, match_vd_neq_vm, INSN_DREF },
  12011. +{"vssseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E512V, MASK_VSSSEG4E512V, match_opcode, INSN_DREF },
  12012. +{"vlsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E512V, MASK_VLSSEG5E512V, match_vd_neq_vm, INSN_DREF },
  12013. +{"vssseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E512V, MASK_VSSSEG5E512V, match_opcode, INSN_DREF },
  12014. +{"vlsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E512V, MASK_VLSSEG6E512V, match_vd_neq_vm, INSN_DREF },
  12015. +{"vssseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E512V, MASK_VSSSEG6E512V, match_opcode, INSN_DREF },
  12016. +{"vlsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E512V, MASK_VLSSEG7E512V, match_vd_neq_vm, INSN_DREF },
  12017. +{"vssseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E512V, MASK_VSSSEG7E512V, match_opcode, INSN_DREF },
  12018. +{"vlsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E512V, MASK_VLSSEG8E512V, match_vd_neq_vm, INSN_DREF },
  12019. +{"vssseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E512V, MASK_VSSSEG8E512V, match_opcode, INSN_DREF },
  12020. +
  12021. +{"vlsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E1024V, MASK_VLSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
  12022. +{"vssseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E1024V, MASK_VSSSEG2E1024V, match_opcode, INSN_DREF },
  12023. +{"vlsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E1024V, MASK_VLSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
  12024. +{"vssseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E1024V, MASK_VSSSEG3E1024V, match_opcode, INSN_DREF },
  12025. +{"vlsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E1024V, MASK_VLSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
  12026. +{"vssseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E1024V, MASK_VSSSEG4E1024V, match_opcode, INSN_DREF },
  12027. +{"vlsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E1024V, MASK_VLSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
  12028. +{"vssseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E1024V, MASK_VSSSEG5E1024V, match_opcode, INSN_DREF },
  12029. +{"vlsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E1024V, MASK_VLSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
  12030. +{"vssseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E1024V, MASK_VSSSEG6E1024V, match_opcode, INSN_DREF },
  12031. +{"vlsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E1024V, MASK_VLSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
  12032. +{"vssseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E1024V, MASK_VSSSEG7E1024V, match_opcode, INSN_DREF },
  12033. +{"vlsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E1024V, MASK_VLSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
  12034. +{"vssseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_opcode, INSN_DREF },
  12035. +
  12036. +{"vlxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI8V, MASK_VLXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12037. +{"vsxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI8V, MASK_VSXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12038. +{"vlxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI8V, MASK_VLXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12039. +{"vsxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI8V, MASK_VSXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12040. +{"vlxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI8V, MASK_VLXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12041. +{"vsxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI8V, MASK_VSXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12042. +{"vlxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI8V, MASK_VLXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12043. +{"vsxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI8V, MASK_VSXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12044. +{"vlxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI8V, MASK_VLXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12045. +{"vsxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI8V, MASK_VSXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12046. +{"vlxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI8V, MASK_VLXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12047. +{"vsxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI8V, MASK_VSXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12048. +{"vlxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI8V, MASK_VLXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12049. +{"vsxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI8V, MASK_VSXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12050. +
  12051. +{"vlxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI16V, MASK_VLXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12052. +{"vsxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI16V, MASK_VSXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12053. +{"vlxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI16V, MASK_VLXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12054. +{"vsxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI16V, MASK_VSXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12055. +{"vlxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI16V, MASK_VLXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12056. +{"vsxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI16V, MASK_VSXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12057. +{"vlxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI16V, MASK_VLXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12058. +{"vsxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI16V, MASK_VSXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12059. +{"vlxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI16V, MASK_VLXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12060. +{"vsxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI16V, MASK_VSXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12061. +{"vlxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI16V, MASK_VLXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12062. +{"vsxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI16V, MASK_VSXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12063. +{"vlxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI16V, MASK_VLXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12064. +{"vsxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI16V, MASK_VSXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12065. +
  12066. +{"vlxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI32V, MASK_VLXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12067. +{"vsxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI32V, MASK_VSXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12068. +{"vlxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI32V, MASK_VLXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12069. +{"vsxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI32V, MASK_VSXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12070. +{"vlxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI32V, MASK_VLXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12071. +{"vsxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI32V, MASK_VSXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12072. +{"vlxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI32V, MASK_VLXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12073. +{"vsxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI32V, MASK_VSXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12074. +{"vlxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI32V, MASK_VLXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12075. +{"vsxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI32V, MASK_VSXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12076. +{"vlxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI32V, MASK_VLXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12077. +{"vsxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI32V, MASK_VSXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12078. +{"vlxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI32V, MASK_VLXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12079. +{"vsxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI32V, MASK_VSXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12080. +
  12081. +{"vlxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI64V, MASK_VLXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12082. +{"vsxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI64V, MASK_VSXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12083. +{"vlxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI64V, MASK_VLXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12084. +{"vsxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI64V, MASK_VSXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12085. +{"vlxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI64V, MASK_VLXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12086. +{"vsxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI64V, MASK_VSXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12087. +{"vlxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI64V, MASK_VLXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12088. +{"vsxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI64V, MASK_VSXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12089. +{"vlxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI64V, MASK_VLXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12090. +{"vsxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI64V, MASK_VSXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12091. +{"vlxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI64V, MASK_VLXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12092. +{"vsxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI64V, MASK_VSXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12093. +{"vlxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI64V, MASK_VLXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12094. +{"vsxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI64V, MASK_VSXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12095. +
  12096. +{"vlxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI128V, MASK_VLXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12097. +{"vsxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI128V, MASK_VSXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12098. +{"vlxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI128V, MASK_VLXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12099. +{"vsxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI128V, MASK_VSXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12100. +{"vlxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI128V, MASK_VLXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12101. +{"vsxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI128V, MASK_VSXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12102. +{"vlxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI128V, MASK_VLXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12103. +{"vsxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI128V, MASK_VSXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12104. +{"vlxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI128V, MASK_VLXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12105. +{"vsxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI128V, MASK_VSXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12106. +{"vlxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI128V, MASK_VLXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12107. +{"vsxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI128V, MASK_VSXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12108. +{"vlxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI128V, MASK_VLXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12109. +{"vsxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI128V, MASK_VSXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12110. +
  12111. +{"vlxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI256V, MASK_VLXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12112. +{"vsxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI256V, MASK_VSXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12113. +{"vlxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI256V, MASK_VLXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12114. +{"vsxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI256V, MASK_VSXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12115. +{"vlxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI256V, MASK_VLXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12116. +{"vsxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI256V, MASK_VSXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12117. +{"vlxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI256V, MASK_VLXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12118. +{"vsxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI256V, MASK_VSXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12119. +{"vlxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI256V, MASK_VLXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12120. +{"vsxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI256V, MASK_VSXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12121. +{"vlxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI256V, MASK_VLXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12122. +{"vsxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI256V, MASK_VSXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12123. +{"vlxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI256V, MASK_VLXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12124. +{"vsxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI256V, MASK_VSXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12125. +
  12126. +{"vlxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI512V, MASK_VLXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12127. +{"vsxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI512V, MASK_VSXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12128. +{"vlxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI512V, MASK_VLXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12129. +{"vsxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI512V, MASK_VSXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12130. +{"vlxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI512V, MASK_VLXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12131. +{"vsxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI512V, MASK_VSXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12132. +{"vlxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI512V, MASK_VLXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12133. +{"vsxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI512V, MASK_VSXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12134. +{"vlxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI512V, MASK_VLXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12135. +{"vsxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI512V, MASK_VSXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12136. +{"vlxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI512V, MASK_VLXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12137. +{"vsxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI512V, MASK_VSXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12138. +{"vlxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI512V, MASK_VLXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12139. +{"vsxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI512V, MASK_VSXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12140. +
  12141. +{"vlxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI1024V, MASK_VLXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12142. +{"vsxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI1024V, MASK_VSXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12143. +{"vlxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI1024V, MASK_VLXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12144. +{"vsxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI1024V, MASK_VSXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12145. +{"vlxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI1024V, MASK_VLXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12146. +{"vsxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI1024V, MASK_VSXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12147. +{"vlxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI1024V, MASK_VLXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12148. +{"vsxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI1024V, MASK_VSXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12149. +{"vlxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI1024V, MASK_VLXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12150. +{"vsxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI1024V, MASK_VSXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12151. +{"vlxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI1024V, MASK_VLXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12152. +{"vsxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI1024V, MASK_VSXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12153. +{"vlxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI1024V, MASK_VLXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12154. +{"vsxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI1024V, MASK_VSXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  12155. +
  12156. +{"vlseg2e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
  12157. +{"vlseg3e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
  12158. +{"vlseg4e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_vd_neq_vm, INSN_DREF },
  12159. +{"vlseg5e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_vd_neq_vm, INSN_DREF },
  12160. +{"vlseg6e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_vd_neq_vm, INSN_DREF },
  12161. +{"vlseg7e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_vd_neq_vm, INSN_DREF },
  12162. +{"vlseg8e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_vd_neq_vm, INSN_DREF },
  12163. +
  12164. +{"vlseg2e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_vd_neq_vm, INSN_DREF },
  12165. +{"vlseg3e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_vd_neq_vm, INSN_DREF },
  12166. +{"vlseg4e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_vd_neq_vm, INSN_DREF },
  12167. +{"vlseg5e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_vd_neq_vm, INSN_DREF },
  12168. +{"vlseg6e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_vd_neq_vm, INSN_DREF },
  12169. +{"vlseg7e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_vd_neq_vm, INSN_DREF },
  12170. +{"vlseg8e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_vd_neq_vm, INSN_DREF },
  12171. +
  12172. +{"vlseg2e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_vd_neq_vm, INSN_DREF },
  12173. +{"vlseg3e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_vd_neq_vm, INSN_DREF },
  12174. +{"vlseg4e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_vd_neq_vm, INSN_DREF },
  12175. +{"vlseg5e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_vd_neq_vm, INSN_DREF },
  12176. +{"vlseg6e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_vd_neq_vm, INSN_DREF },
  12177. +{"vlseg7e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
  12178. +{"vlseg8e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
  12179. +
  12180. +{"vlseg2e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
  12181. +{"vlseg3e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
  12182. +{"vlseg4e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
  12183. +{"vlseg5e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
  12184. +{"vlseg6e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
  12185. +{"vlseg7e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
  12186. +{"vlseg8e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
  12187. +
  12188. +{"vlseg2e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E128FFV, MASK_VLSEG2E128FFV, match_vd_neq_vm, INSN_DREF },
  12189. +{"vlseg3e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E128FFV, MASK_VLSEG3E128FFV, match_vd_neq_vm, INSN_DREF },
  12190. +{"vlseg4e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E128FFV, MASK_VLSEG4E128FFV, match_vd_neq_vm, INSN_DREF },
  12191. +{"vlseg5e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E128FFV, MASK_VLSEG5E128FFV, match_vd_neq_vm, INSN_DREF },
  12192. +{"vlseg6e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E128FFV, MASK_VLSEG6E128FFV, match_vd_neq_vm, INSN_DREF },
  12193. +{"vlseg7e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E128FFV, MASK_VLSEG7E128FFV, match_vd_neq_vm, INSN_DREF },
  12194. +{"vlseg8e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E128FFV, MASK_VLSEG8E128FFV, match_vd_neq_vm, INSN_DREF },
  12195. +
  12196. +{"vlseg2e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E256FFV, MASK_VLSEG2E256FFV, match_vd_neq_vm, INSN_DREF },
  12197. +{"vlseg3e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E256FFV, MASK_VLSEG3E256FFV, match_vd_neq_vm, INSN_DREF },
  12198. +{"vlseg4e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E256FFV, MASK_VLSEG4E256FFV, match_vd_neq_vm, INSN_DREF },
  12199. +{"vlseg5e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E256FFV, MASK_VLSEG5E256FFV, match_vd_neq_vm, INSN_DREF },
  12200. +{"vlseg6e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E256FFV, MASK_VLSEG6E256FFV, match_vd_neq_vm, INSN_DREF },
  12201. +{"vlseg7e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E256FFV, MASK_VLSEG7E256FFV, match_vd_neq_vm, INSN_DREF },
  12202. +{"vlseg8e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E256FFV, MASK_VLSEG8E256FFV, match_vd_neq_vm, INSN_DREF },
  12203. +
  12204. +{"vlseg2e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E512FFV, MASK_VLSEG2E512FFV, match_vd_neq_vm, INSN_DREF },
  12205. +{"vlseg3e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E512FFV, MASK_VLSEG3E512FFV, match_vd_neq_vm, INSN_DREF },
  12206. +{"vlseg4e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E512FFV, MASK_VLSEG4E512FFV, match_vd_neq_vm, INSN_DREF },
  12207. +{"vlseg5e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E512FFV, MASK_VLSEG5E512FFV, match_vd_neq_vm, INSN_DREF },
  12208. +{"vlseg6e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E512FFV, MASK_VLSEG6E512FFV, match_vd_neq_vm, INSN_DREF },
  12209. +{"vlseg7e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E512FFV, MASK_VLSEG7E512FFV, match_vd_neq_vm, INSN_DREF },
  12210. +{"vlseg8e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E512FFV, MASK_VLSEG8E512FFV, match_vd_neq_vm, INSN_DREF },
  12211. +
  12212. +{"vlseg2e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E1024FFV, MASK_VLSEG2E1024FFV, match_vd_neq_vm, INSN_DREF },
  12213. +{"vlseg3e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E1024FFV, MASK_VLSEG3E1024FFV, match_vd_neq_vm, INSN_DREF },
  12214. +{"vlseg4e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E1024FFV, MASK_VLSEG4E1024FFV, match_vd_neq_vm, INSN_DREF },
  12215. +{"vlseg5e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E1024FFV, MASK_VLSEG5E1024FFV, match_vd_neq_vm, INSN_DREF },
  12216. +{"vlseg6e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E1024FFV, MASK_VLSEG6E1024FFV, match_vd_neq_vm, INSN_DREF },
  12217. +{"vlseg7e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E1024FFV, MASK_VLSEG7E1024FFV, match_vd_neq_vm, INSN_DREF },
  12218. +{"vlseg8e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
  12219. +
  12220. +{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RV, MASK_VL1RV, match_opcode, INSN_DREF },
  12221. +{"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
  12222. +
  12223. +{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_opcode, INSN_DREF},
  12224. +{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_opcode, INSN_DREF},
  12225. +{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_opcode, INSN_DREF},
  12226. +{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_opcode, INSN_DREF},
  12227. +{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_opcode, INSN_DREF},
  12228. +{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_opcode, INSN_DREF},
  12229. +{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_opcode, INSN_DREF},
  12230. +{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_opcode, INSN_DREF},
  12231. +{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_opcode, INSN_DREF},
  12232. +
  12233. +{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_opcode, INSN_DREF},
  12234. +{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_opcode, INSN_DREF},
  12235. +{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_opcode, INSN_DREF},
  12236. +{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_opcode, INSN_DREF},
  12237. +{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_opcode, INSN_DREF},
  12238. +{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_opcode, INSN_DREF},
  12239. +{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_opcode, INSN_DREF},
  12240. +{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_opcode, INSN_DREF},
  12241. +{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_opcode, INSN_DREF},
  12242. +
  12243. +{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_opcode, INSN_DREF},
  12244. +{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_opcode, INSN_DREF},
  12245. +{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_opcode, INSN_DREF},
  12246. +{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_opcode, INSN_DREF},
  12247. +{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_opcode, INSN_DREF},
  12248. +{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_opcode, INSN_DREF},
  12249. +{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_opcode, INSN_DREF},
  12250. +{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_opcode, INSN_DREF},
  12251. +{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_opcode, INSN_DREF},
  12252. +
  12253. +{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_opcode, INSN_DREF},
  12254. +{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_opcode, INSN_DREF},
  12255. +{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_opcode, INSN_DREF},
  12256. +{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_opcode, INSN_DREF},
  12257. +{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_opcode, INSN_DREF},
  12258. +{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_opcode, INSN_DREF},
  12259. +{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_opcode, INSN_DREF},
  12260. +{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_opcode, INSN_DREF},
  12261. +{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_opcode, INSN_DREF},
  12262. +
  12263. +{"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
  12264. +{"vadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
  12265. +{"vadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
  12266. +{"vsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
  12267. +{"vsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
  12268. +{"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
  12269. +{"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
  12270. +
  12271. +{"vwcvt.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
  12272. +{"vwcvtu.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
  12273. +
  12274. +{"vwaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
  12275. +{"vwaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
  12276. +{"vwsubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
  12277. +{"vwsubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
  12278. +{"vwadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
  12279. +{"vwadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
  12280. +{"vwsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
  12281. +{"vwsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
  12282. +{"vwaddu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
  12283. +{"vwaddu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
  12284. +{"vwsubu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
  12285. +{"vwsubu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
  12286. +{"vwadd.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
  12287. +{"vwadd.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
  12288. +{"vwsub.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
  12289. +{"vwsub.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
  12290. +
  12291. +{"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_opcode, 0 },
  12292. +{"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_opcode, 0 },
  12293. +{"vzext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_opcode, 0 },
  12294. +{"vsext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_opcode, 0 },
  12295. +{"vzext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_opcode, 0 },
  12296. +{"vsext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_opcode, 0 },
  12297. +
  12298. +{"vadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_opcode, 0 },
  12299. +{"vadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_opcode, 0 },
  12300. +{"vadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_opcode, 0 },
  12301. +{"vmadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
  12302. +{"vmadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
  12303. +{"vmadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
  12304. +{"vmadc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
  12305. +{"vmadc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
  12306. +{"vmadc.vi", 0, INSN_CLASS_V, "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
  12307. +{"vsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_opcode, 0 },
  12308. +{"vsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_opcode, 0 },
  12309. +{"vmsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
  12310. +{"vmsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
  12311. +{"vmsbc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
  12312. +{"vmsbc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
  12313. +
  12314. +{"vnot.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
  12315. +
  12316. +{"vand.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
  12317. +{"vand.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
  12318. +{"vand.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
  12319. +{"vor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
  12320. +{"vor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
  12321. +{"vor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
  12322. +{"vxor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
  12323. +{"vxor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
  12324. +{"vxor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
  12325. +
  12326. +{"vsll.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
  12327. +{"vsll.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
  12328. +{"vsll.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
  12329. +{"vsrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
  12330. +{"vsrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
  12331. +{"vsrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
  12332. +{"vsra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
  12333. +{"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
  12334. +{"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
  12335. +
  12336. +{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2, 0 },
  12337. +{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2, 0 },
  12338. +{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2, 0 },
  12339. +{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2, 0 },
  12340. +{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2, 0 },
  12341. +{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2, 0 },
  12342. +
  12343. +{"vmseq.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
  12344. +{"vmseq.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
  12345. +{"vmseq.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
  12346. +{"vmsne.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
  12347. +{"vmsne.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
  12348. +{"vmsne.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
  12349. +{"vmsltu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
  12350. +{"vmsltu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
  12351. +{"vmslt.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
  12352. +{"vmslt.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
  12353. +{"vmsleu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
  12354. +{"vmsleu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
  12355. +{"vmsleu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
  12356. +{"vmsle.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
  12357. +{"vmsle.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
  12358. +{"vmsle.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
  12359. +{"vmsgtu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
  12360. +{"vmsgtu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
  12361. +{"vmsgt.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
  12362. +{"vmsgt.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
  12363. +
  12364. +/* These aliases are for assembly but not disassembly. */
  12365. +{"vmsgt.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
  12366. +{"vmsgtu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
  12367. +{"vmsge.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
  12368. +{"vmsgeu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
  12369. +{"vmslt.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
  12370. +{"vmsltu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, INSN_ALIAS },
  12371. +{"vmsltu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
  12372. +{"vmsge.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
  12373. +{"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, INSN_ALIAS },
  12374. +{"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
  12375. +
  12376. +{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
  12377. +{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
  12378. +{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
  12379. +{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
  12380. +
  12381. +{"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
  12382. +{"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
  12383. +{"vmin.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
  12384. +{"vmin.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
  12385. +{"vmaxu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
  12386. +{"vmaxu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
  12387. +{"vmax.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
  12388. +{"vmax.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
  12389. +
  12390. +{"vmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
  12391. +{"vmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
  12392. +{"vmulh.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
  12393. +{"vmulh.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
  12394. +{"vmulhu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
  12395. +{"vmulhu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
  12396. +{"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
  12397. +{"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
  12398. +
  12399. +{"vwmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
  12400. +{"vwmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
  12401. +{"vwmulu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
  12402. +{"vwmulu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
  12403. +{"vwmulsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
  12404. +{"vwmulsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
  12405. +
  12406. +{"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
  12407. +{"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
  12408. +{"vnmsac.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
  12409. +{"vnmsac.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
  12410. +{"vmadd.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
  12411. +{"vmadd.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
  12412. +{"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
  12413. +{"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
  12414. +
  12415. +{"vwmaccu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12416. +{"vwmaccu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
  12417. +{"vwmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12418. +{"vwmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
  12419. +{"vwmaccsu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12420. +{"vwmaccsu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
  12421. +{"vwmaccus.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
  12422. +
  12423. +{"vqmaccu.vv", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,Vs,VtVm", MATCH_VQMACCUVV, MASK_VQMACCUVV, match_quad_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12424. +{"vqmaccu.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCUVX, MASK_VQMACCUVX, match_quad_vd_neq_vs2_neq_vm, 0},
  12425. +{"vqmacc.vv", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,Vs,VtVm", MATCH_VQMACCVV, MASK_VQMACCVV, match_quad_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12426. +{"vqmacc.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCVX, MASK_VQMACCVX, match_quad_vd_neq_vs2_neq_vm, 0},
  12427. +{"vqmaccsu.vv", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,Vs,VtVm", MATCH_VQMACCSUVV, MASK_VQMACCSUVV, match_quad_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12428. +{"vqmaccsu.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_quad_vd_neq_vs2_neq_vm, 0},
  12429. +{"vqmaccus.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_quad_vd_neq_vs2_neq_vm, 0},
  12430. +
  12431. +{"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
  12432. +{"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
  12433. +{"vdiv.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
  12434. +{"vdiv.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
  12435. +{"vremu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
  12436. +{"vremu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
  12437. +{"vrem.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
  12438. +{"vrem.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
  12439. +
  12440. +{"vmerge.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
  12441. +{"vmerge.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
  12442. +{"vmerge.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
  12443. +
  12444. +{"vmv.v.v", 0, INSN_CLASS_V, "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
  12445. +{"vmv.v.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
  12446. +{"vmv.v.i", 0, INSN_CLASS_V, "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
  12447. +
  12448. +{"vsaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
  12449. +{"vsaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
  12450. +{"vsaddu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
  12451. +{"vsadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
  12452. +{"vsadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
  12453. +{"vsadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
  12454. +{"vssubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
  12455. +{"vssubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
  12456. +{"vssub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
  12457. +{"vssub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
  12458. +
  12459. +{"vaaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_opcode, 0 },
  12460. +{"vaaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_opcode, 0 },
  12461. +{"vaadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_opcode, 0 },
  12462. +{"vaadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_opcode, 0 },
  12463. +{"vasubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_opcode, 0 },
  12464. +{"vasubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_opcode, 0 },
  12465. +{"vasub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_opcode, 0 },
  12466. +{"vasub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_opcode, 0 },
  12467. +
  12468. +{"vsmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
  12469. +{"vsmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
  12470. +
  12471. +{"vssrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
  12472. +{"vssrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
  12473. +{"vssrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
  12474. +{"vssra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
  12475. +{"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
  12476. +{"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
  12477. +
  12478. +{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2, 0 },
  12479. +{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2, 0 },
  12480. +{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2, 0 },
  12481. +{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2, 0 },
  12482. +{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2, 0 },
  12483. +{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2, 0 },
  12484. +
  12485. +{"vfadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
  12486. +{"vfadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
  12487. +{"vfsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
  12488. +{"vfsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
  12489. +{"vfrsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
  12490. +
  12491. +{"vfwadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12492. +{"vfwadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
  12493. +{"vfwsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12494. +{"vfwsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
  12495. +{"vfwadd.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
  12496. +{"vfwadd.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
  12497. +{"vfwsub.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
  12498. +{"vfwsub.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
  12499. +
  12500. +{"vfmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
  12501. +{"vfmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
  12502. +{"vfdiv.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
  12503. +{"vfdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
  12504. +{"vfrdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
  12505. +
  12506. +{"vfwmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12507. +{"vfwmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
  12508. +
  12509. +{"vfmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
  12510. +{"vfmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
  12511. +{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
  12512. +{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
  12513. +{"vfmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
  12514. +{"vfmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
  12515. +{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
  12516. +{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
  12517. +{"vfmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
  12518. +{"vfmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
  12519. +{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
  12520. +{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
  12521. +{"vfmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
  12522. +{"vfmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
  12523. +{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
  12524. +{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
  12525. +
  12526. +{"vfwmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12527. +{"vfwmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
  12528. +{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12529. +{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
  12530. +{"vfwmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12531. +{"vfwmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
  12532. +{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12533. +{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
  12534. +
  12535. +{"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0},
  12536. +
  12537. +{"vfmin.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
  12538. +{"vfmin.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
  12539. +{"vfmax.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
  12540. +{"vfmax.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
  12541. +
  12542. +{"vfsgnj.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
  12543. +{"vfsgnj.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
  12544. +{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
  12545. +{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
  12546. +{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
  12547. +{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
  12548. +
  12549. +{"vmfeq.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
  12550. +{"vmfeq.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
  12551. +{"vmfne.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
  12552. +{"vmfne.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
  12553. +{"vmflt.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
  12554. +{"vmflt.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
  12555. +{"vmfle.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
  12556. +{"vmfle.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
  12557. +{"vmfgt.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
  12558. +{"vmfge.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
  12559. +
  12560. +/* These aliases are for assembly but not disassembly. */
  12561. +{"vmfgt.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
  12562. +{"vmfge.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
  12563. +
  12564. +{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
  12565. +
  12566. +{"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
  12567. +{"vfmv.v.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
  12568. +
  12569. +{"vfcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_opcode, 0},
  12570. +{"vfcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_opcode, 0},
  12571. +{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_opcode, 0},
  12572. +{"vfcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_opcode, 0},
  12573. +{"vfcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_opcode, 0},
  12574. +{"vfcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_opcode, 0},
  12575. +
  12576. +{"vfwcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
  12577. +{"vfwcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
  12578. +{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
  12579. +{"vfwcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
  12580. +{"vfwcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
  12581. +{"vfwcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
  12582. +{"vfwcvt.f.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
  12583. +
  12584. +{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2, 0},
  12585. +{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2, 0},
  12586. +{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2, 0},
  12587. +{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2, 0},
  12588. +{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2, 0},
  12589. +{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2, 0},
  12590. +{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2, 0},
  12591. +{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2, 0},
  12592. +
  12593. +{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
  12594. +{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
  12595. +{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
  12596. +{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
  12597. +{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
  12598. +{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
  12599. +{"vredor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
  12600. +{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
  12601. +
  12602. +{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
  12603. +{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
  12604. +
  12605. +{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
  12606. +{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
  12607. +{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
  12608. +{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
  12609. +
  12610. +{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
  12611. +{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
  12612. +
  12613. +{"vmmv.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
  12614. +{"vmcpy.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
  12615. +{"vmclr.m", 0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
  12616. +{"vmset.m", 0, INSN_CLASS_V, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
  12617. +{"vmnot.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
  12618. +
  12619. +{"vmand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
  12620. +{"vmnand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
  12621. +{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
  12622. +{"vmxor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
  12623. +{"vmor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
  12624. +{"vmnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
  12625. +{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
  12626. +{"vmxnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
  12627. +
  12628. +{"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
  12629. +{"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
  12630. +{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_opcode, 0},
  12631. +{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_opcode, 0},
  12632. +{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_opcode, 0},
  12633. +{"viota.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
  12634. +{"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_opcode, 0},
  12635. +
  12636. +{"vmv.x.s", 0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
  12637. +{"vmv.s.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
  12638. +
  12639. +{"vfmv.f.s", 0, INSN_CLASS_V_AND_F, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
  12640. +{"vfmv.s.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
  12641. +
  12642. +{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2, 0},
  12643. +{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2, 0},
  12644. +{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
  12645. +{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
  12646. +
  12647. +{"vslide1up.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2, 0},
  12648. +{"vslide1down.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
  12649. +{"vfslide1up.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2, 0},
  12650. +{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_opcode, 0},
  12651. +
  12652. +{"vrgather.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12653. +{"vrgather.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
  12654. +{"vrgather.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
  12655. +
  12656. +{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
  12657. +
  12658. +{"vmv1r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
  12659. +{"vmv2r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
  12660. +{"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_vmv_nf_rv, 0},
  12661. +{"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
  12662. +
  12663. +{"vdot.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDOTVV, MASK_VDOTVV, match_opcode, 0},
  12664. +{"vdotu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDOTUVV, MASK_VDOTUVV, match_opcode, 0},
  12665. +{"vfdot.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VFDOTVV, MASK_VFDOTVV, match_opcode, 0},
  12666. +/* END RVV */
  12667. +
  12668. /* Terminate the list. */
  12669. {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
  12670. };
  12671. @@ -797,6 +2027,26 @@ const struct riscv_opcode riscv_insn_types[] =
  12672. {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,T", 0, 0, match_opcode, 0 },
  12673. {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,T", 0, 0, match_opcode, 0 },
  12674. +{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,s,t", 0, 0, match_opcode, 0 },
  12675. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,S,t", 0, 0, match_opcode, 0 },
  12676. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,s,T", 0, 0, match_opcode, 0 },
  12677. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,S,T", 0, 0, match_opcode, 0 },
  12678. +{"r", 0, INSN_CLASS_V, "O4,F3,F7,d,Vs,t", 0, 0, match_opcode, 0 },
  12679. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,Vs,t", 0, 0, match_opcode, 0 },
  12680. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,d,Vs,T", 0, 0, match_opcode, 0 },
  12681. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,Vs,T", 0, 0, match_opcode, 0 },
  12682. +{"r", 0, INSN_CLASS_V, "O4,F3,F7,d,s,Vt", 0, 0, match_opcode, 0 },
  12683. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,s,Vt", 0, 0, match_opcode, 0 },
  12684. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,d,S,Vt", 0, 0, match_opcode, 0 },
  12685. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,S,Vt", 0, 0, match_opcode, 0 },
  12686. +{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,Vs,t", 0, 0, match_opcode, 0 },
  12687. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,Vs,T", 0, 0, match_opcode, 0 },
  12688. +{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,s,Vt", 0, 0, match_opcode, 0 },
  12689. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,S,Vt", 0, 0, match_opcode, 0 },
  12690. +{"r", 0, INSN_CLASS_V, "O4,F3,F7,d,Vs,Vt", 0, 0, match_opcode, 0 },
  12691. +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,Vs,Vt", 0, 0, match_opcode, 0 },
  12692. +{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,Vs,Vt", 0, 0, match_opcode, 0 },
  12693. +
  12694. {"r", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 },
  12695. {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 },
  12696. {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 },
  12697. --
  12698. 2.33.0