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|
- From 9fc7114a93d01d5c4e656331ba38fcd0b0d458f9 Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Wed, 8 Jul 2020 14:50:08 +0800
- Subject: [PATCH 12/48] RISC-V: Support RVV according to vector spec
- v1.0-draft-20200516.
- 2020-05-16 Jim Wilson <jimw@sifive.com>
- Kito Cheng <kito.cheng@sifive.com>
- Nelson Chu <nelson.chu@sifive.com>
- ---
- bfd/elfxx-riscv.c | 4 +-
- gas/config/tc-riscv.c | 438 ++-
- gas/testsuite/gas/riscv/csr-dw-regnums.d | 9 +-
- gas/testsuite/gas/riscv/csr-dw-regnums.s | 7 +
- gas/testsuite/gas/riscv/insn.d | 69 +-
- gas/testsuite/gas/riscv/insn.s | 84 +
- .../gas/riscv/march-fail-s-with-version | 2 +
- .../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
- .../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
- .../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
- gas/testsuite/gas/riscv/priv-reg-fail-vext.d | 3 +
- gas/testsuite/gas/riscv/priv-reg-fail-vext.l | 9 +
- .../gas/riscv/priv-reg-version-1p10.d | 9 +-
- .../gas/riscv/priv-reg-version-1p11.d | 9 +-
- .../gas/riscv/priv-reg-version-1p9p1.d | 9 +-
- gas/testsuite/gas/riscv/priv-reg.s | 9 +
- gas/testsuite/gas/riscv/v-zero-imm.d | 17 +
- gas/testsuite/gas/riscv/v-zero-imm.s | 8 +
- .../gas/riscv/vector-insns-fail-01.d | 3 +
- .../gas/riscv/vector-insns-fail-01.l | 393 +++
- .../gas/riscv/vector-insns-fail-01.s | 1037 +++++++
- .../gas/riscv/vector-insns-fail-02.d | 3 +
- .../gas/riscv/vector-insns-fail-02.l | 121 +
- .../gas/riscv/vector-insns-fail-02.s | 162 +
- .../gas/riscv/vector-insns-fail-03.d | 3 +
- .../gas/riscv/vector-insns-fail-03.l | 125 +
- .../gas/riscv/vector-insns-fail-03.s | 187 ++
- .../gas/riscv/vector-insns-fail-04.d | 3 +
- .../gas/riscv/vector-insns-fail-04.l | 49 +
- .../gas/riscv/vector-insns-fail-04.s | 85 +
- .../gas/riscv/vector-insns-fail-05.d | 3 +
- .../gas/riscv/vector-insns-fail-05.l | 61 +
- .../gas/riscv/vector-insns-fail-05.s | 133 +
- .../gas/riscv/vector-insns-fail-06.d | 3 +
- .../gas/riscv/vector-insns-fail-06.l | 22 +
- .../gas/riscv/vector-insns-fail-06.s | 67 +
- .../gas/riscv/vector-insns-fail-zvediv.d | 20 +
- .../gas/riscv/vector-insns-fail-zvediv.l | 6 +
- .../gas/riscv/vector-insns-fail-zvediv.s | 9 +
- .../gas/riscv/vector-insns-vmsgtvx.d | 29 +
- .../gas/riscv/vector-insns-vmsgtvx.s | 9 +
- gas/testsuite/gas/riscv/vector-insns.d | 2384 +++++++++++++++
- gas/testsuite/gas/riscv/vector-insns.s | 2718 +++++++++++++++++
- include/opcode/riscv-opc.h | 2138 +++++++++++++
- include/opcode/riscv.h | 99 +-
- opcodes/riscv-dis.c | 86 +-
- opcodes/riscv-opc.c | 1306 +++++++-
- 47 files changed, 11910 insertions(+), 46 deletions(-)
- create mode 100644 gas/testsuite/gas/riscv/march-fail-s-with-version
- create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-vext.d
- create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-vext.l
- create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.d
- create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns.s
- diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
- index 86c0d94d0e..f797d28f59 100644
- --- a/bfd/elfxx-riscv.c
- +++ b/bfd/elfxx-riscv.c
- @@ -1566,7 +1566,9 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
-
- static const char * const riscv_std_z_ext_strtab[] =
- {
- - "zicsr", "zifencei", NULL
- + "zicsr", "zifencei",
- + "zvamo", "zvediv", "zvlsseg", "zvqmac",
- + NULL
- };
-
- static const char * const riscv_std_s_ext_strtab[] =
- diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
- index c21bb719d8..222214d7e4 100644
- --- a/gas/config/tc-riscv.c
- +++ b/gas/config/tc-riscv.c
- @@ -178,6 +178,7 @@ struct riscv_set_options
- int relax; /* Emit relocs the linker is allowed to relax. */
- int arch_attr; /* Emit arch attribute. */
- int csr_check; /* Enable the CSR checking. */
- + int check_constraints; /* Enable/disable the match_func checking. */
- };
-
- static struct riscv_set_options riscv_opts =
- @@ -187,7 +188,8 @@ static struct riscv_set_options riscv_opts =
- 0, /* rve */
- 1, /* relax */
- DEFAULT_RISCV_ATTR, /* arch_attr */
- - 0. /* csr_check */
- + 0, /* csr_check */
- + 0, /* check_constraints */
- };
-
- static void
- @@ -237,6 +239,20 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
-
- case INSN_CLASS_Q: return riscv_subset_supports ("q");
-
- + case INSN_CLASS_V: return riscv_subset_supports ("v");
- + case INSN_CLASS_V_AND_F:
- + return riscv_subset_supports ("v") && riscv_subset_supports ("f");
- + case INSN_CLASS_V_OR_ZVAMO:
- + return (riscv_subset_supports ("a")
- + && (riscv_subset_supports ("v")
- + || riscv_subset_supports ("zvamo")));
- + case INSN_CLASS_V_AND_ZVEDIV:
- + return riscv_subset_supports ("v") && riscv_subset_supports ("zvediv");
- + case INSN_CLASS_V_OR_ZVLSSEG:
- + return riscv_subset_supports ("v") || riscv_subset_supports ("zvlsseg");
- + case INSN_CLASS_V_AND_ZVQMAC:
- + return riscv_subset_supports ("v") && riscv_subset_supports ("zvqmac");
- +
- default:
- as_fatal ("Unreachable");
- return FALSE;
- @@ -598,6 +614,8 @@ enum reg_class
- {
- RCLASS_GPR,
- RCLASS_FPR,
- + RCLASS_VECR,
- + RCLASS_VECM,
- RCLASS_MAX,
-
- RCLASS_CSR
- @@ -696,6 +714,12 @@ riscv_csr_address (const char *csr_name,
- result = riscv_subset_supports ("f");
- need_check_version = FALSE;
- break;
- + case CSR_CLASS_V:
- + result = (riscv_subset_supports ("v")
- + || riscv_subset_supports ("zvamo")
- + || riscv_subset_supports ("zvlsseg"));
- + need_check_version = FALSE;
- + break;
- case CSR_CLASS_DEBUG:
- need_check_version = FALSE;
- break;
- @@ -735,10 +759,8 @@ riscv_csr_address (const char *csr_name,
- return saved_entry->address;
- }
-
- -/* Once the CSR is defined, including the old privilege spec, then we call
- - riscv_csr_class_check and riscv_csr_version_check to do the further checking
- - and get the corresponding address. Return -1 if the CSR is never been
- - defined. Otherwise, return the address. */
- +/* Return -1 if the CSR is never been defined. Otherwise, return the
- + address. */
-
- static unsigned int
- reg_csr_lookup_internal (const char *s)
- @@ -773,6 +795,11 @@ reg_lookup_internal (const char *s, enum reg_class class)
- if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
- return -1;
-
- + if (class == RCLASS_CSR
- + && riscv_opts.csr_check
- + && !reg_csr_lookup_internal (s))
- + return -1;
- +
- return DECODE_REG_NUM (r);
- }
-
- @@ -965,6 +992,32 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
- return FALSE;
- }
- break;
- +
- + case 'V': /* RVV */
- + switch (c = *p++)
- + {
- + case 'd':
- + case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break;
- + case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break;
- + case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break;
- + case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
- + case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1);
- + USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
- + case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD);
- + USE_BITS (OP_MASK_VS1, OP_SH_VS1);
- + USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
- + case '0': break;
- + case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break;
- + case 'i':
- + case 'j':
- + case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
- + case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
- + default:
- + as_bad (_("internal: bad RISC-V opcode (unknown operand type `V%c'): %s %s"),
- + c, opc->name, opc->args);
- + }
- + break;
- +
- default:
- as_bad (_("internal: bad RISC-V opcode "
- "(unknown operand type `%c'): %s %s"),
- @@ -1043,6 +1096,8 @@ md_begin (void)
- hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
- hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
- hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
- + hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR);
- + hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM);
- /* Add "fp" as an alias for "s0". */
- hash_reg_name (RCLASS_GPR, "fp", 8);
-
- @@ -1201,6 +1256,42 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
- break;
- case ',':
- continue;
- +
- + case 'V': /* RVV */
- + {
- + switch (*fmt++)
- + {
- + case 'd':
- + INSERT_OPERAND (VD, insn, va_arg (args, int));
- + continue;
- +
- + case 's':
- + INSERT_OPERAND (VS1, insn, va_arg (args, int));
- + continue;
- +
- + case 't':
- + INSERT_OPERAND (VS2, insn, va_arg (args, int));
- + continue;
- +
- + case 'm':
- + {
- + int reg = va_arg (args, int);
- + if (reg == -1)
- + {
- + INSERT_OPERAND (VMASK, insn, 1);
- + continue;
- + }
- + else if (reg == 0)
- + {
- + INSERT_OPERAND (VMASK, insn, 0);
- + continue;
- + }
- + }
- + /* fallthru */
- + }
- + }
- + /* fallthru */
- +
- default:
- as_fatal (_("internal error: invalid macro"));
- }
- @@ -1365,6 +1456,96 @@ load_const (int reg, expressionS *ep)
- }
- }
-
- +/* Expand RISC-V Vector macros into one of more instructions. */
- +
- +static void
- +vector_macro (struct riscv_cl_insn *ip)
- +{
- + int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD;
- + int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1;
- + int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2;
- + int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK;
- + int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6;
- + int mask = ip->insn_mo->mask;
- +
- + switch (mask)
- + {
- + case M_VMSGE:
- + if (vm)
- + {
- + /* Unmasked. */
- + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
- + macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
- + break;
- + }
- + if (vtemp != 0)
- + {
- + /* Masked. Have vtemp to avoid overlap constraints. */
- + if (vd == vm)
- + {
- + macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
- + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
- + }
- + else
- + {
- + /* Preserve the value of vd if not updating by vm. */
- + macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
- + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
- + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
- + macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
- + }
- + }
- + else if (vd != vm)
- + {
- + /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
- + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
- + macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
- + }
- + else
- + as_bad (_("must provide temp if destination overlaps mask"));
- + break;
- +
- + case M_VMSGEU:
- + if (vm)
- + {
- + /* Unmasked. */
- + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
- + macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
- + break;
- + }
- + if (vtemp != 0)
- + {
- + /* Masked. Have vtemp to avoid overlap constraints. */
- + if (vd == vm)
- + {
- + macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
- + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
- + }
- + else
- + {
- + /* Preserve the value of vd if not updating by vm. */
- + macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
- + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
- + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
- + macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
- + }
- + }
- + else if (vd != vm)
- + {
- + /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
- + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
- + macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
- + }
- + else
- + as_bad (_("must provide temp if destination overlaps mask"));
- + break;
- +
- + default:
- + as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
- + break;
- + }
- +}
- +
- /* Expand RISC-V assembly macros into one or more instructions. */
- static void
- macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
- @@ -1486,6 +1667,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
- riscv_call (rd, rs1, imm_expr, *imm_reloc);
- break;
-
- + case M_VMSGE:
- + case M_VMSGEU:
- + vector_macro (ip);
- + break;
- +
- default:
- as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
- break;
- @@ -1639,6 +1825,81 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
- return reloc_index;
- }
-
- +/* Parse string STR as a vsetvli operand. Store the expression in *EP.
- + On exit, EXPR_END points to the first character after the expression. */
- +
- +static void
- +my_getVsetvliExpression (expressionS *ep, char *str)
- +{
- + unsigned int vsew_value = 0, vlmul_value = 0, vediv_value = 0;
- + unsigned int vta_value = 0, vma_value = 0;
- + bfd_boolean vsew_found = FALSE, vlmul_found = FALSE, vediv_found = FALSE;
- + bfd_boolean vta_found = FALSE, vma_found = FALSE;
- +
- + if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
- + {
- + if (*str == ',')
- + ++str;
- + if (vsew_found)
- + as_bad (_("multiple vsew constants"));
- + vsew_found = TRUE;
- + }
- + if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
- + {
- + if (*str == ',')
- + ++str;
- + if (vlmul_found)
- + as_bad (_("multiple vlmul constants"));
- + vlmul_found = TRUE;
- + }
- + if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value))
- + {
- + if (*str == ',')
- + ++str;
- + if (vta_found)
- + as_bad (_("multiple vta constants"));
- + vta_found = TRUE;
- + }
- + if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value))
- + {
- + if (*str == ',')
- + ++str;
- + if (vma_found)
- + as_bad (_("multiple vma constants"));
- + vma_found = TRUE;
- + }
- + if (arg_lookup (&str, riscv_vediv, ARRAY_SIZE (riscv_vediv), &vediv_value))
- + {
- + if (*str == ',')
- + ++str;
- + if (vediv_found)
- + as_bad (_("multiple vediv constants"));
- + vediv_found = TRUE;
- + }
- +
- + if (vsew_found || vlmul_found || vediv_found || vta_found || vma_found)
- + {
- + ep->X_op = O_constant;
- + ep->X_add_number = (vediv_value << OP_SH_VEDIV)
- + | (vsew_value << OP_SH_VSEW)
- + | (vta_value << OP_SH_VTA)
- + | (vma_value << OP_SH_VMA) ;
- + INSERT_VLMUL (ep->X_add_number, vlmul_value);
- + expr_end = str;
- + }
- + else
- + {
- + my_getExpression (ep, str);
- + str = expr_end;
- + }
- +
- + /* Report warning message if the vediv field is set, but the Zvediv
- + extension isn't enabled. */
- + if (!riscv_multi_subset_supports (INSN_CLASS_V_AND_ZVEDIV)
- + && (ep->X_add_number & (OP_MASK_VEDIV << OP_SH_VEDIV)))
- + as_warn ("vediv is set but Zvediv extension isn't enabled");
- +}
- +
- /* Parse opcode name, could be an mnemonics or number. */
- static size_t
- my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
- @@ -1811,7 +2072,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
- case '\0': /* End of args. */
- if (insn->pinfo != INSN_MACRO)
- {
- - if (!insn->match_func (insn, ip->insn_opcode))
- + if (!insn->match_func (insn, ip->insn_opcode,
- + riscv_opts.check_constraints))
- break;
-
- /* For .insn, insn->match and insn->mask are 0. */
- @@ -2502,6 +2764,154 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
- imm_expr->X_op = O_absent;
- continue;
-
- + case 'V': /* RVV */
- + switch (*++args)
- + {
- + case 'd': /* VD */
- + if (!reg_lookup (&s, RCLASS_VECR, ®no))
- + break;
- + INSERT_OPERAND (VD, *ip, regno);
- + continue;
- +
- + case 'e': /* AMO VD */
- + if (reg_lookup (&s, RCLASS_GPR, ®no) && regno == 0)
- + INSERT_OPERAND (VWD, *ip, 0);
- + else if (reg_lookup (&s, RCLASS_VECR, ®no))
- + {
- + INSERT_OPERAND (VWD, *ip, 1);
- + INSERT_OPERAND (VD, *ip, regno);
- + }
- + else
- + break;
- + continue;
- +
- + case 'f': /* AMO VS3 */
- + if (!reg_lookup (&s, RCLASS_VECR, ®no))
- + break;
- + if (!EXTRACT_OPERAND (VWD, ip->insn_opcode))
- + INSERT_OPERAND (VD, *ip, regno);
- + else
- + {
- + /* VS3 must match VD. */
- + if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno)
- + break;
- + }
- + continue;
- +
- + case 's': /* VS1 */
- + if (!reg_lookup (&s, RCLASS_VECR, ®no))
- + break;
- + INSERT_OPERAND (VS1, *ip, regno);
- + continue;
- +
- + case 't': /* VS2 */
- + if (!reg_lookup (&s, RCLASS_VECR, ®no))
- + break;
- + INSERT_OPERAND (VS2, *ip, regno);
- + continue;
- +
- + case 'u': /* VS1 == VS2 */
- + if (!reg_lookup (&s, RCLASS_VECR, ®no))
- + break;
- + INSERT_OPERAND (VS1, *ip, regno);
- + INSERT_OPERAND (VS2, *ip, regno);
- + continue;
- +
- + case 'v': /* VD == VS1 == VS2 */
- + if (!reg_lookup (&s, RCLASS_VECR, ®no))
- + break;
- + INSERT_OPERAND (VD, *ip, regno);
- + INSERT_OPERAND (VS1, *ip, regno);
- + INSERT_OPERAND (VS2, *ip, regno);
- + continue;
- +
- + case '0': /* required vector mask register without .t */
- + if (reg_lookup (&s, RCLASS_VECR, ®no) && regno == 0)
- + continue;
- + break;
- +
- + case 'c': /* vtypei for vsetvli */
- + my_getVsetvliExpression (imm_expr, s);
- + check_absolute_expr (ip, imm_expr, FALSE);
- + if (!VALID_RVV_VC_IMM (imm_expr->X_add_number))
- + as_bad (_("bad value for vsetvli immediate field, "
- + "value must be 0..2047"));
- + ip->insn_opcode
- + |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number);
- + imm_expr->X_op = O_absent;
- + s = expr_end;
- + continue;
- +
- + case 'i': /* vector arith signed immediate */
- + my_getExpression (imm_expr, s);
- + check_absolute_expr (ip, imm_expr, FALSE);
- + if (imm_expr->X_add_number > 15
- + || imm_expr->X_add_number < -16)
- + as_bad (_("bad value for vector immediate field, "
- + "value must be -16...15"));
- + INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
- + imm_expr->X_op = O_absent;
- + s = expr_end;
- + continue;
- +
- + case 'j': /* vector arith unsigned immediate */
- + my_getExpression (imm_expr, s);
- + check_absolute_expr (ip, imm_expr, FALSE);
- + if (imm_expr->X_add_number < 0
- + || imm_expr->X_add_number >= 32)
- + as_bad (_("bad value for vector immediate field, "
- + "value must be 0...31"));
- + INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
- + imm_expr->X_op = O_absent;
- + s = expr_end;
- + continue;
- +
- + case 'k': /* vector arith signed immediate, minus 1 */
- + my_getExpression (imm_expr, s);
- + check_absolute_expr (ip, imm_expr, FALSE);
- + if (imm_expr->X_add_number > 16
- + || imm_expr->X_add_number < -15)
- + as_bad (_("bad value for vector immediate field, "
- + "value must be -15...16"));
- + INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1);
- + imm_expr->X_op = O_absent;
- + s = expr_end;
- + continue;
- +
- + case 'm': /* optional vector mask */
- + if (*s == '\0')
- + {
- + INSERT_OPERAND (VMASK, *ip, 1);
- + continue;
- + }
- + else if (*s == ',' && s++
- + && reg_lookup (&s, RCLASS_VECM, ®no)
- + && regno == 0)
- + {
- + INSERT_OPERAND (VMASK, *ip, 0);
- + continue;
- + }
- + break;
- +
- + /* The following ones are only used in macros. */
- + case 'M': /* required vector mask */
- + if (reg_lookup (&s, RCLASS_VECM, ®no) && regno == 0)
- + {
- + INSERT_OPERAND (VMASK, *ip, 0);
- + continue;
- + }
- + break;
- +
- + case 'T': /* vector macro temporary register */
- + if (!reg_lookup (&s, RCLASS_VECR, ®no) || regno == 0)
- + break;
- + /* Store it in the FUNCT6 field as we don't have anyplace
- + else to store it. */
- + INSERT_OPERAND (VFUNCT6, *ip, regno);
- + continue;
- + }
- + break;
- +
- default:
- as_fatal (_("internal error: bad argument type %c"), *args);
- }
- @@ -2579,6 +2989,8 @@ enum options
- OPTION_NO_CSR_CHECK,
- OPTION_MISA_SPEC,
- OPTION_MPRIV_SPEC,
- + OPTION_CHECK_CONSTRAINTS,
- + OPTION_NO_CHECK_CONSTRAINTS,
- OPTION_END_OF_ENUM
- };
-
- @@ -2597,6 +3009,8 @@ struct option md_longopts[] =
- {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
- {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
- {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
- + {"mcheck-constraints", no_argument, NULL, OPTION_CHECK_CONSTRAINTS},
- + {"mno-check-constraints", no_argument, NULL, OPTION_NO_CHECK_CONSTRAINTS},
-
- {NULL, no_argument, NULL, 0}
- };
- @@ -2691,6 +3105,14 @@ md_parse_option (int c, const char *arg)
- case OPTION_MPRIV_SPEC:
- return riscv_set_default_priv_spec (arg);
-
- + case OPTION_CHECK_CONSTRAINTS:
- + riscv_opts.check_constraints = TRUE;
- + break;
- +
- + case OPTION_NO_CHECK_CONSTRAINTS:
- + riscv_opts.check_constraints = FALSE;
- + break;
- +
- default:
- return 0;
- }
- @@ -3117,6 +3539,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
- riscv_opts.csr_check = TRUE;
- else if (strcmp (name, "no-csr-check") == 0)
- riscv_opts.csr_check = FALSE;
- + else if (strcmp (name, "checkconstraints") == 0)
- + riscv_opts.check_constraints = TRUE;
- + else if (strcmp (name, "nocheckconstraints") == 0)
- + riscv_opts.check_constraints = FALSE;
- else if (strcmp (name, "push") == 0)
- {
- struct riscv_option_stack *s;
- diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
- index de17ad81fb..06b62fd808 100644
- --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
- +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
- @@ -1,4 +1,4 @@
- -#as: -march=rv32if -mpriv-spec=1.11
- +#as: -march=rv32ifv -mpriv-spec=1.11
- #objdump: --dwarf=frames
-
-
- @@ -250,6 +250,13 @@ Contents of the .* section:
- DW_CFA_offset_extended_sf: r4097 \(fflags\) at cfa\+4
- DW_CFA_offset_extended_sf: r4098 \(frm\) at cfa\+8
- DW_CFA_offset_extended_sf: r4099 \(fcsr\) at cfa\+12
- + DW_CFA_offset_extended_sf: r4104 \(vstart\) at cfa\+32
- + DW_CFA_offset_extended_sf: r4105 \(vxsat\) at cfa\+36
- + DW_CFA_offset_extended_sf: r4106 \(vxrm\) at cfa\+40
- + DW_CFA_offset_extended_sf: r4111 \(vcsr\) at cfa\+60
- + DW_CFA_offset_extended_sf: r7200 \(vl\) at cfa\+12416
- + DW_CFA_offset_extended_sf: r7201 \(vtype\) at cfa\+12420
- + DW_CFA_offset_extended_sf: r7202 \(vlenb\) at cfa\+12424
- DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
- DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
- DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
- diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
- index ecc8014697..399e786440 100644
- --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
- +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
- @@ -242,6 +242,13 @@ _start:
- .cfi_offset fflags, 4
- .cfi_offset frm, 8
- .cfi_offset fcsr, 12
- + .cfi_offset vstart, 32
- + .cfi_offset vxsat, 36
- + .cfi_offset vxrm, 40
- + .cfi_offset vcsr, 60
- + .cfi_offset vl, 12416
- + .cfi_offset vtype, 12420
- + .cfi_offset vlenb, 12424
- .cfi_offset dcsr, 7872
- .cfi_offset dpc, 7876
- .cfi_offset dscratch0, 7880
- diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
- index 8f0badfce1..9d417b0794 100644
- --- a/gas/testsuite/gas/riscv/insn.d
- +++ b/gas/testsuite/gas/riscv/insn.d
- @@ -1,4 +1,4 @@
- -#as: -march=rv32ifc
- +#as: -march=rv32ifcv
- #objdump: -dr
-
- .*:[ ]+file format .*
- @@ -63,3 +63,70 @@ Disassembly of section .text:
- [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
- [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
- [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+00d675af[ ]+vamoaddei64.v[ ]+zero,\(a2\),v13,v11,v0.t
- +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+08d67587[ ]+vlse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+0ad67587[ ]+vlse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+08d675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3,v0.t
- +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+0ad675a7[ ]+vsse64.v[ ]+v11,\(a2\),a3
- +[^:]+:[ ]+00067587[ ]+vle64.v[ ]+v11,\(a2\),v0.t
- +[^:]+:[ ]+03067587[ ]+vle64ff.v[ ]+v11,\(a2\)
- +[^:]+:[ ]+000675a7[ ]+vse64.v[ ]+v11,\(a2\),v0.t
- +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d605d7[ ]+vadd.vv[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d615d7[ ]+vfadd.vv[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d615d7[ ]+vfadd.vv[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d625d7[ ]+vredsum.vs[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d625d7[ ]+vredsum.vs[ ]+v11,v13,v12,v0.t
- +[^:]+:[ ]+00d645d7[ ]+vadd.vx[ ]+v11,v13,a2,v0.t
- +[^:]+:[ ]+00d645d7[ ]+vadd.vx[ ]+v11,v13,a2,v0.t
- +[^:]+:[ ]+00d655d7[ ]+vfadd.vf[ ]+v11,v13,fa2,v0.t
- +[^:]+:[ ]+00d655d7[ ]+vfadd.vf[ ]+v11,v13,fa2,v0.t
- +[^:]+:[ ]+38d665d7[ ]+vslide1up.vx[ ]+v11,v13,a2,v0.t
- +[^:]+:[ ]+3cd665d7[ ]+vslide1down.vx[ ]+v11,v13,a2,v0.t
- +[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e64,m2,tu,mu,d1
- +[^:]+:[ ]+00d675d7[ ]+vsetvli[ ]+a1,a2,e64,m2,tu,mu,d1
- +[^:]+:[ ]+00d035d7[ ]+vadd.vi[ ]+v11,v13,0,v0.t
- +[^:]+:[ ]+00d0b5d7[ ]+vadd.vi[ ]+v11,v13,1,v0.t
- +[^:]+:[ ]+00d7b5d7[ ]+vadd.vi[ ]+v11,v13,15,v0.t
- +[^:]+:[ ]+00d835d7[ ]+vadd.vi[ ]+v11,v13,-16,v0.t
- +[^:]+:[ ]+00df35d7[ ]+vadd.vi[ ]+v11,v13,-2,v0.t
- +[^:]+:[ ]+00dfb5d7[ ]+vadd.vi[ ]+v11,v13,-1,v0.t
- diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
- index 6c08f49d43..b7cd92e96d 100644
- --- a/gas/testsuite/gas/riscv/insn.s
- +++ b/gas/testsuite/gas/riscv/insn.s
- @@ -47,3 +47,87 @@ target:
- .insn r 0x33, 0, 0, fa0, a1, fa2
- .insn r 0x33, 0, 0, a0, fa1, fa2
- .insn r 0x33, 0, 0, fa0, fa1, fa2
- +
- +# vamo
- +# F3: width[14:12]
- +# F7: amoop[31:27] + wd[26] + vm[25]
- +
- + .insn r AMO, 0x7, 0x0, v11, a2, a3
- + .insn r AMO, 0x7, 0x0, v11, fa2, a3
- + .insn r AMO, 0x7, 0x0, v11, a2, fa3
- + .insn r AMO, 0x7, 0x0, v11, fa2, fa3
- + .insn r AMO, 0x7, 0x0, a1, v12, a3
- + .insn r AMO, 0x7, 0x0, fa1, v12, a3
- + .insn r AMO, 0x7, 0x0, a1, v12, fa3
- + .insn r AMO, 0x7, 0x0, fa1, v12, fa3
- + .insn r AMO, 0x7, 0x0, a1, a2, v13
- + .insn r AMO, 0x7, 0x0, fa1, a2, v13
- + .insn r 0x2f, 0x7, 0x0, a1, fa2, v13
- + .insn r 0x2f, 0x7, 0x0, fa1, fa2, v13
- + .insn r 0x2f, 0x7, 0x0, a1, v12, v13
- + .insn r 0x2f, 0x7, 0x0, fa1, v12, v13
- + .insn r 0x2f, 0x7, 0x0, v11, a2, v13
- + .insn r 0x2f, 0x7, 0x0, v11, fa2, v13
- + .insn r 0x2f, 0x7, 0x0, v11, v12, a3
- + .insn r 0x2f, 0x7, 0x0, v11, v12, fa3
- + .insn r 0x2f, 0x7, 0x0, v11, v12, v13
- +
- +# vmem
- +# F3: width[14:12]
- +# F7: nf[31:29] + mop[28:26] + vm[25]
- +
- + .insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
- + .insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
- + .insn r LOAD_FP, 0x7, 0x4, v11, fa2, a3
- + .insn r LOAD_FP, 0x7, 0x4, v11, a2, fa3
- + .insn r LOAD_FP, 0x7, 0x4, v11, fa2, fa3
- + .insn r 0x7, 0x7, 0x5, a1, v12, a3
- + .insn r 0x7, 0x7, 0x5, fa1, v12, a3
- + .insn r 0x7, 0x7, 0x5, a1, v12, fa3
- + .insn r 0x7, 0x7, 0x5, fa1, v12, fa3
- + .insn r 0x7, 0x7, 0x5, a1, a2, v13
- + .insn r STORE_FP, 0x7, 0x4, fa1, a2, v13
- + .insn r STORE_FP, 0x7, 0x4, a1, fa2, v13
- + .insn r STORE_FP, 0x7, 0x4, fa1, fa2, v13
- + .insn r STORE_FP, 0x7, 0x4, a1, v12, v13
- + .insn r STORE_FP, 0x7, 0x4, fa1, v12, v13
- + .insn r 0x27, 0x7, 0x5, v11, a2, v13
- + .insn r 0x27, 0x7, 0x5, v11, fa2, v13
- + .insn r 0x27, 0x7, 0x5, v11, v12, a3
- + .insn r 0x27, 0x7, 0x5, v11, v12, fa3
- + .insn r 0x27, 0x7, 0x5, v11, v12, v13
- + # unit-stride
- + .insn r LOAD_FP, 0x7, 0x0, v11, a2, x0
- + .insn r LOAD_FP, 0x7, 0x1, v11, a2, x16
- + .insn r STORE_FP, 0x7, 0x0, v11, a2, x0
- +
- +# valu and vcfg
- +# F3: funct3[14:12]
- +# F7: F6[31:26] + vm[25]
- +
- + .insn r 0x57, 0x0, 0x0, v11, a2, a3
- + .insn r 0x57, 0x0, 0x0, v11, fa2, a3
- + .insn r 0x57, 0x0, 0x0, v11, a2, fa3
- + .insn r 0x57, 0x0, 0x0, v11, fa2, fa3
- + .insn r 0x57, 0x0, 0x0, a1, v12, a3
- + .insn r 0x57, 0x0, 0x0, fa1, v12, a3
- + .insn r 0x57, 0x0, 0x0, a1, v12, fa3
- + .insn r 0x57, 0x1, 0x0, fa1, v12, fa3
- + .insn r 0x57, 0x1, 0x0, a1, a2, v13
- + .insn r 0x57, 0x2, 0x0, fa1, a2, v13
- + .insn r 0x57, 0x2, 0x0, a1, fa2, v13
- + .insn r 0x57, 0x4, 0x0, fa1, fa2, v13
- + .insn r 0x57, 0x4, 0x0, a1, v12, v13
- + .insn r 0x57, 0x5, 0x0, fa1, v12, v13
- + .insn r 0x57, 0x5, 0x0, v11, a2, v13
- + .insn r 0x57, 0x6, 0x1c, v11, fa2, v13
- + .insn r 0x57, 0x6, 0x1e, v11, v12, a3
- + .insn r 0x57, 0x7, 0x0, v11, v12, fa3
- + .insn r 0x57, 0x7, 0x0, v11, v12, v13
- + # OPIVI
- + .insn r 0x57, 0x3, 0x0, v11, x0, a3
- + .insn r 0x57, 0x3, 0x0, v11, x1, a3
- + .insn r 0x57, 0x3, 0x0, v11, x15, a3
- + .insn r 0x57, 0x3, 0x0, v11, x16, a3
- + .insn r 0x57, 0x3, 0x0, v11, x30, a3
- + .insn r 0x57, 0x3, 0x0, v11, x31, a3
- diff --git a/gas/testsuite/gas/riscv/march-fail-s-with-version b/gas/testsuite/gas/riscv/march-fail-s-with-version
- new file mode 100644
- index 0000000000..a514d4aec7
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/march-fail-s-with-version
- @@ -0,0 +1,2 @@
- +Assembler messages:
- +.*: Invalid or unknown s ISA extension: 'sfoo'
- \ No newline at end of file
- diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
- index 07cf05a9c2..4fa2b18911 100644
- --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
- +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
- @@ -1,4 +1,4 @@
- -#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr
- +#as: -march=rv32ifv -mcsr-check -mpriv-spec=1.10 -march-attr
- #source: priv-reg.s
- #warning_output: priv-reg-fail-version-1p10.l
- #readelf: -A
- diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
- index bf4b1db3ed..852ce8bf64 100644
- --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
- +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
- @@ -1,4 +1,4 @@
- -#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr
- +#as: -march=rv32ifv -mcsr-check -mpriv-spec=1.11 -march-attr
- #source: priv-reg.s
- #warning_output: priv-reg-fail-version-1p11.l
- #readelf: -A
- diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
- index e2c33d81dc..e6f9fc9500 100644
- --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
- +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
- @@ -1,4 +1,4 @@
- -#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr
- +#as: -march=rv32ifv -mcsr-check -mpriv-spec=1.9.1 -march-attr
- #source: priv-reg.s
- #warning_output: priv-reg-fail-version-1p9p1.l
- #readelf: -A
- diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-vext.d b/gas/testsuite/gas/riscv/priv-reg-fail-vext.d
- new file mode 100644
- index 0000000000..13e731c2e7
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/priv-reg-fail-vext.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32if -mcsr-check
- +#source: priv-reg.s
- +#warning_output: priv-reg-fail-vext.l
- diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-vext.l b/gas/testsuite/gas/riscv/priv-reg-fail-vext.l
- new file mode 100644
- index 0000000000..1243fc7c12
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/priv-reg-fail-vext.l
- @@ -0,0 +1,9 @@
- +.*Assembler messages:
- +#...
- +.*Warning: Invalid CSR `vstart' for the current ISA
- +.*Warning: Invalid CSR `vxsat' for the current ISA
- +.*Warning: Invalid CSR `vxrm' for the current ISA
- +.*Warning: Invalid CSR `vcsr' for the current ISA
- +.*Warning: Invalid CSR `vl' for the current ISA
- +.*Warning: Invalid CSR `vtype' for the current ISA
- +#...
- diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
- index 3ad8eebe85..0a023ea5a2 100644
- --- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
- +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
- @@ -1,4 +1,4 @@
- -#as: -march=rv32if -mpriv-spec=1.10
- +#as: -march=rv32ifv -mpriv-spec=1.10
- #source: priv-reg.s
- #objdump: -dr -Mpriv-spec=1.10
-
- @@ -246,6 +246,13 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
- [ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
- [ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
- +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
- +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
- +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
- +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
- +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
- +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
- +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
- [ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
- [ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
- [ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
- diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
- index 5824bc5e1f..5956b0d9fd 100644
- --- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
- +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
- @@ -1,4 +1,4 @@
- -#as: -march=rv32if -mpriv-spec=1.11
- +#as: -march=rv32ifv -mpriv-spec=1.11
- #source: priv-reg.s
- #objdump: -dr -Mpriv-spec=1.11
-
- @@ -246,6 +246,13 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
- [ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
- [ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
- +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
- +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
- +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
- +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
- +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
- +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
- +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
- [ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
- [ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
- [ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
- diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
- index 569b9587e2..3fea56d947 100644
- --- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
- +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
- @@ -1,4 +1,4 @@
- -#as: -march=rv32if -mpriv-spec=1.9.1
- +#as: -march=rv32ifv -mpriv-spec=1.9.1
- #source: priv-reg.s
- #objdump: -dr -Mpriv-spec=1.9.1
-
- @@ -246,6 +246,13 @@ Disassembly of section .text:
- [ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
- [ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
- [ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
- +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
- +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
- +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
- +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
- +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
- +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
- +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
- [ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
- [ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
- [ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
- diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
- index c40d28862b..8f625054c1 100644
- --- a/gas/testsuite/gas/riscv/priv-reg.s
- +++ b/gas/testsuite/gas/riscv/priv-reg.s
- @@ -260,6 +260,15 @@
- csr frm
- csr fcsr
-
- + # Vector
- + csr vstart
- + csr vxsat
- + csr vxrm
- + csr vcsr
- + csr vl
- + csr vtype
- + csr vlenb
- +
- # Core debug
- csr dcsr
- csr dpc
- diff --git a/gas/testsuite/gas/riscv/v-zero-imm.d b/gas/testsuite/gas/riscv/v-zero-imm.d
- new file mode 100644
- index 0000000000..f6fe2ffaa8
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/v-zero-imm.d
- @@ -0,0 +1,17 @@
- +#as: -march=rv32ifv
- +#objdump: -dr
- +
- +.*:[ ]+file format .*
- +
- +
- +Disassembly of section .text:
- +
- +0+000 <.text>:
- +[ ]+[0-9a-f]+:[ ]+768fb257[ ]+vmsle.vi[ ]+v4,v8,-1
- +[ ]+[0-9a-f]+:[ ]+748fb257[ ]+vmsle.vi[ ]+v4,v8,-1,v0.t
- +[ ]+[0-9a-f]+:[ ]+66840257[ ]+vmsne.vv[ ]+v4,v8,v8
- +[ ]+[0-9a-f]+:[ ]+64840257[ ]+vmsne.vv[ ]+v4,v8,v8,v0.t
- +[ ]+[0-9a-f]+:[ ]+7e8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1
- +[ ]+[0-9a-f]+:[ ]+7c8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1,v0.t
- +[ ]+[0-9a-f]+:[ ]+62840257[ ]+vmseq.vv[ ]+v4,v8,v8
- +[ ]+[0-9a-f]+:[ ]+60840257[ ]+vmseq.vv[ ]+v4,v8,v8,v0.t
- diff --git a/gas/testsuite/gas/riscv/v-zero-imm.s b/gas/testsuite/gas/riscv/v-zero-imm.s
- new file mode 100644
- index 0000000000..98b7063880
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/v-zero-imm.s
- @@ -0,0 +1,8 @@
- + vmslt.vi v4, v8, 0
- + vmslt.vi v4, v8, 0, v0.t
- + vmsltu.vi v4, v8, 0
- + vmsltu.vi v4, v8, 0, v0.t
- + vmsge.vi v4, v8, 0
- + vmsge.vi v4, v8, 0, v0.t
- + vmsgeu.vi v4, v8, 0
- + vmsgeu.vi v4, v8, 0, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.d b/gas/testsuite/gas/riscv/vector-insns-fail-01.d
- new file mode 100644
- index 0000000000..ade7888937
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-01.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv -mcheck-constraints
- +#source: vector-insns-fail-01.s
- +#error_output: vector-insns-fail-01.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.l b/gas/testsuite/gas/riscv/vector-insns-fail-01.l
- new file mode 100644
- index 0000000000..61687938c9
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-01.l
- @@ -0,0 +1,393 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlxseg2ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg2ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg3ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg3ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg4ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg4ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg5ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg5ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg6ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg6ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg7ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg7ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg8ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg8ei8.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg2ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg2ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg3ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg3ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg4ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg4ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg5ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg5ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg6ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg6ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg7ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg7ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg8ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg8ei16.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg2ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg2ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg3ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg3ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg4ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg4ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg5ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg5ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg6ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg6ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg7ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg7ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg8ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg8ei32.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg2ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg2ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg3ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg3ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg4ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg4ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg5ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg5ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg6ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg6ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg7ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg7ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg8ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg8ei64.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg2ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg2ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg3ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg3ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg4ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg4ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg5ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg5ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg6ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg6ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg7ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg7ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg8ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg8ei128.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg2ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg2ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg3ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg3ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg4ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg4ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg5ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg5ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg6ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg6ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg7ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg7ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg8ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg8ei256.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg2ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg2ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg3ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg3ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg4ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg4ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg5ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg5ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg6ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg6ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg7ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg7ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg8ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg8ei512.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg2ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg2ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg3ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg3ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg4ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg4ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg5ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg5ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg6ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg6ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg7ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg7ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vlxseg8ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v2,v0.t'
- +.*Error: illegal operands `vsxseg8ei1024.v v2,\(a0\),v2'
- +.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v2,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.s b/gas/testsuite/gas/riscv/vector-insns-fail-01.s
- new file mode 100644
- index 0000000000..4c1a913f2d
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-01.s
- @@ -0,0 +1,1037 @@
- +# Vector Unit-Stride Segment Loads and Stores
- +
- + vlseg2e8.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e8.v v4, (a0), v0.t # OK
- + vsseg2e8.v v0, (a0), v0.t # OK
- + vsseg2e8.v v4, (a0), v0.t # OK
- + vlseg2e8ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e8ff.v v4, (a0), v0.t # OK
- + vlseg3e8.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e8.v v4, (a0), v0.t # OK
- + vsseg3e8.v v0, (a0), v0.t # OK
- + vsseg3e8.v v4, (a0), v0.t # OK
- + vlseg3e8ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e8ff.v v4, (a0), v0.t # OK
- + vlseg4e8.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e8.v v4, (a0), v0.t # OK
- + vsseg4e8.v v0, (a0), v0.t # OK
- + vsseg4e8.v v4, (a0), v0.t # OK
- + vlseg4e8ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e8ff.v v4, (a0), v0.t # OK
- + vlseg5e8.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e8.v v4, (a0), v0.t # OK
- + vsseg5e8.v v0, (a0), v0.t # OK
- + vsseg5e8.v v4, (a0), v0.t # OK
- + vlseg5e8ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e8ff.v v4, (a0), v0.t # OK
- + vlseg6e8.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e8.v v4, (a0), v0.t # OK
- + vsseg6e8.v v0, (a0), v0.t # OK
- + vsseg6e8.v v4, (a0), v0.t # OK
- + vlseg6e8ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e8ff.v v4, (a0), v0.t # OK
- + vlseg7e8.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e8.v v4, (a0), v0.t # OK
- + vsseg7e8.v v0, (a0), v0.t # OK
- + vsseg7e8.v v4, (a0), v0.t # OK
- + vlseg7e8ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e8ff.v v4, (a0), v0.t # OK
- + vlseg8e8.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e8.v v4, (a0), v0.t # OK
- + vsseg8e8.v v0, (a0), v0.t # OK
- + vsseg8e8.v v4, (a0), v0.t # OK
- + vlseg8e8ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e8ff.v v4, (a0), v0.t # OK
- +
- + vlseg2e16.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e16.v v4, (a0), v0.t # OK
- + vsseg2e16.v v0, (a0), v0.t # OK
- + vsseg2e16.v v4, (a0), v0.t # OK
- + vlseg2e16ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e16ff.v v4, (a0), v0.t # OK
- + vlseg3e16.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e16.v v4, (a0), v0.t # OK
- + vsseg3e16.v v0, (a0), v0.t # OK
- + vsseg3e16.v v4, (a0), v0.t # OK
- + vlseg3e16ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e16ff.v v4, (a0), v0.t # OK
- + vlseg4e16.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e16.v v4, (a0), v0.t # OK
- + vsseg4e16.v v0, (a0), v0.t # OK
- + vsseg4e16.v v4, (a0), v0.t # OK
- + vlseg4e16ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e16ff.v v4, (a0), v0.t # OK
- + vlseg5e16.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e16.v v4, (a0), v0.t # OK
- + vsseg5e16.v v0, (a0), v0.t # OK
- + vsseg5e16.v v4, (a0), v0.t # OK
- + vlseg5e16ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e16ff.v v4, (a0), v0.t # OK
- + vlseg6e16.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e16.v v4, (a0), v0.t # OK
- + vsseg6e16.v v0, (a0), v0.t # OK
- + vsseg6e16.v v4, (a0), v0.t # OK
- + vlseg6e16ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e16ff.v v4, (a0), v0.t # OK
- + vlseg7e16.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e16.v v4, (a0), v0.t # OK
- + vsseg7e16.v v0, (a0), v0.t # OK
- + vsseg7e16.v v4, (a0), v0.t # OK
- + vlseg7e16ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e16ff.v v4, (a0), v0.t # OK
- + vlseg8e16.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e16.v v4, (a0), v0.t # OK
- + vsseg8e16.v v0, (a0), v0.t # OK
- + vsseg8e16.v v4, (a0), v0.t # OK
- + vlseg8e16ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e16ff.v v4, (a0), v0.t # OK
- +
- + vlseg2e32.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e32.v v4, (a0), v0.t # OK
- + vsseg2e32.v v0, (a0), v0.t # OK
- + vsseg2e32.v v4, (a0), v0.t # OK
- + vlseg2e32ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e32ff.v v4, (a0), v0.t # OK
- + vlseg3e32.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e32.v v4, (a0), v0.t # OK
- + vsseg3e32.v v0, (a0), v0.t # OK
- + vsseg3e32.v v4, (a0), v0.t # OK
- + vlseg3e32ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e32ff.v v4, (a0), v0.t # OK
- + vlseg4e32.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e32.v v4, (a0), v0.t # OK
- + vsseg4e32.v v0, (a0), v0.t # OK
- + vsseg4e32.v v4, (a0), v0.t # OK
- + vlseg4e32ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e32ff.v v4, (a0), v0.t # OK
- + vlseg5e32.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e32.v v4, (a0), v0.t # OK
- + vsseg5e32.v v0, (a0), v0.t # OK
- + vsseg5e32.v v4, (a0), v0.t # OK
- + vlseg5e32ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e32ff.v v4, (a0), v0.t # OK
- + vlseg6e32.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e32.v v4, (a0), v0.t # OK
- + vsseg6e32.v v0, (a0), v0.t # OK
- + vsseg6e32.v v4, (a0), v0.t # OK
- + vlseg6e32ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e32ff.v v4, (a0), v0.t # OK
- + vlseg7e32.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e32.v v4, (a0), v0.t # OK
- + vsseg7e32.v v0, (a0), v0.t # OK
- + vsseg7e32.v v4, (a0), v0.t # OK
- + vlseg7e32ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e32ff.v v4, (a0), v0.t # OK
- + vlseg8e32.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e32.v v4, (a0), v0.t # OK
- + vsseg8e32.v v0, (a0), v0.t # OK
- + vsseg8e32.v v4, (a0), v0.t # OK
- + vlseg8e32ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e32ff.v v4, (a0), v0.t # OK
- +
- + vlseg2e64.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e64.v v4, (a0), v0.t # OK
- + vsseg2e64.v v0, (a0), v0.t # OK
- + vsseg2e64.v v4, (a0), v0.t # OK
- + vlseg2e64ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e64ff.v v4, (a0), v0.t # OK
- + vlseg3e64.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e64.v v4, (a0), v0.t # OK
- + vsseg3e64.v v0, (a0), v0.t # OK
- + vsseg3e64.v v4, (a0), v0.t # OK
- + vlseg3e64ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e64ff.v v4, (a0), v0.t # OK
- + vlseg4e64.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e64.v v4, (a0), v0.t # OK
- + vsseg4e64.v v0, (a0), v0.t # OK
- + vsseg4e64.v v4, (a0), v0.t # OK
- + vlseg4e64ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e64ff.v v4, (a0), v0.t # OK
- + vlseg5e64.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e64.v v4, (a0), v0.t # OK
- + vsseg5e64.v v0, (a0), v0.t # OK
- + vsseg5e64.v v4, (a0), v0.t # OK
- + vlseg5e64ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e64ff.v v4, (a0), v0.t # OK
- + vlseg6e64.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e64.v v4, (a0), v0.t # OK
- + vsseg6e64.v v0, (a0), v0.t # OK
- + vsseg6e64.v v4, (a0), v0.t # OK
- + vlseg6e64ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e64ff.v v4, (a0), v0.t # OK
- + vlseg7e64.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e64.v v4, (a0), v0.t # OK
- + vsseg7e64.v v0, (a0), v0.t # OK
- + vsseg7e64.v v4, (a0), v0.t # OK
- + vlseg7e64ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e64ff.v v4, (a0), v0.t # OK
- + vlseg8e64.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e64.v v4, (a0), v0.t # OK
- + vsseg8e64.v v0, (a0), v0.t # OK
- + vsseg8e64.v v4, (a0), v0.t # OK
- + vlseg8e64ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e64ff.v v4, (a0), v0.t # OK
- +
- + vlseg2e128.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e128.v v4, (a0), v0.t # OK
- + vsseg2e128.v v0, (a0), v0.t # OK
- + vsseg2e128.v v4, (a0), v0.t # OK
- + vlseg2e128ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e128ff.v v4, (a0), v0.t # OK
- + vlseg3e128.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e128.v v4, (a0), v0.t # OK
- + vsseg3e128.v v0, (a0), v0.t # OK
- + vsseg3e128.v v4, (a0), v0.t # OK
- + vlseg3e128ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e128ff.v v4, (a0), v0.t # OK
- + vlseg4e128.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e128.v v4, (a0), v0.t # OK
- + vsseg4e128.v v0, (a0), v0.t # OK
- + vsseg4e128.v v4, (a0), v0.t # OK
- + vlseg4e128ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e128ff.v v4, (a0), v0.t # OK
- + vlseg5e128.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e128.v v4, (a0), v0.t # OK
- + vsseg5e128.v v0, (a0), v0.t # OK
- + vsseg5e128.v v4, (a0), v0.t # OK
- + vlseg5e128ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e128ff.v v4, (a0), v0.t # OK
- + vlseg6e128.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e128.v v4, (a0), v0.t # OK
- + vsseg6e128.v v0, (a0), v0.t # OK
- + vsseg6e128.v v4, (a0), v0.t # OK
- + vlseg6e128ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e128ff.v v4, (a0), v0.t # OK
- + vlseg7e128.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e128.v v4, (a0), v0.t # OK
- + vsseg7e128.v v0, (a0), v0.t # OK
- + vsseg7e128.v v4, (a0), v0.t # OK
- + vlseg7e128ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e128ff.v v4, (a0), v0.t # OK
- + vlseg8e128.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e128.v v4, (a0), v0.t # OK
- + vsseg8e128.v v0, (a0), v0.t # OK
- + vsseg8e128.v v4, (a0), v0.t # OK
- + vlseg8e128ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e128ff.v v4, (a0), v0.t # OK
- +
- + vlseg2e256.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e256.v v4, (a0), v0.t # OK
- + vsseg2e256.v v0, (a0), v0.t # OK
- + vsseg2e256.v v4, (a0), v0.t # OK
- + vlseg2e256ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e256ff.v v4, (a0), v0.t # OK
- + vlseg3e256.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e256.v v4, (a0), v0.t # OK
- + vsseg3e256.v v0, (a0), v0.t # OK
- + vsseg3e256.v v4, (a0), v0.t # OK
- + vlseg3e256ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e256ff.v v4, (a0), v0.t # OK
- + vlseg4e256.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e256.v v4, (a0), v0.t # OK
- + vsseg4e256.v v0, (a0), v0.t # OK
- + vsseg4e256.v v4, (a0), v0.t # OK
- + vlseg4e256ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e256ff.v v4, (a0), v0.t # OK
- + vlseg5e256.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e256.v v4, (a0), v0.t # OK
- + vsseg5e256.v v0, (a0), v0.t # OK
- + vsseg5e256.v v4, (a0), v0.t # OK
- + vlseg5e256ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e256ff.v v4, (a0), v0.t # OK
- + vlseg6e256.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e256.v v4, (a0), v0.t # OK
- + vsseg6e256.v v0, (a0), v0.t # OK
- + vsseg6e256.v v4, (a0), v0.t # OK
- + vlseg6e256ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e256ff.v v4, (a0), v0.t # OK
- + vlseg7e256.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e256.v v4, (a0), v0.t # OK
- + vsseg7e256.v v0, (a0), v0.t # OK
- + vsseg7e256.v v4, (a0), v0.t # OK
- + vlseg7e256ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e256ff.v v4, (a0), v0.t # OK
- + vlseg8e256.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e256.v v4, (a0), v0.t # OK
- + vsseg8e256.v v0, (a0), v0.t # OK
- + vsseg8e256.v v4, (a0), v0.t # OK
- + vlseg8e256ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e256ff.v v4, (a0), v0.t # OK
- +
- + vlseg2e512.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e512.v v4, (a0), v0.t # OK
- + vsseg2e512.v v0, (a0), v0.t # OK
- + vsseg2e512.v v4, (a0), v0.t # OK
- + vlseg2e512ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e512ff.v v4, (a0), v0.t # OK
- + vlseg3e512.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e512.v v4, (a0), v0.t # OK
- + vsseg3e512.v v0, (a0), v0.t # OK
- + vsseg3e512.v v4, (a0), v0.t # OK
- + vlseg3e512ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e512ff.v v4, (a0), v0.t # OK
- + vlseg4e512.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e512.v v4, (a0), v0.t # OK
- + vsseg4e512.v v0, (a0), v0.t # OK
- + vsseg4e512.v v4, (a0), v0.t # OK
- + vlseg4e512ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e512ff.v v4, (a0), v0.t # OK
- + vlseg5e512.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e512.v v4, (a0), v0.t # OK
- + vsseg5e512.v v0, (a0), v0.t # OK
- + vsseg5e512.v v4, (a0), v0.t # OK
- + vlseg5e512ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e512ff.v v4, (a0), v0.t # OK
- + vlseg6e512.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e512.v v4, (a0), v0.t # OK
- + vsseg6e512.v v0, (a0), v0.t # OK
- + vsseg6e512.v v4, (a0), v0.t # OK
- + vlseg6e512ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e512ff.v v4, (a0), v0.t # OK
- + vlseg7e512.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e512.v v4, (a0), v0.t # OK
- + vsseg7e512.v v0, (a0), v0.t # OK
- + vsseg7e512.v v4, (a0), v0.t # OK
- + vlseg7e512ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e512ff.v v4, (a0), v0.t # OK
- + vlseg8e512.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e512.v v4, (a0), v0.t # OK
- + vsseg8e512.v v0, (a0), v0.t # OK
- + vsseg8e512.v v4, (a0), v0.t # OK
- + vlseg8e512ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e512ff.v v4, (a0), v0.t # OK
- +
- + vlseg2e1024.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e1024.v v4, (a0), v0.t # OK
- + vsseg2e1024.v v0, (a0), v0.t # OK
- + vsseg2e1024.v v4, (a0), v0.t # OK
- + vlseg2e1024ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e1024ff.v v4, (a0), v0.t # OK
- + vlseg3e1024.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e1024.v v4, (a0), v0.t # OK
- + vsseg3e1024.v v0, (a0), v0.t # OK
- + vsseg3e1024.v v4, (a0), v0.t # OK
- + vlseg3e1024ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e1024ff.v v4, (a0), v0.t # OK
- + vlseg4e1024.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e1024.v v4, (a0), v0.t # OK
- + vsseg4e1024.v v0, (a0), v0.t # OK
- + vsseg4e1024.v v4, (a0), v0.t # OK
- + vlseg4e1024ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg4e1024ff.v v4, (a0), v0.t # OK
- + vlseg5e1024.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e1024.v v4, (a0), v0.t # OK
- + vsseg5e1024.v v0, (a0), v0.t # OK
- + vsseg5e1024.v v4, (a0), v0.t # OK
- + vlseg5e1024ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg5e1024ff.v v4, (a0), v0.t # OK
- + vlseg6e1024.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e1024.v v4, (a0), v0.t # OK
- + vsseg6e1024.v v0, (a0), v0.t # OK
- + vsseg6e1024.v v4, (a0), v0.t # OK
- + vlseg6e1024ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg6e1024ff.v v4, (a0), v0.t # OK
- + vlseg7e1024.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e1024.v v4, (a0), v0.t # OK
- + vsseg7e1024.v v0, (a0), v0.t # OK
- + vsseg7e1024.v v4, (a0), v0.t # OK
- + vlseg7e1024ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg7e1024ff.v v4, (a0), v0.t # OK
- + vlseg8e1024.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e1024.v v4, (a0), v0.t # OK
- + vsseg8e1024.v v0, (a0), v0.t # OK
- + vsseg8e1024.v v4, (a0), v0.t # OK
- + vlseg8e1024ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg8e1024ff.v v4, (a0), v0.t # OK
- +
- +# Vector Strided Segment Loads and Stores
- +
- + vlsseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg2e8.v v4, (a0), a1, v0.t # OK
- + vssseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg2e8.v v4, (a0), a1, v0.t # OK
- + vlsseg3e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg3e8.v v4, (a0), a1, v0.t # OK
- + vssseg3e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg3e8.v v4, (a0), a1, v0.t # OK
- + vlsseg4e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg4e8.v v4, (a0), a1, v0.t # OK
- + vssseg4e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg4e8.v v4, (a0), a1, v0.t # OK
- + vlsseg5e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg5e8.v v4, (a0), a1, v0.t # OK
- + vssseg5e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg5e8.v v4, (a0), a1, v0.t # OK
- + vlsseg6e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg6e8.v v4, (a0), a1, v0.t # OK
- + vssseg6e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg6e8.v v4, (a0), a1, v0.t # OK
- + vlsseg7e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg7e8.v v4, (a0), a1, v0.t # OK
- + vssseg7e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg7e8.v v4, (a0), a1, v0.t # OK
- + vlsseg8e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg8e8.v v4, (a0), a1, v0.t # OK
- + vssseg8e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg8e8.v v4, (a0), a1, v0.t # OK
- +
- + vlsseg2e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg2e16.v v4, (a0), a1, v0.t # OK
- + vssseg2e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg2e16.v v4, (a0), a1, v0.t # OK
- + vlsseg3e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg3e16.v v4, (a0), a1, v0.t # OK
- + vssseg3e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg3e16.v v4, (a0), a1, v0.t # OK
- + vlsseg4e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg4e16.v v4, (a0), a1, v0.t # OK
- + vssseg4e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg4e16.v v4, (a0), a1, v0.t # OK
- + vlsseg5e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg5e16.v v4, (a0), a1, v0.t # OK
- + vssseg5e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg5e16.v v4, (a0), a1, v0.t # OK
- + vlsseg6e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg6e16.v v4, (a0), a1, v0.t # OK
- + vssseg6e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg6e16.v v4, (a0), a1, v0.t # OK
- + vlsseg7e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg7e16.v v4, (a0), a1, v0.t # OK
- + vssseg7e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg7e16.v v4, (a0), a1, v0.t # OK
- + vlsseg8e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg8e16.v v4, (a0), a1, v0.t # OK
- + vssseg8e16.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg8e16.v v4, (a0), a1, v0.t # OK
- +
- + vlsseg2e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg2e32.v v4, (a0), a1, v0.t # OK
- + vssseg2e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg2e32.v v4, (a0), a1, v0.t # OK
- + vlsseg3e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg3e32.v v4, (a0), a1, v0.t # OK
- + vssseg3e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg3e32.v v4, (a0), a1, v0.t # OK
- + vlsseg4e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg4e32.v v4, (a0), a1, v0.t # OK
- + vssseg4e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg4e32.v v4, (a0), a1, v0.t # OK
- + vlsseg5e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg5e32.v v4, (a0), a1, v0.t # OK
- + vssseg5e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg5e32.v v4, (a0), a1, v0.t # OK
- + vlsseg6e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg6e32.v v4, (a0), a1, v0.t # OK
- + vssseg6e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg6e32.v v4, (a0), a1, v0.t # OK
- + vlsseg7e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg7e32.v v4, (a0), a1, v0.t # OK
- + vssseg7e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg7e32.v v4, (a0), a1, v0.t # OK
- + vlsseg8e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg8e32.v v4, (a0), a1, v0.t # OK
- + vssseg8e32.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg8e32.v v4, (a0), a1, v0.t # OK
- +
- + vlsseg2e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg2e64.v v4, (a0), a1, v0.t # OK
- + vssseg2e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg2e64.v v4, (a0), a1, v0.t # OK
- + vlsseg3e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg3e64.v v4, (a0), a1, v0.t # OK
- + vssseg3e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg3e64.v v4, (a0), a1, v0.t # OK
- + vlsseg4e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg4e64.v v4, (a0), a1, v0.t # OK
- + vssseg4e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg4e64.v v4, (a0), a1, v0.t # OK
- + vlsseg5e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg5e64.v v4, (a0), a1, v0.t # OK
- + vssseg5e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg5e64.v v4, (a0), a1, v0.t # OK
- + vlsseg6e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg6e64.v v4, (a0), a1, v0.t # OK
- + vssseg6e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg6e64.v v4, (a0), a1, v0.t # OK
- + vlsseg7e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg7e64.v v4, (a0), a1, v0.t # OK
- + vssseg7e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg7e64.v v4, (a0), a1, v0.t # OK
- + vlsseg8e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg8e64.v v4, (a0), a1, v0.t # OK
- + vssseg8e64.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg8e64.v v4, (a0), a1, v0.t # OK
- +
- + vlsseg2e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg2e128.v v4, (a0), a1, v0.t # OK
- + vssseg2e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg2e128.v v4, (a0), a1, v0.t # OK
- + vlsseg3e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg3e128.v v4, (a0), a1, v0.t # OK
- + vssseg3e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg3e128.v v4, (a0), a1, v0.t # OK
- + vlsseg4e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg4e128.v v4, (a0), a1, v0.t # OK
- + vssseg4e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg4e128.v v4, (a0), a1, v0.t # OK
- + vlsseg5e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg5e128.v v4, (a0), a1, v0.t # OK
- + vssseg5e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg5e128.v v4, (a0), a1, v0.t # OK
- + vlsseg6e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg6e128.v v4, (a0), a1, v0.t # OK
- + vssseg6e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg6e128.v v4, (a0), a1, v0.t # OK
- + vlsseg7e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg7e128.v v4, (a0), a1, v0.t # OK
- + vssseg7e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg7e128.v v4, (a0), a1, v0.t # OK
- + vlsseg8e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg8e128.v v4, (a0), a1, v0.t # OK
- + vssseg8e128.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg8e128.v v4, (a0), a1, v0.t # OK
- +
- + vlsseg2e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg2e256.v v4, (a0), a1, v0.t # OK
- + vssseg2e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg2e256.v v4, (a0), a1, v0.t # OK
- + vlsseg3e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg3e256.v v4, (a0), a1, v0.t # OK
- + vssseg3e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg3e256.v v4, (a0), a1, v0.t # OK
- + vlsseg4e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg4e256.v v4, (a0), a1, v0.t # OK
- + vssseg4e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg4e256.v v4, (a0), a1, v0.t # OK
- + vlsseg5e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg5e256.v v4, (a0), a1, v0.t # OK
- + vssseg5e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg5e256.v v4, (a0), a1, v0.t # OK
- + vlsseg6e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg6e256.v v4, (a0), a1, v0.t # OK
- + vssseg6e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg6e256.v v4, (a0), a1, v0.t # OK
- + vlsseg7e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg7e256.v v4, (a0), a1, v0.t # OK
- + vssseg7e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg7e256.v v4, (a0), a1, v0.t # OK
- + vlsseg8e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg8e256.v v4, (a0), a1, v0.t # OK
- + vssseg8e256.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg8e256.v v4, (a0), a1, v0.t # OK
- +
- + vlsseg2e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg2e512.v v4, (a0), a1, v0.t # OK
- + vssseg2e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg2e512.v v4, (a0), a1, v0.t # OK
- + vlsseg3e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg3e512.v v4, (a0), a1, v0.t # OK
- + vssseg3e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg3e512.v v4, (a0), a1, v0.t # OK
- + vlsseg4e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg4e512.v v4, (a0), a1, v0.t # OK
- + vssseg4e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg4e512.v v4, (a0), a1, v0.t # OK
- + vlsseg5e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg5e512.v v4, (a0), a1, v0.t # OK
- + vssseg5e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg5e512.v v4, (a0), a1, v0.t # OK
- + vlsseg6e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg6e512.v v4, (a0), a1, v0.t # OK
- + vssseg6e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg6e512.v v4, (a0), a1, v0.t # OK
- + vlsseg7e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg7e512.v v4, (a0), a1, v0.t # OK
- + vssseg7e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg7e512.v v4, (a0), a1, v0.t # OK
- + vlsseg8e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg8e512.v v4, (a0), a1, v0.t # OK
- + vssseg8e512.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg8e512.v v4, (a0), a1, v0.t # OK
- +
- + vlsseg2e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg2e1024.v v4, (a0), a1, v0.t # OK
- + vssseg2e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg2e1024.v v4, (a0), a1, v0.t # OK
- + vlsseg3e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg3e1024.v v4, (a0), a1, v0.t # OK
- + vssseg3e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg3e1024.v v4, (a0), a1, v0.t # OK
- + vlsseg4e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg4e1024.v v4, (a0), a1, v0.t # OK
- + vssseg4e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg4e1024.v v4, (a0), a1, v0.t # OK
- + vlsseg5e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg5e1024.v v4, (a0), a1, v0.t # OK
- + vssseg5e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg5e1024.v v4, (a0), a1, v0.t # OK
- + vlsseg6e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg6e1024.v v4, (a0), a1, v0.t # OK
- + vssseg6e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg6e1024.v v4, (a0), a1, v0.t # OK
- + vlsseg7e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg7e1024.v v4, (a0), a1, v0.t # OK
- + vssseg7e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg7e1024.v v4, (a0), a1, v0.t # OK
- + vlsseg8e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg8e1024.v v4, (a0), a1, v0.t # OK
- + vssseg8e1024.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg8e1024.v v4, (a0), a1, v0.t # OK
- +
- +# Vector Indexed Segment Loads and Stores
- +
- + vlxseg2ei8.v v0, (a0), v2 # OK
- + vlxseg2ei8.v v1, (a0), v2 # OK
- + vlxseg2ei8.v v2, (a0), v2 # vd overlap vs2
- + vlxseg2ei8.v v0, (a0), v2, v0.t # vd overlap vm
- + vsxseg2ei8.v v0, (a0), v2
- + vsxseg2ei8.v v1, (a0), v2
- + vsxseg2ei8.v v2, (a0), v2
- + vsxseg2ei8.v v0, (a0), v2, v0.t
- + vlxseg3ei8.v v0, (a0), v2
- + vlxseg3ei8.v v1, (a0), v2
- + vlxseg3ei8.v v2, (a0), v2
- + vlxseg3ei8.v v0, (a0), v2, v0.t
- + vsxseg3ei8.v v0, (a0), v2
- + vsxseg3ei8.v v1, (a0), v2
- + vsxseg3ei8.v v2, (a0), v2
- + vsxseg3ei8.v v0, (a0), v2, v0.t
- + vlxseg4ei8.v v0, (a0), v2
- + vlxseg4ei8.v v1, (a0), v2
- + vlxseg4ei8.v v2, (a0), v2
- + vlxseg4ei8.v v0, (a0), v2, v0.t
- + vsxseg4ei8.v v0, (a0), v2
- + vsxseg4ei8.v v1, (a0), v2
- + vsxseg4ei8.v v2, (a0), v2
- + vsxseg4ei8.v v0, (a0), v2, v0.t
- + vlxseg5ei8.v v0, (a0), v2
- + vlxseg5ei8.v v1, (a0), v2
- + vlxseg5ei8.v v2, (a0), v2
- + vlxseg5ei8.v v0, (a0), v2, v0.t
- + vsxseg5ei8.v v0, (a0), v2
- + vsxseg5ei8.v v1, (a0), v2
- + vsxseg5ei8.v v2, (a0), v2
- + vsxseg5ei8.v v0, (a0), v2, v0.t
- + vlxseg6ei8.v v0, (a0), v2
- + vlxseg6ei8.v v1, (a0), v2
- + vlxseg6ei8.v v2, (a0), v2
- + vlxseg6ei8.v v0, (a0), v2, v0.t
- + vsxseg6ei8.v v0, (a0), v2
- + vsxseg6ei8.v v1, (a0), v2
- + vsxseg6ei8.v v2, (a0), v2
- + vsxseg6ei8.v v0, (a0), v2, v0.t
- + vlxseg7ei8.v v0, (a0), v2
- + vlxseg7ei8.v v1, (a0), v2
- + vlxseg7ei8.v v2, (a0), v2
- + vlxseg7ei8.v v0, (a0), v2, v0.t
- + vsxseg7ei8.v v0, (a0), v2
- + vsxseg7ei8.v v1, (a0), v2
- + vsxseg7ei8.v v2, (a0), v2
- + vsxseg7ei8.v v0, (a0), v2, v0.t
- + vlxseg8ei8.v v0, (a0), v2
- + vlxseg8ei8.v v1, (a0), v2
- + vlxseg8ei8.v v2, (a0), v2
- + vlxseg8ei8.v v0, (a0), v2, v0.t
- + vsxseg8ei8.v v0, (a0), v2
- + vsxseg8ei8.v v1, (a0), v2
- + vsxseg8ei8.v v2, (a0), v2
- + vsxseg8ei8.v v0, (a0), v2, v0.t
- +
- + vlxseg2ei16.v v0, (a0), v2 # OK
- + vlxseg2ei16.v v1, (a0), v2 # OK
- + vlxseg2ei16.v v2, (a0), v2 # vd overlap vs2
- + vlxseg2ei16.v v0, (a0), v2, v0.t # vd overlap vm
- + vsxseg2ei16.v v0, (a0), v2
- + vsxseg2ei16.v v1, (a0), v2
- + vsxseg2ei16.v v2, (a0), v2
- + vsxseg2ei16.v v0, (a0), v2, v0.t
- + vlxseg3ei16.v v0, (a0), v2
- + vlxseg3ei16.v v1, (a0), v2
- + vlxseg3ei16.v v2, (a0), v2
- + vlxseg3ei16.v v0, (a0), v2, v0.t
- + vsxseg3ei16.v v0, (a0), v2
- + vsxseg3ei16.v v1, (a0), v2
- + vsxseg3ei16.v v2, (a0), v2
- + vsxseg3ei16.v v0, (a0), v2, v0.t
- + vlxseg4ei16.v v0, (a0), v2
- + vlxseg4ei16.v v1, (a0), v2
- + vlxseg4ei16.v v2, (a0), v2
- + vlxseg4ei16.v v0, (a0), v2, v0.t
- + vsxseg4ei16.v v0, (a0), v2
- + vsxseg4ei16.v v1, (a0), v2
- + vsxseg4ei16.v v2, (a0), v2
- + vsxseg4ei16.v v0, (a0), v2, v0.t
- + vlxseg5ei16.v v0, (a0), v2
- + vlxseg5ei16.v v1, (a0), v2
- + vlxseg5ei16.v v2, (a0), v2
- + vlxseg5ei16.v v0, (a0), v2, v0.t
- + vsxseg5ei16.v v0, (a0), v2
- + vsxseg5ei16.v v1, (a0), v2
- + vsxseg5ei16.v v2, (a0), v2
- + vsxseg5ei16.v v0, (a0), v2, v0.t
- + vlxseg6ei16.v v0, (a0), v2
- + vlxseg6ei16.v v1, (a0), v2
- + vlxseg6ei16.v v2, (a0), v2
- + vlxseg6ei16.v v0, (a0), v2, v0.t
- + vsxseg6ei16.v v0, (a0), v2
- + vsxseg6ei16.v v1, (a0), v2
- + vsxseg6ei16.v v2, (a0), v2
- + vsxseg6ei16.v v0, (a0), v2, v0.t
- + vlxseg7ei16.v v0, (a0), v2
- + vlxseg7ei16.v v1, (a0), v2
- + vlxseg7ei16.v v2, (a0), v2
- + vlxseg7ei16.v v0, (a0), v2, v0.t
- + vsxseg7ei16.v v0, (a0), v2
- + vsxseg7ei16.v v1, (a0), v2
- + vsxseg7ei16.v v2, (a0), v2
- + vsxseg7ei16.v v0, (a0), v2, v0.t
- + vlxseg8ei16.v v0, (a0), v2
- + vlxseg8ei16.v v1, (a0), v2
- + vlxseg8ei16.v v2, (a0), v2
- + vlxseg8ei16.v v0, (a0), v2, v0.t
- + vsxseg8ei16.v v0, (a0), v2
- + vsxseg8ei16.v v1, (a0), v2
- + vsxseg8ei16.v v2, (a0), v2
- + vsxseg8ei16.v v0, (a0), v2, v0.t
- +
- + vlxseg2ei32.v v0, (a0), v2 # OK
- + vlxseg2ei32.v v1, (a0), v2 # OK
- + vlxseg2ei32.v v2, (a0), v2 # vd overlap vs2
- + vlxseg2ei32.v v0, (a0), v2, v0.t # vd overlap vm
- + vsxseg2ei32.v v0, (a0), v2
- + vsxseg2ei32.v v1, (a0), v2
- + vsxseg2ei32.v v2, (a0), v2
- + vsxseg2ei32.v v0, (a0), v2, v0.t
- + vlxseg3ei32.v v0, (a0), v2
- + vlxseg3ei32.v v1, (a0), v2
- + vlxseg3ei32.v v2, (a0), v2
- + vlxseg3ei32.v v0, (a0), v2, v0.t
- + vsxseg3ei32.v v0, (a0), v2
- + vsxseg3ei32.v v1, (a0), v2
- + vsxseg3ei32.v v2, (a0), v2
- + vsxseg3ei32.v v0, (a0), v2, v0.t
- + vlxseg4ei32.v v0, (a0), v2
- + vlxseg4ei32.v v1, (a0), v2
- + vlxseg4ei32.v v2, (a0), v2
- + vlxseg4ei32.v v0, (a0), v2, v0.t
- + vsxseg4ei32.v v0, (a0), v2
- + vsxseg4ei32.v v1, (a0), v2
- + vsxseg4ei32.v v2, (a0), v2
- + vsxseg4ei32.v v0, (a0), v2, v0.t
- + vlxseg5ei32.v v0, (a0), v2
- + vlxseg5ei32.v v1, (a0), v2
- + vlxseg5ei32.v v2, (a0), v2
- + vlxseg5ei32.v v0, (a0), v2, v0.t
- + vsxseg5ei32.v v0, (a0), v2
- + vsxseg5ei32.v v1, (a0), v2
- + vsxseg5ei32.v v2, (a0), v2
- + vsxseg5ei32.v v0, (a0), v2, v0.t
- + vlxseg6ei32.v v0, (a0), v2
- + vlxseg6ei32.v v1, (a0), v2
- + vlxseg6ei32.v v2, (a0), v2
- + vlxseg6ei32.v v0, (a0), v2, v0.t
- + vsxseg6ei32.v v0, (a0), v2
- + vsxseg6ei32.v v1, (a0), v2
- + vsxseg6ei32.v v2, (a0), v2
- + vsxseg6ei32.v v0, (a0), v2, v0.t
- + vlxseg7ei32.v v0, (a0), v2
- + vlxseg7ei32.v v1, (a0), v2
- + vlxseg7ei32.v v2, (a0), v2
- + vlxseg7ei32.v v0, (a0), v2, v0.t
- + vsxseg7ei32.v v0, (a0), v2
- + vsxseg7ei32.v v1, (a0), v2
- + vsxseg7ei32.v v2, (a0), v2
- + vsxseg7ei32.v v0, (a0), v2, v0.t
- + vlxseg8ei32.v v0, (a0), v2
- + vlxseg8ei32.v v1, (a0), v2
- + vlxseg8ei32.v v2, (a0), v2
- + vlxseg8ei32.v v0, (a0), v2, v0.t
- + vsxseg8ei32.v v0, (a0), v2
- + vsxseg8ei32.v v1, (a0), v2
- + vsxseg8ei32.v v2, (a0), v2
- + vsxseg8ei32.v v0, (a0), v2, v0.t
- +
- + vlxseg2ei64.v v0, (a0), v2 # OK
- + vlxseg2ei64.v v1, (a0), v2 # OK
- + vlxseg2ei64.v v2, (a0), v2 # vd overlap vs2
- + vlxseg2ei64.v v0, (a0), v2, v0.t # vd overlap vm
- + vsxseg2ei64.v v0, (a0), v2
- + vsxseg2ei64.v v1, (a0), v2
- + vsxseg2ei64.v v2, (a0), v2
- + vsxseg2ei64.v v0, (a0), v2, v0.t
- + vlxseg3ei64.v v0, (a0), v2
- + vlxseg3ei64.v v1, (a0), v2
- + vlxseg3ei64.v v2, (a0), v2
- + vlxseg3ei64.v v0, (a0), v2, v0.t
- + vsxseg3ei64.v v0, (a0), v2
- + vsxseg3ei64.v v1, (a0), v2
- + vsxseg3ei64.v v2, (a0), v2
- + vsxseg3ei64.v v0, (a0), v2, v0.t
- + vlxseg4ei64.v v0, (a0), v2
- + vlxseg4ei64.v v1, (a0), v2
- + vlxseg4ei64.v v2, (a0), v2
- + vlxseg4ei64.v v0, (a0), v2, v0.t
- + vsxseg4ei64.v v0, (a0), v2
- + vsxseg4ei64.v v1, (a0), v2
- + vsxseg4ei64.v v2, (a0), v2
- + vsxseg4ei64.v v0, (a0), v2, v0.t
- + vlxseg5ei64.v v0, (a0), v2
- + vlxseg5ei64.v v1, (a0), v2
- + vlxseg5ei64.v v2, (a0), v2
- + vlxseg5ei64.v v0, (a0), v2, v0.t
- + vsxseg5ei64.v v0, (a0), v2
- + vsxseg5ei64.v v1, (a0), v2
- + vsxseg5ei64.v v2, (a0), v2
- + vsxseg5ei64.v v0, (a0), v2, v0.t
- + vlxseg6ei64.v v0, (a0), v2
- + vlxseg6ei64.v v1, (a0), v2
- + vlxseg6ei64.v v2, (a0), v2
- + vlxseg6ei64.v v0, (a0), v2, v0.t
- + vsxseg6ei64.v v0, (a0), v2
- + vsxseg6ei64.v v1, (a0), v2
- + vsxseg6ei64.v v2, (a0), v2
- + vsxseg6ei64.v v0, (a0), v2, v0.t
- + vlxseg7ei64.v v0, (a0), v2
- + vlxseg7ei64.v v1, (a0), v2
- + vlxseg7ei64.v v2, (a0), v2
- + vlxseg7ei64.v v0, (a0), v2, v0.t
- + vsxseg7ei64.v v0, (a0), v2
- + vsxseg7ei64.v v1, (a0), v2
- + vsxseg7ei64.v v2, (a0), v2
- + vsxseg7ei64.v v0, (a0), v2, v0.t
- + vlxseg8ei64.v v0, (a0), v2
- + vlxseg8ei64.v v1, (a0), v2
- + vlxseg8ei64.v v2, (a0), v2
- + vlxseg8ei64.v v0, (a0), v2, v0.t
- + vsxseg8ei64.v v0, (a0), v2
- + vsxseg8ei64.v v1, (a0), v2
- + vsxseg8ei64.v v2, (a0), v2
- + vsxseg8ei64.v v0, (a0), v2, v0.t
- +
- + vlxseg2ei128.v v0, (a0), v2 # OK
- + vlxseg2ei128.v v1, (a0), v2 # OK
- + vlxseg2ei128.v v2, (a0), v2 # vd overlap vs2
- + vlxseg2ei128.v v0, (a0), v2, v0.t # vd overlap vm
- + vsxseg2ei128.v v0, (a0), v2
- + vsxseg2ei128.v v1, (a0), v2
- + vsxseg2ei128.v v2, (a0), v2
- + vsxseg2ei128.v v0, (a0), v2, v0.t
- + vlxseg3ei128.v v0, (a0), v2
- + vlxseg3ei128.v v1, (a0), v2
- + vlxseg3ei128.v v2, (a0), v2
- + vlxseg3ei128.v v0, (a0), v2, v0.t
- + vsxseg3ei128.v v0, (a0), v2
- + vsxseg3ei128.v v1, (a0), v2
- + vsxseg3ei128.v v2, (a0), v2
- + vsxseg3ei128.v v0, (a0), v2, v0.t
- + vlxseg4ei128.v v0, (a0), v2
- + vlxseg4ei128.v v1, (a0), v2
- + vlxseg4ei128.v v2, (a0), v2
- + vlxseg4ei128.v v0, (a0), v2, v0.t
- + vsxseg4ei128.v v0, (a0), v2
- + vsxseg4ei128.v v1, (a0), v2
- + vsxseg4ei128.v v2, (a0), v2
- + vsxseg4ei128.v v0, (a0), v2, v0.t
- + vlxseg5ei128.v v0, (a0), v2
- + vlxseg5ei128.v v1, (a0), v2
- + vlxseg5ei128.v v2, (a0), v2
- + vlxseg5ei128.v v0, (a0), v2, v0.t
- + vsxseg5ei128.v v0, (a0), v2
- + vsxseg5ei128.v v1, (a0), v2
- + vsxseg5ei128.v v2, (a0), v2
- + vsxseg5ei128.v v0, (a0), v2, v0.t
- + vlxseg6ei128.v v0, (a0), v2
- + vlxseg6ei128.v v1, (a0), v2
- + vlxseg6ei128.v v2, (a0), v2
- + vlxseg6ei128.v v0, (a0), v2, v0.t
- + vsxseg6ei128.v v0, (a0), v2
- + vsxseg6ei128.v v1, (a0), v2
- + vsxseg6ei128.v v2, (a0), v2
- + vsxseg6ei128.v v0, (a0), v2, v0.t
- + vlxseg7ei128.v v0, (a0), v2
- + vlxseg7ei128.v v1, (a0), v2
- + vlxseg7ei128.v v2, (a0), v2
- + vlxseg7ei128.v v0, (a0), v2, v0.t
- + vsxseg7ei128.v v0, (a0), v2
- + vsxseg7ei128.v v1, (a0), v2
- + vsxseg7ei128.v v2, (a0), v2
- + vsxseg7ei128.v v0, (a0), v2, v0.t
- + vlxseg8ei128.v v0, (a0), v2
- + vlxseg8ei128.v v1, (a0), v2
- + vlxseg8ei128.v v2, (a0), v2
- + vlxseg8ei128.v v0, (a0), v2, v0.t
- + vsxseg8ei128.v v0, (a0), v2
- + vsxseg8ei128.v v1, (a0), v2
- + vsxseg8ei128.v v2, (a0), v2
- + vsxseg8ei128.v v0, (a0), v2, v0.t
- +
- + vlxseg2ei256.v v0, (a0), v2 # OK
- + vlxseg2ei256.v v1, (a0), v2 # OK
- + vlxseg2ei256.v v2, (a0), v2 # vd overlap vs2
- + vlxseg2ei256.v v0, (a0), v2, v0.t # vd overlap vm
- + vsxseg2ei256.v v0, (a0), v2
- + vsxseg2ei256.v v1, (a0), v2
- + vsxseg2ei256.v v2, (a0), v2
- + vsxseg2ei256.v v0, (a0), v2, v0.t
- + vlxseg3ei256.v v0, (a0), v2
- + vlxseg3ei256.v v1, (a0), v2
- + vlxseg3ei256.v v2, (a0), v2
- + vlxseg3ei256.v v0, (a0), v2, v0.t
- + vsxseg3ei256.v v0, (a0), v2
- + vsxseg3ei256.v v1, (a0), v2
- + vsxseg3ei256.v v2, (a0), v2
- + vsxseg3ei256.v v0, (a0), v2, v0.t
- + vlxseg4ei256.v v0, (a0), v2
- + vlxseg4ei256.v v1, (a0), v2
- + vlxseg4ei256.v v2, (a0), v2
- + vlxseg4ei256.v v0, (a0), v2, v0.t
- + vsxseg4ei256.v v0, (a0), v2
- + vsxseg4ei256.v v1, (a0), v2
- + vsxseg4ei256.v v2, (a0), v2
- + vsxseg4ei256.v v0, (a0), v2, v0.t
- + vlxseg5ei256.v v0, (a0), v2
- + vlxseg5ei256.v v1, (a0), v2
- + vlxseg5ei256.v v2, (a0), v2
- + vlxseg5ei256.v v0, (a0), v2, v0.t
- + vsxseg5ei256.v v0, (a0), v2
- + vsxseg5ei256.v v1, (a0), v2
- + vsxseg5ei256.v v2, (a0), v2
- + vsxseg5ei256.v v0, (a0), v2, v0.t
- + vlxseg6ei256.v v0, (a0), v2
- + vlxseg6ei256.v v1, (a0), v2
- + vlxseg6ei256.v v2, (a0), v2
- + vlxseg6ei256.v v0, (a0), v2, v0.t
- + vsxseg6ei256.v v0, (a0), v2
- + vsxseg6ei256.v v1, (a0), v2
- + vsxseg6ei256.v v2, (a0), v2
- + vsxseg6ei256.v v0, (a0), v2, v0.t
- + vlxseg7ei256.v v0, (a0), v2
- + vlxseg7ei256.v v1, (a0), v2
- + vlxseg7ei256.v v2, (a0), v2
- + vlxseg7ei256.v v0, (a0), v2, v0.t
- + vsxseg7ei256.v v0, (a0), v2
- + vsxseg7ei256.v v1, (a0), v2
- + vsxseg7ei256.v v2, (a0), v2
- + vsxseg7ei256.v v0, (a0), v2, v0.t
- + vlxseg8ei256.v v0, (a0), v2
- + vlxseg8ei256.v v1, (a0), v2
- + vlxseg8ei256.v v2, (a0), v2
- + vlxseg8ei256.v v0, (a0), v2, v0.t
- + vsxseg8ei256.v v0, (a0), v2
- + vsxseg8ei256.v v1, (a0), v2
- + vsxseg8ei256.v v2, (a0), v2
- + vsxseg8ei256.v v0, (a0), v2, v0.t
- +
- + vlxseg2ei512.v v0, (a0), v2 # OK
- + vlxseg2ei512.v v1, (a0), v2 # OK
- + vlxseg2ei512.v v2, (a0), v2 # vd overlap vs2
- + vlxseg2ei512.v v0, (a0), v2, v0.t # vd overlap vm
- + vsxseg2ei512.v v0, (a0), v2
- + vsxseg2ei512.v v1, (a0), v2
- + vsxseg2ei512.v v2, (a0), v2
- + vsxseg2ei512.v v0, (a0), v2, v0.t
- + vlxseg3ei512.v v0, (a0), v2
- + vlxseg3ei512.v v1, (a0), v2
- + vlxseg3ei512.v v2, (a0), v2
- + vlxseg3ei512.v v0, (a0), v2, v0.t
- + vsxseg3ei512.v v0, (a0), v2
- + vsxseg3ei512.v v1, (a0), v2
- + vsxseg3ei512.v v2, (a0), v2
- + vsxseg3ei512.v v0, (a0), v2, v0.t
- + vlxseg4ei512.v v0, (a0), v2
- + vlxseg4ei512.v v1, (a0), v2
- + vlxseg4ei512.v v2, (a0), v2
- + vlxseg4ei512.v v0, (a0), v2, v0.t
- + vsxseg4ei512.v v0, (a0), v2
- + vsxseg4ei512.v v1, (a0), v2
- + vsxseg4ei512.v v2, (a0), v2
- + vsxseg4ei512.v v0, (a0), v2, v0.t
- + vlxseg5ei512.v v0, (a0), v2
- + vlxseg5ei512.v v1, (a0), v2
- + vlxseg5ei512.v v2, (a0), v2
- + vlxseg5ei512.v v0, (a0), v2, v0.t
- + vsxseg5ei512.v v0, (a0), v2
- + vsxseg5ei512.v v1, (a0), v2
- + vsxseg5ei512.v v2, (a0), v2
- + vsxseg5ei512.v v0, (a0), v2, v0.t
- + vlxseg6ei512.v v0, (a0), v2
- + vlxseg6ei512.v v1, (a0), v2
- + vlxseg6ei512.v v2, (a0), v2
- + vlxseg6ei512.v v0, (a0), v2, v0.t
- + vsxseg6ei512.v v0, (a0), v2
- + vsxseg6ei512.v v1, (a0), v2
- + vsxseg6ei512.v v2, (a0), v2
- + vsxseg6ei512.v v0, (a0), v2, v0.t
- + vlxseg7ei512.v v0, (a0), v2
- + vlxseg7ei512.v v1, (a0), v2
- + vlxseg7ei512.v v2, (a0), v2
- + vlxseg7ei512.v v0, (a0), v2, v0.t
- + vsxseg7ei512.v v0, (a0), v2
- + vsxseg7ei512.v v1, (a0), v2
- + vsxseg7ei512.v v2, (a0), v2
- + vsxseg7ei512.v v0, (a0), v2, v0.t
- + vlxseg8ei512.v v0, (a0), v2
- + vlxseg8ei512.v v1, (a0), v2
- + vlxseg8ei512.v v2, (a0), v2
- + vlxseg8ei512.v v0, (a0), v2, v0.t
- + vsxseg8ei512.v v0, (a0), v2
- + vsxseg8ei512.v v1, (a0), v2
- + vsxseg8ei512.v v2, (a0), v2
- + vsxseg8ei512.v v0, (a0), v2, v0.t
- +
- + vlxseg2ei1024.v v0, (a0), v2 # OK
- + vlxseg2ei1024.v v1, (a0), v2 # OK
- + vlxseg2ei1024.v v2, (a0), v2 # vd overlap vs2
- + vlxseg2ei1024.v v0, (a0), v2, v0.t # vd overlap vm
- + vsxseg2ei1024.v v0, (a0), v2
- + vsxseg2ei1024.v v1, (a0), v2
- + vsxseg2ei1024.v v2, (a0), v2
- + vsxseg2ei1024.v v0, (a0), v2, v0.t
- + vlxseg3ei1024.v v0, (a0), v2
- + vlxseg3ei1024.v v1, (a0), v2
- + vlxseg3ei1024.v v2, (a0), v2
- + vlxseg3ei1024.v v0, (a0), v2, v0.t
- + vsxseg3ei1024.v v0, (a0), v2
- + vsxseg3ei1024.v v1, (a0), v2
- + vsxseg3ei1024.v v2, (a0), v2
- + vsxseg3ei1024.v v0, (a0), v2, v0.t
- + vlxseg4ei1024.v v0, (a0), v2
- + vlxseg4ei1024.v v1, (a0), v2
- + vlxseg4ei1024.v v2, (a0), v2
- + vlxseg4ei1024.v v0, (a0), v2, v0.t
- + vsxseg4ei1024.v v0, (a0), v2
- + vsxseg4ei1024.v v1, (a0), v2
- + vsxseg4ei1024.v v2, (a0), v2
- + vsxseg4ei1024.v v0, (a0), v2, v0.t
- + vlxseg5ei1024.v v0, (a0), v2
- + vlxseg5ei1024.v v1, (a0), v2
- + vlxseg5ei1024.v v2, (a0), v2
- + vlxseg5ei1024.v v0, (a0), v2, v0.t
- + vsxseg5ei1024.v v0, (a0), v2
- + vsxseg5ei1024.v v1, (a0), v2
- + vsxseg5ei1024.v v2, (a0), v2
- + vsxseg5ei1024.v v0, (a0), v2, v0.t
- + vlxseg6ei1024.v v0, (a0), v2
- + vlxseg6ei1024.v v1, (a0), v2
- + vlxseg6ei1024.v v2, (a0), v2
- + vlxseg6ei1024.v v0, (a0), v2, v0.t
- + vsxseg6ei1024.v v0, (a0), v2
- + vsxseg6ei1024.v v1, (a0), v2
- + vsxseg6ei1024.v v2, (a0), v2
- + vsxseg6ei1024.v v0, (a0), v2, v0.t
- + vlxseg7ei1024.v v0, (a0), v2
- + vlxseg7ei1024.v v1, (a0), v2
- + vlxseg7ei1024.v v2, (a0), v2
- + vlxseg7ei1024.v v0, (a0), v2, v0.t
- + vsxseg7ei1024.v v0, (a0), v2
- + vsxseg7ei1024.v v1, (a0), v2
- + vsxseg7ei1024.v v2, (a0), v2
- + vsxseg7ei1024.v v0, (a0), v2, v0.t
- + vlxseg8ei1024.v v0, (a0), v2
- + vlxseg8ei1024.v v1, (a0), v2
- + vlxseg8ei1024.v v2, (a0), v2
- + vlxseg8ei1024.v v0, (a0), v2, v0.t
- + vsxseg8ei1024.v v0, (a0), v2
- + vsxseg8ei1024.v v1, (a0), v2
- + vsxseg8ei1024.v v2, (a0), v2
- + vsxseg8ei1024.v v0, (a0), v2, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.d b/gas/testsuite/gas/riscv/vector-insns-fail-02.d
- new file mode 100644
- index 0000000000..6780b8553d
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-02.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv_zvqmac -mcheck-constraints
- +#source: vector-insns-fail-02.s
- +#error_output: vector-insns-fail-02.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.l b/gas/testsuite/gas/riscv/vector-insns-fail-02.l
- new file mode 100644
- index 0000000000..c015fd75fc
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-02.l
- @@ -0,0 +1,121 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vwaddu.vv v1,v2,v4'
- +.*Error: illegal operands `vwaddu.vv v2,v2,v4'
- +.*Error: illegal operands `vwaddu.vv v2,v3,v4'
- +.*Error: illegal operands `vwaddu.vv v4,v2,v4'
- +.*Error: illegal operands `vwaddu.vv v4,v2,v5'
- +.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwsubu.vv v1,v2,v4'
- +.*Error: illegal operands `vwsubu.vv v2,v2,v4'
- +.*Error: illegal operands `vwsubu.vv v2,v3,v4'
- +.*Error: illegal operands `vwsubu.vv v4,v2,v4'
- +.*Error: illegal operands `vwsubu.vv v4,v2,v5'
- +.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwadd.vv v1,v2,v4'
- +.*Error: illegal operands `vwadd.vv v2,v2,v4'
- +.*Error: illegal operands `vwadd.vv v2,v3,v4'
- +.*Error: illegal operands `vwadd.vv v4,v2,v4'
- +.*Error: illegal operands `vwadd.vv v4,v2,v5'
- +.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwsub.vv v1,v2,v4'
- +.*Error: illegal operands `vwsub.vv v2,v2,v4'
- +.*Error: illegal operands `vwsub.vv v2,v3,v4'
- +.*Error: illegal operands `vwsub.vv v4,v2,v4'
- +.*Error: illegal operands `vwsub.vv v4,v2,v5'
- +.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmul.vv v1,v2,v4'
- +.*Error: illegal operands `vwmul.vv v2,v2,v4'
- +.*Error: illegal operands `vwmul.vv v2,v3,v4'
- +.*Error: illegal operands `vwmul.vv v4,v2,v4'
- +.*Error: illegal operands `vwmul.vv v4,v2,v5'
- +.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmulu.vv v1,v2,v4'
- +.*Error: illegal operands `vwmulu.vv v2,v2,v4'
- +.*Error: illegal operands `vwmulu.vv v2,v3,v4'
- +.*Error: illegal operands `vwmulu.vv v4,v2,v4'
- +.*Error: illegal operands `vwmulu.vv v4,v2,v5'
- +.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
- +.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
- +.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
- +.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
- +.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
- +.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
- +.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
- +.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
- +.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
- +.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
- +.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmacc.vv v1,v2,v4'
- +.*Error: illegal operands `vwmacc.vv v2,v2,v4'
- +.*Error: illegal operands `vwmacc.vv v2,v3,v4'
- +.*Error: illegal operands `vwmacc.vv v4,v2,v4'
- +.*Error: illegal operands `vwmacc.vv v4,v2,v5'
- +.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
- +.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
- +.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
- +.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
- +.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
- +.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
- +.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
- +.*Error: illegal operands `vqmaccu.vv v4,v6,v8'
- +.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
- +.*Error: illegal operands `vqmaccu.vv v8,v4,v10'
- +.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vqmacc.vv v2,v4,v8'
- +.*Error: illegal operands `vqmacc.vv v4,v4,v8'
- +.*Error: illegal operands `vqmacc.vv v4,v6,v8'
- +.*Error: illegal operands `vqmacc.vv v8,v4,v8'
- +.*Error: illegal operands `vqmacc.vv v8,v4,v10'
- +.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
- +.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
- +.*Error: illegal operands `vqmaccsu.vv v4,v6,v8'
- +.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
- +.*Error: illegal operands `vqmaccsu.vv v8,v4,v10'
- +.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfwadd.vv v1,v2,v4'
- +.*Error: illegal operands `vfwadd.vv v2,v2,v4'
- +.*Error: illegal operands `vfwadd.vv v2,v3,v4'
- +.*Error: illegal operands `vfwadd.vv v4,v2,v4'
- +.*Error: illegal operands `vfwadd.vv v4,v2,v5'
- +.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwsub.vv v1,v2,v4'
- +.*Error: illegal operands `vfwsub.vv v2,v2,v4'
- +.*Error: illegal operands `vfwsub.vv v2,v3,v4'
- +.*Error: illegal operands `vfwsub.vv v4,v2,v4'
- +.*Error: illegal operands `vfwsub.vv v4,v2,v5'
- +.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwmul.vv v1,v2,v4'
- +.*Error: illegal operands `vfwmul.vv v2,v2,v4'
- +.*Error: illegal operands `vfwmul.vv v2,v3,v4'
- +.*Error: illegal operands `vfwmul.vv v4,v2,v4'
- +.*Error: illegal operands `vfwmul.vv v4,v2,v5'
- +.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
- +.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
- +.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
- +.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
- +.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
- +.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
- +.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
- +.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
- +.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
- +.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
- +.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
- +.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
- +.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
- +.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
- +.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
- +.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
- +.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
- +.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
- +.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
- +.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
- +.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.s b/gas/testsuite/gas/riscv/vector-insns-fail-02.s
- new file mode 100644
- index 0000000000..bf493c8ddb
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-02.s
- @@ -0,0 +1,162 @@
- +# Widening Vector Arithmetic Instructions (VV)
- +# Quad-Widening Vector Arithmetic Instructions (VV)
- +
- + vwaddu.vv v0, v2, v4 # OK
- + vwaddu.vv v1, v2, v4 # vd should be multiple of 2
- + vwaddu.vv v2, v2, v4 # vd overlap vs2
- + vwaddu.vv v2, v3, v4 # vd overlap vs2
- + vwaddu.vv v4, v2, v4 # vd overlap vs1
- + vwaddu.vv v4, v2, v5 # vd overlap vs1
- + vwaddu.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwsubu.vv v0, v2, v4 # OK
- + vwsubu.vv v1, v2, v4 # vd should be multiple of 2
- + vwsubu.vv v2, v2, v4 # vd overlap vs2
- + vwsubu.vv v2, v3, v4 # vd overlap vs2
- + vwsubu.vv v4, v2, v4 # vd overlap vs1
- + vwsubu.vv v4, v2, v5 # vd overlap vs1
- + vwsubu.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwadd.vv v0, v2, v4 # OK
- + vwadd.vv v1, v2, v4 # vd should be multiple of 2
- + vwadd.vv v2, v2, v4 # vd overlap vs2
- + vwadd.vv v2, v3, v4 # vd overlap vs2
- + vwadd.vv v4, v2, v4 # vd overlap vs1
- + vwadd.vv v4, v2, v5 # vd overlap vs1
- + vwadd.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwsub.vv v0, v2, v4 # OK
- + vwsub.vv v1, v2, v4 # vd should be multiple of 2
- + vwsub.vv v2, v2, v4 # vd overlap vs2
- + vwsub.vv v2, v3, v4 # vd overlap vs2
- + vwsub.vv v4, v2, v4 # vd overlap vs1
- + vwsub.vv v4, v2, v5 # vd overlap vs1
- + vwsub.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwmul.vv v0, v2, v4 # OK
- + vwmul.vv v1, v2, v4 # vd should be multiple of 2
- + vwmul.vv v2, v2, v4 # vd overlap vs2
- + vwmul.vv v2, v3, v4 # vd overlap vs2
- + vwmul.vv v4, v2, v4 # vd overlap vs1
- + vwmul.vv v4, v2, v5 # vd overlap vs1
- + vwmul.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwmulu.vv v0, v2, v4 # OK
- + vwmulu.vv v1, v2, v4 # vd should be multiple of 2
- + vwmulu.vv v2, v2, v4 # vd overlap vs2
- + vwmulu.vv v2, v3, v4 # vd overlap vs2
- + vwmulu.vv v4, v2, v4 # vd overlap vs1
- + vwmulu.vv v4, v2, v5 # vd overlap vs1
- + vwmulu.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwmulsu.vv v0, v2, v4 # OK
- + vwmulsu.vv v1, v2, v4 # vd should be multiple of 2
- + vwmulsu.vv v2, v2, v4 # vd overlap vs2
- + vwmulsu.vv v2, v3, v4 # vd overlap vs2
- + vwmulsu.vv v4, v2, v4 # vd overlap vs1
- + vwmulsu.vv v4, v2, v5 # vd overlap vs1
- + vwmulsu.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwmaccu.vv v0, v2, v4 # OK
- + vwmaccu.vv v1, v2, v4 # vd should be multiple of 2
- + vwmaccu.vv v2, v2, v4 # vd overlap vs1
- + vwmaccu.vv v2, v3, v4 # vd overlap vs1
- + vwmaccu.vv v4, v2, v4 # vd overlap vs2
- + vwmaccu.vv v4, v2, v5 # vd overlap vs2
- + vwmaccu.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwmacc.vv v0, v2, v4 # OK
- + vwmacc.vv v1, v2, v4 # vd should be multiple of 2
- + vwmacc.vv v2, v2, v4 # vd overlap vs1
- + vwmacc.vv v2, v3, v4 # vd overlap vs1
- + vwmacc.vv v4, v2, v4 # vd overlap vs2
- + vwmacc.vv v4, v2, v5 # vd overlap vs2
- + vwmacc.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwmaccsu.vv v0, v2, v4 # OK
- + vwmaccsu.vv v1, v2, v4 # vd should be multiple of 2
- + vwmaccsu.vv v2, v2, v4 # vd overlap vs1
- + vwmaccsu.vv v2, v3, v4 # vd overlap vs1
- + vwmaccsu.vv v4, v2, v4 # vd overlap vs2
- + vwmaccsu.vv v4, v2, v5 # vd overlap vs2
- + vwmaccsu.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vqmaccu.vv v0, v4, v8 # OK
- + vqmaccu.vv v2, v4, v8 # vd should be multiple of 4
- + vqmaccu.vv v4, v4, v8 # vd overlap vs1
- + vqmaccu.vv v4, v6, v8 # vd overlap vs1
- + vqmaccu.vv v8, v4, v8 # vd overlap vs2
- + vqmaccu.vv v8, v4, v10 # vd overlap vs2
- + vqmaccu.vv v0, v4, v8, v0.t # vd overlap vm
- +
- + vqmacc.vv v0, v4, v8 # OK
- + vqmacc.vv v2, v4, v8 # vd should be multiple of 4
- + vqmacc.vv v4, v4, v8 # vd overlap vs1
- + vqmacc.vv v4, v6, v8 # vd overlap vs1
- + vqmacc.vv v8, v4, v8 # vd overlap vs2
- + vqmacc.vv v8, v4, v10 # vd overlap vs2
- + vqmacc.vv v0, v4, v8, v0.t # vd overlap vm
- +
- + vqmaccsu.vv v0, v4, v8 # OK
- + vqmaccsu.vv v2, v4, v8 # vd should be multiple of 4
- + vqmaccsu.vv v4, v4, v8 # vd overlap vs1
- + vqmaccsu.vv v4, v6, v8 # vd overlap vs1
- + vqmaccsu.vv v8, v4, v8 # vd overlap vs2
- + vqmaccsu.vv v8, v4, v10 # vd overlap vs2
- + vqmaccsu.vv v0, v4, v8, v0.t # vd overlap vm
- +
- + vfwadd.vv v0, v2, v4 # OK
- + vfwadd.vv v1, v2, v4 # vd should be multiple of 2
- + vfwadd.vv v2, v2, v4 # vd overlap vs2
- + vfwadd.vv v2, v3, v4 # vd overlap vs2
- + vfwadd.vv v4, v2, v4 # vd overlap vs1
- + vfwadd.vv v4, v2, v5 # vd overlap vs1
- + vfwadd.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vfwsub.vv v0, v2, v4 # OK
- + vfwsub.vv v1, v2, v4 # vd should be multiple of 2
- + vfwsub.vv v2, v2, v4 # vd overlap vs2
- + vfwsub.vv v2, v3, v4 # vd overlap vs2
- + vfwsub.vv v4, v2, v4 # vd overlap vs1
- + vfwsub.vv v4, v2, v5 # vd overlap vs1
- + vfwsub.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vfwmul.vv v0, v2, v4 # OK
- + vfwmul.vv v1, v2, v4 # vd should be multiple of 2
- + vfwmul.vv v2, v2, v4 # vd overlap vs2
- + vfwmul.vv v2, v3, v4 # vd overlap vs2
- + vfwmul.vv v4, v2, v4 # vd overlap vs1
- + vfwmul.vv v4, v2, v5 # vd overlap vs1
- + vfwmul.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vfwmacc.vv v0, v2, v4 # OK
- + vfwmacc.vv v1, v2, v4 # vd should be multiple of 2
- + vfwmacc.vv v2, v2, v4 # vd overlap vs1
- + vfwmacc.vv v2, v3, v4 # vd overlap vs1
- + vfwmacc.vv v4, v2, v4 # vd overlap vs2
- + vfwmacc.vv v4, v2, v5 # vd overlap vs2
- + vfwmacc.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vfwnmacc.vv v0, v2, v4 # OK
- + vfwnmacc.vv v1, v2, v4 # vd should be multiple of 2
- + vfwnmacc.vv v2, v2, v4 # vd overlap vs1
- + vfwnmacc.vv v2, v3, v4 # vd overlap vs1
- + vfwnmacc.vv v4, v2, v4 # vd overlap vs2
- + vfwnmacc.vv v4, v2, v5 # vd overlap vs2
- + vfwnmacc.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vfwmsac.vv v0, v2, v4 # OK
- + vfwmsac.vv v1, v2, v4 # vd should be multiple of 2
- + vfwmsac.vv v2, v2, v4 # vd overlap vs1
- + vfwmsac.vv v2, v3, v4 # vd overlap vs1
- + vfwmsac.vv v4, v2, v4 # vd overlap vs2
- + vfwmsac.vv v4, v2, v5 # vd overlap vs2
- + vfwmsac.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vfwnmsac.vv v0, v2, v4 # OK
- + vfwnmsac.vv v1, v2, v4 # vd should be multiple of 2
- + vfwnmsac.vv v2, v2, v4 # vd overlap vs1
- + vfwnmsac.vv v2, v3, v4 # vd overlap vs1
- + vfwnmsac.vv v4, v2, v4 # vd overlap vs2
- + vfwnmsac.vv v4, v2, v5 # vd overlap vs2
- + vfwnmsac.vv v0, v2, v4, v0.t # vd overlap vm
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.d b/gas/testsuite/gas/riscv/vector-insns-fail-03.d
- new file mode 100644
- index 0000000000..1bfe441872
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-03.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv_zvqmac -mcheck-constraints
- +#source: vector-insns-fail-03.s
- +#error_output: vector-insns-fail-03.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.l b/gas/testsuite/gas/riscv/vector-insns-fail-03.l
- new file mode 100644
- index 0000000000..128e22726d
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-03.l
- @@ -0,0 +1,125 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vwcvt.x.x.v v1,v2'
- +.*Error: illegal operands `vwcvt.x.x.v v2,v2'
- +.*Error: illegal operands `vwcvt.x.x.v v2,v3'
- +.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
- +.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
- +.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
- +.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
- +.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
- +.*Error: illegal operands `vwaddu.vx v1,v2,a1'
- +.*Error: illegal operands `vwaddu.vx v2,v2,a1'
- +.*Error: illegal operands `vwaddu.vx v2,v3,a1'
- +.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwsubu.vx v1,v2,a1'
- +.*Error: illegal operands `vwsubu.vx v2,v2,a1'
- +.*Error: illegal operands `vwsubu.vx v2,v3,a1'
- +.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwadd.vx v1,v2,a1'
- +.*Error: illegal operands `vwadd.vx v2,v2,a1'
- +.*Error: illegal operands `vwadd.vx v2,v3,a1'
- +.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwsub.vx v1,v2,a1'
- +.*Error: illegal operands `vwsub.vx v2,v2,a1'
- +.*Error: illegal operands `vwsub.vx v2,v3,a1'
- +.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwmul.vx v1,v2,a1'
- +.*Error: illegal operands `vwmul.vx v2,v2,a1'
- +.*Error: illegal operands `vwmul.vx v2,v3,a1'
- +.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwmulu.vx v1,v2,a1'
- +.*Error: illegal operands `vwmulu.vx v2,v2,a1'
- +.*Error: illegal operands `vwmulu.vx v2,v3,a1'
- +.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
- +.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
- +.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
- +.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwmaccu.vx v1,a1,v4'
- +.*Error: illegal operands `vwmaccu.vx v4,a1,v4'
- +.*Error: illegal operands `vwmaccu.vx v4,a1,v5'
- +.*Error: illegal operands `vwmaccu.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vwmacc.vx v1,a1,v4'
- +.*Error: illegal operands `vwmacc.vx v4,a1,v4'
- +.*Error: illegal operands `vwmacc.vx v4,a1,v5'
- +.*Error: illegal operands `vwmacc.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vwmaccsu.vx v1,a1,v4'
- +.*Error: illegal operands `vwmaccsu.vx v4,a1,v4'
- +.*Error: illegal operands `vwmaccsu.vx v4,a1,v5'
- +.*Error: illegal operands `vwmaccsu.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vwmaccus.vx v1,a1,v4'
- +.*Error: illegal operands `vwmaccus.vx v4,a1,v4'
- +.*Error: illegal operands `vwmaccus.vx v4,a1,v5'
- +.*Error: illegal operands `vwmaccus.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
- +.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
- +.*Error: illegal operands `vqmaccu.vx v4,a1,v6'
- +.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vqmacc.vx v2,a1,v4'
- +.*Error: illegal operands `vqmacc.vx v4,a1,v4'
- +.*Error: illegal operands `vqmacc.vx v4,a1,v6'
- +.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
- +.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
- +.*Error: illegal operands `vqmaccsu.vx v4,a1,v6'
- +.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
- +.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
- +.*Error: illegal operands `vqmaccus.vx v4,a1,v6'
- +.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
- +.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
- +.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
- +.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
- +.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
- +.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
- +.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
- +.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
- +.*Error: illegal operands `vfwmul.vf v1,v2,fa1'
- +.*Error: illegal operands `vfwmul.vf v2,v2,fa1'
- +.*Error: illegal operands `vfwmul.vf v2,v3,fa1'
- +.*Error: illegal operands `vfwmul.vf v0,v2,fa1,v0.t'
- +.*Error: illegal operands `vfwmacc.vf v1,fa1,v4'
- +.*Error: illegal operands `vfwmacc.vf v4,fa1,v4'
- +.*Error: illegal operands `vfwmacc.vf v4,fa1,v5'
- +.*Error: illegal operands `vfwmacc.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfwnmacc.vf v1,fa1,v4'
- +.*Error: illegal operands `vfwnmacc.vf v4,fa1,v4'
- +.*Error: illegal operands `vfwnmacc.vf v4,fa1,v5'
- +.*Error: illegal operands `vfwnmacc.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfwmsac.vf v1,fa1,v4'
- +.*Error: illegal operands `vfwmsac.vf v4,fa1,v4'
- +.*Error: illegal operands `vfwmsac.vf v4,fa1,v5'
- +.*Error: illegal operands `vfwmsac.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfwnmsac.vf v1,fa1,v4'
- +.*Error: illegal operands `vfwnmsac.vf v4,fa1,v4'
- +.*Error: illegal operands `vfwnmsac.vf v4,fa1,v5'
- +.*Error: illegal operands `vfwnmsac.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
- +.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
- +.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
- +.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
- +.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
- +.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
- +.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.s b/gas/testsuite/gas/riscv/vector-insns-fail-03.s
- new file mode 100644
- index 0000000000..9450b9ceb0
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-03.s
- @@ -0,0 +1,187 @@
- +# Widening Vector Arithmetic Instructions (V[X|F])
- +
- + vwcvt.x.x.v v0, v2 # OK
- + vwcvt.x.x.v v1, v2 # vd should be multiple of 2
- + vwcvt.x.x.v v2, v2 # vd overlap vs2
- + vwcvt.x.x.v v2, v3 # vd overlap vs2
- + vwcvt.x.x.v v0, v2, v0.t # vd overlap vm
- +
- + vwcvtu.x.x.v v0, v2 # OK
- + vwcvtu.x.x.v v1, v2 # vd should be multiple of 2
- + vwcvtu.x.x.v v2, v2 # vd overlap vs2
- + vwcvtu.x.x.v v2, v3 # vd overlap vs2
- + vwcvtu.x.x.v v0, v2, v0.t # vd overlap vm
- +
- + vwaddu.vx v0, v2, a1 # OK
- + vwaddu.vx v1, v2, a1 # vd should be multiple of 2
- + vwaddu.vx v2, v2, a1 # vd overlap vs2
- + vwaddu.vx v2, v3, a1 # vd overlap vs2
- + vwaddu.vx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwsubu.vx v0, v2, a1 # OK
- + vwsubu.vx v1, v2, a1 # vd should be multiple of 2
- + vwsubu.vx v2, v2, a1 # vd overlap vs2
- + vwsubu.vx v2, v3, a1 # vd overlap vs2
- + vwsubu.vx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwadd.vx v0, v2, a1 # OK
- + vwadd.vx v1, v2, a1 # vd should be multiple of 2
- + vwadd.vx v2, v2, a1 # vd overlap vs2
- + vwadd.vx v2, v3, a1 # vd overlap vs2
- + vwadd.vx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwsub.vx v0, v2, a1 # OK
- + vwsub.vx v1, v2, a1 # vd should be multiple of 2
- + vwsub.vx v2, v2, a1 # vd overlap vs2
- + vwsub.vx v2, v3, a1 # vd overlap vs2
- + vwsub.vx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwmul.vx v0, v2, a1 # OK
- + vwmul.vx v1, v2, a1 # vd should be multiple of 2
- + vwmul.vx v2, v2, a1 # vd overlap vs2
- + vwmul.vx v2, v3, a1 # vd overlap vs2
- + vwmul.vx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwmulu.vx v0, v2, a1 # OK
- + vwmulu.vx v1, v2, a1 # vd should be multiple of 2
- + vwmulu.vx v2, v2, a1 # vd overlap vs2
- + vwmulu.vx v2, v3, a1 # vd overlap vs2
- + vwmulu.vx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwmulsu.vx v0, v2, a1 # OK
- + vwmulsu.vx v1, v2, a1 # vd should be multiple of 2
- + vwmulsu.vx v2, v2, a1 # vd overlap vs2
- + vwmulsu.vx v2, v3, a1 # vd overlap vs2
- + vwmulsu.vx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwmaccu.vx v0, a1, v4 # OK
- + vwmaccu.vx v1, a1, v4 # vd should be multiple of 2
- + vwmaccu.vx v4, a1, v4 # vd overlap vs2
- + vwmaccu.vx v4, a1, v5 # vd overlap vs2
- + vwmaccu.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vwmacc.vx v0, a1, v4 # OK
- + vwmacc.vx v1, a1, v4 # vd should be multiple of 2
- + vwmacc.vx v4, a1, v4 # vd overlap vs2
- + vwmacc.vx v4, a1, v5 # vd overlap vs2
- + vwmacc.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vwmaccsu.vx v0, a1, v4 # OK
- + vwmaccsu.vx v1, a1, v4 # vd should be multiple of 2
- + vwmaccsu.vx v4, a1, v4 # vd overlap vs2
- + vwmaccsu.vx v4, a1, v5 # vd overlap vs2
- + vwmaccsu.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vwmaccus.vx v0, a1, v4 # OK
- + vwmaccus.vx v1, a1, v4 # vd should be multiple of 2
- + vwmaccus.vx v4, a1, v4 # vd overlap vs2
- + vwmaccus.vx v4, a1, v5 # vd overlap vs2
- + vwmaccus.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vqmaccu.vx v0, a1, v4 # OK
- + vqmaccu.vx v2, a1, v4 # vd should be multiple of 4
- + vqmaccu.vx v4, a1, v4 # vd overlap vs2
- + vqmaccu.vx v4, a1, v6 # vd overlap vs2
- + vqmaccu.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vqmacc.vx v0, a1, v4 # OK
- + vqmacc.vx v2, a1, v4 # vd should be multiple of 4
- + vqmacc.vx v4, a1, v4 # vd overlap vs2
- + vqmacc.vx v4, a1, v6 # vd overlap vs2
- + vqmacc.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vqmaccsu.vx v0, a1, v4 # OK
- + vqmaccsu.vx v2, a1, v4 # vd should be multiple of 4
- + vqmaccsu.vx v4, a1, v4 # vd overlap vs2
- + vqmaccsu.vx v4, a1, v6 # vd overlap vs2
- + vqmaccsu.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vqmaccus.vx v0, a1, v4 # OK
- + vqmaccus.vx v2, a1, v4 # vd should be multiple of 4
- + vqmaccus.vx v4, a1, v4 # vd overlap vs2
- + vqmaccus.vx v4, a1, v6 # vd overlap vs2
- + vqmaccus.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vfwadd.vf v0, v2, fa1 # OK
- + vfwadd.vf v1, v2, fa1 # vd should be multiple of 2
- + vfwadd.vf v2, v2, fa1 # vd overlap vs2
- + vfwadd.vf v2, v3, fa1 # vd overlap vs2
- + vfwadd.vf v0, v2, fa1, v0.t # vd overlap vm
- +
- + vfwsub.vf v0, v2, fa1 # OK
- + vfwsub.vf v1, v2, fa1 # vd should be multiple of 2
- + vfwsub.vf v2, v2, fa1 # vd overlap vs2
- + vfwsub.vf v2, v3, fa1 # vd overlap vs2
- + vfwsub.vf v0, v2, fa1, v0.t # vd overlap vm
- +
- + vfwmul.vf v0, v2, fa1 # OK
- + vfwmul.vf v1, v2, fa1 # vd should be multiple of 2
- + vfwmul.vf v2, v2, fa1 # vd overlap vs2
- + vfwmul.vf v2, v3, fa1 # vd overlap vs2
- + vfwmul.vf v0, v2, fa1, v0.t # vd overlap vm
- +
- + vfwmacc.vf v0, fa1, v4 # OK
- + vfwmacc.vf v1, fa1, v4 # vd should be multiple of 2
- + vfwmacc.vf v4, fa1, v4 # vd overlap vs2
- + vfwmacc.vf v4, fa1, v5 # vd overlap vs2
- + vfwmacc.vf v0, fa1, v4, v0.t # vd overlap vm
- +
- + vfwnmacc.vf v0, fa1, v4 # OK
- + vfwnmacc.vf v1, fa1, v4 # vd should be multiple of 2
- + vfwnmacc.vf v4, fa1, v4 # vd overlap vs2
- + vfwnmacc.vf v4, fa1, v5 # vd overlap vs2
- + vfwnmacc.vf v0, fa1, v4, v0.t # vd overlap vm
- +
- + vfwmsac.vf v0, fa1, v4 # OK
- + vfwmsac.vf v1, fa1, v4 # vd should be multiple of 2
- + vfwmsac.vf v4, fa1, v4 # vd overlap vs2
- + vfwmsac.vf v4, fa1, v5 # vd overlap vs2
- + vfwmsac.vf v0, fa1, v4, v0.t # vd overlap vm
- +
- + vfwnmsac.vf v0, fa1, v4 # OK
- + vfwnmsac.vf v1, fa1, v4 # vd should be multiple of 2
- + vfwnmsac.vf v4, fa1, v4 # vd overlap vs2
- + vfwnmsac.vf v4, fa1, v5 # vd overlap vs2
- + vfwnmsac.vf v0, fa1, v4, v0.t # vd overlap vm
- +
- + vfwcvt.xu.f.v v0, v2 # OK
- + vfwcvt.xu.f.v v1, v2 # vd should be multiple of 2
- + vfwcvt.xu.f.v v2, v2 # vd overlap vs2
- + vfwcvt.xu.f.v v2, v3 # vd overlap vs2
- + vfwcvt.xu.f.v v0, v2, v0.t # vd overlap vm
- +
- + vfwcvt.x.f.v v0, v2 # OK
- + vfwcvt.x.f.v v1, v2 # vd should be multiple of 2
- + vfwcvt.x.f.v v2, v2 # vd overlap vs2
- + vfwcvt.x.f.v v2, v3 # vd overlap vs2
- + vfwcvt.x.f.v v0, v2, v0.t # vd overlap vm
- +
- + vfwcvt.rtz.xu.f.v v0, v2 # OK
- + vfwcvt.rtz.xu.f.v v1, v2 # vd should be multiple of 2
- + vfwcvt.rtz.xu.f.v v2, v2 # vd overlap vs2
- + vfwcvt.rtz.xu.f.v v2, v3 # vd overlap vs2
- + vfwcvt.rtz.xu.f.v v0, v2, v0.t # vd overlap vm
- +
- + vfwcvt.rtz.x.f.v v0, v2 # OK
- + vfwcvt.rtz.x.f.v v1, v2 # vd should be multiple of 2
- + vfwcvt.rtz.x.f.v v2, v2 # vd overlap vs2
- + vfwcvt.rtz.x.f.v v2, v3 # vd overlap vs2
- + vfwcvt.rtz.x.f.v v0, v2, v0.t # vd overlap vm
- +
- + vfwcvt.f.xu.v v0, v2 # OK
- + vfwcvt.f.xu.v v1, v2 # vd should be multiple of 2
- + vfwcvt.f.xu.v v2, v2 # vd overlap vs2
- + vfwcvt.f.xu.v v2, v3 # vd overlap vs2
- + vfwcvt.f.xu.v v0, v2, v0.t # vd overlap vm
- +
- + vfwcvt.f.x.v v0, v2 # OK
- + vfwcvt.f.x.v v1, v2 # vd should be multiple of 2
- + vfwcvt.f.x.v v2, v2 # vd overlap vs2
- + vfwcvt.f.x.v v2, v3 # vd overlap vs2
- + vfwcvt.f.x.v v0, v2, v0.t # vd overlap vm
- +
- + vfwcvt.f.f.v v0, v2 # OK
- + vfwcvt.f.f.v v1, v2 # vd should be multiple of 2
- + vfwcvt.f.f.v v2, v2 # vd overlap vs2
- + vfwcvt.f.f.v v2, v3 # vd overlap vs2
- + vfwcvt.f.f.v v0, v2, v0.t # vd overlap vm
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.d b/gas/testsuite/gas/riscv/vector-insns-fail-04.d
- new file mode 100644
- index 0000000000..d483884544
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-04.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv -mcheck-constraints
- +#source: vector-insns-fail-04.s
- +#error_output: vector-insns-fail-04.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.l b/gas/testsuite/gas/riscv/vector-insns-fail-04.l
- new file mode 100644
- index 0000000000..9a9c76c19d
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-04.l
- @@ -0,0 +1,49 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vwaddu.wv v1,v2,v4'
- +.*Error: illegal operands `vwaddu.wv v2,v3,v4'
- +.*Error: illegal operands `vwaddu.wv v4,v2,v4'
- +.*Error: illegal operands `vwaddu.wv v4,v2,v5'
- +.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwsubu.wv v1,v2,v4'
- +.*Error: illegal operands `vwsubu.wv v2,v3,v4'
- +.*Error: illegal operands `vwsubu.wv v4,v2,v4'
- +.*Error: illegal operands `vwsubu.wv v4,v2,v5'
- +.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwadd.wv v1,v2,v4'
- +.*Error: illegal operands `vwadd.wv v2,v3,v4'
- +.*Error: illegal operands `vwadd.wv v4,v2,v4'
- +.*Error: illegal operands `vwadd.wv v4,v2,v5'
- +.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwsub.wv v1,v2,v4'
- +.*Error: illegal operands `vwsub.wv v2,v3,v4'
- +.*Error: illegal operands `vwsub.wv v4,v2,v4'
- +.*Error: illegal operands `vwsub.wv v4,v2,v5'
- +.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwadd.wv v1,v2,v4'
- +.*Error: illegal operands `vfwadd.wv v2,v3,v4'
- +.*Error: illegal operands `vfwadd.wv v4,v2,v4'
- +.*Error: illegal operands `vfwadd.wv v4,v2,v5'
- +.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwsub.wv v1,v2,v4'
- +.*Error: illegal operands `vfwsub.wv v2,v3,v4'
- +.*Error: illegal operands `vfwsub.wv v4,v2,v4'
- +.*Error: illegal operands `vfwsub.wv v4,v2,v5'
- +.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwaddu.wx v1,v2,a1'
- +.*Error: illegal operands `vwaddu.wx v2,v3,a1'
- +.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwsubu.wx v1,v2,a1'
- +.*Error: illegal operands `vwsubu.wx v2,v3,a1'
- +.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwadd.wx v1,v2,a1'
- +.*Error: illegal operands `vwadd.wx v2,v3,a1'
- +.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwsub.wx v1,v2,a1'
- +.*Error: illegal operands `vwsub.wx v2,v3,a1'
- +.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vfwadd.wf v1,v2,fa1'
- +.*Error: illegal operands `vfwadd.wf v2,v3,fa1'
- +.*Error: illegal operands `vfwadd.wf v0,v2,fa1,v0.t'
- +.*Error: illegal operands `vfwsub.wf v1,v2,fa1'
- +.*Error: illegal operands `vfwsub.wf v2,v3,fa1'
- +.*Error: illegal operands `vfwsub.wf v0,v2,fa1,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.s b/gas/testsuite/gas/riscv/vector-insns-fail-04.s
- new file mode 100644
- index 0000000000..e1db16d53b
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-04.s
- @@ -0,0 +1,85 @@
- +# Widening Vector Arithmetic Instructions (W[V|X])
- +
- + vwaddu.wv v0, v2, v4 # OK
- + vwaddu.wv v1, v2, v4 # vd should be multiple of 2
- + vwaddu.wv v2, v2, v4 # OK
- + vwaddu.wv v2, v3, v4 # vs2 should be multiple of 2
- + vwaddu.wv v4, v2, v4 # vd overlap vs1
- + vwaddu.wv v4, v2, v5 # vd overlap vs1
- + vwaddu.wv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwsubu.wv v0, v2, v4 # OK
- + vwsubu.wv v1, v2, v4 # vd should be multiple of 2
- + vwsubu.wv v2, v2, v4 # OK
- + vwsubu.wv v2, v3, v4 # vs2 should be multiple of 2
- + vwsubu.wv v4, v2, v4 # vd overlap vs1
- + vwsubu.wv v4, v2, v5 # vd overlap vs1
- + vwsubu.wv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwadd.wv v0, v2, v4 # OK
- + vwadd.wv v1, v2, v4 # vd should be multiple of 2
- + vwadd.wv v2, v2, v4 # OK
- + vwadd.wv v2, v3, v4 # vs2 should be multiple of 2
- + vwadd.wv v4, v2, v4 # vd overlap vs1
- + vwadd.wv v4, v2, v5 # vd overlap vs1
- + vwadd.wv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwsub.wv v0, v2, v4 # OK
- + vwsub.wv v1, v2, v4 # vd should be multiple of 2
- + vwsub.wv v2, v2, v4 # OK
- + vwsub.wv v2, v3, v4 # vs2 should be multiple of 2
- + vwsub.wv v4, v2, v4 # vd overlap vs1
- + vwsub.wv v4, v2, v5 # vd overlap vs1
- + vwsub.wv v0, v2, v4, v0.t # vd overlap vm
- +
- + vfwadd.wv v0, v2, v4 # OK
- + vfwadd.wv v1, v2, v4 # vd should be multiple of 2
- + vfwadd.wv v2, v2, v4 # OK
- + vfwadd.wv v2, v3, v4 # vs2 should be multiple of 2
- + vfwadd.wv v4, v2, v4 # vd overlap vs1
- + vfwadd.wv v4, v2, v5 # vd overlap vs1
- + vfwadd.wv v0, v2, v4, v0.t # vd overlap vm
- +
- + vfwsub.wv v0, v2, v4 # OK
- + vfwsub.wv v1, v2, v4 # vd should be multiple of 2
- + vfwsub.wv v2, v2, v4 # OK
- + vfwsub.wv v2, v3, v4 # vs2 should be multiple of 2
- + vfwsub.wv v4, v2, v4 # vd overlap vs1
- + vfwsub.wv v4, v2, v5 # vd overlap vs1
- + vfwsub.wv v0, v2, v4, v0.t # vd overlap vm
- +
- + vwaddu.wx v0, v2, a1 # OK
- + vwaddu.wx v1, v2, a1 # vd should be multiple of 2
- + vwaddu.wx v2, v2, a1 # OK
- + vwaddu.wx v2, v3, a1 # vs2 should be multiple of 2
- + vwaddu.wx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwsubu.wx v0, v2, a1 # OK
- + vwsubu.wx v1, v2, a1 # vd should be multiple of 2
- + vwsubu.wx v2, v2, a1 # OK
- + vwsubu.wx v2, v3, a1 # vs2 should be multiple of 2
- + vwsubu.wx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwadd.wx v0, v2, a1 # OK
- + vwadd.wx v1, v2, a1 # vd should be multiple of 2
- + vwadd.wx v2, v2, a1 # OK
- + vwadd.wx v2, v3, a1 # vs2 should be multiple of 2
- + vwadd.wx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwsub.wx v0, v2, a1 # OK
- + vwsub.wx v1, v2, a1 # vd should be multiple of 2
- + vwsub.wx v2, v2, a1 # OK
- + vwsub.wx v2, v3, a1 # vs2 should be multiple of 2
- + vwsub.wx v0, v2, a1, v0.t # vd overlap vm
- +
- + vfwadd.wf v0, v2, fa1 # OK
- + vfwadd.wf v1, v2, fa1 # vd should be multiple of 2
- + vfwadd.wf v2, v2, fa1 # OK
- + vfwadd.wf v2, v3, fa1 # vs2 should be multiple of 2
- + vfwadd.wf v0, v2, fa1, v0.t # vd overlap vm
- +
- + vfwsub.wf v0, v2, fa1 # OK
- + vfwsub.wf v1, v2, fa1 # vd should be multiple of 2
- + vfwsub.wf v2, v2, fa1 # OK
- + vfwsub.wf v2, v3, fa1 # vs2 should be multiple of 2
- + vfwsub.wf v0, v2, fa1, v0.t # vd overlap vm
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.d b/gas/testsuite/gas/riscv/vector-insns-fail-05.d
- new file mode 100644
- index 0000000000..b13053ab06
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv -mcheck-constraints
- +#source: vector-insns-fail-05.s
- +#error_output: vector-insns-fail-05.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.l b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
- new file mode 100644
- index 0000000000..fa519ffcf9
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.l
- @@ -0,0 +1,61 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vnsrl.wv v2,v2,v4'
- +.*Error: illegal operands `vnsrl.wv v2,v3,v4'
- +.*Error: illegal operands `vnsrl.wv v3,v2,v4'
- +.*Error: illegal operands `vnsrl.wx v2,v2,a1'
- +.*Error: illegal operands `vnsrl.wx v2,v3,a1'
- +.*Error: illegal operands `vnsrl.wx v3,v2,a1'
- +.*Error: illegal operands `vnsrl.wi v2,v2,1'
- +.*Error: illegal operands `vnsrl.wi v2,v3,1'
- +.*Error: illegal operands `vnsrl.wi v3,v2,1'
- +.*Error: illegal operands `vnsra.wv v2,v2,v4'
- +.*Error: illegal operands `vnsra.wv v2,v3,v4'
- +.*Error: illegal operands `vnsra.wv v3,v2,v4'
- +.*Error: illegal operands `vnsra.wx v2,v2,a1'
- +.*Error: illegal operands `vnsra.wx v2,v3,a1'
- +.*Error: illegal operands `vnsra.wx v3,v2,a1'
- +.*Error: illegal operands `vnsra.wi v2,v2,1'
- +.*Error: illegal operands `vnsra.wi v2,v3,1'
- +.*Error: illegal operands `vnsra.wi v3,v2,1'
- +.*Error: illegal operands `vnclipu.wv v2,v2,v4'
- +.*Error: illegal operands `vnclipu.wv v2,v3,v4'
- +.*Error: illegal operands `vnclipu.wv v3,v2,v4'
- +.*Error: illegal operands `vnclipu.wx v2,v2,a1'
- +.*Error: illegal operands `vnclipu.wx v2,v3,a1'
- +.*Error: illegal operands `vnclipu.wx v3,v2,a1'
- +.*Error: illegal operands `vnclipu.wi v2,v2,1'
- +.*Error: illegal operands `vnclipu.wi v2,v3,1'
- +.*Error: illegal operands `vnclipu.wi v3,v2,1'
- +.*Error: illegal operands `vnclip.wv v2,v2,v4'
- +.*Error: illegal operands `vnclip.wv v2,v3,v4'
- +.*Error: illegal operands `vnclip.wv v3,v2,v4'
- +.*Error: illegal operands `vnclip.wx v2,v2,a1'
- +.*Error: illegal operands `vnclip.wx v2,v3,a1'
- +.*Error: illegal operands `vnclip.wx v3,v2,a1'
- +.*Error: illegal operands `vnclip.wi v2,v2,1'
- +.*Error: illegal operands `vnclip.wi v2,v3,1'
- +.*Error: illegal operands `vnclip.wi v3,v2,1'
- +.*Error: illegal operands `vfncvt.xu.f.w v2,v2'
- +.*Error: illegal operands `vfncvt.xu.f.w v2,v3'
- +.*Error: illegal operands `vfncvt.xu.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.x.f.w v2,v2'
- +.*Error: illegal operands `vfncvt.x.f.w v2,v3'
- +.*Error: illegal operands `vfncvt.x.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v2'
- +.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v3'
- +.*Error: illegal operands `vfncvt.rtz.xu.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v2'
- +.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v3'
- +.*Error: illegal operands `vfncvt.rtz.x.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.f.xu.w v2,v2'
- +.*Error: illegal operands `vfncvt.f.xu.w v2,v3'
- +.*Error: illegal operands `vfncvt.f.xu.w v3,v2'
- +.*Error: illegal operands `vfncvt.f.x.w v2,v2'
- +.*Error: illegal operands `vfncvt.f.x.w v2,v3'
- +.*Error: illegal operands `vfncvt.f.x.w v3,v2'
- +.*Error: illegal operands `vfncvt.f.f.w v2,v2'
- +.*Error: illegal operands `vfncvt.f.f.w v2,v3'
- +.*Error: illegal operands `vfncvt.f.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.rod.f.f.w v2,v2'
- +.*Error: illegal operands `vfncvt.rod.f.f.w v2,v3'
- +.*Error: illegal operands `vfncvt.rod.f.f.w v3,v2'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.s b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
- new file mode 100644
- index 0000000000..2ec027299c
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
- @@ -0,0 +1,133 @@
- +# Narrowing Vector Arithmetic Instructions
- +
- + vnsrl.wv v0, v2, v4 # OK
- + vnsrl.wv v2, v2, v4 # vd overlap vs2
- + vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
- + vnsrl.wv v3, v2, v4 # vd overlap vs2
- + vnsrl.wv v4, v2, v4 # OK
- + vnsrl.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnsrl.wx v0, v2, a1 # OK
- + vnsrl.wx v2, v2, a1 # vd overlap vs2
- + vnsrl.wx v2, v3, a1 # vs2 should be multiple of 2
- + vnsrl.wx v3, v2, a1 # vd overlap vs2
- + vnsrl.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnsrl.wi v0, v2, 1 # OK
- + vnsrl.wi v2, v2, 1 # vd overlap vs2
- + vnsrl.wi v2, v3, 1 # vs2 should be multiple of 2
- + vnsrl.wi v3, v2, 1 # vd overlap vs2
- + vnsrl.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnsra.wv v0, v2, v4 # OK
- + vnsra.wv v2, v2, v4 # vd overlap vs2
- + vnsra.wv v2, v3, v4 # vs2 should be multiple of 2
- + vnsra.wv v3, v2, v4 # vd overlap vs2
- + vnsra.wv v4, v2, v4 # OK
- + vnsra.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnsra.wx v0, v2, a1 # OK
- + vnsra.wx v2, v2, a1 # vd overlap vs2
- + vnsra.wx v2, v3, a1 # vs2 should be multiple of 2
- + vnsra.wx v3, v2, a1 # vd overlap vs2
- + vnsra.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnsra.wi v0, v2, 1 # OK
- + vnsra.wi v2, v2, 1 # vd overlap vs2
- + vnsra.wi v2, v3, 1 # vs2 should be multiple of 2
- + vnsra.wi v3, v2, 1 # vd overlap vs2
- + vnsra.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnclipu.wv v0, v2, v4 # OK
- + vnclipu.wv v2, v2, v4 # vd overlap vs2
- + vnclipu.wv v2, v3, v4 # vs2 should be multiple of 2
- + vnclipu.wv v3, v2, v4 # vd overlap vs2
- + vnclipu.wv v4, v2, v4 # OK
- + vnclipu.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnclipu.wx v0, v2, a1 # OK
- + vnclipu.wx v2, v2, a1 # vd overlap vs2
- + vnclipu.wx v2, v3, a1 # vs2 should be multiple of 2
- + vnclipu.wx v3, v2, a1 # vd overlap vs2
- + vnclipu.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnclipu.wi v0, v2, 1 # OK
- + vnclipu.wi v2, v2, 1 # vd overlap vs2
- + vnclipu.wi v2, v3, 1 # vs2 should be multiple of 2
- + vnclipu.wi v3, v2, 1 # vd overlap vs2
- + vnclipu.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnclip.wv v0, v2, v4 # OK
- + vnclip.wv v2, v2, v4 # vd overlap vs2
- + vnclip.wv v2, v3, v4 # vs2 should be multiple of 2
- + vnclip.wv v3, v2, v4 # vd overlap vs2
- + vnclip.wv v4, v2, v4 # OK
- + vnclip.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnclip.wx v0, v2, a1 # OK
- + vnclip.wx v2, v2, a1 # vd overlap vs2
- + vnclip.wx v2, v3, a1 # vs2 should be multiple of 2
- + vnclip.wx v3, v2, a1 # vd overlap vs2
- + vnclip.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vnclip.wi v0, v2, 1 # OK
- + vnclip.wi v2, v2, 1 # vd overlap vs2
- + vnclip.wi v2, v3, 1 # vs2 should be multiple of 2
- + vnclip.wi v3, v2, 1 # vd overlap vs2
- + vnclip.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vfncvt.xu.f.w v0, v2 # OK
- + vfncvt.xu.f.w v2, v2 # vd overlap vs2
- + vfncvt.xu.f.w v2, v3 # vs2 should be multiple of 2
- + vfncvt.xu.f.w v3, v2 # vd overlap vs2
- + vfncvt.xu.f.w v4, v2 # OK
- + vfncvt.xu.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vfncvt.x.f.w v0, v2 # OK
- + vfncvt.x.f.w v2, v2 # vd overlap vs2
- + vfncvt.x.f.w v2, v3 # vs2 should be multiple of 2
- + vfncvt.x.f.w v3, v2 # vd overlap vs2
- + vfncvt.x.f.w v4, v2 # OK
- + vfncvt.x.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vfncvt.rtz.xu.f.w v0, v2 # OK
- + vfncvt.rtz.xu.f.w v2, v2 # vd overlap vs2
- + vfncvt.rtz.xu.f.w v2, v3 # vs2 should be multiple of 2
- + vfncvt.rtz.xu.f.w v3, v2 # vd overlap vs2
- + vfncvt.rtz.xu.f.w v4, v2 # OK
- + vfncvt.rtz.xu.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vfncvt.rtz.x.f.w v0, v2 # OK
- + vfncvt.rtz.x.f.w v2, v2 # vd overlap vs2
- + vfncvt.rtz.x.f.w v2, v3 # vs2 should be multiple of 2
- + vfncvt.rtz.x.f.w v3, v2 # vd overlap vs2
- + vfncvt.rtz.x.f.w v4, v2 # OK
- + vfncvt.rtz.x.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vfncvt.f.xu.w v0, v2 # OK
- + vfncvt.f.xu.w v2, v2 # vd overlap vs2
- + vfncvt.f.xu.w v2, v3 # vs2 should be multiple of 2
- + vfncvt.f.xu.w v3, v2 # vd overlap vs2
- + vfncvt.f.xu.w v4, v2 # OK
- + vfncvt.f.xu.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vfncvt.f.x.w v0, v2 # OK
- + vfncvt.f.x.w v2, v2 # vd overlap vs2
- + vfncvt.f.x.w v2, v3 # vs2 should be multiple of 2
- + vfncvt.f.x.w v3, v2 # vd overlap vs2
- + vfncvt.f.x.w v4, v2 # OK
- + vfncvt.f.x.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vfncvt.f.f.w v0, v2 # OK
- + vfncvt.f.f.w v2, v2 # vd overlap vs2
- + vfncvt.f.f.w v2, v3 # vs2 should be multiple of 2
- + vfncvt.f.f.w v3, v2 # vd overlap vs2
- + vfncvt.f.f.w v4, v2 # OK
- + vfncvt.f.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- +
- + vfncvt.rod.f.f.w v0, v2 # OK
- + vfncvt.rod.f.f.w v2, v2 # vd overlap vs2
- + vfncvt.rod.f.f.w v2, v3 # vs2 should be multiple of 2
- + vfncvt.rod.f.f.w v3, v2 # vd overlap vs2
- + vfncvt.rod.f.f.w v4, v2 # OK
- + vfncvt.rod.f.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.d b/gas/testsuite/gas/riscv/vector-insns-fail-06.d
- new file mode 100644
- index 0000000000..a2a2220d68
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv -mcheck-constraints
- +#source: vector-insns-fail-06.s
- +#error_output: vector-insns-fail-06.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.l b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
- new file mode 100644
- index 0000000000..9a86dd37b5
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
- @@ -0,0 +1,22 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `viota.m v2,v2'
- +.*Error: illegal operands `viota.m v0,v2,v0.t'
- +.*Error: illegal operands `vslideup.vx v2,v2,a4'
- +.*Error: illegal operands `vslideup.vi v2,v2,1'
- +.*Error: illegal operands `vslide1up.vx v2,v2,a4'
- +.*Error: illegal operands `vfslide1up.vf v2,v2,fa4'
- +.*Error: illegal operands `vrgather.vv v2,v2,v4'
- +.*Error: illegal operands `vrgather.vv v4,v2,v4'
- +.*Error: illegal operands `vrgather.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vrgather.vx v2,v2,a4'
- +.*Error: illegal operands `vrgather.vx v0,v2,a4,v0.t'
- +.*Error: illegal operands `vrgather.vi v2,v2,1'
- +.*Error: illegal operands `vrgather.vi v0,v2,1,v0.t'
- +.*Error: illegal operands `vcompress.vm v2,v2,v4'
- +.*Error: illegal operands `vcompress.vm v4,v2,v4'
- +.*Error: illegal operands `vmv2r.v v1,v2'
- +.*Error: illegal operands `vmv2r.v v2,v3'
- +.*Error: illegal operands `vmv4r.v v2,v4'
- +.*Error: illegal operands `vmv4r.v v4,v7'
- +.*Error: illegal operands `vmv8r.v v6,v8'
- +.*Error: illegal operands `vmv8r.v v8,v12'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.s b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
- new file mode 100644
- index 0000000000..df0edd44c9
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
- @@ -0,0 +1,67 @@
- +# Vector Iota Instruction
- +# Vector Slideup Instructions
- +# Vector Slide1up
- +# Vector Register Gather Instruction
- +# Vector Compress Instruction
- +# Vector Load/Store Whole Register Instructions
- +# Whole Vector Register Move
- +
- + viota.m v0, v2 # OK
- + viota.m v2, v2 # vd overlap vs2
- + viota.m v0, v2, v0.t # vd overlap vm
- +
- + vslideup.vx v0, v2, a4 # OK
- + vslideup.vx v1, v2, a4 # OK
- + vslideup.vx v2, v2, a4 # vd overlap vs2
- + vslideup.vx v0, v2, a4, v0.t # vd overlap vm
- +
- + vslideup.vi v0, v2, 1 # OK
- + vslideup.vi v1, v2, 1 # OK
- + vslideup.vi v2, v2, 1 # vd overlap vs2
- + vslideup.vi v0, v2, 1, v0.t # vd overlap vm
- +
- + vslide1up.vx v0, v2, a4 # OK
- + vslide1up.vx v1, v2, a4 # OK
- + vslide1up.vx v2, v2, a4 # vd overlap vs2
- + vslide1up.vx v0, v2, a4, v0.t # vd overlap vm
- +
- + vfslide1up.vf v0, v2, fa4 # OK
- + vfslide1up.vf v1, v2, fa4 # OK
- + vfslide1up.vf v2, v2, fa4 # vd overlap vs2
- + vfslide1up.vf v0, v2, fa4, v0.t # vd overlap vm
- +
- + vrgather.vv v0, v2, v4 # OK
- + vrgather.vv v1, v2, v4 # OK
- + vrgather.vv v2, v2, v4 # vd overlap vs2
- + vrgather.vv v4, v2, v4 # vd overlap vs1
- + vrgather.vv v0, v2, v4, v0.t # vd overlap vm
- +
- + vrgather.vx v0, v2, a4 # OK
- + vrgather.vx v1, v2, a4 # OK
- + vrgather.vx v2, v2, a4 # vd overlap vs2
- + vrgather.vx v0, v2, a4, v0.t # vd overlap vm
- +
- + vrgather.vi v0, v2, 1 # OK
- + vrgather.vi v1, v2, 1 # OK
- + vrgather.vi v2, v2, 1 # vd overlap vs2
- + vrgather.vi v0, v2, 1, v0.t # vd overlap vm
- +
- + vcompress.vm v0, v2, v4 # OK
- + vcompress.vm v1, v2, v4 # OK
- + vcompress.vm v2, v2, v4 # vd overlap vs2
- + vcompress.vm v4, v2, v4 # vd overlap vs1
- +
- + vmv1r.v v0, v1 # OK
- + vmv1r.v v2, v3 # OK
- +
- + vmv2r.v v0, v2 # OK
- + vmv2r.v v1, v2 # vd must be aligned to 2
- + vmv2r.v v2, v3 # vs2 must be aligned to 2
- +
- + vmv4r.v v0, v4 # OK
- + vmv4r.v v2, v4 # vd must be aligned to 4
- + vmv4r.v v4, v7 # vs2 must be aligned to 4
- +
- + vmv8r.v v0, v8 # OK
- + vmv8r.v v6, v8 # vd must be aligned to 8
- + vmv8r.v v8, v12 # vs2 must be aligned to 8
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d
- new file mode 100644
- index 0000000000..a730a2e941
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.d
- @@ -0,0 +1,20 @@
- +#as: -march=rv32iv
- +#source: vector-insns-fail-zvediv.s
- +#warning_output: vector-insns-fail-zvediv.l
- +#objdump: -dr
- +
- +.*:[ ]+file format .*
- +
- +
- +Disassembly of section .text:
- +
- +0+000 <.text>:
- +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d1
- +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
- +[ ]+[0-9a-f]+:[ ]+3005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d8
- +[ ]+[0-9a-f]+:[ ]+4ff5f557[ ]+vsetvli[ ]+a0,a1,1279
- +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d1
- +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d1
- +[ ]+[0-9a-f]+:[ ]+1005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d2
- +[ ]+[0-9a-f]+:[ ]+2005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d4
- +[ ]+[0-9a-f]+:[ ]+3005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d8
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l
- new file mode 100644
- index 0000000000..2b0b73bc64
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.l
- @@ -0,0 +1,6 @@
- +.*Assembler messages:
- +.*2: Warning: vediv is set but Zvediv extension isn't enabled
- +.*3: Warning: vediv is set but Zvediv extension isn't enabled
- +.*7: Warning: vediv is set but Zvediv extension isn't enabled
- +.*8: Warning: vediv is set but Zvediv extension isn't enabled
- +.*9: Warning: vediv is set but Zvediv extension isn't enabled
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s
- new file mode 100644
- index 0000000000..834cc17c4a
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvediv.s
- @@ -0,0 +1,9 @@
- + vsetvli a0, a1, 0
- + vsetvli a0, a1, 0x7ff
- + vsetvli a0, a1, 0x300
- + vsetvli a0, a1, 0x4ff
- + vsetvli a0, a1, e8, m1
- + vsetvli a0, a1, e8, m1, d1
- + vsetvli a0, a1, e8, m1, d2
- + vsetvli a0, a1, e8, m1, d4
- + vsetvli a0, a1, e8, m1, d8
- diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
- new file mode 100644
- index 0000000000..4d33fe7d59
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
- @@ -0,0 +1,29 @@
- +#as: -march=rv32iv
- +#objdump: -dr
- +
- +.*:[ ]+file format .*
- +
- +
- +Disassembly of section .text:
- +
- +0+000 <.text>:
- +[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+vmslt.vx[ ]+v4,v8,a1
- +[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
- +[ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t
- +[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
- +[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
- +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
- +[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
- +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
- +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
- +[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
- +[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1
- +[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
- +[ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t
- +[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
- +[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
- +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
- +[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
- +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
- +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
- +[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
- diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
- new file mode 100644
- index 0000000000..afbb7ccb36
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
- @@ -0,0 +1,9 @@
- + vmsge.vx v4, v8, a1 # unmasked va >= x
- + vmsge.vx v8, v12, a2, v0.t # masked va >= x, vd != v0
- + vmsge.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0
- + vmsge.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd
- +
- + vmsgeu.vx v4, v8, a1 # unmasked va >= x
- + vmsgeu.vx v8, v12, a2, v0.t # masked va >= x, vd != v0
- + vmsgeu.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0
- + vmsgeu.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd
- diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
- new file mode 100644
- index 0000000000..5e7267c3f8
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns.d
- @@ -0,0 +1,2384 @@
- +#as: -march=rv32iafv_zvediv_zvqmac
- +#objdump: -dr
- +
- +.*:[ ]+file format .*
- +
- +
- +Disassembly of section .text:
- +
- +0+000 <.text>:
- +[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2
- +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu,d1
- +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
- +[ ]+[0-9a-f]+:[ ]+2055f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu,d4
- +[ ]+[0-9a-f]+:[ ]+3175f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu,d8
- +[ ]+[0-9a-f]+:[ ]+31b5f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu,d8
- +[ ]+[0-9a-f]+:[ ]+31f5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu,d8
- +[ ]+[0-9a-f]+:[ ]+31c5f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu,d8
- +[ ]+[0-9a-f]+:[ ]+33f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu,d8
- +[ ]+[0-9a-f]+:[ ]+13a5f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu,d2
- +[ ]+[0-9a-f]+:[ ]+2355f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu,d4
- +[ ]+[0-9a-f]+:[ ]+2555f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu,d4
- +[ ]+[0-9a-f]+:[ ]+2955f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma,d4
- +[ ]+[0-9a-f]+:[ ]+2155f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
- +[ ]+[0-9a-f]+:[ ]+2155f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
- +[ ]+[0-9a-f]+:[ ]+2d55f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma,d4
- +[ ]+[0-9a-f]+:[ ]+2955f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma,d4
- +[ ]+[0-9a-f]+:[ ]+2555f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu,d4
- +[ ]+[0-9a-f]+:[ ]+2155f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu,d4
- +[ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+00050207[ ]+vle8.v[ ]+v4,\(a0\),v0.t
- +[ ]+[0-9a-f]+:[ ]+02050227[ ]+vse8.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02050227[ ]+vse8.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+00050227[ ]+vse8.v[ ]+v4,\(a0\),v0.t
- +[ ]+[0-9a-f]+:[ ]+02055207[ ]+vle16.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02055207[ ]+vle16.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+00055207[ ]+vle16.v[ ]+v4,\(a0\),v0.t
- +[ ]+[0-9a-f]+:[ ]+02055227[ ]+vse16.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02055227[ ]+vse16.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+00055227[ ]+vse16.v[ ]+v4,\(a0\),v0.t
- +[ ]+[0-9a-f]+:[ ]+02056207[ ]+vle32.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02056207[ ]+vle32.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+00056207[ ]+vle32.v[ ]+v4,\(a0\),v0.t
- +[ ]+[0-9a-f]+:[ ]+02056227[ ]+vse32.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02056227[ ]+vse32.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+00056227[ ]+vse32.v[ ]+v4,\(a0\),v0.t
- +[ ]+[0-9a-f]+:[ ]+02057207[ ]+vle64.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+02057207[ ]+vle64.v[ ]+v4,\(a0\)
- +[ ]+[0-9a-f]+:[ ]+00057207[ ]+vle64.v[ ]+v4,\(a0\),v0.t
- +[ ]+[0-9a-f]+:[ ]+02057227[ ]+vse64.v[ ]+v4,\(a0\)
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- +[ ]+[0-9a-f]+:[ ]+3e8fb257[ ]+vslidedown.vi[ ]+v4,v8,31
- +[ ]+[0-9a-f]+:[ ]+3885c257[ ]+vslideup.vx[ ]+v4,v8,a1,v0.t
- +[ ]+[0-9a-f]+:[ ]+38803257[ ]+vslideup.vi[ ]+v4,v8,0,v0.t
- +[ ]+[0-9a-f]+:[ ]+388fb257[ ]+vslideup.vi[ ]+v4,v8,31,v0.t
- +[ ]+[0-9a-f]+:[ ]+3c85c257[ ]+vslidedown.vx[ ]+v4,v8,a1,v0.t
- +[ ]+[0-9a-f]+:[ ]+3c803257[ ]+vslidedown.vi[ ]+v4,v8,0,v0.t
- +[ ]+[0-9a-f]+:[ ]+3c8fb257[ ]+vslidedown.vi[ ]+v4,v8,31,v0.t
- +[ ]+[0-9a-f]+:[ ]+3a85e257[ ]+vslide1up.vx[ ]+v4,v8,a1
- +[ ]+[0-9a-f]+:[ ]+3e85e257[ ]+vslide1down.vx[ ]+v4,v8,a1
- +[ ]+[0-9a-f]+:[ ]+3885e257[ ]+vslide1up.vx[ ]+v4,v8,a1,v0.t
- +[ ]+[0-9a-f]+:[ ]+3c85e257[ ]+vslide1down.vx[ ]+v4,v8,a1,v0.t
- +[ ]+[0-9a-f]+:[ ]+3a85d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1
- +[ ]+[0-9a-f]+:[ ]+3e85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1
- +[ ]+[0-9a-f]+:[ ]+3885d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1,v0.t
- +[ ]+[0-9a-f]+:[ ]+3c85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1,v0.t
- +[ ]+[0-9a-f]+:[ ]+32860257[ ]+vrgather.vv[ ]+v4,v8,v12
- +[ ]+[0-9a-f]+:[ ]+3285c257[ ]+vrgather.vx[ ]+v4,v8,a1
- +[ ]+[0-9a-f]+:[ ]+32803257[ ]+vrgather.vi[ ]+v4,v8,0
- +[ ]+[0-9a-f]+:[ ]+328fb257[ ]+vrgather.vi[ ]+v4,v8,31
- +[ ]+[0-9a-f]+:[ ]+30860257[ ]+vrgather.vv[ ]+v4,v8,v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+3085c257[ ]+vrgather.vx[ ]+v4,v8,a1,v0.t
- +[ ]+[0-9a-f]+:[ ]+30803257[ ]+vrgather.vi[ ]+v4,v8,0,v0.t
- +[ ]+[0-9a-f]+:[ ]+308fb257[ ]+vrgather.vi[ ]+v4,v8,31,v0.t
- +[ ]+[0-9a-f]+:[ ]+5e862257[ ]+vcompress.vm[ ]+v4,v8,v12
- +[ ]+[0-9a-f]+:[ ]+9e2030d7[ ]+vmv1r.v[ ]+v1,v2
- +[ ]+[0-9a-f]+:[ ]+9e40b157[ ]+vmv2r.v[ ]+v2,v4
- +[ ]+[0-9a-f]+:[ ]+9e81b257[ ]+vmv4r.v[ ]+v4,v8
- +[ ]+[0-9a-f]+:[ ]+9e83b057[ ]+vmv8r.v[ ]+v0,v8
- +[ ]+[0-9a-f]+:[ ]+e6860257[ ]+vdot.vv[ ]+v4,v8,v12
- +[ ]+[0-9a-f]+:[ ]+e2860257[ ]+vdotu.vv[ ]+v4,v8,v12
- +[ ]+[0-9a-f]+:[ ]+e6861257[ ]+vfdot.vv[ ]+v4,v8,v12
- +[ ]+[0-9a-f]+:[ ]+e4860257[ ]+vdot.vv[ ]+v4,v8,v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+e0860257[ ]+vdotu.vv[ ]+v4,v8,v12,v0.t
- +[ ]+[0-9a-f]+:[ ]+e4861257[ ]+vfdot.vv[ ]+v4,v8,v12,v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
- new file mode 100644
- index 0000000000..8b9a894418
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns.s
- @@ -0,0 +1,2718 @@
- + vsetvl a0, a1, a2
- + vsetvli a0, a1, 0
- + vsetvli a0, a1, 0x7ff
- + vsetvli a0, a1, e16,m2,d4
- + vsetvli a0, a1, e256, m8, d8
- + vsetvli a0, a1, e512, m8, d8
- + vsetvli a0, a1, e1024, m8, d8
- + vsetvli a0, a1, e1024, m1, d8
- + vsetvli a0, a1, e1024, mf2, d8
- + vsetvli a0, a1, e512, mf4, d2
- + vsetvli a0, a1, e256, mf8, d4
- + vsetvli a0, a1, e256, m2, ta, d4
- + vsetvli a0, a1, e256, m2, ma, d4
- + vsetvli a0, a1, e256, m2, tu, d4
- + vsetvli a0, a1, e256, m2, mu, d4
- + vsetvli a0, a1, e256, m2, ta,ma, d4
- + vsetvli a0, a1, e256, m2, tu,ma, d4
- + vsetvli a0, a1, e256, m2, ta,mu, d4
- + vsetvli a0, a1, e256, m2, tu,mu, d4
- +
- + vle8.v v4, (a0)
- + vle8.v v4, 0(a0)
- + vle8.v v4, (a0), v0.t
- + vse8.v v4, (a0)
- + vse8.v v4, 0(a0)
- + vse8.v v4, (a0), v0.t
- +
- + vle16.v v4, (a0)
- + vle16.v v4, 0(a0)
- + vle16.v v4, (a0), v0.t
- + vse16.v v4, (a0)
- + vse16.v v4, 0(a0)
- + vse16.v v4, (a0), v0.t
- +
- + vle32.v v4, (a0)
- + vle32.v v4, 0(a0)
- + vle32.v v4, (a0), v0.t
- + vse32.v v4, (a0)
- + vse32.v v4, 0(a0)
- + vse32.v v4, (a0), v0.t
- +
- + vle64.v v4, (a0)
- + vle64.v v4, 0(a0)
- + vle64.v v4, (a0), v0.t
- + vse64.v v4, (a0)
- + vse64.v v4, 0(a0)
- + vse64.v v4, (a0), v0.t
- +
- + vle128.v v4, (a0)
- + vle128.v v4, 0(a0)
- + vle128.v v4, (a0), v0.t
- + vse128.v v4, (a0)
- + vse128.v v4, 0(a0)
- + vse128.v v4, (a0), v0.t
- +
- + vle256.v v4, (a0)
- + vle256.v v4, 0(a0)
- + vle256.v v4, (a0), v0.t
- + vse256.v v4, (a0)
- + vse256.v v4, 0(a0)
- + vse256.v v4, (a0), v0.t
- +
- + vle512.v v4, (a0)
- + vle512.v v4, 0(a0)
- + vle512.v v4, (a0), v0.t
- + vse512.v v4, (a0)
- + vse512.v v4, 0(a0)
- + vse512.v v4, (a0), v0.t
- +
- + vle1024.v v4, (a0)
- + vle1024.v v4, 0(a0)
- + vle1024.v v4, (a0), v0.t
- + vse1024.v v4, (a0)
- + vse1024.v v4, 0(a0)
- + vse1024.v v4, (a0), v0.t
- +
- + vlse8.v v4, (a0), a1
- + vlse8.v v4, 0(a0), a1
- + vlse8.v v4, (a0), a1, v0.t
- + vsse8.v v4, (a0), a1
- + vsse8.v v4, 0(a0), a1
- + vsse8.v v4, (a0), a1, v0.t
- +
- + vlse16.v v4, (a0), a1
- + vlse16.v v4, 0(a0), a1
- + vlse16.v v4, (a0), a1, v0.t
- + vsse16.v v4, (a0), a1
- + vsse16.v v4, 0(a0), a1
- + vsse16.v v4, (a0), a1, v0.t
- +
- + vlse32.v v4, (a0), a1
- + vlse32.v v4, 0(a0), a1
- + vlse32.v v4, (a0), a1, v0.t
- + vsse32.v v4, (a0), a1
- + vsse32.v v4, 0(a0), a1
- + vsse32.v v4, (a0), a1, v0.t
- +
- + vlse64.v v4, (a0), a1
- + vlse64.v v4, 0(a0), a1
- + vlse64.v v4, (a0), a1, v0.t
- + vsse64.v v4, (a0), a1
- + vsse64.v v4, 0(a0), a1
- + vsse64.v v4, (a0), a1, v0.t
- +
- + vlse128.v v4, (a0), a1
- + vlse128.v v4, 0(a0), a1
- + vlse128.v v4, (a0), a1, v0.t
- + vsse128.v v4, (a0), a1
- + vsse128.v v4, 0(a0), a1
- + vsse128.v v4, (a0), a1, v0.t
- +
- + vlse256.v v4, (a0), a1
- + vlse256.v v4, 0(a0), a1
- + vlse256.v v4, (a0), a1, v0.t
- + vsse256.v v4, (a0), a1
- + vsse256.v v4, 0(a0), a1
- + vsse256.v v4, (a0), a1, v0.t
- +
- + vlse512.v v4, (a0), a1
- + vlse512.v v4, 0(a0), a1
- + vlse512.v v4, (a0), a1, v0.t
- + vsse512.v v4, (a0), a1
- + vsse512.v v4, 0(a0), a1
- + vsse512.v v4, (a0), a1, v0.t
- +
- + vlse1024.v v4, (a0), a1
- + vlse1024.v v4, 0(a0), a1
- + vlse1024.v v4, (a0), a1, v0.t
- + vsse1024.v v4, (a0), a1
- + vsse1024.v v4, 0(a0), a1
- + vsse1024.v v4, (a0), a1, v0.t
- +
- + vlxei8.v v4, (a0), v12
- + vlxei8.v v4, 0(a0), v12
- + vlxei8.v v4, (a0), v12, v0.t
- + vsxei8.v v4, (a0), v12
- + vsxei8.v v4, 0(a0), v12
- + vsxei8.v v4, (a0), v12, v0.t
- + vsuxei8.v v4, (a0), v12
- + vsuxei8.v v4, 0(a0), v12
- + vsuxei8.v v4, (a0), v12, v0.t
- +
- + vlxei16.v v4, (a0), v12
- + vlxei16.v v4, 0(a0), v12
- + vlxei16.v v4, (a0), v12, v0.t
- + vsxei16.v v4, (a0), v12
- + vsxei16.v v4, 0(a0), v12
- + vsxei16.v v4, (a0), v12, v0.t
- + vsuxei16.v v4, (a0), v12
- + vsuxei16.v v4, 0(a0), v12
- + vsuxei16.v v4, (a0), v12, v0.t
- +
- + vlxei32.v v4, (a0), v12
- + vlxei32.v v4, 0(a0), v12
- + vlxei32.v v4, (a0), v12, v0.t
- + vsxei32.v v4, (a0), v12
- + vsxei32.v v4, 0(a0), v12
- + vsxei32.v v4, (a0), v12, v0.t
- + vsuxei32.v v4, (a0), v12
- + vsuxei32.v v4, 0(a0), v12
- + vsuxei32.v v4, (a0), v12, v0.t
- +
- + vlxei64.v v4, (a0), v12
- + vlxei64.v v4, 0(a0), v12
- + vlxei64.v v4, (a0), v12, v0.t
- + vsxei64.v v4, (a0), v12
- + vsxei64.v v4, 0(a0), v12
- + vsxei64.v v4, (a0), v12, v0.t
- + vsuxei64.v v4, (a0), v12
- + vsuxei64.v v4, 0(a0), v12
- + vsuxei64.v v4, (a0), v12, v0.t
- +
- + vlxei128.v v4, (a0), v12
- + vlxei128.v v4, 0(a0), v12
- + vlxei128.v v4, (a0), v12, v0.t
- + vsxei128.v v4, (a0), v12
- + vsxei128.v v4, 0(a0), v12
- + vsxei128.v v4, (a0), v12, v0.t
- + vsuxei128.v v4, (a0), v12
- + vsuxei128.v v4, 0(a0), v12
- + vsuxei128.v v4, (a0), v12, v0.t
- +
- + vlxei256.v v4, (a0), v12
- + vlxei256.v v4, 0(a0), v12
- + vlxei256.v v4, (a0), v12, v0.t
- + vsxei256.v v4, (a0), v12
- + vsxei256.v v4, 0(a0), v12
- + vsxei256.v v4, (a0), v12, v0.t
- + vsuxei256.v v4, (a0), v12
- + vsuxei256.v v4, 0(a0), v12
- + vsuxei256.v v4, (a0), v12, v0.t
- +
- + vlxei512.v v4, (a0), v12
- + vlxei512.v v4, 0(a0), v12
- + vlxei512.v v4, (a0), v12, v0.t
- + vsxei512.v v4, (a0), v12
- + vsxei512.v v4, 0(a0), v12
- + vsxei512.v v4, (a0), v12, v0.t
- + vsuxei512.v v4, (a0), v12
- + vsuxei512.v v4, 0(a0), v12
- + vsuxei512.v v4, (a0), v12, v0.t
- +
- + vlxei1024.v v4, (a0), v12
- + vlxei1024.v v4, 0(a0), v12
- + vlxei1024.v v4, (a0), v12, v0.t
- + vsxei1024.v v4, (a0), v12
- + vsxei1024.v v4, 0(a0), v12
- + vsxei1024.v v4, (a0), v12, v0.t
- + vsuxei1024.v v4, (a0), v12
- + vsuxei1024.v v4, 0(a0), v12
- + vsuxei1024.v v4, (a0), v12, v0.t
- +
- + vle8ff.v v4, (a0)
- + vle8ff.v v4, 0(a0)
- + vle8ff.v v4, (a0), v0.t
- +
- + vle16ff.v v4, (a0)
- + vle16ff.v v4, 0(a0)
- + vle16ff.v v4, (a0), v0.t
- +
- + vle32ff.v v4, (a0)
- + vle32ff.v v4, 0(a0)
- + vle32ff.v v4, (a0), v0.t
- +
- + vle64ff.v v4, (a0)
- + vle64ff.v v4, 0(a0)
- + vle64ff.v v4, (a0), v0.t
- +
- + vle128ff.v v4, (a0)
- + vle128ff.v v4, 0(a0)
- + vle128ff.v v4, (a0), v0.t
- +
- + vle256ff.v v4, (a0)
- + vle256ff.v v4, 0(a0)
- + vle256ff.v v4, (a0), v0.t
- +
- + vle512ff.v v4, (a0)
- + vle512ff.v v4, 0(a0)
- + vle512ff.v v4, (a0), v0.t
- +
- + vle1024ff.v v4, (a0)
- + vle1024ff.v v4, 0(a0)
- + vle1024ff.v v4, (a0), v0.t
- +
- + vlseg2e8.v v4, (a0)
- + vlseg2e8.v v4, 0(a0)
- + vlseg2e8.v v4, (a0), v0.t
- + vsseg2e8.v v4, (a0)
- + vsseg2e8.v v4, 0(a0)
- + vsseg2e8.v v4, (a0), v0.t
- +
- + vlseg3e8.v v4, (a0)
- + vlseg3e8.v v4, 0(a0)
- + vlseg3e8.v v4, (a0), v0.t
- + vsseg3e8.v v4, (a0)
- + vsseg3e8.v v4, 0(a0)
- + vsseg3e8.v v4, (a0), v0.t
- +
- + vlseg4e8.v v4, (a0)
- + vlseg4e8.v v4, 0(a0)
- + vlseg4e8.v v4, (a0), v0.t
- + vsseg4e8.v v4, (a0)
- + vsseg4e8.v v4, 0(a0)
- + vsseg4e8.v v4, (a0), v0.t
- +
- + vlseg5e8.v v4, (a0)
- + vlseg5e8.v v4, 0(a0)
- + vlseg5e8.v v4, (a0), v0.t
- + vsseg5e8.v v4, (a0)
- + vsseg5e8.v v4, 0(a0)
- + vsseg5e8.v v4, (a0), v0.t
- +
- + vlseg6e8.v v4, (a0)
- + vlseg6e8.v v4, 0(a0)
- + vlseg6e8.v v4, (a0), v0.t
- + vsseg6e8.v v4, (a0)
- + vsseg6e8.v v4, 0(a0)
- + vsseg6e8.v v4, (a0), v0.t
- +
- + vlseg7e8.v v4, (a0)
- + vlseg7e8.v v4, 0(a0)
- + vlseg7e8.v v4, (a0), v0.t
- + vsseg7e8.v v4, (a0)
- + vsseg7e8.v v4, 0(a0)
- + vsseg7e8.v v4, (a0), v0.t
- +
- + vlseg8e8.v v4, (a0)
- + vlseg8e8.v v4, 0(a0)
- + vlseg8e8.v v4, (a0), v0.t
- + vsseg8e8.v v4, (a0)
- + vsseg8e8.v v4, 0(a0)
- + vsseg8e8.v v4, (a0), v0.t
- +
- + vlseg2e16.v v4, (a0)
- + vlseg2e16.v v4, 0(a0)
- + vlseg2e16.v v4, (a0), v0.t
- + vsseg2e16.v v4, (a0)
- + vsseg2e16.v v4, 0(a0)
- + vsseg2e16.v v4, (a0), v0.t
- +
- + vlseg3e16.v v4, (a0)
- + vlseg3e16.v v4, 0(a0)
- + vlseg3e16.v v4, (a0), v0.t
- + vsseg3e16.v v4, (a0)
- + vsseg3e16.v v4, 0(a0)
- + vsseg3e16.v v4, (a0), v0.t
- +
- + vlseg4e16.v v4, (a0)
- + vlseg4e16.v v4, 0(a0)
- + vlseg4e16.v v4, (a0), v0.t
- + vsseg4e16.v v4, (a0)
- + vsseg4e16.v v4, 0(a0)
- + vsseg4e16.v v4, (a0), v0.t
- +
- + vlseg5e16.v v4, (a0)
- + vlseg5e16.v v4, 0(a0)
- + vlseg5e16.v v4, (a0), v0.t
- + vsseg5e16.v v4, (a0)
- + vsseg5e16.v v4, 0(a0)
- + vsseg5e16.v v4, (a0), v0.t
- +
- + vlseg6e16.v v4, (a0)
- + vlseg6e16.v v4, 0(a0)
- + vlseg6e16.v v4, (a0), v0.t
- + vsseg6e16.v v4, (a0)
- + vsseg6e16.v v4, 0(a0)
- + vsseg6e16.v v4, (a0), v0.t
- +
- + vlseg7e16.v v4, (a0)
- + vlseg7e16.v v4, 0(a0)
- + vlseg7e16.v v4, (a0), v0.t
- + vsseg7e16.v v4, (a0)
- + vsseg7e16.v v4, 0(a0)
- + vsseg7e16.v v4, (a0), v0.t
- +
- + vlseg8e16.v v4, (a0)
- + vlseg8e16.v v4, 0(a0)
- + vlseg8e16.v v4, (a0), v0.t
- + vsseg8e16.v v4, (a0)
- + vsseg8e16.v v4, 0(a0)
- + vsseg8e16.v v4, (a0), v0.t
- +
- + vlseg2e32.v v4, (a0)
- + vlseg2e32.v v4, 0(a0)
- + vlseg2e32.v v4, (a0), v0.t
- + vsseg2e32.v v4, (a0)
- + vsseg2e32.v v4, 0(a0)
- + vsseg2e32.v v4, (a0), v0.t
- +
- + vlseg3e32.v v4, (a0)
- + vlseg3e32.v v4, 0(a0)
- + vlseg3e32.v v4, (a0), v0.t
- + vsseg3e32.v v4, (a0)
- + vsseg3e32.v v4, 0(a0)
- + vsseg3e32.v v4, (a0), v0.t
- +
- + vlseg4e32.v v4, (a0)
- + vlseg4e32.v v4, 0(a0)
- + vlseg4e32.v v4, (a0), v0.t
- + vsseg4e32.v v4, (a0)
- + vsseg4e32.v v4, 0(a0)
- + vsseg4e32.v v4, (a0), v0.t
- +
- + vlseg5e32.v v4, (a0)
- + vlseg5e32.v v4, 0(a0)
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- +
- + vlseg6e1024ff.v v4, (a0)
- + vlseg6e1024ff.v v4, 0(a0)
- + vlseg6e1024ff.v v4, (a0), v0.t
- +
- + vlseg7e1024ff.v v4, (a0)
- + vlseg7e1024ff.v v4, 0(a0)
- + vlseg7e1024ff.v v4, (a0), v0.t
- +
- + vlseg8e1024ff.v v4, (a0)
- + vlseg8e1024ff.v v4, 0(a0)
- + vlseg8e1024ff.v v4, (a0), v0.t
- +
- + vl1r.v v3, (a0)
- + vl1r.v v3, 0(a0)
- + vs1r.v v3, (a1)
- + vs1r.v v3, 0(a1)
- +
- + vamoaddei8.v v4, (a1), v8, v4
- + vamoaddei8.v x0, (a1), v8, v4
- + vamoaddei8.v v4, (a1), v8, v4, v0.t
- + vamoaddei8.v x0, (a1), v8, v4, v0.t
- + vamoswapei8.v v4, (a1), v8, v4
- + vamoswapei8.v x0, (a1), v8, v4
- + vamoswapei8.v v4, (a1), v8, v4, v0.t
- + vamoswapei8.v x0, (a1), v8, v4, v0.t
- +
- + vamoxorei8.v v4, (a1), v8, v4
- + vamoxorei8.v x0, (a1), v8, v4
- + vamoxorei8.v v4, (a1), v8, v4, v0.t
- + vamoxorei8.v x0, (a1), v8, v4, v0.t
- + vamoandei8.v v4, (a1), v8, v4
- + vamoandei8.v x0, (a1), v8, v4
- + vamoandei8.v v4, (a1), v8, v4, v0.t
- + vamoandei8.v x0, (a1), v8, v4, v0.t
- + vamoorei8.v v4, (a1), v8, v4
- + vamoorei8.v x0, (a1), v8, v4
- + vamoorei8.v v4, (a1), v8, v4, v0.t
- + vamoorei8.v x0, (a1), v8, v4, v0.t
- +
- + vamominei8.v v4, (a1), v8, v4
- + vamominei8.v x0, (a1), v8, v4
- + vamominei8.v v4, (a1), v8, v4, v0.t
- + vamominei8.v x0, (a1), v8, v4, v0.t
- + vamomaxei8.v v4, (a1), v8, v4
- + vamomaxei8.v x0, (a1), v8, v4
- + vamomaxei8.v v4, (a1), v8, v4, v0.t
- + vamomaxei8.v x0, (a1), v8, v4, v0.t
- + vamominuei8.v v4, (a1), v8, v4
- + vamominuei8.v x0, (a1), v8, v4
- + vamominuei8.v v4, (a1), v8, v4, v0.t
- + vamominuei8.v x0, (a1), v8, v4, v0.t
- + vamomaxuei8.v v4, (a1), v8, v4
- + vamomaxuei8.v x0, (a1), v8, v4
- + vamomaxuei8.v v4, (a1), v8, v4, v0.t
- + vamomaxuei8.v x0, (a1), v8, v4, v0.t
- +
- + vamoaddei8.v v4, 0(a1), v8, v4
- + vamoaddei8.v x0, 0(a1), v8, v4
- + vamoaddei8.v v4, 0(a1), v8, v4, v0.t
- + vamoaddei8.v x0, 0(a1), v8, v4, v0.t
- + vamoswapei8.v v4, 0(a1), v8, v4
- + vamoswapei8.v x0, 0(a1), v8, v4
- + vamoswapei8.v v4, 0(a1), v8, v4, v0.t
- + vamoswapei8.v x0, 0(a1), v8, v4, v0.t
- +
- + vamoxorei8.v v4, 0(a1), v8, v4
- + vamoxorei8.v x0, 0(a1), v8, v4
- + vamoxorei8.v v4, 0(a1), v8, v4, v0.t
- + vamoxorei8.v x0, 0(a1), v8, v4, v0.t
- + vamoandei8.v v4, 0(a1), v8, v4
- + vamoandei8.v x0, 0(a1), v8, v4
- + vamoandei8.v v4, 0(a1), v8, v4, v0.t
- + vamoandei8.v x0, 0(a1), v8, v4, v0.t
- + vamoorei8.v v4, 0(a1), v8, v4
- + vamoorei8.v x0, 0(a1), v8, v4
- + vamoorei8.v v4, 0(a1), v8, v4, v0.t
- + vamoorei8.v x0, 0(a1), v8, v4, v0.t
- +
- + vamominei8.v v4, 0(a1), v8, v4
- + vamominei8.v x0, 0(a1), v8, v4
- + vamominei8.v v4, 0(a1), v8, v4, v0.t
- + vamominei8.v x0, 0(a1), v8, v4, v0.t
- + vamomaxei8.v v4, 0(a1), v8, v4
- + vamomaxei8.v x0, 0(a1), v8, v4
- + vamomaxei8.v v4, 0(a1), v8, v4, v0.t
- + vamomaxei8.v x0, 0(a1), v8, v4, v0.t
- + vamominuei8.v v4, 0(a1), v8, v4
- + vamominuei8.v x0, 0(a1), v8, v4
- + vamominuei8.v v4, 0(a1), v8, v4, v0.t
- + vamominuei8.v x0, 0(a1), v8, v4, v0.t
- + vamomaxuei8.v v4, 0(a1), v8, v4
- + vamomaxuei8.v x0, 0(a1), v8, v4
- + vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
- + vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
- +
- + vamoaddei16.v v4, (a1), v8, v4
- + vamoaddei16.v x0, (a1), v8, v4
- + vamoaddei16.v v4, (a1), v8, v4, v0.t
- + vamoaddei16.v x0, (a1), v8, v4, v0.t
- + vamoswapei16.v v4, (a1), v8, v4
- + vamoswapei16.v x0, (a1), v8, v4
- + vamoswapei16.v v4, (a1), v8, v4, v0.t
- + vamoswapei16.v x0, (a1), v8, v4, v0.t
- +
- + vamoxorei16.v v4, (a1), v8, v4
- + vamoxorei16.v x0, (a1), v8, v4
- + vamoxorei16.v v4, (a1), v8, v4, v0.t
- + vamoxorei16.v x0, (a1), v8, v4, v0.t
- + vamoandei16.v v4, (a1), v8, v4
- + vamoandei16.v x0, (a1), v8, v4
- + vamoandei16.v v4, (a1), v8, v4, v0.t
- + vamoandei16.v x0, (a1), v8, v4, v0.t
- + vamoorei16.v v4, (a1), v8, v4
- + vamoorei16.v x0, (a1), v8, v4
- + vamoorei16.v v4, (a1), v8, v4, v0.t
- + vamoorei16.v x0, (a1), v8, v4, v0.t
- +
- + vamominei16.v v4, (a1), v8, v4
- + vamominei16.v x0, (a1), v8, v4
- + vamominei16.v v4, (a1), v8, v4, v0.t
- + vamominei16.v x0, (a1), v8, v4, v0.t
- + vamomaxei16.v v4, (a1), v8, v4
- + vamomaxei16.v x0, (a1), v8, v4
- + vamomaxei16.v v4, (a1), v8, v4, v0.t
- + vamomaxei16.v x0, (a1), v8, v4, v0.t
- + vamominuei16.v v4, (a1), v8, v4
- + vamominuei16.v x0, (a1), v8, v4
- + vamominuei16.v v4, (a1), v8, v4, v0.t
- + vamominuei16.v x0, (a1), v8, v4, v0.t
- + vamomaxuei16.v v4, (a1), v8, v4
- + vamomaxuei16.v x0, (a1), v8, v4
- + vamomaxuei16.v v4, (a1), v8, v4, v0.t
- + vamomaxuei16.v x0, (a1), v8, v4, v0.t
- +
- + vamoaddei16.v v4, 0(a1), v8, v4
- + vamoaddei16.v x0, 0(a1), v8, v4
- + vamoaddei16.v v4, 0(a1), v8, v4, v0.t
- + vamoaddei16.v x0, 0(a1), v8, v4, v0.t
- + vamoswapei16.v v4, 0(a1), v8, v4
- + vamoswapei16.v x0, 0(a1), v8, v4
- + vamoswapei16.v v4, 0(a1), v8, v4, v0.t
- + vamoswapei16.v x0, 0(a1), v8, v4, v0.t
- +
- + vamoxorei16.v v4, 0(a1), v8, v4
- + vamoxorei16.v x0, 0(a1), v8, v4
- + vamoxorei16.v v4, 0(a1), v8, v4, v0.t
- + vamoxorei16.v x0, 0(a1), v8, v4, v0.t
- + vamoandei16.v v4, 0(a1), v8, v4
- + vamoandei16.v x0, 0(a1), v8, v4
- + vamoandei16.v v4, 0(a1), v8, v4, v0.t
- + vamoandei16.v x0, 0(a1), v8, v4, v0.t
- + vamoorei16.v v4, 0(a1), v8, v4
- + vamoorei16.v x0, 0(a1), v8, v4
- + vamoorei16.v v4, 0(a1), v8, v4, v0.t
- + vamoorei16.v x0, 0(a1), v8, v4, v0.t
- +
- + vamominei16.v v4, 0(a1), v8, v4
- + vamominei16.v x0, 0(a1), v8, v4
- + vamominei16.v v4, 0(a1), v8, v4, v0.t
- + vamominei16.v x0, 0(a1), v8, v4, v0.t
- + vamomaxei16.v v4, 0(a1), v8, v4
- + vamomaxei16.v x0, 0(a1), v8, v4
- + vamomaxei16.v v4, 0(a1), v8, v4, v0.t
- + vamomaxei16.v x0, 0(a1), v8, v4, v0.t
- + vamominuei16.v v4, 0(a1), v8, v4
- + vamominuei16.v x0, 0(a1), v8, v4
- + vamominuei16.v v4, 0(a1), v8, v4, v0.t
- + vamominuei16.v x0, 0(a1), v8, v4, v0.t
- + vamomaxuei16.v v4, 0(a1), v8, v4
- + vamomaxuei16.v x0, 0(a1), v8, v4
- + vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
- + vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
- +
- + vamoaddei32.v v4, (a1), v8, v4
- + vamoaddei32.v x0, (a1), v8, v4
- + vamoaddei32.v v4, (a1), v8, v4, v0.t
- + vamoaddei32.v x0, (a1), v8, v4, v0.t
- + vamoswapei32.v v4, (a1), v8, v4
- + vamoswapei32.v x0, (a1), v8, v4
- + vamoswapei32.v v4, (a1), v8, v4, v0.t
- + vamoswapei32.v x0, (a1), v8, v4, v0.t
- +
- + vamoxorei32.v v4, (a1), v8, v4
- + vamoxorei32.v x0, (a1), v8, v4
- + vamoxorei32.v v4, (a1), v8, v4, v0.t
- + vamoxorei32.v x0, (a1), v8, v4, v0.t
- + vamoandei32.v v4, (a1), v8, v4
- + vamoandei32.v x0, (a1), v8, v4
- + vamoandei32.v v4, (a1), v8, v4, v0.t
- + vamoandei32.v x0, (a1), v8, v4, v0.t
- + vamoorei32.v v4, (a1), v8, v4
- + vamoorei32.v x0, (a1), v8, v4
- + vamoorei32.v v4, (a1), v8, v4, v0.t
- + vamoorei32.v x0, (a1), v8, v4, v0.t
- +
- + vamominei32.v v4, (a1), v8, v4
- + vamominei32.v x0, (a1), v8, v4
- + vamominei32.v v4, (a1), v8, v4, v0.t
- + vamominei32.v x0, (a1), v8, v4, v0.t
- + vamomaxei32.v v4, (a1), v8, v4
- + vamomaxei32.v x0, (a1), v8, v4
- + vamomaxei32.v v4, (a1), v8, v4, v0.t
- + vamomaxei32.v x0, (a1), v8, v4, v0.t
- + vamominuei32.v v4, (a1), v8, v4
- + vamominuei32.v x0, (a1), v8, v4
- + vamominuei32.v v4, (a1), v8, v4, v0.t
- + vamominuei32.v x0, (a1), v8, v4, v0.t
- + vamomaxuei32.v v4, (a1), v8, v4
- + vamomaxuei32.v x0, (a1), v8, v4
- + vamomaxuei32.v v4, (a1), v8, v4, v0.t
- + vamomaxuei32.v x0, (a1), v8, v4, v0.t
- +
- + vamoaddei32.v v4, 0(a1), v8, v4
- + vamoaddei32.v x0, 0(a1), v8, v4
- + vamoaddei32.v v4, 0(a1), v8, v4, v0.t
- + vamoaddei32.v x0, 0(a1), v8, v4, v0.t
- + vamoswapei32.v v4, 0(a1), v8, v4
- + vamoswapei32.v x0, 0(a1), v8, v4
- + vamoswapei32.v v4, 0(a1), v8, v4, v0.t
- + vamoswapei32.v x0, 0(a1), v8, v4, v0.t
- +
- + vamoxorei32.v v4, 0(a1), v8, v4
- + vamoxorei32.v x0, 0(a1), v8, v4
- + vamoxorei32.v v4, 0(a1), v8, v4, v0.t
- + vamoxorei32.v x0, 0(a1), v8, v4, v0.t
- + vamoandei32.v v4, 0(a1), v8, v4
- + vamoandei32.v x0, 0(a1), v8, v4
- + vamoandei32.v v4, 0(a1), v8, v4, v0.t
- + vamoandei32.v x0, 0(a1), v8, v4, v0.t
- + vamoorei32.v v4, 0(a1), v8, v4
- + vamoorei32.v x0, 0(a1), v8, v4
- + vamoorei32.v v4, 0(a1), v8, v4, v0.t
- + vamoorei32.v x0, 0(a1), v8, v4, v0.t
- +
- + vamominei32.v v4, 0(a1), v8, v4
- + vamominei32.v x0, 0(a1), v8, v4
- + vamominei32.v v4, 0(a1), v8, v4, v0.t
- + vamominei32.v x0, 0(a1), v8, v4, v0.t
- + vamomaxei32.v v4, 0(a1), v8, v4
- + vamomaxei32.v x0, 0(a1), v8, v4
- + vamomaxei32.v v4, 0(a1), v8, v4, v0.t
- + vamomaxei32.v x0, 0(a1), v8, v4, v0.t
- + vamominuei32.v v4, 0(a1), v8, v4
- + vamominuei32.v x0, 0(a1), v8, v4
- + vamominuei32.v v4, 0(a1), v8, v4, v0.t
- + vamominuei32.v x0, 0(a1), v8, v4, v0.t
- + vamomaxuei32.v v4, 0(a1), v8, v4
- + vamomaxuei32.v x0, 0(a1), v8, v4
- + vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
- + vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
- +
- + vamoaddei64.v v4, (a1), v8, v4
- + vamoaddei64.v x0, (a1), v8, v4
- + vamoaddei64.v v4, (a1), v8, v4, v0.t
- + vamoaddei64.v x0, (a1), v8, v4, v0.t
- + vamoswapei64.v v4, (a1), v8, v4
- + vamoswapei64.v x0, (a1), v8, v4
- + vamoswapei64.v v4, (a1), v8, v4, v0.t
- + vamoswapei64.v x0, (a1), v8, v4, v0.t
- +
- + vamoxorei64.v v4, (a1), v8, v4
- + vamoxorei64.v x0, (a1), v8, v4
- + vamoxorei64.v v4, (a1), v8, v4, v0.t
- + vamoxorei64.v x0, (a1), v8, v4, v0.t
- + vamoandei64.v v4, (a1), v8, v4
- + vamoandei64.v x0, (a1), v8, v4
- + vamoandei64.v v4, (a1), v8, v4, v0.t
- + vamoandei64.v x0, (a1), v8, v4, v0.t
- + vamoorei64.v v4, (a1), v8, v4
- + vamoorei64.v x0, (a1), v8, v4
- + vamoorei64.v v4, (a1), v8, v4, v0.t
- + vamoorei64.v x0, (a1), v8, v4, v0.t
- +
- + vamominei64.v v4, (a1), v8, v4
- + vamominei64.v x0, (a1), v8, v4
- + vamominei64.v v4, (a1), v8, v4, v0.t
- + vamominei64.v x0, (a1), v8, v4, v0.t
- + vamomaxei64.v v4, (a1), v8, v4
- + vamomaxei64.v x0, (a1), v8, v4
- + vamomaxei64.v v4, (a1), v8, v4, v0.t
- + vamomaxei64.v x0, (a1), v8, v4, v0.t
- + vamominuei64.v v4, (a1), v8, v4
- + vamominuei64.v x0, (a1), v8, v4
- + vamominuei64.v v4, (a1), v8, v4, v0.t
- + vamominuei64.v x0, (a1), v8, v4, v0.t
- + vamomaxuei64.v v4, (a1), v8, v4
- + vamomaxuei64.v x0, (a1), v8, v4
- + vamomaxuei64.v v4, (a1), v8, v4, v0.t
- + vamomaxuei64.v x0, (a1), v8, v4, v0.t
- +
- + vamoaddei64.v v4, 0(a1), v8, v4
- + vamoaddei64.v x0, 0(a1), v8, v4
- + vamoaddei64.v v4, 0(a1), v8, v4, v0.t
- + vamoaddei64.v x0, 0(a1), v8, v4, v0.t
- + vamoswapei64.v v4, 0(a1), v8, v4
- + vamoswapei64.v x0, 0(a1), v8, v4
- + vamoswapei64.v v4, 0(a1), v8, v4, v0.t
- + vamoswapei64.v x0, 0(a1), v8, v4, v0.t
- +
- + vamoxorei64.v v4, 0(a1), v8, v4
- + vamoxorei64.v x0, 0(a1), v8, v4
- + vamoxorei64.v v4, 0(a1), v8, v4, v0.t
- + vamoxorei64.v x0, 0(a1), v8, v4, v0.t
- + vamoandei64.v v4, 0(a1), v8, v4
- + vamoandei64.v x0, 0(a1), v8, v4
- + vamoandei64.v v4, 0(a1), v8, v4, v0.t
- + vamoandei64.v x0, 0(a1), v8, v4, v0.t
- + vamoorei64.v v4, 0(a1), v8, v4
- + vamoorei64.v x0, 0(a1), v8, v4
- + vamoorei64.v v4, 0(a1), v8, v4, v0.t
- + vamoorei64.v x0, 0(a1), v8, v4, v0.t
- +
- + vamominei64.v v4, 0(a1), v8, v4
- + vamominei64.v x0, 0(a1), v8, v4
- + vamominei64.v v4, 0(a1), v8, v4, v0.t
- + vamominei64.v x0, 0(a1), v8, v4, v0.t
- + vamomaxei64.v v4, 0(a1), v8, v4
- + vamomaxei64.v x0, 0(a1), v8, v4
- + vamomaxei64.v v4, 0(a1), v8, v4, v0.t
- + vamomaxei64.v x0, 0(a1), v8, v4, v0.t
- + vamominuei64.v v4, 0(a1), v8, v4
- + vamominuei64.v x0, 0(a1), v8, v4
- + vamominuei64.v v4, 0(a1), v8, v4, v0.t
- + vamominuei64.v x0, 0(a1), v8, v4, v0.t
- + vamomaxuei64.v v4, 0(a1), v8, v4
- + vamomaxuei64.v x0, 0(a1), v8, v4
- + vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
- + vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
- +
- + vadd.vv v4, v8, v12
- + vadd.vx v4, v8, a1
- + vadd.vi v4, v8, 15
- + vadd.vi v4, v8, -16
- + vadd.vv v4, v8, v12, v0.t
- + vadd.vx v4, v8, a1, v0.t
- + vadd.vi v4, v8, 15, v0.t
- + vadd.vi v4, v8, -16, v0.t
- + vsub.vv v4, v8, v12
- + vsub.vx v4, v8, a1
- + vrsub.vx v4, v8, a1
- + vrsub.vi v4, v8, 15
- + vrsub.vi v4, v8, -16
- + vsub.vv v4, v8, v12, v0.t
- + vsub.vx v4, v8, a1, v0.t
- + vrsub.vx v4, v8, a1, v0.t
- + vrsub.vi v4, v8, 15, v0.t
- + vrsub.vi v4, v8, -16, v0.t
- +
- + # Aliases
- + vwcvt.x.x.v v4, v8
- + vwcvtu.x.x.v v4, v8
- + vwcvt.x.x.v v4, v8, v0.t
- + vwcvtu.x.x.v v4, v8, v0.t
- +
- + vwaddu.vv v4, v8, v12
- + vwaddu.vx v4, v8, a1
- + vwaddu.vv v4, v8, v12, v0.t
- + vwaddu.vx v4, v8, a1, v0.t
- + vwsubu.vv v4, v8, v12
- + vwsubu.vx v4, v8, a1
- + vwsubu.vv v4, v8, v12, v0.t
- + vwsubu.vx v4, v8, a1, v0.t
- + vwadd.vv v4, v8, v12
- + vwadd.vx v4, v8, a1
- + vwadd.vv v4, v8, v12, v0.t
- + vwadd.vx v4, v8, a1, v0.t
- + vwsub.vv v4, v8, v12
- + vwsub.vx v4, v8, a1
- + vwsub.vv v4, v8, v12, v0.t
- + vwsub.vx v4, v8, a1, v0.t
- + vwaddu.wv v4, v8, v12
- + vwaddu.wx v4, v8, a1
- + vwaddu.wv v4, v8, v12, v0.t
- + vwaddu.wx v4, v8, a1, v0.t
- + vwsubu.wv v4, v8, v12
- + vwsubu.wx v4, v8, a1
- + vwsubu.wv v4, v8, v12, v0.t
- + vwsubu.wx v4, v8, a1, v0.t
- + vwadd.wv v4, v8, v12
- + vwadd.wx v4, v8, a1
- + vwadd.wv v4, v8, v12, v0.t
- + vwadd.wx v4, v8, a1, v0.t
- + vwsub.wv v4, v8, v12
- + vwsub.wx v4, v8, a1
- + vwsub.wv v4, v8, v12, v0.t
- + vwsub.wx v4, v8, a1, v0.t
- +
- + vzext.vf2 v4, v8
- + vzext.vf2 v4, v8, v0.t
- + vsext.vf2 v4, v8
- + vsext.vf2 v4, v8, v0.t
- + vzext.vf4 v4, v8
- + vzext.vf4 v4, v8, v0.t
- + vsext.vf4 v4, v8
- + vsext.vf4 v4, v8, v0.t
- + vzext.vf8 v4, v8
- + vzext.vf8 v4, v8, v0.t
- + vsext.vf8 v4, v8
- + vsext.vf8 v4, v8, v0.t
- +
- + vadc.vvm v4, v8, v12, v0
- + vadc.vxm v4, v8, a1, v0
- + vadc.vim v4, v8, 15, v0
- + vadc.vim v4, v8, -16, v0
- + vmadc.vvm v4, v8, v12, v0
- + vmadc.vxm v4, v8, a1, v0
- + vmadc.vim v4, v8, 15, v0
- + vmadc.vim v4, v8, -16, v0
- + vmadc.vv v4, v8, v12
- + vmadc.vx v4, v8, a1
- + vmadc.vi v4, v8, 15
- + vmadc.vi v4, v8, -16
- + vsbc.vvm v4, v8, v12, v0
- + vsbc.vxm v4, v8, a1, v0
- + vmsbc.vvm v4, v8, v12, v0
- + vmsbc.vxm v4, v8, a1, v0
- + vmsbc.vv v4, v8, v12
- + vmsbc.vx v4, v8, a1
- +
- + # Aliases
- + vnot.v v4, v8
- + vnot.v v4, v8, v0.t
- +
- + vand.vv v4, v8, v12
- + vand.vx v4, v8, a1
- + vand.vi v4, v8, 15
- + vand.vi v4, v8, -16
- + vand.vv v4, v8, v12, v0.t
- + vand.vx v4, v8, a1, v0.t
- + vand.vi v4, v8, 15, v0.t
- + vand.vi v4, v8, -16, v0.t
- + vor.vv v4, v8, v12
- + vor.vx v4, v8, a1
- + vor.vi v4, v8, 15
- + vor.vi v4, v8, -16
- + vor.vv v4, v8, v12, v0.t
- + vor.vx v4, v8, a1, v0.t
- + vor.vi v4, v8, 15, v0.t
- + vor.vi v4, v8, -16, v0.t
- + vxor.vv v4, v8, v12
- + vxor.vx v4, v8, a1
- + vxor.vi v4, v8, 15
- + vxor.vi v4, v8, -16
- + vxor.vv v4, v8, v12, v0.t
- + vxor.vx v4, v8, a1, v0.t
- + vxor.vi v4, v8, 15, v0.t
- + vxor.vi v4, v8, -16, v0.t
- +
- + vsll.vv v4, v8, v12
- + vsll.vx v4, v8, a1
- + vsll.vi v4, v8, 1
- + vsll.vi v4, v8, 31
- + vsll.vv v4, v8, v12, v0.t
- + vsll.vx v4, v8, a1, v0.t
- + vsll.vi v4, v8, 1, v0.t
- + vsll.vi v4, v8, 31, v0.t
- + vsrl.vv v4, v8, v12
- + vsrl.vx v4, v8, a1
- + vsrl.vi v4, v8, 1
- + vsrl.vi v4, v8, 31
- + vsrl.vv v4, v8, v12, v0.t
- + vsrl.vx v4, v8, a1, v0.t
- + vsrl.vi v4, v8, 1, v0.t
- + vsrl.vi v4, v8, 31, v0.t
- + vsra.vv v4, v8, v12
- + vsra.vx v4, v8, a1
- + vsra.vi v4, v8, 1
- + vsra.vi v4, v8, 31
- + vsra.vv v4, v8, v12, v0.t
- + vsra.vx v4, v8, a1, v0.t
- + vsra.vi v4, v8, 1, v0.t
- + vsra.vi v4, v8, 31, v0.t
- +
- + vnsrl.wv v4, v8, v12
- + vnsrl.wx v4, v8, a1
- + vnsrl.wi v4, v8, 1
- + vnsrl.wi v4, v8, 31
- + vnsrl.wv v4, v8, v12, v0.t
- + vnsrl.wx v4, v8, a1, v0.t
- + vnsrl.wi v4, v8, 1, v0.t
- + vnsrl.wi v4, v8, 31, v0.t
- + vnsra.wv v4, v8, v12
- + vnsra.wx v4, v8, a1
- + vnsra.wi v4, v8, 1
- + vnsra.wi v4, v8, 31
- + vnsra.wv v4, v8, v12, v0.t
- + vnsra.wx v4, v8, a1, v0.t
- + vnsra.wi v4, v8, 1, v0.t
- + vnsra.wi v4, v8, 31, v0.t
- +
- + # Aliases
- + vmsgt.vv v4, v8, v12
- + vmsgtu.vv v4, v8, v12
- + vmsge.vv v4, v8, v12
- + vmsgeu.vv v4, v8, v12
- + vmsgt.vv v4, v8, v12, v0.t
- + vmsgtu.vv v4, v8, v12, v0.t
- + vmsge.vv v4, v8, v12, v0.t
- + vmsgeu.vv v4, v8, v12, v0.t
- + vmslt.vi v4, v8, 16
- + vmslt.vi v4, v8, -15
- + vmsltu.vi v4, v8, 16
- + vmsltu.vi v4, v8, -15
- + vmsge.vi v4, v8, 16
- + vmsge.vi v4, v8, -15
- + vmsgeu.vi v4, v8, 16
- + vmsgeu.vi v4, v8, -15
- + vmslt.vi v4, v8, 16, v0.t
- + vmslt.vi v4, v8, -15, v0.t
- + vmsltu.vi v4, v8, 16, v0.t
- + vmsltu.vi v4, v8, -15, v0.t
- + vmsge.vi v4, v8, 16, v0.t
- + vmsge.vi v4, v8, -15, v0.t
- + vmsgeu.vi v4, v8, 16, v0.t
- + vmsgeu.vi v4, v8, -15, v0.t
- +
- + vmseq.vv v4, v8, v12
- + vmseq.vx v4, v8, a1
- + vmseq.vi v4, v8, 15
- + vmseq.vi v4, v8, -16
- + vmseq.vv v4, v8, v12, v0.t
- + vmseq.vx v4, v8, a1, v0.t
- + vmseq.vi v4, v8, 15, v0.t
- + vmseq.vi v4, v8, -16, v0.t
- + vmsne.vv v4, v8, v12
- + vmsne.vx v4, v8, a1
- + vmsne.vi v4, v8, 15
- + vmsne.vi v4, v8, -16
- + vmsne.vv v4, v8, v12, v0.t
- + vmsne.vx v4, v8, a1, v0.t
- + vmsne.vi v4, v8, 15, v0.t
- + vmsne.vi v4, v8, -16, v0.t
- + vmsltu.vv v4, v8, v12
- + vmsltu.vx v4, v8, a1
- + vmsltu.vv v4, v8, v12, v0.t
- + vmsltu.vx v4, v8, a1, v0.t
- + vmslt.vv v4, v8, v12
- + vmslt.vx v4, v8, a1
- + vmslt.vv v4, v8, v12, v0.t
- + vmslt.vx v4, v8, a1, v0.t
- + vmsleu.vv v4, v8, v12
- + vmsleu.vx v4, v8, a1
- + vmsleu.vi v4, v8, 15
- + vmsleu.vi v4, v8, -16
- + vmsleu.vv v4, v8, v12, v0.t
- + vmsleu.vx v4, v8, a1, v0.t
- + vmsleu.vi v4, v8, 15, v0.t
- + vmsleu.vi v4, v8, -16, v0.t
- + vmsle.vv v4, v8, v12
- + vmsle.vx v4, v8, a1
- + vmsle.vi v4, v8, 15
- + vmsle.vi v4, v8, -16
- + vmsle.vv v4, v8, v12, v0.t
- + vmsle.vx v4, v8, a1, v0.t
- + vmsle.vi v4, v8, 15, v0.t
- + vmsle.vi v4, v8, -16, v0.t
- + vmsgtu.vx v4, v8, a1
- + vmsgtu.vi v4, v8, 15
- + vmsgtu.vi v4, v8, -16
- + vmsgtu.vx v4, v8, a1, v0.t
- + vmsgtu.vi v4, v8, 15, v0.t
- + vmsgtu.vi v4, v8, -16, v0.t
- + vmsgt.vx v4, v8, a1
- + vmsgt.vi v4, v8, 15
- + vmsgt.vi v4, v8, -16
- + vmsgt.vx v4, v8, a1, v0.t
- + vmsgt.vi v4, v8, 15, v0.t
- + vmsgt.vi v4, v8, -16, v0.t
- +
- + vminu.vv v4, v8, v12
- + vminu.vx v4, v8, a1
- + vminu.vv v4, v8, v12, v0.t
- + vminu.vx v4, v8, a1, v0.t
- + vmin.vv v4, v8, v12
- + vmin.vx v4, v8, a1
- + vmin.vv v4, v8, v12, v0.t
- + vmin.vx v4, v8, a1, v0.t
- + vmaxu.vv v4, v8, v12
- + vmaxu.vx v4, v8, a1
- + vmaxu.vv v4, v8, v12, v0.t
- + vmaxu.vx v4, v8, a1, v0.t
- + vmax.vv v4, v8, v12
- + vmax.vx v4, v8, a1
- + vmax.vv v4, v8, v12, v0.t
- + vmax.vx v4, v8, a1, v0.t
- +
- + vmul.vv v4, v8, v12
- + vmul.vx v4, v8, a1
- + vmul.vv v4, v8, v12, v0.t
- + vmul.vx v4, v8, a1, v0.t
- + vmulh.vv v4, v8, v12
- + vmulh.vx v4, v8, a1
- + vmulh.vv v4, v8, v12, v0.t
- + vmulh.vx v4, v8, a1, v0.t
- + vmulhu.vv v4, v8, v12
- + vmulhu.vx v4, v8, a1
- + vmulhu.vv v4, v8, v12, v0.t
- + vmulhu.vx v4, v8, a1, v0.t
- + vmulhsu.vv v4, v8, v12
- + vmulhsu.vx v4, v8, a1
- + vmulhsu.vv v4, v8, v12, v0.t
- + vmulhsu.vx v4, v8, a1, v0.t
- +
- + vwmul.vv v4, v8, v12
- + vwmul.vx v4, v8, a1
- + vwmul.vv v4, v8, v12, v0.t
- + vwmul.vx v4, v8, a1, v0.t
- + vwmulu.vv v4, v8, v12
- + vwmulu.vx v4, v8, a1
- + vwmulu.vv v4, v8, v12, v0.t
- + vwmulu.vx v4, v8, a1, v0.t
- + vwmulsu.vv v4, v8, v12
- + vwmulsu.vx v4, v8, a1
- + vwmulsu.vv v4, v8, v12, v0.t
- + vwmulsu.vx v4, v8, a1, v0.t
- +
- + vmacc.vv v4, v12, v8
- + vmacc.vx v4, a1, v8
- + vmacc.vv v4, v12, v8, v0.t
- + vmacc.vx v4, a1, v8, v0.t
- + vnmsac.vv v4, v12, v8
- + vnmsac.vx v4, a1, v8
- + vnmsac.vv v4, v12, v8, v0.t
- + vnmsac.vx v4, a1, v8, v0.t
- + vmadd.vv v4, v12, v8
- + vmadd.vx v4, a1, v8
- + vmadd.vv v4, v12, v8, v0.t
- + vmadd.vx v4, a1, v8, v0.t
- + vnmsub.vv v4, v12, v8
- + vnmsub.vx v4, a1, v8
- + vnmsub.vv v4, v12, v8, v0.t
- + vnmsub.vx v4, a1, v8, v0.t
- +
- + vwmaccu.vv v4, v12, v8
- + vwmaccu.vx v4, a1, v8
- + vwmaccu.vv v4, v12, v8, v0.t
- + vwmaccu.vx v4, a1, v8, v0.t
- + vwmacc.vv v4, v12, v8
- + vwmacc.vx v4, a1, v8
- + vwmacc.vv v4, v12, v8, v0.t
- + vwmacc.vx v4, a1, v8, v0.t
- + vwmaccsu.vv v4, v12, v8
- + vwmaccsu.vx v4, a1, v8
- + vwmaccsu.vv v4, v12, v8, v0.t
- + vwmaccsu.vx v4, a1, v8, v0.t
- + vwmaccus.vx v4, a1, v8
- + vwmaccus.vx v4, a1, v8, v0.t
- +
- + vqmaccu.vv v4, v12, v8
- + vqmaccu.vx v4, a1, v8
- + vqmaccu.vv v4, v12, v8, v0.t
- + vqmaccu.vx v4, a1, v8, v0.t
- + vqmacc.vv v4, v12, v8
- + vqmacc.vx v4, a1, v8
- + vqmacc.vv v4, v12, v8, v0.t
- + vqmacc.vx v4, a1, v8, v0.t
- + vqmaccsu.vv v4, v12, v8
- + vqmaccsu.vx v4, a1, v8
- + vqmaccsu.vv v4, v12, v8, v0.t
- + vqmaccsu.vx v4, a1, v8, v0.t
- + vqmaccus.vx v4, a1, v8
- + vqmaccus.vx v4, a1, v8, v0.t
- +
- + vdivu.vv v4, v8, v12
- + vdivu.vx v4, v8, a1
- + vdivu.vv v4, v8, v12, v0.t
- + vdivu.vx v4, v8, a1, v0.t
- + vdiv.vv v4, v8, v12
- + vdiv.vx v4, v8, a1
- + vdiv.vv v4, v8, v12, v0.t
- + vdiv.vx v4, v8, a1, v0.t
- + vremu.vv v4, v8, v12
- + vremu.vx v4, v8, a1
- + vremu.vv v4, v8, v12, v0.t
- + vremu.vx v4, v8, a1, v0.t
- + vrem.vv v4, v8, v12
- + vrem.vx v4, v8, a1
- + vrem.vv v4, v8, v12, v0.t
- + vrem.vx v4, v8, a1, v0.t
- +
- + vmerge.vvm v4, v8, v12, v0
- + vmerge.vxm v4, v8, a1, v0
- + vmerge.vim v4, v8, 15, v0
- + vmerge.vim v4, v8, -16, v0
- +
- + vmv.v.v v8, v12
- + vmv.v.x v8, a1
- + vmv.v.i v8, 15
- + vmv.v.i v8, -16
- +
- + vsaddu.vv v4, v8, v12
- + vsaddu.vx v4, v8, a1
- + vsaddu.vi v4, v8, 15
- + vsaddu.vi v4, v8, -16
- + vsaddu.vv v4, v8, v12, v0.t
- + vsaddu.vx v4, v8, a1, v0.t
- + vsaddu.vi v4, v8, 15, v0.t
- + vsaddu.vi v4, v8, -16, v0.t
- + vsadd.vv v4, v8, v12
- + vsadd.vx v4, v8, a1
- + vsadd.vi v4, v8, 15
- + vsadd.vi v4, v8, -16
- + vsadd.vv v4, v8, v12, v0.t
- + vsadd.vx v4, v8, a1, v0.t
- + vsadd.vi v4, v8, 15, v0.t
- + vsadd.vi v4, v8, -16, v0.t
- + vssubu.vv v4, v8, v12
- + vssubu.vx v4, v8, a1
- + vssubu.vv v4, v8, v12, v0.t
- + vssubu.vx v4, v8, a1, v0.t
- + vssub.vv v4, v8, v12
- + vssub.vx v4, v8, a1
- + vssub.vv v4, v8, v12, v0.t
- + vssub.vx v4, v8, a1, v0.t
- +
- + vaaddu.vv v4, v8, v12
- + vaaddu.vx v4, v8, a1
- + vaaddu.vv v4, v8, v12, v0.t
- + vaaddu.vx v4, v8, a1, v0.t
- + vaadd.vv v4, v8, v12
- + vaadd.vx v4, v8, a1
- + vaadd.vv v4, v8, v12, v0.t
- + vaadd.vx v4, v8, a1, v0.t
- + vasubu.vv v4, v8, v12
- + vasubu.vx v4, v8, a1
- + vasubu.vv v4, v8, v12, v0.t
- + vasubu.vx v4, v8, a1, v0.t
- + vasub.vv v4, v8, v12
- + vasub.vx v4, v8, a1
- + vasub.vv v4, v8, v12, v0.t
- + vasub.vx v4, v8, a1, v0.t
- +
- + vsmul.vv v4, v8, v12
- + vsmul.vx v4, v8, a1
- + vsmul.vv v4, v8, v12, v0.t
- + vsmul.vx v4, v8, a1, v0.t
- +
- + vssrl.vv v4, v8, v12
- + vssrl.vx v4, v8, a1
- + vssrl.vi v4, v8, 1
- + vssrl.vi v4, v8, 31
- + vssrl.vv v4, v8, v12, v0.t
- + vssrl.vx v4, v8, a1, v0.t
- + vssrl.vi v4, v8, 1, v0.t
- + vssrl.vi v4, v8, 31, v0.t
- + vssra.vv v4, v8, v12
- + vssra.vx v4, v8, a1
- + vssra.vi v4, v8, 1
- + vssra.vi v4, v8, 31
- + vssra.vv v4, v8, v12, v0.t
- + vssra.vx v4, v8, a1, v0.t
- + vssra.vi v4, v8, 1, v0.t
- + vssra.vi v4, v8, 31, v0.t
- +
- + vnclipu.wv v4, v8, v12
- + vnclipu.wx v4, v8, a1
- + vnclipu.wi v4, v8, 1
- + vnclipu.wi v4, v8, 31
- + vnclipu.wv v4, v8, v12, v0.t
- + vnclipu.wx v4, v8, a1, v0.t
- + vnclipu.wi v4, v8, 1, v0.t
- + vnclipu.wi v4, v8, 31, v0.t
- + vnclip.wv v4, v8, v12
- + vnclip.wx v4, v8, a1
- + vnclip.wi v4, v8, 1
- + vnclip.wi v4, v8, 31
- + vnclip.wv v4, v8, v12, v0.t
- + vnclip.wx v4, v8, a1, v0.t
- + vnclip.wi v4, v8, 1, v0.t
- + vnclip.wi v4, v8, 31, v0.t
- +
- + vfadd.vv v4, v8, v12
- + vfadd.vf v4, v8, fa2
- + vfadd.vv v4, v8, v12, v0.t
- + vfadd.vf v4, v8, fa2, v0.t
- + vfsub.vv v4, v8, v12
- + vfsub.vf v4, v8, fa2
- + vfsub.vv v4, v8, v12, v0.t
- + vfsub.vf v4, v8, fa2, v0.t
- + vfrsub.vf v4, v8, fa2
- + vfrsub.vf v4, v8, fa2, v0.t
- +
- + vfwadd.vv v4, v8, v12
- + vfwadd.vf v4, v8, fa2
- + vfwadd.vv v4, v8, v12, v0.t
- + vfwadd.vf v4, v8, fa2, v0.t
- + vfwsub.vv v4, v8, v12
- + vfwsub.vf v4, v8, fa2
- + vfwsub.vv v4, v8, v12, v0.t
- + vfwsub.vf v4, v8, fa2, v0.t
- + vfwadd.wv v4, v8, v12
- + vfwadd.wf v4, v8, fa2
- + vfwadd.wv v4, v8, v12, v0.t
- + vfwadd.wf v4, v8, fa2, v0.t
- + vfwsub.wv v4, v8, v12
- + vfwsub.wf v4, v8, fa2
- + vfwsub.wv v4, v8, v12, v0.t
- + vfwsub.wf v4, v8, fa2, v0.t
- +
- + vfmul.vv v4, v8, v12
- + vfmul.vf v4, v8, fa2
- + vfmul.vv v4, v8, v12, v0.t
- + vfmul.vf v4, v8, fa2, v0.t
- + vfdiv.vv v4, v8, v12
- + vfdiv.vf v4, v8, fa2
- + vfdiv.vv v4, v8, v12, v0.t
- + vfdiv.vf v4, v8, fa2, v0.t
- + vfrdiv.vf v4, v8, fa2
- + vfrdiv.vf v4, v8, fa2, v0.t
- +
- + vfwmul.vv v4, v8, v12
- + vfwmul.vf v4, v8, fa2
- + vfwmul.vv v4, v8, v12, v0.t
- + vfwmul.vf v4, v8, fa2, v0.t
- +
- + vfmadd.vv v4, v12, v8
- + vfmadd.vf v4, fa2, v8
- + vfnmadd.vv v4, v12, v8
- + vfnmadd.vf v4, fa2, v8
- + vfmsub.vv v4, v12, v8
- + vfmsub.vf v4, fa2, v8
- + vfnmsub.vv v4, v12, v8
- + vfnmsub.vf v4, fa2, v8
- + vfmadd.vv v4, v12, v8, v0.t
- + vfmadd.vf v4, fa2, v8, v0.t
- + vfnmadd.vv v4, v12, v8, v0.t
- + vfnmadd.vf v4, fa2, v8, v0.t
- + vfmsub.vv v4, v12, v8, v0.t
- + vfmsub.vf v4, fa2, v8, v0.t
- + vfnmsub.vv v4, v12, v8, v0.t
- + vfnmsub.vf v4, fa2, v8, v0.t
- + vfmacc.vv v4, v12, v8
- + vfmacc.vf v4, fa2, v8
- + vfnmacc.vv v4, v12, v8
- + vfnmacc.vf v4, fa2, v8
- + vfmsac.vv v4, v12, v8
- + vfmsac.vf v4, fa2, v8
- + vfnmsac.vv v4, v12, v8
- + vfnmsac.vf v4, fa2, v8
- + vfmacc.vv v4, v12, v8, v0.t
- + vfmacc.vf v4, fa2, v8, v0.t
- + vfnmacc.vv v4, v12, v8, v0.t
- + vfnmacc.vf v4, fa2, v8, v0.t
- + vfmsac.vv v4, v12, v8, v0.t
- + vfmsac.vf v4, fa2, v8, v0.t
- + vfnmsac.vv v4, v12, v8, v0.t
- + vfnmsac.vf v4, fa2, v8, v0.t
- +
- + vfwmacc.vv v4, v12, v8
- + vfwmacc.vf v4, fa2, v8
- + vfwnmacc.vv v4, v12, v8
- + vfwnmacc.vf v4, fa2, v8
- + vfwmsac.vv v4, v12, v8
- + vfwmsac.vf v4, fa2, v8
- + vfwnmsac.vv v4, v12, v8
- + vfwnmsac.vf v4, fa2, v8
- + vfwmacc.vv v4, v12, v8, v0.t
- + vfwmacc.vf v4, fa2, v8, v0.t
- + vfwnmacc.vv v4, v12, v8, v0.t
- + vfwnmacc.vf v4, fa2, v8, v0.t
- + vfwmsac.vv v4, v12, v8, v0.t
- + vfwmsac.vf v4, fa2, v8, v0.t
- + vfwnmsac.vv v4, v12, v8, v0.t
- + vfwnmsac.vf v4, fa2, v8, v0.t
- +
- + vfsqrt.v v4, v8
- + vfsqrt.v v4, v8, v0.t
- +
- + vfmin.vv v4, v8, v12
- + vfmin.vf v4, v8, fa2
- + vfmax.vv v4, v8, v12
- + vfmax.vf v4, v8, fa2
- + vfmin.vv v4, v8, v12, v0.t
- + vfmin.vf v4, v8, fa2, v0.t
- + vfmax.vv v4, v8, v12, v0.t
- + vfmax.vf v4, v8, fa2, v0.t
- +
- + vfsgnj.vv v4, v8, v12
- + vfsgnj.vf v4, v8, fa2
- + vfsgnjn.vv v4, v8, v12
- + vfsgnjn.vf v4, v8, fa2
- + vfsgnjx.vv v4, v8, v12
- + vfsgnjx.vf v4, v8, fa2
- + vfsgnj.vv v4, v8, v12, v0.t
- + vfsgnj.vf v4, v8, fa2, v0.t
- + vfsgnjn.vv v4, v8, v12, v0.t
- + vfsgnjn.vf v4, v8, fa2, v0.t
- + vfsgnjx.vv v4, v8, v12, v0.t
- + vfsgnjx.vf v4, v8, fa2, v0.t
- +
- + # Aliases
- + vmfgt.vv v4, v8, v12
- + vmfge.vv v4, v8, v12
- + vmfgt.vv v4, v8, v12, v0.t
- + vmfge.vv v4, v8, v12, v0.t
- +
- + vmfeq.vv v4, v8, v12
- + vmfeq.vf v4, v8, fa2
- + vmfne.vv v4, v8, v12
- + vmfne.vf v4, v8, fa2
- + vmflt.vv v4, v8, v12
- + vmflt.vf v4, v8, fa2
- + vmfle.vv v4, v8, v12
- + vmfle.vf v4, v8, fa2
- + vmfgt.vf v4, v8, fa2
- + vmfge.vf v4, v8, fa2
- + vmfeq.vv v4, v8, v12, v0.t
- + vmfeq.vf v4, v8, fa2, v0.t
- + vmfne.vv v4, v8, v12, v0.t
- + vmfne.vf v4, v8, fa2, v0.t
- + vmflt.vv v4, v8, v12, v0.t
- + vmflt.vf v4, v8, fa2, v0.t
- + vmfle.vv v4, v8, v12, v0.t
- + vmfle.vf v4, v8, fa2, v0.t
- + vmfgt.vf v4, v8, fa2, v0.t
- + vmfge.vf v4, v8, fa2, v0.t
- +
- + vfclass.v v4, v8
- + vfclass.v v4, v8, v0.t
- +
- + vfmerge.vfm v4, v8, fa2, v0
- + vfmv.v.f v4, fa1
- +
- + vfcvt.xu.f.v v4, v8
- + vfcvt.x.f.v v4, v8
- + vfcvt.rtz.xu.f.v v4, v8
- + vfcvt.rtz.x.f.v v4, v8
- + vfcvt.f.xu.v v4, v8
- + vfcvt.f.x.v v4, v8
- + vfcvt.xu.f.v v4, v8, v0.t
- + vfcvt.x.f.v v4, v8, v0.t
- + vfcvt.rtz.xu.f.v v4, v8, v0.t
- + vfcvt.rtz.x.f.v v4, v8, v0.t
- + vfcvt.f.xu.v v4, v8, v0.t
- + vfcvt.f.x.v v4, v8, v0.t
- +
- + vfwcvt.xu.f.v v4, v8
- + vfwcvt.x.f.v v4, v8
- + vfwcvt.rtz.xu.f.v v4, v8
- + vfwcvt.rtz.x.f.v v4, v8
- + vfwcvt.f.xu.v v4, v8
- + vfwcvt.f.x.v v4, v8
- + vfwcvt.f.f.v v4, v8
- + vfwcvt.xu.f.v v4, v8, v0.t
- + vfwcvt.x.f.v v4, v8, v0.t
- + vfwcvt.rtz.xu.f.v v4, v8, v0.t
- + vfwcvt.rtz.x.f.v v4, v8, v0.t
- + vfwcvt.f.xu.v v4, v8, v0.t
- + vfwcvt.f.x.v v4, v8, v0.t
- + vfwcvt.f.f.v v4, v8, v0.t
- +
- + vfncvt.xu.f.w v4, v8
- + vfncvt.x.f.w v4, v8
- + vfncvt.rtz.xu.f.w v4, v8
- + vfncvt.rtz.x.f.w v4, v8
- + vfncvt.f.xu.w v4, v8
- + vfncvt.f.x.w v4, v8
- + vfncvt.f.f.w v4, v8
- + vfncvt.rod.f.f.w v4, v8
- + vfncvt.xu.f.w v4, v8, v0.t
- + vfncvt.x.f.w v4, v8, v0.t
- + vfncvt.rtz.xu.f.w v4, v8, v0.t
- + vfncvt.rtz.x.f.w v4, v8, v0.t
- + vfncvt.f.xu.w v4, v8, v0.t
- + vfncvt.f.x.w v4, v8, v0.t
- + vfncvt.f.f.w v4, v8, v0.t
- + vfncvt.rod.f.f.w v4, v8, v0.t
- +
- + vredsum.vs v4, v8, v12
- + vredmaxu.vs v4, v8, v8
- + vredmax.vs v4, v8, v8
- + vredminu.vs v4, v8, v8
- + vredmin.vs v4, v8, v8
- + vredand.vs v4, v8, v12
- + vredor.vs v4, v8, v12
- + vredxor.vs v4, v8, v12
- + vredsum.vs v4, v8, v12, v0.t
- + vredmaxu.vs v4, v8, v8, v0.t
- + vredmax.vs v4, v8, v8, v0.t
- + vredminu.vs v4, v8, v8, v0.t
- + vredmin.vs v4, v8, v8, v0.t
- + vredand.vs v4, v8, v12, v0.t
- + vredor.vs v4, v8, v12, v0.t
- + vredxor.vs v4, v8, v12, v0.t
- +
- + vwredsumu.vs v4, v8, v12
- + vwredsum.vs v4, v8, v12
- + vwredsumu.vs v4, v8, v12, v0.t
- + vwredsum.vs v4, v8, v12, v0.t
- +
- + vfredosum.vs v4, v8, v12
- + vfredsum.vs v4, v8, v12
- + vfredmax.vs v4, v8, v12
- + vfredmin.vs v4, v8, v12
- + vfredosum.vs v4, v8, v12, v0.t
- + vfredsum.vs v4, v8, v12, v0.t
- + vfredmax.vs v4, v8, v12, v0.t
- + vfredmin.vs v4, v8, v12, v0.t
- +
- + vfwredosum.vs v4, v8, v12
- + vfwredsum.vs v4, v8, v12
- + vfwredosum.vs v4, v8, v12, v0.t
- + vfwredsum.vs v4, v8, v12, v0.t
- +
- + # Aliases
- + vmcpy.m v4, v8
- + vmmv.m v4, v8
- + vmclr.m v4
- + vmset.m v4
- + vmnot.m v4, v8
- +
- + vmand.mm v4, v8, v12
- + vmnand.mm v4, v8, v12
- + vmandnot.mm v4, v8, v12
- + vmxor.mm v4, v8, v12
- + vmor.mm v4, v8, v12
- + vmnor.mm v4, v8, v12
- + vmornot.mm v4, v8, v12
- + vmxnor.mm v4, v8, v12
- +
- + vpopc.m a0, v12
- + vfirst.m a0, v12
- + vmsbf.m v4, v8
- + vmsif.m v4, v8
- + vmsof.m v4, v8
- + viota.m v4, v8
- + vid.v v4
- + vpopc.m a0, v12, v0.t
- + vfirst.m a0, v12, v0.t
- + vmsbf.m v4, v8, v0.t
- + vmsif.m v4, v8, v0.t
- + vmsof.m v4, v8, v0.t
- + viota.m v4, v8, v0.t
- + vid.v v4, v0.t
- +
- + vmv.x.s a0, v12
- + vmv.s.x v4, a0
- +
- + vfmv.f.s fa0, v8
- + vfmv.s.f v4, fa1
- +
- + vslideup.vx v4, v8, a1
- + vslideup.vi v4, v8, 0
- + vslideup.vi v4, v8, 31
- + vslidedown.vx v4, v8, a1
- + vslidedown.vi v4, v8, 0
- + vslidedown.vi v4, v8, 31
- + vslideup.vx v4, v8, a1, v0.t
- + vslideup.vi v4, v8, 0, v0.t
- + vslideup.vi v4, v8, 31, v0.t
- + vslidedown.vx v4, v8, a1, v0.t
- + vslidedown.vi v4, v8, 0, v0.t
- + vslidedown.vi v4, v8, 31, v0.t
- +
- + vslide1up.vx v4, v8, a1
- + vslide1down.vx v4, v8, a1
- + vslide1up.vx v4, v8, a1, v0.t
- + vslide1down.vx v4, v8, a1, v0.t
- +
- + vfslide1up.vf v4, v8, fa1
- + vfslide1down.vf v4, v8, fa1
- + vfslide1up.vf v4, v8, fa1, v0.t
- + vfslide1down.vf v4, v8, fa1, v0.t
- +
- + vrgather.vv v4, v8, v12
- + vrgather.vx v4, v8, a1
- + vrgather.vi v4, v8, 0
- + vrgather.vi v4, v8, 31
- + vrgather.vv v4, v8, v12, v0.t
- + vrgather.vx v4, v8, a1, v0.t
- + vrgather.vi v4, v8, 0, v0.t
- + vrgather.vi v4, v8, 31, v0.t
- +
- + vcompress.vm v4, v8, v12
- +
- + vmv1r.v v1, v2
- + vmv2r.v v2, v4
- + vmv4r.v v4, v8
- + vmv8r.v v0, v8
- +
- + vdot.vv v4, v8, v12
- + vdotu.vv v4, v8, v12
- + vfdot.vv v4, v8, v12
- + vdot.vv v4, v8, v12, v0.t
- + vdotu.vv v4, v8, v12, v0.t
- + vfdot.vv v4, v8, v12, v0.t
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index 158de32485..6ec4c2a33a 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -547,6 +547,2130 @@
- #define MASK_C_LDSP 0xe003
- #define MATCH_C_SDSP 0xe002
- #define MASK_C_SDSP 0xe003
- +
- +/* RVV */
- +/* Version 1.0-draft-20200516. */
- +
- +#define MATCH_VSETVL 0x80007057
- +#define MASK_VSETVL 0xfe00707f
- +#define MATCH_VSETVLI 0x00007057
- +#define MASK_VSETVLI 0x8000707f
- +
- +/* Temporary Load/store encoding info
- +MOP load
- +00 unit-stride VLE<EEW>, VLE<EEW>FF, VL<nf>RV (nf = 1)
- +01 reserved
- +10 strided VLSE<EEW>
- +11 indexed VLXEI<EEW>
- +
- +MOP store
- +00 unit-stride VSE<EEW>, VS<nf>RV (nf = 1)
- +01 indexed-unordered VSUXEI<EEW>
- +10 strided VSSE<EEW>
- +11 indexed-ordered VSXEI<EEW>
- +
- +VM 0 masked
- +VM 1 unmasked
- +
- +LUMOP
- +00000 unit-stride
- +00xxx reserved, x!=0
- +01000 unit-stride, whole registers
- +01xxx reserved, x!=0
- +10000 unit-stride first-fault
- +1xxxx reserved, x!=0
- +
- +SUMOP
- +00000 unit-stride
- +00xxx reserved, x!=0
- +01000 unit-stride, whole registers
- +01xxx reserved, x!=0
- +1xxxx reserved
- +
- +MEW WIDTH
- +- ---
- +x 001 FLH/FSH
- +x 010 FLW/FSW
- +x 011 FLD/FSW
- +x 100 FLQ/FSQ
- +0 000 VLxE8/VSxE8
- +0 101 VLxE16/VSxE16
- +0 110 VLxE32/VSxE32
- +0 111 VLxE64/VSxE64
- +1 000 VLxE128/VSxE128
- +1 101 VLxE256/VSxE256
- +1 110 VLxE512/VSxE512
- +1 111 VLxE1024/VSxE1024
- +
- +NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
- +000 - 00 x 00000 xxxxx --- xxxxx 0000111 VLE<EEW>
- +000 - 00 x 00000 xxxxx --- xxxxx 0100111 VSE<EEW>
- +000 - 10 x xxxxx xxxxx --- xxxxx 0000111 VLSE<EEW>
- +000 - 10 x xxxxx xxxxx --- xxxxx 0100111 VSSE<EEW>
- +000 - 11 x xxxxx xxxxx --- xxxxx 0000111 VLXE<EEW>I
- +000 - 11 x xxxxx xxxxx --- xxxxx 0100111 VSXE<EEW>I
- +000 - 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
- +000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
- +000 0 00 1 01000 xxxxx 000 xxxxx 0000111 VL<nf>R, nf = 1
- +000 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1
- +
- +xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
- +xxx - 00 x 00000 xxxxx --- xxxxx 0100111 VSSEG<nf>E<EEW>
- +xxx - 10 x 00000 xxxxx --- xxxxx 0000111 VLSSEG<nf>E<EEW>
- +xxx - 10 x 00000 xxxxx --- xxxxx 0100111 VSSSEG<nf>E<EEW>
- +xxx - 11 x 00000 xxxxx --- xxxxx 0000111 VLXSEG<nf>E<EEW>I
- +xxx - 11 x 00000 xxxxx --- xxxxx 0100111 VSXSEG<nf>E<EEW>I
- +xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
- +*/
- +
- +#define MATCH_VLE8V 0x00000007
- +#define MASK_VLE8V 0xfdf0707f
- +#define MATCH_VLE16V 0x00005007
- +#define MASK_VLE16V 0xfdf0707f
- +#define MATCH_VLE32V 0x00006007
- +#define MASK_VLE32V 0xfdf0707f
- +#define MATCH_VLE64V 0x00007007
- +#define MASK_VLE64V 0xfdf0707f
- +#define MATCH_VLE128V 0x10000007
- +#define MASK_VLE128V 0xfdf0707f
- +#define MATCH_VLE256V 0x10005007
- +#define MASK_VLE256V 0xfdf0707f
- +#define MATCH_VLE512V 0x10006007
- +#define MASK_VLE512V 0xfdf0707f
- +#define MATCH_VLE1024V 0x10007007
- +#define MASK_VLE1024V 0xfdf0707f
- +
- +#define MATCH_VSE8V 0x00000027
- +#define MASK_VSE8V 0xfdf0707f
- +#define MATCH_VSE16V 0x00005027
- +#define MASK_VSE16V 0xfdf0707f
- +#define MATCH_VSE32V 0x00006027
- +#define MASK_VSE32V 0xfdf0707f
- +#define MATCH_VSE64V 0x00007027
- +#define MASK_VSE64V 0xfdf0707f
- +#define MATCH_VSE128V 0x10000027
- +#define MASK_VSE128V 0xfdf0707f
- +#define MATCH_VSE256V 0x10005027
- +#define MASK_VSE256V 0xfdf0707f
- +#define MATCH_VSE512V 0x10006027
- +#define MASK_VSE512V 0xfdf0707f
- +#define MATCH_VSE1024V 0x10007027
- +#define MASK_VSE1024V 0xfdf0707f
- +
- +#define MATCH_VLSE8V 0x08000007
- +#define MASK_VLSE8V 0xfc00707f
- +#define MATCH_VLSE16V 0x08005007
- +#define MASK_VLSE16V 0xfc00707f
- +#define MATCH_VLSE32V 0x08006007
- +#define MASK_VLSE32V 0xfc00707f
- +#define MATCH_VLSE64V 0x08007007
- +#define MASK_VLSE64V 0xfc00707f
- +#define MATCH_VLSE128V 0x18000007
- +#define MASK_VLSE128V 0xfc00707f
- +#define MATCH_VLSE256V 0x18005007
- +#define MASK_VLSE256V 0xfc00707f
- +#define MATCH_VLSE512V 0x18006007
- +#define MASK_VLSE512V 0xfc00707f
- +#define MATCH_VLSE1024V 0x18007007
- +#define MASK_VLSE1024V 0xfc00707f
- +
- +#define MATCH_VSSE8V 0x08000027
- +#define MASK_VSSE8V 0xfc00707f
- +#define MATCH_VSSE16V 0x08005027
- +#define MASK_VSSE16V 0xfc00707f
- +#define MATCH_VSSE32V 0x08006027
- +#define MASK_VSSE32V 0xfc00707f
- +#define MATCH_VSSE64V 0x08007027
- +#define MASK_VSSE64V 0xfc00707f
- +#define MATCH_VSSE128V 0x18000027
- +#define MASK_VSSE128V 0xfc00707f
- +#define MATCH_VSSE256V 0x18005027
- +#define MASK_VSSE256V 0xfc00707f
- +#define MATCH_VSSE512V 0x18006027
- +#define MASK_VSSE512V 0xfc00707f
- +#define MATCH_VSSE1024V 0x18007027
- +#define MASK_VSSE1024V 0xfc00707f
- +
- +#define MATCH_VLXEI8V 0x0c000007
- +#define MASK_VLXEI8V 0xfc00707f
- +#define MATCH_VLXEI16V 0x0c005007
- +#define MASK_VLXEI16V 0xfc00707f
- +#define MATCH_VLXEI32V 0x0c006007
- +#define MASK_VLXEI32V 0xfc00707f
- +#define MATCH_VLXEI64V 0x0c007007
- +#define MASK_VLXEI64V 0xfc00707f
- +#define MATCH_VLXEI128V 0x1c000007
- +#define MASK_VLXEI128V 0xfc00707f
- +#define MATCH_VLXEI256V 0x1c005007
- +#define MASK_VLXEI256V 0xfc00707f
- +#define MATCH_VLXEI512V 0x1c006007
- +#define MASK_VLXEI512V 0xfc00707f
- +#define MATCH_VLXEI1024V 0x1c007007
- +#define MASK_VLXEI1024V 0xfc00707f
- +
- +#define MATCH_VSXEI8V 0x0c000027
- +#define MASK_VSXEI8V 0xfc00707f
- +#define MATCH_VSXEI16V 0x0c005027
- +#define MASK_VSXEI16V 0xfc00707f
- +#define MATCH_VSXEI32V 0x0c006027
- +#define MASK_VSXEI32V 0xfc00707f
- +#define MATCH_VSXEI64V 0x0c007027
- +#define MASK_VSXEI64V 0xfc00707f
- +#define MATCH_VSXEI128V 0x1c000027
- +#define MASK_VSXEI128V 0xfc00707f
- +#define MATCH_VSXEI256V 0x1c005027
- +#define MASK_VSXEI256V 0xfc00707f
- +#define MATCH_VSXEI512V 0x1c006027
- +#define MASK_VSXEI512V 0xfc00707f
- +#define MATCH_VSXEI1024V 0x1c007027
- +#define MASK_VSXEI1024V 0xfc00707f
- +
- +#define MATCH_VSUXEI8V 0x04000027
- +#define MASK_VSUXEI8V 0xfc00707f
- +#define MATCH_VSUXEI16V 0x04005027
- +#define MASK_VSUXEI16V 0xfc00707f
- +#define MATCH_VSUXEI32V 0x04006027
- +#define MASK_VSUXEI32V 0xfc00707f
- +#define MATCH_VSUXEI64V 0x04007027
- +#define MASK_VSUXEI64V 0xfc00707f
- +#define MATCH_VSUXEI128V 0x14000027
- +#define MASK_VSUXEI128V 0xfc00707f
- +#define MATCH_VSUXEI256V 0x14005027
- +#define MASK_VSUXEI256V 0xfc00707f
- +#define MATCH_VSUXEI512V 0x14006027
- +#define MASK_VSUXEI512V 0xfc00707f
- +#define MATCH_VSUXEI1024V 0x14007027
- +#define MASK_VSUXEI1024V 0xfc00707f
- +
- +#define MATCH_VLE8FFV 0x01000007
- +#define MASK_VLE8FFV 0xfdf0707f
- +#define MATCH_VLE16FFV 0x01005007
- +#define MASK_VLE16FFV 0xfdf0707f
- +#define MATCH_VLE32FFV 0x01006007
- +#define MASK_VLE32FFV 0xfdf0707f
- +#define MATCH_VLE64FFV 0x01007007
- +#define MASK_VLE64FFV 0xfdf0707f
- +#define MATCH_VLE128FFV 0x11000007
- +#define MASK_VLE128FFV 0xfdf0707f
- +#define MATCH_VLE256FFV 0x11005007
- +#define MASK_VLE256FFV 0xfdf0707f
- +#define MATCH_VLE512FFV 0x11006007
- +#define MASK_VLE512FFV 0xfdf0707f
- +#define MATCH_VLE1024FFV 0x11007007
- +#define MASK_VLE1024FFV 0xfdf0707f
- +
- +#define MATCH_VLSEG2E8V 0x20000007
- +#define MASK_VLSEG2E8V 0xfdf0707f
- +#define MATCH_VSSEG2E8V 0x20000027
- +#define MASK_VSSEG2E8V 0xfdf0707f
- +#define MATCH_VLSEG3E8V 0x40000007
- +#define MASK_VLSEG3E8V 0xfdf0707f
- +#define MATCH_VSSEG3E8V 0x40000027
- +#define MASK_VSSEG3E8V 0xfdf0707f
- +#define MATCH_VLSEG4E8V 0x60000007
- +#define MASK_VLSEG4E8V 0xfdf0707f
- +#define MATCH_VSSEG4E8V 0x60000027
- +#define MASK_VSSEG4E8V 0xfdf0707f
- +#define MATCH_VLSEG5E8V 0x80000007
- +#define MASK_VLSEG5E8V 0xfdf0707f
- +#define MATCH_VSSEG5E8V 0x80000027
- +#define MASK_VSSEG5E8V 0xfdf0707f
- +#define MATCH_VLSEG6E8V 0xa0000007
- +#define MASK_VLSEG6E8V 0xfdf0707f
- +#define MATCH_VSSEG6E8V 0xa0000027
- +#define MASK_VSSEG6E8V 0xfdf0707f
- +#define MATCH_VLSEG7E8V 0xc0000007
- +#define MASK_VLSEG7E8V 0xfdf0707f
- +#define MATCH_VSSEG7E8V 0xc0000027
- +#define MASK_VSSEG7E8V 0xfdf0707f
- +#define MATCH_VLSEG8E8V 0xe0000007
- +#define MASK_VLSEG8E8V 0xfdf0707f
- +#define MATCH_VSSEG8E8V 0xe0000027
- +#define MASK_VSSEG8E8V 0xfdf0707f
- +
- +#define MATCH_VLSEG2E16V 0x20005007
- +#define MASK_VLSEG2E16V 0xfdf0707f
- +#define MATCH_VSSEG2E16V 0x20005027
- +#define MASK_VSSEG2E16V 0xfdf0707f
- +#define MATCH_VLSEG3E16V 0x40005007
- +#define MASK_VLSEG3E16V 0xfdf0707f
- +#define MATCH_VSSEG3E16V 0x40005027
- +#define MASK_VSSEG3E16V 0xfdf0707f
- +#define MATCH_VLSEG4E16V 0x60005007
- +#define MASK_VLSEG4E16V 0xfdf0707f
- +#define MATCH_VSSEG4E16V 0x60005027
- +#define MASK_VSSEG4E16V 0xfdf0707f
- +#define MATCH_VLSEG5E16V 0x80005007
- +#define MASK_VLSEG5E16V 0xfdf0707f
- +#define MATCH_VSSEG5E16V 0x80005027
- +#define MASK_VSSEG5E16V 0xfdf0707f
- +#define MATCH_VLSEG6E16V 0xa0005007
- +#define MASK_VLSEG6E16V 0xfdf0707f
- +#define MATCH_VSSEG6E16V 0xa0005027
- +#define MASK_VSSEG6E16V 0xfdf0707f
- +#define MATCH_VLSEG7E16V 0xc0005007
- +#define MASK_VLSEG7E16V 0xfdf0707f
- +#define MATCH_VSSEG7E16V 0xc0005027
- +#define MASK_VSSEG7E16V 0xfdf0707f
- +#define MATCH_VLSEG8E16V 0xe0005007
- +#define MASK_VLSEG8E16V 0xfdf0707f
- +#define MATCH_VSSEG8E16V 0xe0005027
- +#define MASK_VSSEG8E16V 0xfdf0707f
- +
- +#define MATCH_VLSEG2E32V 0x20006007
- +#define MASK_VLSEG2E32V 0xfdf0707f
- +#define MATCH_VSSEG2E32V 0x20006027
- +#define MASK_VSSEG2E32V 0xfdf0707f
- +#define MATCH_VLSEG3E32V 0x40006007
- +#define MASK_VLSEG3E32V 0xfdf0707f
- +#define MATCH_VSSEG3E32V 0x40006027
- +#define MASK_VSSEG3E32V 0xfdf0707f
- +#define MATCH_VLSEG4E32V 0x60006007
- +#define MASK_VLSEG4E32V 0xfdf0707f
- +#define MATCH_VSSEG4E32V 0x60006027
- +#define MASK_VSSEG4E32V 0xfdf0707f
- +#define MATCH_VLSEG5E32V 0x80006007
- +#define MASK_VLSEG5E32V 0xfdf0707f
- +#define MATCH_VSSEG5E32V 0x80006027
- +#define MASK_VSSEG5E32V 0xfdf0707f
- +#define MATCH_VLSEG6E32V 0xa0006007
- +#define MASK_VLSEG6E32V 0xfdf0707f
- +#define MATCH_VSSEG6E32V 0xa0006027
- +#define MASK_VSSEG6E32V 0xfdf0707f
- +#define MATCH_VLSEG7E32V 0xc0006007
- +#define MASK_VLSEG7E32V 0xfdf0707f
- +#define MATCH_VSSEG7E32V 0xc0006027
- +#define MASK_VSSEG7E32V 0xfdf0707f
- +#define MATCH_VLSEG8E32V 0xe0006007
- +#define MASK_VLSEG8E32V 0xfdf0707f
- +#define MATCH_VSSEG8E32V 0xe0006027
- +#define MASK_VSSEG8E32V 0xfdf0707f
- +
- +#define MATCH_VLSEG2E64V 0x20007007
- +#define MASK_VLSEG2E64V 0xfdf0707f
- +#define MATCH_VSSEG2E64V 0x20007027
- +#define MASK_VSSEG2E64V 0xfdf0707f
- +#define MATCH_VLSEG3E64V 0x40007007
- +#define MASK_VLSEG3E64V 0xfdf0707f
- +#define MATCH_VSSEG3E64V 0x40007027
- +#define MASK_VSSEG3E64V 0xfdf0707f
- +#define MATCH_VLSEG4E64V 0x60007007
- +#define MASK_VLSEG4E64V 0xfdf0707f
- +#define MATCH_VSSEG4E64V 0x60007027
- +#define MASK_VSSEG4E64V 0xfdf0707f
- +#define MATCH_VLSEG5E64V 0x80007007
- +#define MASK_VLSEG5E64V 0xfdf0707f
- +#define MATCH_VSSEG5E64V 0x80007027
- +#define MASK_VSSEG5E64V 0xfdf0707f
- +#define MATCH_VLSEG6E64V 0xa0007007
- +#define MASK_VLSEG6E64V 0xfdf0707f
- +#define MATCH_VSSEG6E64V 0xa0007027
- +#define MASK_VSSEG6E64V 0xfdf0707f
- +#define MATCH_VLSEG7E64V 0xc0007007
- +#define MASK_VLSEG7E64V 0xfdf0707f
- +#define MATCH_VSSEG7E64V 0xc0007027
- +#define MASK_VSSEG7E64V 0xfdf0707f
- +#define MATCH_VLSEG8E64V 0xe0007007
- +#define MASK_VLSEG8E64V 0xfdf0707f
- +#define MATCH_VSSEG8E64V 0xe0007027
- +#define MASK_VSSEG8E64V 0xfdf0707f
- +
- +#define MATCH_VLSEG2E128V 0x30000007
- +#define MASK_VLSEG2E128V 0xfdf0707f
- +#define MATCH_VSSEG2E128V 0x30000027
- +#define MASK_VSSEG2E128V 0xfdf0707f
- +#define MATCH_VLSEG3E128V 0x50000007
- +#define MASK_VLSEG3E128V 0xfdf0707f
- +#define MATCH_VSSEG3E128V 0x50000027
- +#define MASK_VSSEG3E128V 0xfdf0707f
- +#define MATCH_VLSEG4E128V 0x70000007
- +#define MASK_VLSEG4E128V 0xfdf0707f
- +#define MATCH_VSSEG4E128V 0x70000027
- +#define MASK_VSSEG4E128V 0xfdf0707f
- +#define MATCH_VLSEG5E128V 0x90000007
- +#define MASK_VLSEG5E128V 0xfdf0707f
- +#define MATCH_VSSEG5E128V 0x90000027
- +#define MASK_VSSEG5E128V 0xfdf0707f
- +#define MATCH_VLSEG6E128V 0xb0000007
- +#define MASK_VLSEG6E128V 0xfdf0707f
- +#define MATCH_VSSEG6E128V 0xb0000027
- +#define MASK_VSSEG6E128V 0xfdf0707f
- +#define MATCH_VLSEG7E128V 0xd0000007
- +#define MASK_VLSEG7E128V 0xfdf0707f
- +#define MATCH_VSSEG7E128V 0xd0000027
- +#define MASK_VSSEG7E128V 0xfdf0707f
- +#define MATCH_VLSEG8E128V 0xf0000007
- +#define MASK_VLSEG8E128V 0xfdf0707f
- +#define MATCH_VSSEG8E128V 0xf0000027
- +#define MASK_VSSEG8E128V 0xfdf0707f
- +
- +#define MATCH_VLSEG2E256V 0x30005007
- +#define MASK_VLSEG2E256V 0xfdf0707f
- +#define MATCH_VSSEG2E256V 0x30005027
- +#define MASK_VSSEG2E256V 0xfdf0707f
- +#define MATCH_VLSEG3E256V 0x50005007
- +#define MASK_VLSEG3E256V 0xfdf0707f
- +#define MATCH_VSSEG3E256V 0x50005027
- +#define MASK_VSSEG3E256V 0xfdf0707f
- +#define MATCH_VLSEG4E256V 0x70005007
- +#define MASK_VLSEG4E256V 0xfdf0707f
- +#define MATCH_VSSEG4E256V 0x70005027
- +#define MASK_VSSEG4E256V 0xfdf0707f
- +#define MATCH_VLSEG5E256V 0x90005007
- +#define MASK_VLSEG5E256V 0xfdf0707f
- +#define MATCH_VSSEG5E256V 0x90005027
- +#define MASK_VSSEG5E256V 0xfdf0707f
- +#define MATCH_VLSEG6E256V 0xb0005007
- +#define MASK_VLSEG6E256V 0xfdf0707f
- +#define MATCH_VSSEG6E256V 0xb0005027
- +#define MASK_VSSEG6E256V 0xfdf0707f
- +#define MATCH_VLSEG7E256V 0xd0005007
- +#define MASK_VLSEG7E256V 0xfdf0707f
- +#define MATCH_VSSEG7E256V 0xd0005027
- +#define MASK_VSSEG7E256V 0xfdf0707f
- +#define MATCH_VLSEG8E256V 0xf0005007
- +#define MASK_VLSEG8E256V 0xfdf0707f
- +#define MATCH_VSSEG8E256V 0xf0005027
- +#define MASK_VSSEG8E256V 0xfdf0707f
- +
- +#define MATCH_VLSEG2E512V 0x30006007
- +#define MASK_VLSEG2E512V 0xfdf0707f
- +#define MATCH_VSSEG2E512V 0x30006027
- +#define MASK_VSSEG2E512V 0xfdf0707f
- +#define MATCH_VLSEG3E512V 0x50006007
- +#define MASK_VLSEG3E512V 0xfdf0707f
- +#define MATCH_VSSEG3E512V 0x50006027
- +#define MASK_VSSEG3E512V 0xfdf0707f
- +#define MATCH_VLSEG4E512V 0x70006007
- +#define MASK_VLSEG4E512V 0xfdf0707f
- +#define MATCH_VSSEG4E512V 0x70006027
- +#define MASK_VSSEG4E512V 0xfdf0707f
- +#define MATCH_VLSEG5E512V 0x90006007
- +#define MASK_VLSEG5E512V 0xfdf0707f
- +#define MATCH_VSSEG5E512V 0x90006027
- +#define MASK_VSSEG5E512V 0xfdf0707f
- +#define MATCH_VLSEG6E512V 0xb0006007
- +#define MASK_VLSEG6E512V 0xfdf0707f
- +#define MATCH_VSSEG6E512V 0xb0006027
- +#define MASK_VSSEG6E512V 0xfdf0707f
- +#define MATCH_VLSEG7E512V 0xd0006007
- +#define MASK_VLSEG7E512V 0xfdf0707f
- +#define MATCH_VSSEG7E512V 0xd0006027
- +#define MASK_VSSEG7E512V 0xfdf0707f
- +#define MATCH_VLSEG8E512V 0xf0006007
- +#define MASK_VLSEG8E512V 0xfdf0707f
- +#define MATCH_VSSEG8E512V 0xf0006027
- +#define MASK_VSSEG8E512V 0xfdf0707f
- +
- +#define MATCH_VLSEG2E1024V 0x30007007
- +#define MASK_VLSEG2E1024V 0xfdf0707f
- +#define MATCH_VSSEG2E1024V 0x30007027
- +#define MASK_VSSEG2E1024V 0xfdf0707f
- +#define MATCH_VLSEG3E1024V 0x50007007
- +#define MASK_VLSEG3E1024V 0xfdf0707f
- +#define MATCH_VSSEG3E1024V 0x50007027
- +#define MASK_VSSEG3E1024V 0xfdf0707f
- +#define MATCH_VLSEG4E1024V 0x70007007
- +#define MASK_VLSEG4E1024V 0xfdf0707f
- +#define MATCH_VSSEG4E1024V 0x70007027
- +#define MASK_VSSEG4E1024V 0xfdf0707f
- +#define MATCH_VLSEG5E1024V 0x90007007
- +#define MASK_VLSEG5E1024V 0xfdf0707f
- +#define MATCH_VSSEG5E1024V 0x90007027
- +#define MASK_VSSEG5E1024V 0xfdf0707f
- +#define MATCH_VLSEG6E1024V 0xb0007007
- +#define MASK_VLSEG6E1024V 0xfdf0707f
- +#define MATCH_VSSEG6E1024V 0xb0007027
- +#define MASK_VSSEG6E1024V 0xfdf0707f
- +#define MATCH_VLSEG7E1024V 0xd0007007
- +#define MASK_VLSEG7E1024V 0xfdf0707f
- +#define MATCH_VSSEG7E1024V 0xd0007027
- +#define MASK_VSSEG7E1024V 0xfdf0707f
- +#define MATCH_VLSEG8E1024V 0xf0007007
- +#define MASK_VLSEG8E1024V 0xfdf0707f
- +#define MATCH_VSSEG8E1024V 0xf0007027
- +#define MASK_VSSEG8E1024V 0xfdf0707f
- +
- +#define MATCH_VLSSEG2E8V 0x28000007
- +#define MASK_VLSSEG2E8V 0xfc00707f
- +#define MATCH_VSSSEG2E8V 0x28000027
- +#define MASK_VSSSEG2E8V 0xfc00707f
- +#define MATCH_VLSSEG3E8V 0x48000007
- +#define MASK_VLSSEG3E8V 0xfc00707f
- +#define MATCH_VSSSEG3E8V 0x48000027
- +#define MASK_VSSSEG3E8V 0xfc00707f
- +#define MATCH_VLSSEG4E8V 0x68000007
- +#define MASK_VLSSEG4E8V 0xfc00707f
- +#define MATCH_VSSSEG4E8V 0x68000027
- +#define MASK_VSSSEG4E8V 0xfc00707f
- +#define MATCH_VLSSEG5E8V 0x88000007
- +#define MASK_VLSSEG5E8V 0xfc00707f
- +#define MATCH_VSSSEG5E8V 0x88000027
- +#define MASK_VSSSEG5E8V 0xfc00707f
- +#define MATCH_VLSSEG6E8V 0xa8000007
- +#define MASK_VLSSEG6E8V 0xfc00707f
- +#define MATCH_VSSSEG6E8V 0xa8000027
- +#define MASK_VSSSEG6E8V 0xfc00707f
- +#define MATCH_VLSSEG7E8V 0xc8000007
- +#define MASK_VLSSEG7E8V 0xfc00707f
- +#define MATCH_VSSSEG7E8V 0xc8000027
- +#define MASK_VSSSEG7E8V 0xfc00707f
- +#define MATCH_VLSSEG8E8V 0xe8000007
- +#define MASK_VLSSEG8E8V 0xfc00707f
- +#define MATCH_VSSSEG8E8V 0xe8000027
- +#define MASK_VSSSEG8E8V 0xfc00707f
- +
- +#define MATCH_VLSSEG2E16V 0x28005007
- +#define MASK_VLSSEG2E16V 0xfc00707f
- +#define MATCH_VSSSEG2E16V 0x28005027
- +#define MASK_VSSSEG2E16V 0xfc00707f
- +#define MATCH_VLSSEG3E16V 0x48005007
- +#define MASK_VLSSEG3E16V 0xfc00707f
- +#define MATCH_VSSSEG3E16V 0x48005027
- +#define MASK_VSSSEG3E16V 0xfc00707f
- +#define MATCH_VLSSEG4E16V 0x68005007
- +#define MASK_VLSSEG4E16V 0xfc00707f
- +#define MATCH_VSSSEG4E16V 0x68005027
- +#define MASK_VSSSEG4E16V 0xfc00707f
- +#define MATCH_VLSSEG5E16V 0x88005007
- +#define MASK_VLSSEG5E16V 0xfc00707f
- +#define MATCH_VSSSEG5E16V 0x88005027
- +#define MASK_VSSSEG5E16V 0xfc00707f
- +#define MATCH_VLSSEG6E16V 0xa8005007
- +#define MASK_VLSSEG6E16V 0xfc00707f
- +#define MATCH_VSSSEG6E16V 0xa8005027
- +#define MASK_VSSSEG6E16V 0xfc00707f
- +#define MATCH_VLSSEG7E16V 0xc8005007
- +#define MASK_VLSSEG7E16V 0xfc00707f
- +#define MATCH_VSSSEG7E16V 0xc8005027
- +#define MASK_VSSSEG7E16V 0xfc00707f
- +#define MATCH_VLSSEG8E16V 0xe8005007
- +#define MASK_VLSSEG8E16V 0xfc00707f
- +#define MATCH_VSSSEG8E16V 0xe8005027
- +#define MASK_VSSSEG8E16V 0xfc00707f
- +
- +#define MATCH_VLSSEG2E32V 0x28006007
- +#define MASK_VLSSEG2E32V 0xfc00707f
- +#define MATCH_VSSSEG2E32V 0x28006027
- +#define MASK_VSSSEG2E32V 0xfc00707f
- +#define MATCH_VLSSEG3E32V 0x48006007
- +#define MASK_VLSSEG3E32V 0xfc00707f
- +#define MATCH_VSSSEG3E32V 0x48006027
- +#define MASK_VSSSEG3E32V 0xfc00707f
- +#define MATCH_VLSSEG4E32V 0x68006007
- +#define MASK_VLSSEG4E32V 0xfc00707f
- +#define MATCH_VSSSEG4E32V 0x68006027
- +#define MASK_VSSSEG4E32V 0xfc00707f
- +#define MATCH_VLSSEG5E32V 0x88006007
- +#define MASK_VLSSEG5E32V 0xfc00707f
- +#define MATCH_VSSSEG5E32V 0x88006027
- +#define MASK_VSSSEG5E32V 0xfc00707f
- +#define MATCH_VLSSEG6E32V 0xa8006007
- +#define MASK_VLSSEG6E32V 0xfc00707f
- +#define MATCH_VSSSEG6E32V 0xa8006027
- +#define MASK_VSSSEG6E32V 0xfc00707f
- +#define MATCH_VLSSEG7E32V 0xc8006007
- +#define MASK_VLSSEG7E32V 0xfc00707f
- +#define MATCH_VSSSEG7E32V 0xc8006027
- +#define MASK_VSSSEG7E32V 0xfc00707f
- +#define MATCH_VLSSEG8E32V 0xe8006007
- +#define MASK_VLSSEG8E32V 0xfc00707f
- +#define MATCH_VSSSEG8E32V 0xe8006027
- +#define MASK_VSSSEG8E32V 0xfc00707f
- +
- +#define MATCH_VLSSEG2E64V 0x28007007
- +#define MASK_VLSSEG2E64V 0xfc00707f
- +#define MATCH_VSSSEG2E64V 0x28007027
- +#define MASK_VSSSEG2E64V 0xfc00707f
- +#define MATCH_VLSSEG3E64V 0x48007007
- +#define MASK_VLSSEG3E64V 0xfc00707f
- +#define MATCH_VSSSEG3E64V 0x48007027
- +#define MASK_VSSSEG3E64V 0xfc00707f
- +#define MATCH_VLSSEG4E64V 0x68007007
- +#define MASK_VLSSEG4E64V 0xfc00707f
- +#define MATCH_VSSSEG4E64V 0x68007027
- +#define MASK_VSSSEG4E64V 0xfc00707f
- +#define MATCH_VLSSEG5E64V 0x88007007
- +#define MASK_VLSSEG5E64V 0xfc00707f
- +#define MATCH_VSSSEG5E64V 0x88007027
- +#define MASK_VSSSEG5E64V 0xfc00707f
- +#define MATCH_VLSSEG6E64V 0xa8007007
- +#define MASK_VLSSEG6E64V 0xfc00707f
- +#define MATCH_VSSSEG6E64V 0xa8007027
- +#define MASK_VSSSEG6E64V 0xfc00707f
- +#define MATCH_VLSSEG7E64V 0xc8007007
- +#define MASK_VLSSEG7E64V 0xfc00707f
- +#define MATCH_VSSSEG7E64V 0xc8007027
- +#define MASK_VSSSEG7E64V 0xfc00707f
- +#define MATCH_VLSSEG8E64V 0xe8007007
- +#define MASK_VLSSEG8E64V 0xfc00707f
- +#define MATCH_VSSSEG8E64V 0xe8007027
- +#define MASK_VSSSEG8E64V 0xfc00707f
- +
- +#define MATCH_VLSSEG2E128V 0x38000007
- +#define MASK_VLSSEG2E128V 0xfc00707f
- +#define MATCH_VSSSEG2E128V 0x38000027
- +#define MASK_VSSSEG2E128V 0xfc00707f
- +#define MATCH_VLSSEG3E128V 0x58000007
- +#define MASK_VLSSEG3E128V 0xfc00707f
- +#define MATCH_VSSSEG3E128V 0x58000027
- +#define MASK_VSSSEG3E128V 0xfc00707f
- +#define MATCH_VLSSEG4E128V 0x78000007
- +#define MASK_VLSSEG4E128V 0xfc00707f
- +#define MATCH_VSSSEG4E128V 0x78000027
- +#define MASK_VSSSEG4E128V 0xfc00707f
- +#define MATCH_VLSSEG5E128V 0x98000007
- +#define MASK_VLSSEG5E128V 0xfc00707f
- +#define MATCH_VSSSEG5E128V 0x98000027
- +#define MASK_VSSSEG5E128V 0xfc00707f
- +#define MATCH_VLSSEG6E128V 0xb8000007
- +#define MASK_VLSSEG6E128V 0xfc00707f
- +#define MATCH_VSSSEG6E128V 0xb8000027
- +#define MASK_VSSSEG6E128V 0xfc00707f
- +#define MATCH_VLSSEG7E128V 0xd8000007
- +#define MASK_VLSSEG7E128V 0xfc00707f
- +#define MATCH_VSSSEG7E128V 0xd8000027
- +#define MASK_VSSSEG7E128V 0xfc00707f
- +#define MATCH_VLSSEG8E128V 0xf8000007
- +#define MASK_VLSSEG8E128V 0xfc00707f
- +#define MATCH_VSSSEG8E128V 0xf8000027
- +#define MASK_VSSSEG8E128V 0xfc00707f
- +
- +#define MATCH_VLSSEG2E256V 0x38005007
- +#define MASK_VLSSEG2E256V 0xfc00707f
- +#define MATCH_VSSSEG2E256V 0x38005027
- +#define MASK_VSSSEG2E256V 0xfc00707f
- +#define MATCH_VLSSEG3E256V 0x58005007
- +#define MASK_VLSSEG3E256V 0xfc00707f
- +#define MATCH_VSSSEG3E256V 0x58005027
- +#define MASK_VSSSEG3E256V 0xfc00707f
- +#define MATCH_VLSSEG4E256V 0x78005007
- +#define MASK_VLSSEG4E256V 0xfc00707f
- +#define MATCH_VSSSEG4E256V 0x78005027
- +#define MASK_VSSSEG4E256V 0xfc00707f
- +#define MATCH_VLSSEG5E256V 0x98005007
- +#define MASK_VLSSEG5E256V 0xfc00707f
- +#define MATCH_VSSSEG5E256V 0x98005027
- +#define MASK_VSSSEG5E256V 0xfc00707f
- +#define MATCH_VLSSEG6E256V 0xb8005007
- +#define MASK_VLSSEG6E256V 0xfc00707f
- +#define MATCH_VSSSEG6E256V 0xb8005027
- +#define MASK_VSSSEG6E256V 0xfc00707f
- +#define MATCH_VLSSEG7E256V 0xd8005007
- +#define MASK_VLSSEG7E256V 0xfc00707f
- +#define MATCH_VSSSEG7E256V 0xd8005027
- +#define MASK_VSSSEG7E256V 0xfc00707f
- +#define MATCH_VLSSEG8E256V 0xf8005007
- +#define MASK_VLSSEG8E256V 0xfc00707f
- +#define MATCH_VSSSEG8E256V 0xf8005027
- +#define MASK_VSSSEG8E256V 0xfc00707f
- +
- +#define MATCH_VLSSEG2E512V 0x38006007
- +#define MASK_VLSSEG2E512V 0xfc00707f
- +#define MATCH_VSSSEG2E512V 0x38006027
- +#define MASK_VSSSEG2E512V 0xfc00707f
- +#define MATCH_VLSSEG3E512V 0x58006007
- +#define MASK_VLSSEG3E512V 0xfc00707f
- +#define MATCH_VSSSEG3E512V 0x58006027
- +#define MASK_VSSSEG3E512V 0xfc00707f
- +#define MATCH_VLSSEG4E512V 0x78006007
- +#define MASK_VLSSEG4E512V 0xfc00707f
- +#define MATCH_VSSSEG4E512V 0x78006027
- +#define MASK_VSSSEG4E512V 0xfc00707f
- +#define MATCH_VLSSEG5E512V 0x98006007
- +#define MASK_VLSSEG5E512V 0xfc00707f
- +#define MATCH_VSSSEG5E512V 0x98006027
- +#define MASK_VSSSEG5E512V 0xfc00707f
- +#define MATCH_VLSSEG6E512V 0xb8006007
- +#define MASK_VLSSEG6E512V 0xfc00707f
- +#define MATCH_VSSSEG6E512V 0xb8006027
- +#define MASK_VSSSEG6E512V 0xfc00707f
- +#define MATCH_VLSSEG7E512V 0xd8006007
- +#define MASK_VLSSEG7E512V 0xfc00707f
- +#define MATCH_VSSSEG7E512V 0xd8006027
- +#define MASK_VSSSEG7E512V 0xfc00707f
- +#define MATCH_VLSSEG8E512V 0xf8006007
- +#define MASK_VLSSEG8E512V 0xfc00707f
- +#define MATCH_VSSSEG8E512V 0xf8006027
- +#define MASK_VSSSEG8E512V 0xfc00707f
- +
- +#define MATCH_VLSSEG2E1024V 0x38007007
- +#define MASK_VLSSEG2E1024V 0xfc00707f
- +#define MATCH_VSSSEG2E1024V 0x38007027
- +#define MASK_VSSSEG2E1024V 0xfc00707f
- +#define MATCH_VLSSEG3E1024V 0x58007007
- +#define MASK_VLSSEG3E1024V 0xfc00707f
- +#define MATCH_VSSSEG3E1024V 0x58007027
- +#define MASK_VSSSEG3E1024V 0xfc00707f
- +#define MATCH_VLSSEG4E1024V 0x78007007
- +#define MASK_VLSSEG4E1024V 0xfc00707f
- +#define MATCH_VSSSEG4E1024V 0x78007027
- +#define MASK_VSSSEG4E1024V 0xfc00707f
- +#define MATCH_VLSSEG5E1024V 0x98007007
- +#define MASK_VLSSEG5E1024V 0xfc00707f
- +#define MATCH_VSSSEG5E1024V 0x98007027
- +#define MASK_VSSSEG5E1024V 0xfc00707f
- +#define MATCH_VLSSEG6E1024V 0xb8007007
- +#define MASK_VLSSEG6E1024V 0xfc00707f
- +#define MATCH_VSSSEG6E1024V 0xb8007027
- +#define MASK_VSSSEG6E1024V 0xfc00707f
- +#define MATCH_VLSSEG7E1024V 0xd8007007
- +#define MASK_VLSSEG7E1024V 0xfc00707f
- +#define MATCH_VSSSEG7E1024V 0xd8007027
- +#define MASK_VSSSEG7E1024V 0xfc00707f
- +#define MATCH_VLSSEG8E1024V 0xf8007007
- +#define MASK_VLSSEG8E1024V 0xfc00707f
- +#define MATCH_VSSSEG8E1024V 0xf8007027
- +#define MASK_VSSSEG8E1024V 0xfc00707f
- +
- +#define MATCH_VLXSEG2EI8V 0x2c000007
- +#define MASK_VLXSEG2EI8V 0xfc00707f
- +#define MATCH_VSXSEG2EI8V 0x2c000027
- +#define MASK_VSXSEG2EI8V 0xfc00707f
- +#define MATCH_VLXSEG3EI8V 0x4c000007
- +#define MASK_VLXSEG3EI8V 0xfc00707f
- +#define MATCH_VSXSEG3EI8V 0x4c000027
- +#define MASK_VSXSEG3EI8V 0xfc00707f
- +#define MATCH_VLXSEG4EI8V 0x6c000007
- +#define MASK_VLXSEG4EI8V 0xfc00707f
- +#define MATCH_VSXSEG4EI8V 0x6c000027
- +#define MASK_VSXSEG4EI8V 0xfc00707f
- +#define MATCH_VLXSEG5EI8V 0x8c000007
- +#define MASK_VLXSEG5EI8V 0xfc00707f
- +#define MATCH_VSXSEG5EI8V 0x8c000027
- +#define MASK_VSXSEG5EI8V 0xfc00707f
- +#define MATCH_VLXSEG6EI8V 0xac000007
- +#define MASK_VLXSEG6EI8V 0xfc00707f
- +#define MATCH_VSXSEG6EI8V 0xac000027
- +#define MASK_VSXSEG6EI8V 0xfc00707f
- +#define MATCH_VLXSEG7EI8V 0xcc000007
- +#define MASK_VLXSEG7EI8V 0xfc00707f
- +#define MATCH_VSXSEG7EI8V 0xcc000027
- +#define MASK_VSXSEG7EI8V 0xfc00707f
- +#define MATCH_VLXSEG8EI8V 0xec000007
- +#define MASK_VLXSEG8EI8V 0xfc00707f
- +#define MATCH_VSXSEG8EI8V 0xec000027
- +#define MASK_VSXSEG8EI8V 0xfc00707f
- +
- +#define MATCH_VLXSEG2EI16V 0x2c005007
- +#define MASK_VLXSEG2EI16V 0xfc00707f
- +#define MATCH_VSXSEG2EI16V 0x2c005027
- +#define MASK_VSXSEG2EI16V 0xfc00707f
- +#define MATCH_VLXSEG3EI16V 0x4c005007
- +#define MASK_VLXSEG3EI16V 0xfc00707f
- +#define MATCH_VSXSEG3EI16V 0x4c005027
- +#define MASK_VSXSEG3EI16V 0xfc00707f
- +#define MATCH_VLXSEG4EI16V 0x6c005007
- +#define MASK_VLXSEG4EI16V 0xfc00707f
- +#define MATCH_VSXSEG4EI16V 0x6c005027
- +#define MASK_VSXSEG4EI16V 0xfc00707f
- +#define MATCH_VLXSEG5EI16V 0x8c005007
- +#define MASK_VLXSEG5EI16V 0xfc00707f
- +#define MATCH_VSXSEG5EI16V 0x8c005027
- +#define MASK_VSXSEG5EI16V 0xfc00707f
- +#define MATCH_VLXSEG6EI16V 0xac005007
- +#define MASK_VLXSEG6EI16V 0xfc00707f
- +#define MATCH_VSXSEG6EI16V 0xac005027
- +#define MASK_VSXSEG6EI16V 0xfc00707f
- +#define MATCH_VLXSEG7EI16V 0xcc005007
- +#define MASK_VLXSEG7EI16V 0xfc00707f
- +#define MATCH_VSXSEG7EI16V 0xcc005027
- +#define MASK_VSXSEG7EI16V 0xfc00707f
- +#define MATCH_VLXSEG8EI16V 0xec005007
- +#define MASK_VLXSEG8EI16V 0xfc00707f
- +#define MATCH_VSXSEG8EI16V 0xec005027
- +#define MASK_VSXSEG8EI16V 0xfc00707f
- +
- +#define MATCH_VLXSEG2EI32V 0x2c006007
- +#define MASK_VLXSEG2EI32V 0xfc00707f
- +#define MATCH_VSXSEG2EI32V 0x2c006027
- +#define MASK_VSXSEG2EI32V 0xfc00707f
- +#define MATCH_VLXSEG3EI32V 0x4c006007
- +#define MASK_VLXSEG3EI32V 0xfc00707f
- +#define MATCH_VSXSEG3EI32V 0x4c006027
- +#define MASK_VSXSEG3EI32V 0xfc00707f
- +#define MATCH_VLXSEG4EI32V 0x6c006007
- +#define MASK_VLXSEG4EI32V 0xfc00707f
- +#define MATCH_VSXSEG4EI32V 0x6c006027
- +#define MASK_VSXSEG4EI32V 0xfc00707f
- +#define MATCH_VLXSEG5EI32V 0x8c006007
- +#define MASK_VLXSEG5EI32V 0xfc00707f
- +#define MATCH_VSXSEG5EI32V 0x8c006027
- +#define MASK_VSXSEG5EI32V 0xfc00707f
- +#define MATCH_VLXSEG6EI32V 0xac006007
- +#define MASK_VLXSEG6EI32V 0xfc00707f
- +#define MATCH_VSXSEG6EI32V 0xac006027
- +#define MASK_VSXSEG6EI32V 0xfc00707f
- +#define MATCH_VLXSEG7EI32V 0xcc006007
- +#define MASK_VLXSEG7EI32V 0xfc00707f
- +#define MATCH_VSXSEG7EI32V 0xcc006027
- +#define MASK_VSXSEG7EI32V 0xfc00707f
- +#define MATCH_VLXSEG8EI32V 0xec006007
- +#define MASK_VLXSEG8EI32V 0xfc00707f
- +#define MATCH_VSXSEG8EI32V 0xec006027
- +#define MASK_VSXSEG8EI32V 0xfc00707f
- +
- +#define MATCH_VLXSEG2EI64V 0x2c007007
- +#define MASK_VLXSEG2EI64V 0xfc00707f
- +#define MATCH_VSXSEG2EI64V 0x2c007027
- +#define MASK_VSXSEG2EI64V 0xfc00707f
- +#define MATCH_VLXSEG3EI64V 0x4c007007
- +#define MASK_VLXSEG3EI64V 0xfc00707f
- +#define MATCH_VSXSEG3EI64V 0x4c007027
- +#define MASK_VSXSEG3EI64V 0xfc00707f
- +#define MATCH_VLXSEG4EI64V 0x6c007007
- +#define MASK_VLXSEG4EI64V 0xfc00707f
- +#define MATCH_VSXSEG4EI64V 0x6c007027
- +#define MASK_VSXSEG4EI64V 0xfc00707f
- +#define MATCH_VLXSEG5EI64V 0x8c007007
- +#define MASK_VLXSEG5EI64V 0xfc00707f
- +#define MATCH_VSXSEG5EI64V 0x8c007027
- +#define MASK_VSXSEG5EI64V 0xfc00707f
- +#define MATCH_VLXSEG6EI64V 0xac007007
- +#define MASK_VLXSEG6EI64V 0xfc00707f
- +#define MATCH_VSXSEG6EI64V 0xac007027
- +#define MASK_VSXSEG6EI64V 0xfc00707f
- +#define MATCH_VLXSEG7EI64V 0xcc007007
- +#define MASK_VLXSEG7EI64V 0xfc00707f
- +#define MATCH_VSXSEG7EI64V 0xcc007027
- +#define MASK_VSXSEG7EI64V 0xfc00707f
- +#define MATCH_VLXSEG8EI64V 0xec007007
- +#define MASK_VLXSEG8EI64V 0xfc00707f
- +#define MATCH_VSXSEG8EI64V 0xec007027
- +#define MASK_VSXSEG8EI64V 0xfc00707f
- +
- +#define MATCH_VLXSEG2EI128V 0x3c000007
- +#define MASK_VLXSEG2EI128V 0xfc00707f
- +#define MATCH_VSXSEG2EI128V 0x3c000027
- +#define MASK_VSXSEG2EI128V 0xfc00707f
- +#define MATCH_VLXSEG3EI128V 0x5c000007
- +#define MASK_VLXSEG3EI128V 0xfc00707f
- +#define MATCH_VSXSEG3EI128V 0x5c000027
- +#define MASK_VSXSEG3EI128V 0xfc00707f
- +#define MATCH_VLXSEG4EI128V 0x7c000007
- +#define MASK_VLXSEG4EI128V 0xfc00707f
- +#define MATCH_VSXSEG4EI128V 0x7c000027
- +#define MASK_VSXSEG4EI128V 0xfc00707f
- +#define MATCH_VLXSEG5EI128V 0x9c000007
- +#define MASK_VLXSEG5EI128V 0xfc00707f
- +#define MATCH_VSXSEG5EI128V 0x9c000027
- +#define MASK_VSXSEG5EI128V 0xfc00707f
- +#define MATCH_VLXSEG6EI128V 0xbc000007
- +#define MASK_VLXSEG6EI128V 0xfc00707f
- +#define MATCH_VSXSEG6EI128V 0xbc000027
- +#define MASK_VSXSEG6EI128V 0xfc00707f
- +#define MATCH_VLXSEG7EI128V 0xdc000007
- +#define MASK_VLXSEG7EI128V 0xfc00707f
- +#define MATCH_VSXSEG7EI128V 0xdc000027
- +#define MASK_VSXSEG7EI128V 0xfc00707f
- +#define MATCH_VLXSEG8EI128V 0xfc000007
- +#define MASK_VLXSEG8EI128V 0xfc00707f
- +#define MATCH_VSXSEG8EI128V 0xfc000027
- +#define MASK_VSXSEG8EI128V 0xfc00707f
- +
- +#define MATCH_VLXSEG2EI256V 0x3c005007
- +#define MASK_VLXSEG2EI256V 0xfc00707f
- +#define MATCH_VSXSEG2EI256V 0x3c005027
- +#define MASK_VSXSEG2EI256V 0xfc00707f
- +#define MATCH_VLXSEG3EI256V 0x5c005007
- +#define MASK_VLXSEG3EI256V 0xfc00707f
- +#define MATCH_VSXSEG3EI256V 0x5c005027
- +#define MASK_VSXSEG3EI256V 0xfc00707f
- +#define MATCH_VLXSEG4EI256V 0x7c005007
- +#define MASK_VLXSEG4EI256V 0xfc00707f
- +#define MATCH_VSXSEG4EI256V 0x7c005027
- +#define MASK_VSXSEG4EI256V 0xfc00707f
- +#define MATCH_VLXSEG5EI256V 0x9c005007
- +#define MASK_VLXSEG5EI256V 0xfc00707f
- +#define MATCH_VSXSEG5EI256V 0x9c005027
- +#define MASK_VSXSEG5EI256V 0xfc00707f
- +#define MATCH_VLXSEG6EI256V 0xbc005007
- +#define MASK_VLXSEG6EI256V 0xfc00707f
- +#define MATCH_VSXSEG6EI256V 0xbc005027
- +#define MASK_VSXSEG6EI256V 0xfc00707f
- +#define MATCH_VLXSEG7EI256V 0xdc005007
- +#define MASK_VLXSEG7EI256V 0xfc00707f
- +#define MATCH_VSXSEG7EI256V 0xdc005027
- +#define MASK_VSXSEG7EI256V 0xfc00707f
- +#define MATCH_VLXSEG8EI256V 0xfc005007
- +#define MASK_VLXSEG8EI256V 0xfc00707f
- +#define MATCH_VSXSEG8EI256V 0xfc005027
- +#define MASK_VSXSEG8EI256V 0xfc00707f
- +
- +#define MATCH_VLXSEG2EI512V 0x3c006007
- +#define MASK_VLXSEG2EI512V 0xfc00707f
- +#define MATCH_VSXSEG2EI512V 0x3c006027
- +#define MASK_VSXSEG2EI512V 0xfc00707f
- +#define MATCH_VLXSEG3EI512V 0x5c006007
- +#define MASK_VLXSEG3EI512V 0xfc00707f
- +#define MATCH_VSXSEG3EI512V 0x5c006027
- +#define MASK_VSXSEG3EI512V 0xfc00707f
- +#define MATCH_VLXSEG4EI512V 0x7c006007
- +#define MASK_VLXSEG4EI512V 0xfc00707f
- +#define MATCH_VSXSEG4EI512V 0x7c006027
- +#define MASK_VSXSEG4EI512V 0xfc00707f
- +#define MATCH_VLXSEG5EI512V 0x9c006007
- +#define MASK_VLXSEG5EI512V 0xfc00707f
- +#define MATCH_VSXSEG5EI512V 0x9c006027
- +#define MASK_VSXSEG5EI512V 0xfc00707f
- +#define MATCH_VLXSEG6EI512V 0xbc006007
- +#define MASK_VLXSEG6EI512V 0xfc00707f
- +#define MATCH_VSXSEG6EI512V 0xbc006027
- +#define MASK_VSXSEG6EI512V 0xfc00707f
- +#define MATCH_VLXSEG7EI512V 0xdc006007
- +#define MASK_VLXSEG7EI512V 0xfc00707f
- +#define MATCH_VSXSEG7EI512V 0xdc006027
- +#define MASK_VSXSEG7EI512V 0xfc00707f
- +#define MATCH_VLXSEG8EI512V 0xfc006007
- +#define MASK_VLXSEG8EI512V 0xfc00707f
- +#define MATCH_VSXSEG8EI512V 0xfc006027
- +#define MASK_VSXSEG8EI512V 0xfc00707f
- +
- +#define MATCH_VLXSEG2EI1024V 0x3c007007
- +#define MASK_VLXSEG2EI1024V 0xfc00707f
- +#define MATCH_VSXSEG2EI1024V 0x3c007027
- +#define MASK_VSXSEG2EI1024V 0xfc00707f
- +#define MATCH_VLXSEG3EI1024V 0x5c007007
- +#define MASK_VLXSEG3EI1024V 0xfc00707f
- +#define MATCH_VSXSEG3EI1024V 0x5c007027
- +#define MASK_VSXSEG3EI1024V 0xfc00707f
- +#define MATCH_VLXSEG4EI1024V 0x7c007007
- +#define MASK_VLXSEG4EI1024V 0xfc00707f
- +#define MATCH_VSXSEG4EI1024V 0x7c007027
- +#define MASK_VSXSEG4EI1024V 0xfc00707f
- +#define MATCH_VLXSEG5EI1024V 0x9c007007
- +#define MASK_VLXSEG5EI1024V 0xfc00707f
- +#define MATCH_VSXSEG5EI1024V 0x9c007027
- +#define MASK_VSXSEG5EI1024V 0xfc00707f
- +#define MATCH_VLXSEG6EI1024V 0xbc007007
- +#define MASK_VLXSEG6EI1024V 0xfc00707f
- +#define MATCH_VSXSEG6EI1024V 0xbc007027
- +#define MASK_VSXSEG6EI1024V 0xfc00707f
- +#define MATCH_VLXSEG7EI1024V 0xdc007007
- +#define MASK_VLXSEG7EI1024V 0xfc00707f
- +#define MATCH_VSXSEG7EI1024V 0xdc007027
- +#define MASK_VSXSEG7EI1024V 0xfc00707f
- +#define MATCH_VLXSEG8EI1024V 0xfc007007
- +#define MASK_VLXSEG8EI1024V 0xfc00707f
- +#define MATCH_VSXSEG8EI1024V 0xfc007027
- +#define MASK_VSXSEG8EI1024V 0xfc00707f
- +
- +#define MATCH_VLSEG2E8FFV 0x21000007
- +#define MASK_VLSEG2E8FFV 0xfdf0707f
- +#define MATCH_VLSEG3E8FFV 0x41000007
- +#define MASK_VLSEG3E8FFV 0xfdf0707f
- +#define MATCH_VLSEG4E8FFV 0x61000007
- +#define MASK_VLSEG4E8FFV 0xfdf0707f
- +#define MATCH_VLSEG5E8FFV 0x81000007
- +#define MASK_VLSEG5E8FFV 0xfdf0707f
- +#define MATCH_VLSEG6E8FFV 0xa1000007
- +#define MASK_VLSEG6E8FFV 0xfdf0707f
- +#define MATCH_VLSEG7E8FFV 0xc1000007
- +#define MASK_VLSEG7E8FFV 0xfdf0707f
- +#define MATCH_VLSEG8E8FFV 0xe1000007
- +#define MASK_VLSEG8E8FFV 0xfdf0707f
- +
- +#define MATCH_VLSEG2E16FFV 0x21005007
- +#define MASK_VLSEG2E16FFV 0xfdf0707f
- +#define MATCH_VLSEG3E16FFV 0x41005007
- +#define MASK_VLSEG3E16FFV 0xfdf0707f
- +#define MATCH_VLSEG4E16FFV 0x61005007
- +#define MASK_VLSEG4E16FFV 0xfdf0707f
- +#define MATCH_VLSEG5E16FFV 0x81005007
- +#define MASK_VLSEG5E16FFV 0xfdf0707f
- +#define MATCH_VLSEG6E16FFV 0xa1005007
- +#define MASK_VLSEG6E16FFV 0xfdf0707f
- +#define MATCH_VLSEG7E16FFV 0xc1005007
- +#define MASK_VLSEG7E16FFV 0xfdf0707f
- +#define MATCH_VLSEG8E16FFV 0xe1005007
- +#define MASK_VLSEG8E16FFV 0xfdf0707f
- +
- +#define MATCH_VLSEG2E32FFV 0x21006007
- +#define MASK_VLSEG2E32FFV 0xfdf0707f
- +#define MATCH_VLSEG3E32FFV 0x41006007
- +#define MASK_VLSEG3E32FFV 0xfdf0707f
- +#define MATCH_VLSEG4E32FFV 0x61006007
- +#define MASK_VLSEG4E32FFV 0xfdf0707f
- +#define MATCH_VLSEG5E32FFV 0x81006007
- +#define MASK_VLSEG5E32FFV 0xfdf0707f
- +#define MATCH_VLSEG6E32FFV 0xa1006007
- +#define MASK_VLSEG6E32FFV 0xfdf0707f
- +#define MATCH_VLSEG7E32FFV 0xc1006007
- +#define MASK_VLSEG7E32FFV 0xfdf0707f
- +#define MATCH_VLSEG8E32FFV 0xe1006007
- +#define MASK_VLSEG8E32FFV 0xfdf0707f
- +
- +#define MATCH_VLSEG2E64FFV 0x21007007
- +#define MASK_VLSEG2E64FFV 0xfdf0707f
- +#define MATCH_VLSEG3E64FFV 0x41007007
- +#define MASK_VLSEG3E64FFV 0xfdf0707f
- +#define MATCH_VLSEG4E64FFV 0x61007007
- +#define MASK_VLSEG4E64FFV 0xfdf0707f
- +#define MATCH_VLSEG5E64FFV 0x81007007
- +#define MASK_VLSEG5E64FFV 0xfdf0707f
- +#define MATCH_VLSEG6E64FFV 0xa1007007
- +#define MASK_VLSEG6E64FFV 0xfdf0707f
- +#define MATCH_VLSEG7E64FFV 0xc1007007
- +#define MASK_VLSEG7E64FFV 0xfdf0707f
- +#define MATCH_VLSEG8E64FFV 0xe1007007
- +#define MASK_VLSEG8E64FFV 0xfdf0707f
- +
- +#define MATCH_VLSEG2E128FFV 0x31000007
- +#define MASK_VLSEG2E128FFV 0xfdf0707f
- +#define MATCH_VLSEG3E128FFV 0x51000007
- +#define MASK_VLSEG3E128FFV 0xfdf0707f
- +#define MATCH_VLSEG4E128FFV 0x71000007
- +#define MASK_VLSEG4E128FFV 0xfdf0707f
- +#define MATCH_VLSEG5E128FFV 0x91000007
- +#define MASK_VLSEG5E128FFV 0xfdf0707f
- +#define MATCH_VLSEG6E128FFV 0xb1000007
- +#define MASK_VLSEG6E128FFV 0xfdf0707f
- +#define MATCH_VLSEG7E128FFV 0xd1000007
- +#define MASK_VLSEG7E128FFV 0xfdf0707f
- +#define MATCH_VLSEG8E128FFV 0xf1000007
- +#define MASK_VLSEG8E128FFV 0xfdf0707f
- +
- +#define MATCH_VLSEG2E256FFV 0x31005007
- +#define MASK_VLSEG2E256FFV 0xfdf0707f
- +#define MATCH_VLSEG3E256FFV 0x51005007
- +#define MASK_VLSEG3E256FFV 0xfdf0707f
- +#define MATCH_VLSEG4E256FFV 0x71005007
- +#define MASK_VLSEG4E256FFV 0xfdf0707f
- +#define MATCH_VLSEG5E256FFV 0x91005007
- +#define MASK_VLSEG5E256FFV 0xfdf0707f
- +#define MATCH_VLSEG6E256FFV 0xb1005007
- +#define MASK_VLSEG6E256FFV 0xfdf0707f
- +#define MATCH_VLSEG7E256FFV 0xd1005007
- +#define MASK_VLSEG7E256FFV 0xfdf0707f
- +#define MATCH_VLSEG8E256FFV 0xf1005007
- +#define MASK_VLSEG8E256FFV 0xfdf0707f
- +
- +#define MATCH_VLSEG2E512FFV 0x31006007
- +#define MASK_VLSEG2E512FFV 0xfdf0707f
- +#define MATCH_VLSEG3E512FFV 0x51006007
- +#define MASK_VLSEG3E512FFV 0xfdf0707f
- +#define MATCH_VLSEG4E512FFV 0x71006007
- +#define MASK_VLSEG4E512FFV 0xfdf0707f
- +#define MATCH_VLSEG5E512FFV 0x91006007
- +#define MASK_VLSEG5E512FFV 0xfdf0707f
- +#define MATCH_VLSEG6E512FFV 0xb1006007
- +#define MASK_VLSEG6E512FFV 0xfdf0707f
- +#define MATCH_VLSEG7E512FFV 0xd1006007
- +#define MASK_VLSEG7E512FFV 0xfdf0707f
- +#define MATCH_VLSEG8E512FFV 0xf1006007
- +#define MASK_VLSEG8E512FFV 0xfdf0707f
- +
- +#define MATCH_VLSEG2E1024FFV 0x31007007
- +#define MASK_VLSEG2E1024FFV 0xfdf0707f
- +#define MATCH_VLSEG3E1024FFV 0x51007007
- +#define MASK_VLSEG3E1024FFV 0xfdf0707f
- +#define MATCH_VLSEG4E1024FFV 0x71007007
- +#define MASK_VLSEG4E1024FFV 0xfdf0707f
- +#define MATCH_VLSEG5E1024FFV 0x91007007
- +#define MASK_VLSEG5E1024FFV 0xfdf0707f
- +#define MATCH_VLSEG6E1024FFV 0xb1007007
- +#define MASK_VLSEG6E1024FFV 0xfdf0707f
- +#define MATCH_VLSEG7E1024FFV 0xd1007007
- +#define MASK_VLSEG7E1024FFV 0xfdf0707f
- +#define MATCH_VLSEG8E1024FFV 0xf1007007
- +#define MASK_VLSEG8E1024FFV 0xfdf0707f
- +
- +#define MATCH_VL1RV 0x02800007
- +#define MASK_VL1RV 0xfff0707f
- +#define MATCH_VS1RV 0x02800027
- +#define MASK_VS1RV 0xfff0707f
- +
- +/* Temporary AMO encoding info
- +
- +width
- +010 AMO*.W
- +011 AMO*.D
- +100 AMO*.Q
- +000 VAMO*EI8.V
- +101 VAMO*EI16.V
- +110 VAMO*EI32.V
- +111 VAMO*EI64.V
- +
- +amoop
- +00001 vamoswap
- +00000 vamoadd
- +00100 vamoxor
- +01100 vamoand
- +01000 vamoor
- +10000 vamomin
- +10100 vamomax
- +11000 vamominu
- +11100 vamomaxu
- +
- + 31-27 26 25 24-20 19-15 14-12 11-7 6-0
- + amoop wd vm vs2 rs1 width vs3/vd opcode
- + 00001 x 1 xxxxx xxxxx 110 xxxxx 0101111
- + 0000 1x1x xxxx xxxx x110 xxxx x010 1111
- + 1111 1010 0000 0000 0111 0000 0111 1111 */
- +
- +#define MATCH_VAMOADDEI8V 0x0000002f
- +#define MASK_VAMOADDEI8V 0xf800707f
- +#define MATCH_VAMOSWAPEI8V 0x0800002f
- +#define MASK_VAMOSWAPEI8V 0xf800707f
- +#define MATCH_VAMOXOREI8V 0x2000002f
- +#define MASK_VAMOXOREI8V 0xf800707f
- +#define MATCH_VAMOANDEI8V 0x6000002f
- +#define MASK_VAMOANDEI8V 0xf800707f
- +#define MATCH_VAMOOREI8V 0x4000002f
- +#define MASK_VAMOOREI8V 0xf800707f
- +#define MATCH_VAMOMINEI8V 0x8000002f
- +#define MASK_VAMOMINEI8V 0xf800707f
- +#define MATCH_VAMOMAXEI8V 0xa000002f
- +#define MASK_VAMOMAXEI8V 0xf800707f
- +#define MATCH_VAMOMINUEI8V 0xc000002f
- +#define MASK_VAMOMINUEI8V 0xf800707f
- +#define MATCH_VAMOMAXUEI8V 0xe000002f
- +#define MASK_VAMOMAXUEI8V 0xf800707f
- +
- +#define MATCH_VAMOADDEI16V 0x0000502f
- +#define MASK_VAMOADDEI16V 0xf800707f
- +#define MATCH_VAMOSWAPEI16V 0x0800502f
- +#define MASK_VAMOSWAPEI16V 0xf800707f
- +#define MATCH_VAMOXOREI16V 0x2000502f
- +#define MASK_VAMOXOREI16V 0xf800707f
- +#define MATCH_VAMOANDEI16V 0x6000502f
- +#define MASK_VAMOANDEI16V 0xf800707f
- +#define MATCH_VAMOOREI16V 0x4000502f
- +#define MASK_VAMOOREI16V 0xf800707f
- +#define MATCH_VAMOMINEI16V 0x8000502f
- +#define MASK_VAMOMINEI16V 0xf800707f
- +#define MATCH_VAMOMAXEI16V 0xa000502f
- +#define MASK_VAMOMAXEI16V 0xf800707f
- +#define MATCH_VAMOMINUEI16V 0xc000502f
- +#define MASK_VAMOMINUEI16V 0xf800707f
- +#define MATCH_VAMOMAXUEI16V 0xe000502f
- +#define MASK_VAMOMAXUEI16V 0xf800707f
- +
- +#define MATCH_VAMOADDEI32V 0x0000602f
- +#define MASK_VAMOADDEI32V 0xf800707f
- +#define MATCH_VAMOSWAPEI32V 0x0800602f
- +#define MASK_VAMOSWAPEI32V 0xf800707f
- +#define MATCH_VAMOXOREI32V 0x2000602f
- +#define MASK_VAMOXOREI32V 0xf800707f
- +#define MATCH_VAMOANDEI32V 0x6000602f
- +#define MASK_VAMOANDEI32V 0xf800707f
- +#define MATCH_VAMOOREI32V 0x4000602f
- +#define MASK_VAMOOREI32V 0xf800707f
- +#define MATCH_VAMOMINEI32V 0x8000602f
- +#define MASK_VAMOMINEI32V 0xf800707f
- +#define MATCH_VAMOMAXEI32V 0xa000602f
- +#define MASK_VAMOMAXEI32V 0xf800707f
- +#define MATCH_VAMOMINUEI32V 0xc000602f
- +#define MASK_VAMOMINUEI32V 0xf800707f
- +#define MATCH_VAMOMAXUEI32V 0xe000602f
- +#define MASK_VAMOMAXUEI32V 0xf800707f
- +
- +#define MATCH_VAMOADDEI64V 0x0000702f
- +#define MASK_VAMOADDEI64V 0xf800707f
- +#define MATCH_VAMOSWAPEI64V 0x0800702f
- +#define MASK_VAMOSWAPEI64V 0xf800707f
- +#define MATCH_VAMOXOREI64V 0x2000702f
- +#define MASK_VAMOXOREI64V 0xf800707f
- +#define MATCH_VAMOANDEI64V 0x6000702f
- +#define MASK_VAMOANDEI64V 0xf800707f
- +#define MATCH_VAMOOREI64V 0x4000702f
- +#define MASK_VAMOOREI64V 0xf800707f
- +#define MATCH_VAMOMINEI64V 0x8000702f
- +#define MASK_VAMOMINEI64V 0xf800707f
- +#define MATCH_VAMOMAXEI64V 0xa000702f
- +#define MASK_VAMOMAXEI64V 0xf800707f
- +#define MATCH_VAMOMINUEI64V 0xc000702f
- +#define MASK_VAMOMINUEI64V 0xf800707f
- +#define MATCH_VAMOMAXUEI64V 0xe000702f
- +#define MASK_VAMOMAXUEI64V 0xf800707f
- +
- +/* Temporary ALU encoding info
- +
- +funct3
- +000 OPIVV vv
- +001 OPFVV vv
- +010 OPMVV vv
- +011 OPIVI vi simm[4:0]
- +100 OPIVX vx GPR x-reg rs1
- +101 OPFVF vf FP f-reg rs1
- +110 OPMVX vx GPR x-reg rs1
- +111 OPCFG si GPR x-reg rs1 & rs2/imm
- +
- +INT OPI
- +funct6
- +000000 vadd
- +000001
- +000010 vsub
- +000011 vrsub
- +000100 vminu
- +000101 vmin
- +000110 vmaxu
- +000111 vmax
- +001000
- +001001 vand
- +001010 vor
- +001011 vxor
- +001100 vrgather
- +001101
- +001110 vslideup
- +001111 vslidedown
- +010000 vadc
- +010001 vmadc
- +010010 vsbc
- +010011 vmsbc
- +010100
- +010101
- +010110
- +010111 vmerge/vmv
- +011000 vmseq
- +011001 vmsne
- +011010 vmsltu
- +011011 vmslt
- +011100 vmsleu
- +011101 vmsle
- +011110 vmsgtu
- +011111 vmsgt
- +100000 vsaddu
- +100001 vsadd
- +100010 vssubu
- +100011 vssub
- +100100
- +100101 vsll
- +100110
- +100111 vmv<nf>r (nf = 1, 2, 4, 8)
- +101000 vsrl
- +101001 vsra
- +101010 vssrl
- +101011 vssra
- +101100 vnsrl
- +101101 vnsra
- +101110 vnclipu
- +101111 vnclip
- +110000 vwredsumu
- +110001 vwredsum
- +110010
- +110011
- +110100
- +110101
- +110110
- +110111
- +111000 vdotu **
- +111001 vdot **
- +111010
- +111011
- +111100 vqmaccu
- +111101 vqmacc
- +111110 vqmaccus
- +111111 vqmaccsu
- +
- +INT OPM
- +funct6
- +000000 vredsum
- +000001 vredand
- +000010 vredor
- +000011 vredxor
- +000100 vredminu
- +000101 vredmin
- +000110 vredmaxu
- +000111 vredmax
- +001000 vaaddu
- +001001 vaadd
- +001010 vasubu
- +001011 vasub
- +001100
- +001101
- +001110 vslide1up
- +001111 vslide1down
- +010000 VRXUNARY0/VWXUNARY0
- +010001
- +010010 VXUNARY0
- +010011
- +010100 VMUNARY0
- +010101
- +010110
- +010111 vcompress
- +011000 vmandnot
- +011001 vmand
- +011010 vmor
- +011011 vmxor
- +011100 vmornot
- +011101 vmnand
- +011110 vmnor
- +011111 vmxnor
- +100000 vdivu
- +100001 vdiv
- +100010 vremu
- +100011 vrem
- +100100 vmulhu
- +100101 vmul
- +100110 vmulhsu
- +100111 vmulh
- +101000
- +101001 vmadd
- +101010
- +101011 vnmsub
- +101100
- +101101 vmacc
- +101110
- +101111 vnmsac
- +110000 vwaddu
- +110001 vwadd
- +110010 vwsubu
- +110011 vwsub
- +110100 vwaddu.w
- +110101 vwadd.w
- +110110 vwsubu.w
- +110111 vwsub.w
- +111000 vwmulu
- +111001
- +111010 vwmulsu
- +111011 vwmul
- +111100 vwmaccu
- +111101 vwmacc
- +111110 vwmaccus
- +111111 vwmaccsu
- +
- +VRXUNARY0
- +vs2, funct3=X
- +00000 vmv.s.x
- +
- +VWXUNARY0
- +vs1, funct3=V
- +00000 vmv.x.s
- +10000 vpopc
- +10001 vfirst
- +
- +VXUNARY0
- +vs1, funct3=V
- +00010 vzext.vf8
- +00011 vsext.vf8
- +00100 vzext.vf4
- +00101 vsext.vf4
- +00110 vzext.vf2
- +00111 vsext.vf2
- +
- +VMUNARY0
- +rs1
- +00001 vmsbf
- +00010 vmsof
- +00011 vmsif
- +10000 viota
- +10001 vid
- +
- +VFLOAT
- +funct6
- +000000 vfadd
- +000001 vfredsum
- +000010 vfsub
- +000011 vfredosum
- +000100 vfmin
- +000101 vfredmin
- +000110 vfmax
- +000111 vfredmax
- +001000 vfsgnj
- +001001 vfsgnn
- +001010 vfsgnx
- +001011
- +001100
- +001101
- +001110 vfslide1up
- +001111 vfslide1down
- +010000 VRFUNARY0/VWFUNARY0
- +010001
- +010010 VFUNARY0
- +010011 VFUNARY1
- +010100
- +010101
- +010110
- +010111 vfmerge/vfmv
- +011000 vmfeq
- +011001 vmfle
- +011010
- +011011 vmflt
- +011100 vmfne
- +011101 vmfgt
- +011110
- +011111 vmfge
- +100000 vfdiv
- +100001 vfrdiv
- +100010
- +100011
- +100100 vfmul
- +100101
- +100110
- +100111 vfrsub
- +101000 vfmadd
- +101001 vfnmadd
- +101010 vfmsub
- +101011 vfnmsub
- +101100 vfmacc
- +101101 vfnmacc
- +101110 vfmsac
- +101111 vfnmsac
- +110000 vfwadd
- +110001 vfwredsum
- +110010 vfwsub
- +110011 vfwredosum
- +110100 vfwadd.w
- +110101
- +110110 vfwsub.w
- +110111
- +111000 vfwmul
- +111001 vfdot
- +111010
- +111011
- +111100 vfwmacc
- +111101 vfwnmacc
- +111110 vfwmsac
- +111111 vfwnmsac
- +
- +VRFUNARY0
- +vs2, funct3=F
- +00000 vfmv.s.f
- +
- +VWFUNARY0
- +vs1, funct3=V
- +00000 vfmv.f.s
- +
- +VFUNARY0
- +vs1
- +00000 vfcvt.xu.f.v
- +00001 vfcvt.x.f.v
- +00010 vfcvt.f.xu.v
- +00011 vfcvt.f.x.v
- +00110 vfcvt.rtz.xu.f.v
- +00111 vfcvt.rtz.x.f.v
- +
- +01000 vfwcvt.xu.f.v
- +01001 vfwcvt.x.f.v
- +01010 vfwcvt.f.xu.v
- +01011 vfwcvt.f.x.v
- +01100 vfwcvt.f.f.v
- +01110 vfwcvt.rtz.xu.f.v
- +01111 vfwcvt.rtz.x.f.v
- +
- +10000 vfncvt.xu.f.w
- +10001 vfncvt.x.f.w
- +10010 vfncvt.f.xu.w
- +10011 vfncvt.f.x.w
- +10100 vfncvt.f.f.w
- +10101 vfncvt.rod.f.f.w
- +10110 vfncvt.rtz.xu.f.v
- +10111 vfncvt.rtz.x.f.v
- +
- +VFUNARY1
- +vs1
- +00000 vfsqrt.v
- +10000 vfclass.v
- +
- +31-26 25 24-20 19-15 14-12 11-7 6-0
- +funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
- +010000 x xxxxx 00000 001 xxxxx 1010111
- +0100 00xx xxxx 0000 0001 xxxx x101 0111
- +*/
- +
- +#define MATCH_VADDVV 0x00000057
- +#define MASK_VADDVV 0xfc00707f
- +#define MATCH_VADDVX 0x00004057
- +#define MASK_VADDVX 0xfc00707f
- +#define MATCH_VADDVI 0x00003057
- +#define MASK_VADDVI 0xfc00707f
- +#define MATCH_VSUBVV 0x08000057
- +#define MASK_VSUBVV 0xfc00707f
- +#define MATCH_VSUBVX 0x08004057
- +#define MASK_VSUBVX 0xfc00707f
- +#define MATCH_VRSUBVX 0x0c004057
- +#define MASK_VRSUBVX 0xfc00707f
- +#define MATCH_VRSUBVI 0x0c003057
- +#define MASK_VRSUBVI 0xfc00707f
- +
- +#define MATCH_VWCVTXXV 0xc4006057
- +#define MASK_VWCVTXXV 0xfc0ff07f
- +#define MATCH_VWCVTUXXV 0xc0006057
- +#define MASK_VWCVTUXXV 0xfc0ff07f
- +
- +#define MATCH_VWADDVV 0xc4002057
- +#define MASK_VWADDVV 0xfc00707f
- +#define MATCH_VWADDVX 0xc4006057
- +#define MASK_VWADDVX 0xfc00707f
- +#define MATCH_VWSUBVV 0xcc002057
- +#define MASK_VWSUBVV 0xfc00707f
- +#define MATCH_VWSUBVX 0xcc006057
- +#define MASK_VWSUBVX 0xfc00707f
- +#define MATCH_VWADDWV 0xd4002057
- +#define MASK_VWADDWV 0xfc00707f
- +#define MATCH_VWADDWX 0xd4006057
- +#define MASK_VWADDWX 0xfc00707f
- +#define MATCH_VWSUBWV 0xdc002057
- +#define MASK_VWSUBWV 0xfc00707f
- +#define MATCH_VWSUBWX 0xdc006057
- +#define MASK_VWSUBWX 0xfc00707f
- +#define MATCH_VWADDUVV 0xc0002057
- +#define MASK_VWADDUVV 0xfc00707f
- +#define MATCH_VWADDUVX 0xc0006057
- +#define MASK_VWADDUVX 0xfc00707f
- +#define MATCH_VWSUBUVV 0xc8002057
- +#define MASK_VWSUBUVV 0xfc00707f
- +#define MATCH_VWSUBUVX 0xc8006057
- +#define MASK_VWSUBUVX 0xfc00707f
- +#define MATCH_VWADDUWV 0xd0002057
- +#define MASK_VWADDUWV 0xfc00707f
- +#define MATCH_VWADDUWX 0xd0006057
- +#define MASK_VWADDUWX 0xfc00707f
- +#define MATCH_VWSUBUWV 0xd8002057
- +#define MASK_VWSUBUWV 0xfc00707f
- +#define MATCH_VWSUBUWX 0xd8006057
- +#define MASK_VWSUBUWX 0xfc00707f
- +
- +#define MATCH_VZEXT_VF8 0x48012057
- +#define MASK_VZEXT_VF8 0xfc0ff07f
- +#define MATCH_VSEXT_VF8 0x4801a057
- +#define MASK_VSEXT_VF8 0xfc0ff07f
- +#define MATCH_VZEXT_VF4 0x48022057
- +#define MASK_VZEXT_VF4 0xfc0ff07f
- +#define MATCH_VSEXT_VF4 0x4802a057
- +#define MASK_VSEXT_VF4 0xfc0ff07f
- +#define MATCH_VZEXT_VF2 0x48032057
- +#define MASK_VZEXT_VF2 0xfc0ff07f
- +#define MATCH_VSEXT_VF2 0x4803a057
- +#define MASK_VSEXT_VF2 0xfc0ff07f
- +
- +#define MATCH_VADCVVM 0x40000057
- +#define MASK_VADCVVM 0xfe00707f
- +#define MATCH_VADCVXM 0x40004057
- +#define MASK_VADCVXM 0xfe00707f
- +#define MATCH_VADCVIM 0x40003057
- +#define MASK_VADCVIM 0xfe00707f
- +#define MATCH_VMADCVVM 0x44000057
- +#define MASK_VMADCVVM 0xfe00707f
- +#define MATCH_VMADCVXM 0x44004057
- +#define MASK_VMADCVXM 0xfe00707f
- +#define MATCH_VMADCVIM 0x44003057
- +#define MASK_VMADCVIM 0xfe00707f
- +#define MATCH_VMADCVV 0x46000057
- +#define MASK_VMADCVV 0xfe00707f
- +#define MATCH_VMADCVX 0x46004057
- +#define MASK_VMADCVX 0xfe00707f
- +#define MATCH_VMADCVI 0x46003057
- +#define MASK_VMADCVI 0xfe00707f
- +#define MATCH_VSBCVVM 0x48000057
- +#define MASK_VSBCVVM 0xfe00707f
- +#define MATCH_VSBCVXM 0x48004057
- +#define MASK_VSBCVXM 0xfe00707f
- +#define MATCH_VMSBCVVM 0x4c000057
- +#define MASK_VMSBCVVM 0xfe00707f
- +#define MATCH_VMSBCVXM 0x4c004057
- +#define MASK_VMSBCVXM 0xfe00707f
- +#define MATCH_VMSBCVV 0x4e000057
- +#define MASK_VMSBCVV 0xfe00707f
- +#define MATCH_VMSBCVX 0x4e004057
- +#define MASK_VMSBCVX 0xfe00707f
- +
- +#define MATCH_VNOTV 0x2c0fb057
- +#define MASK_VNOTV 0xfc0ff07f
- +
- +#define MATCH_VANDVV 0x24000057
- +#define MASK_VANDVV 0xfc00707f
- +#define MATCH_VANDVX 0x24004057
- +#define MASK_VANDVX 0xfc00707f
- +#define MATCH_VANDVI 0x24003057
- +#define MASK_VANDVI 0xfc00707f
- +#define MATCH_VORVV 0x28000057
- +#define MASK_VORVV 0xfc00707f
- +#define MATCH_VORVX 0x28004057
- +#define MASK_VORVX 0xfc00707f
- +#define MATCH_VORVI 0x28003057
- +#define MASK_VORVI 0xfc00707f
- +#define MATCH_VXORVV 0x2c000057
- +#define MASK_VXORVV 0xfc00707f
- +#define MATCH_VXORVX 0x2c004057
- +#define MASK_VXORVX 0xfc00707f
- +#define MATCH_VXORVI 0x2c003057
- +#define MASK_VXORVI 0xfc00707f
- +
- +#define MATCH_VSLLVV 0x94000057
- +#define MASK_VSLLVV 0xfc00707f
- +#define MATCH_VSLLVX 0x94004057
- +#define MASK_VSLLVX 0xfc00707f
- +#define MATCH_VSLLVI 0x94003057
- +#define MASK_VSLLVI 0xfc00707f
- +#define MATCH_VSRLVV 0xa0000057
- +#define MASK_VSRLVV 0xfc00707f
- +#define MATCH_VSRLVX 0xa0004057
- +#define MASK_VSRLVX 0xfc00707f
- +#define MATCH_VSRLVI 0xa0003057
- +#define MASK_VSRLVI 0xfc00707f
- +#define MATCH_VSRAVV 0xa4000057
- +#define MASK_VSRAVV 0xfc00707f
- +#define MATCH_VSRAVX 0xa4004057
- +#define MASK_VSRAVX 0xfc00707f
- +#define MATCH_VSRAVI 0xa4003057
- +#define MASK_VSRAVI 0xfc00707f
- +
- +#define MATCH_VNSRLWV 0xb0000057
- +#define MASK_VNSRLWV 0xfc00707f
- +#define MATCH_VNSRLWX 0xb0004057
- +#define MASK_VNSRLWX 0xfc00707f
- +#define MATCH_VNSRLWI 0xb0003057
- +#define MASK_VNSRLWI 0xfc00707f
- +#define MATCH_VNSRAWV 0xb4000057
- +#define MASK_VNSRAWV 0xfc00707f
- +#define MATCH_VNSRAWX 0xb4004057
- +#define MASK_VNSRAWX 0xfc00707f
- +#define MATCH_VNSRAWI 0xb4003057
- +#define MASK_VNSRAWI 0xfc00707f
- +
- +#define MATCH_VMSEQVV 0x60000057
- +#define MASK_VMSEQVV 0xfc00707f
- +#define MATCH_VMSEQVX 0x60004057
- +#define MASK_VMSEQVX 0xfc00707f
- +#define MATCH_VMSEQVI 0x60003057
- +#define MASK_VMSEQVI 0xfc00707f
- +#define MATCH_VMSNEVV 0x64000057
- +#define MASK_VMSNEVV 0xfc00707f
- +#define MATCH_VMSNEVX 0x64004057
- +#define MASK_VMSNEVX 0xfc00707f
- +#define MATCH_VMSNEVI 0x64003057
- +#define MASK_VMSNEVI 0xfc00707f
- +#define MATCH_VMSLTVV 0x6c000057
- +#define MASK_VMSLTVV 0xfc00707f
- +#define MATCH_VMSLTVX 0x6c004057
- +#define MASK_VMSLTVX 0xfc00707f
- +#define MATCH_VMSLTUVV 0x68000057
- +#define MASK_VMSLTUVV 0xfc00707f
- +#define MATCH_VMSLTUVX 0x68004057
- +#define MASK_VMSLTUVX 0xfc00707f
- +#define MATCH_VMSLEVV 0x74000057
- +#define MASK_VMSLEVV 0xfc00707f
- +#define MATCH_VMSLEVX 0x74004057
- +#define MASK_VMSLEVX 0xfc00707f
- +#define MATCH_VMSLEVI 0x74003057
- +#define MASK_VMSLEVI 0xfc00707f
- +#define MATCH_VMSLEUVV 0x70000057
- +#define MASK_VMSLEUVV 0xfc00707f
- +#define MATCH_VMSLEUVX 0x70004057
- +#define MASK_VMSLEUVX 0xfc00707f
- +#define MATCH_VMSLEUVI 0x70003057
- +#define MASK_VMSLEUVI 0xfc00707f
- +#define MATCH_VMSGTVX 0x7c004057
- +#define MASK_VMSGTVX 0xfc00707f
- +#define MATCH_VMSGTVI 0x7c003057
- +#define MASK_VMSGTVI 0xfc00707f
- +#define MATCH_VMSGTUVX 0x78004057
- +#define MASK_VMSGTUVX 0xfc00707f
- +#define MATCH_VMSGTUVI 0x78003057
- +#define MASK_VMSGTUVI 0xfc00707f
- +
- +#define MATCH_VMINVV 0x14000057
- +#define MASK_VMINVV 0xfc00707f
- +#define MATCH_VMINVX 0x14004057
- +#define MASK_VMINVX 0xfc00707f
- +#define MATCH_VMAXVV 0x1c000057
- +#define MASK_VMAXVV 0xfc00707f
- +#define MATCH_VMAXVX 0x1c004057
- +#define MASK_VMAXVX 0xfc00707f
- +#define MATCH_VMINUVV 0x10000057
- +#define MASK_VMINUVV 0xfc00707f
- +#define MATCH_VMINUVX 0x10004057
- +#define MASK_VMINUVX 0xfc00707f
- +#define MATCH_VMAXUVV 0x18000057
- +#define MASK_VMAXUVV 0xfc00707f
- +#define MATCH_VMAXUVX 0x18004057
- +#define MASK_VMAXUVX 0xfc00707f
- +
- +#define MATCH_VMULVV 0x94002057
- +#define MASK_VMULVV 0xfc00707f
- +#define MATCH_VMULVX 0x94006057
- +#define MASK_VMULVX 0xfc00707f
- +#define MATCH_VMULHVV 0x9c002057
- +#define MASK_VMULHVV 0xfc00707f
- +#define MATCH_VMULHVX 0x9c006057
- +#define MASK_VMULHVX 0xfc00707f
- +#define MATCH_VMULHUVV 0x90002057
- +#define MASK_VMULHUVV 0xfc00707f
- +#define MATCH_VMULHUVX 0x90006057
- +#define MASK_VMULHUVX 0xfc00707f
- +#define MATCH_VMULHSUVV 0x98002057
- +#define MASK_VMULHSUVV 0xfc00707f
- +#define MATCH_VMULHSUVX 0x98006057
- +#define MASK_VMULHSUVX 0xfc00707f
- +
- +#define MATCH_VWMULVV 0xec002057
- +#define MASK_VWMULVV 0xfc00707f
- +#define MATCH_VWMULVX 0xec006057
- +#define MASK_VWMULVX 0xfc00707f
- +#define MATCH_VWMULUVV 0xe0002057
- +#define MASK_VWMULUVV 0xfc00707f
- +#define MATCH_VWMULUVX 0xe0006057
- +#define MASK_VWMULUVX 0xfc00707f
- +#define MATCH_VWMULSUVV 0xe8002057
- +#define MASK_VWMULSUVV 0xfc00707f
- +#define MATCH_VWMULSUVX 0xe8006057
- +#define MASK_VWMULSUVX 0xfc00707f
- +
- +#define MATCH_VMACCVV 0xb4002057
- +#define MASK_VMACCVV 0xfc00707f
- +#define MATCH_VMACCVX 0xb4006057
- +#define MASK_VMACCVX 0xfc00707f
- +#define MATCH_VNMSACVV 0xbc002057
- +#define MASK_VNMSACVV 0xfc00707f
- +#define MATCH_VNMSACVX 0xbc006057
- +#define MASK_VNMSACVX 0xfc00707f
- +#define MATCH_VMADDVV 0xa4002057
- +#define MASK_VMADDVV 0xfc00707f
- +#define MATCH_VMADDVX 0xa4006057
- +#define MASK_VMADDVX 0xfc00707f
- +#define MATCH_VNMSUBVV 0xac002057
- +#define MASK_VNMSUBVV 0xfc00707f
- +#define MATCH_VNMSUBVX 0xac006057
- +#define MASK_VNMSUBVX 0xfc00707f
- +
- +#define MATCH_VWMACCUVV 0xf0002057
- +#define MASK_VWMACCUVV 0xfc00707f
- +#define MATCH_VWMACCUVX 0xf0006057
- +#define MASK_VWMACCUVX 0xfc00707f
- +#define MATCH_VWMACCVV 0xf4002057
- +#define MASK_VWMACCVV 0xfc00707f
- +#define MATCH_VWMACCVX 0xf4006057
- +#define MASK_VWMACCVX 0xfc00707f
- +#define MATCH_VWMACCSUVV 0xfc002057
- +#define MASK_VWMACCSUVV 0xfc00707f
- +#define MATCH_VWMACCSUVX 0xfc006057
- +#define MASK_VWMACCSUVX 0xfc00707f
- +#define MATCH_VWMACCUSVX 0xf8006057
- +#define MASK_VWMACCUSVX 0xfc00707f
- +
- +#define MATCH_VQMACCUVV 0xf0000057
- +#define MASK_VQMACCUVV 0xfc00707f
- +#define MATCH_VQMACCUVX 0xf0004057
- +#define MASK_VQMACCUVX 0xfc00707f
- +#define MATCH_VQMACCVV 0xf4000057
- +#define MASK_VQMACCVV 0xfc00707f
- +#define MATCH_VQMACCVX 0xf4004057
- +#define MASK_VQMACCVX 0xfc00707f
- +#define MATCH_VQMACCSUVV 0xfc000057
- +#define MASK_VQMACCSUVV 0xfc00707f
- +#define MATCH_VQMACCSUVX 0xfc004057
- +#define MASK_VQMACCSUVX 0xfc00707f
- +#define MATCH_VQMACCUSVX 0xf8004057
- +#define MASK_VQMACCUSVX 0xfc00707f
- +
- +#define MATCH_VDIVVV 0x84002057
- +#define MASK_VDIVVV 0xfc00707f
- +#define MATCH_VDIVVX 0x84006057
- +#define MASK_VDIVVX 0xfc00707f
- +#define MATCH_VDIVUVV 0x80002057
- +#define MASK_VDIVUVV 0xfc00707f
- +#define MATCH_VDIVUVX 0x80006057
- +#define MASK_VDIVUVX 0xfc00707f
- +#define MATCH_VREMVV 0x8c002057
- +#define MASK_VREMVV 0xfc00707f
- +#define MATCH_VREMVX 0x8c006057
- +#define MASK_VREMVX 0xfc00707f
- +#define MATCH_VREMUVV 0x88002057
- +#define MASK_VREMUVV 0xfc00707f
- +#define MATCH_VREMUVX 0x88006057
- +#define MASK_VREMUVX 0xfc00707f
- +
- +#define MATCH_VMERGEVVM 0x5c000057
- +#define MASK_VMERGEVVM 0xfe00707f
- +#define MATCH_VMERGEVXM 0x5c004057
- +#define MASK_VMERGEVXM 0xfe00707f
- +#define MATCH_VMERGEVIM 0x5c003057
- +#define MASK_VMERGEVIM 0xfe00707f
- +
- +#define MATCH_VMVVV 0x5e000057
- +#define MASK_VMVVV 0xfff0707f
- +#define MATCH_VMVVX 0x5e004057
- +#define MASK_VMVVX 0xfff0707f
- +#define MATCH_VMVVI 0x5e003057
- +#define MASK_VMVVI 0xfff0707f
- +
- +#define MATCH_VSADDUVV 0x80000057
- +#define MASK_VSADDUVV 0xfc00707f
- +#define MATCH_VSADDUVX 0x80004057
- +#define MASK_VSADDUVX 0xfc00707f
- +#define MATCH_VSADDUVI 0x80003057
- +#define MASK_VSADDUVI 0xfc00707f
- +#define MATCH_VSADDVV 0x84000057
- +#define MASK_VSADDVV 0xfc00707f
- +#define MATCH_VSADDVX 0x84004057
- +#define MASK_VSADDVX 0xfc00707f
- +#define MATCH_VSADDVI 0x84003057
- +#define MASK_VSADDVI 0xfc00707f
- +#define MATCH_VSSUBUVV 0x88000057
- +#define MASK_VSSUBUVV 0xfc00707f
- +#define MATCH_VSSUBUVX 0x88004057
- +#define MASK_VSSUBUVX 0xfc00707f
- +#define MATCH_VSSUBVV 0x8c000057
- +#define MASK_VSSUBVV 0xfc00707f
- +#define MATCH_VSSUBVX 0x8c004057
- +#define MASK_VSSUBVX 0xfc00707f
- +
- +#define MATCH_VAADDUVV 0x20002057
- +#define MASK_VAADDUVV 0xfc00707f
- +#define MATCH_VAADDUVX 0x20006057
- +#define MASK_VAADDUVX 0xfc00707f
- +#define MATCH_VAADDVV 0x24002057
- +#define MASK_VAADDVV 0xfc00707f
- +#define MATCH_VAADDVX 0x24006057
- +#define MASK_VAADDVX 0xfc00707f
- +#define MATCH_VASUBUVV 0x28002057
- +#define MASK_VASUBUVV 0xfc00707f
- +#define MATCH_VASUBUVX 0x28006057
- +#define MASK_VASUBUVX 0xfc00707f
- +#define MATCH_VASUBVV 0x2c002057
- +#define MASK_VASUBVV 0xfc00707f
- +#define MATCH_VASUBVX 0x2c006057
- +#define MASK_VASUBVX 0xfc00707f
- +
- +#define MATCH_VSMULVV 0x9c000057
- +#define MASK_VSMULVV 0xfc00707f
- +#define MATCH_VSMULVX 0x9c004057
- +#define MASK_VSMULVX 0xfc00707f
- +
- +#define MATCH_VSSRLVV 0xa8000057
- +#define MASK_VSSRLVV 0xfc00707f
- +#define MATCH_VSSRLVX 0xa8004057
- +#define MASK_VSSRLVX 0xfc00707f
- +#define MATCH_VSSRLVI 0xa8003057
- +#define MASK_VSSRLVI 0xfc00707f
- +#define MATCH_VSSRAVV 0xac000057
- +#define MASK_VSSRAVV 0xfc00707f
- +#define MATCH_VSSRAVX 0xac004057
- +#define MASK_VSSRAVX 0xfc00707f
- +#define MATCH_VSSRAVI 0xac003057
- +#define MASK_VSSRAVI 0xfc00707f
- +
- +#define MATCH_VNCLIPUWV 0xb8000057
- +#define MASK_VNCLIPUWV 0xfc00707f
- +#define MATCH_VNCLIPUWX 0xb8004057
- +#define MASK_VNCLIPUWX 0xfc00707f
- +#define MATCH_VNCLIPUWI 0xb8003057
- +#define MASK_VNCLIPUWI 0xfc00707f
- +#define MATCH_VNCLIPWV 0xbc000057
- +#define MASK_VNCLIPWV 0xfc00707f
- +#define MATCH_VNCLIPWX 0xbc004057
- +#define MASK_VNCLIPWX 0xfc00707f
- +#define MATCH_VNCLIPWI 0xbc003057
- +#define MASK_VNCLIPWI 0xfc00707f
- +
- +#define MATCH_VFADDVV 0x00001057
- +#define MASK_VFADDVV 0xfc00707f
- +#define MATCH_VFADDVF 0x00005057
- +#define MASK_VFADDVF 0xfc00707f
- +#define MATCH_VFSUBVV 0x08001057
- +#define MASK_VFSUBVV 0xfc00707f
- +#define MATCH_VFSUBVF 0x08005057
- +#define MASK_VFSUBVF 0xfc00707f
- +#define MATCH_VFRSUBVF 0x9c005057
- +#define MASK_VFRSUBVF 0xfc00707f
- +
- +#define MATCH_VFWADDVV 0xc0001057
- +#define MASK_VFWADDVV 0xfc00707f
- +#define MATCH_VFWADDVF 0xc0005057
- +#define MASK_VFWADDVF 0xfc00707f
- +#define MATCH_VFWSUBVV 0xc8001057
- +#define MASK_VFWSUBVV 0xfc00707f
- +#define MATCH_VFWSUBVF 0xc8005057
- +#define MASK_VFWSUBVF 0xfc00707f
- +#define MATCH_VFWADDWV 0xd0001057
- +#define MASK_VFWADDWV 0xfc00707f
- +#define MATCH_VFWADDWF 0xd0005057
- +#define MASK_VFWADDWF 0xfc00707f
- +#define MATCH_VFWSUBWV 0xd8001057
- +#define MASK_VFWSUBWV 0xfc00707f
- +#define MATCH_VFWSUBWF 0xd8005057
- +#define MASK_VFWSUBWF 0xfc00707f
- +
- +#define MATCH_VFMULVV 0x90001057
- +#define MASK_VFMULVV 0xfc00707f
- +#define MATCH_VFMULVF 0x90005057
- +#define MASK_VFMULVF 0xfc00707f
- +#define MATCH_VFDIVVV 0x80001057
- +#define MASK_VFDIVVV 0xfc00707f
- +#define MATCH_VFDIVVF 0x80005057
- +#define MASK_VFDIVVF 0xfc00707f
- +#define MATCH_VFRDIVVF 0x84005057
- +#define MASK_VFRDIVVF 0xfc00707f
- +
- +#define MATCH_VFWMULVV 0xe0001057
- +#define MASK_VFWMULVV 0xfc00707f
- +#define MATCH_VFWMULVF 0xe0005057
- +#define MASK_VFWMULVF 0xfc00707f
- +
- +#define MATCH_VFMADDVV 0xa0001057
- +#define MASK_VFMADDVV 0xfc00707f
- +#define MATCH_VFMADDVF 0xa0005057
- +#define MASK_VFMADDVF 0xfc00707f
- +#define MATCH_VFNMADDVV 0xa4001057
- +#define MASK_VFNMADDVV 0xfc00707f
- +#define MATCH_VFNMADDVF 0xa4005057
- +#define MASK_VFNMADDVF 0xfc00707f
- +#define MATCH_VFMSUBVV 0xa8001057
- +#define MASK_VFMSUBVV 0xfc00707f
- +#define MATCH_VFMSUBVF 0xa8005057
- +#define MASK_VFMSUBVF 0xfc00707f
- +#define MATCH_VFNMSUBVV 0xac001057
- +#define MASK_VFNMSUBVV 0xfc00707f
- +#define MATCH_VFNMSUBVF 0xac005057
- +#define MASK_VFNMSUBVF 0xfc00707f
- +#define MATCH_VFMACCVV 0xb0001057
- +#define MASK_VFMACCVV 0xfc00707f
- +#define MATCH_VFMACCVF 0xb0005057
- +#define MASK_VFMACCVF 0xfc00707f
- +#define MATCH_VFNMACCVV 0xb4001057
- +#define MASK_VFNMACCVV 0xfc00707f
- +#define MATCH_VFNMACCVF 0xb4005057
- +#define MASK_VFNMACCVF 0xfc00707f
- +#define MATCH_VFMSACVV 0xb8001057
- +#define MASK_VFMSACVV 0xfc00707f
- +#define MATCH_VFMSACVF 0xb8005057
- +#define MASK_VFMSACVF 0xfc00707f
- +#define MATCH_VFNMSACVV 0xbc001057
- +#define MASK_VFNMSACVV 0xfc00707f
- +#define MATCH_VFNMSACVF 0xbc005057
- +#define MASK_VFNMSACVF 0xfc00707f
- +
- +#define MATCH_VFWMACCVV 0xf0001057
- +#define MASK_VFWMACCVV 0xfc00707f
- +#define MATCH_VFWMACCVF 0xf0005057
- +#define MASK_VFWMACCVF 0xfc00707f
- +#define MATCH_VFWNMACCVV 0xf4001057
- +#define MASK_VFWNMACCVV 0xfc00707f
- +#define MATCH_VFWNMACCVF 0xf4005057
- +#define MASK_VFWNMACCVF 0xfc00707f
- +#define MATCH_VFWMSACVV 0xf8001057
- +#define MASK_VFWMSACVV 0xfc00707f
- +#define MATCH_VFWMSACVF 0xf8005057
- +#define MASK_VFWMSACVF 0xfc00707f
- +#define MATCH_VFWNMSACVV 0xfc001057
- +#define MASK_VFWNMSACVV 0xfc00707f
- +#define MATCH_VFWNMSACVF 0xfc005057
- +#define MASK_VFWNMSACVF 0xfc00707f
- +
- +#define MATCH_VFSQRTV 0x4c001057
- +#define MASK_VFSQRTV 0xfc0ff07f
- +
- +#define MATCH_VFMINVV 0x10001057
- +#define MASK_VFMINVV 0xfc00707f
- +#define MATCH_VFMINVF 0x10005057
- +#define MASK_VFMINVF 0xfc00707f
- +#define MATCH_VFMAXVV 0x18001057
- +#define MASK_VFMAXVV 0xfc00707f
- +#define MATCH_VFMAXVF 0x18005057
- +#define MASK_VFMAXVF 0xfc00707f
- +
- +#define MATCH_VFSGNJVV 0x20001057
- +#define MASK_VFSGNJVV 0xfc00707f
- +#define MATCH_VFSGNJVF 0x20005057
- +#define MASK_VFSGNJVF 0xfc00707f
- +#define MATCH_VFSGNJNVV 0x24001057
- +#define MASK_VFSGNJNVV 0xfc00707f
- +#define MATCH_VFSGNJNVF 0x24005057
- +#define MASK_VFSGNJNVF 0xfc00707f
- +#define MATCH_VFSGNJXVV 0x28001057
- +#define MASK_VFSGNJXVV 0xfc00707f
- +#define MATCH_VFSGNJXVF 0x28005057
- +#define MASK_VFSGNJXVF 0xfc00707f
- +
- +#define MATCH_VMFEQVV 0x60001057
- +#define MASK_VMFEQVV 0xfc00707f
- +#define MATCH_VMFEQVF 0x60005057
- +#define MASK_VMFEQVF 0xfc00707f
- +#define MATCH_VMFNEVV 0x70001057
- +#define MASK_VMFNEVV 0xfc00707f
- +#define MATCH_VMFNEVF 0x70005057
- +#define MASK_VMFNEVF 0xfc00707f
- +#define MATCH_VMFLTVV 0x6c001057
- +#define MASK_VMFLTVV 0xfc00707f
- +#define MATCH_VMFLTVF 0x6c005057
- +#define MASK_VMFLTVF 0xfc00707f
- +#define MATCH_VMFLEVV 0x64001057
- +#define MASK_VMFLEVV 0xfc00707f
- +#define MATCH_VMFLEVF 0x64005057
- +#define MASK_VMFLEVF 0xfc00707f
- +#define MATCH_VMFGTVF 0x74005057
- +#define MASK_VMFGTVF 0xfc00707f
- +#define MATCH_VMFGEVF 0x7c005057
- +#define MASK_VMFGEVF 0xfc00707f
- +
- +#define MATCH_VFCLASSV 0x4c081057
- +#define MASK_VFCLASSV 0xfc0ff07f
- +
- +#define MATCH_VFMERGEVFM 0x5c005057
- +#define MASK_VFMERGEVFM 0xfe00707f
- +#define MATCH_VFMVVF 0x5e005057
- +#define MASK_VFMVVF 0xfff0707f
- +
- +#define MATCH_VFCVTXUFV 0x48001057
- +#define MASK_VFCVTXUFV 0xfc0ff07f
- +#define MATCH_VFCVTXFV 0x48009057
- +#define MASK_VFCVTXFV 0xfc0ff07f
- +#define MATCH_VFCVTFXUV 0x48011057
- +#define MASK_VFCVTFXUV 0xfc0ff07f
- +#define MATCH_VFCVTFXV 0x48019057
- +#define MASK_VFCVTFXV 0xfc0ff07f
- +#define MATCH_VFCVTRTZXUFV 0x48031057
- +#define MASK_VFCVTRTZXUFV 0xfc0ff07f
- +#define MATCH_VFCVTRTZXFV 0x48039057
- +#define MASK_VFCVTRTZXFV 0xfc0ff07f
- +#define MATCH_VFWCVTXUFV 0x48041057
- +#define MASK_VFWCVTXUFV 0xfc0ff07f
- +#define MATCH_VFWCVTXFV 0x48049057
- +#define MASK_VFWCVTXFV 0xfc0ff07f
- +#define MATCH_VFWCVTFXUV 0x48051057
- +#define MASK_VFWCVTFXUV 0xfc0ff07f
- +#define MATCH_VFWCVTFXV 0x48059057
- +#define MASK_VFWCVTFXV 0xfc0ff07f
- +#define MATCH_VFWCVTFFV 0x48061057
- +#define MASK_VFWCVTFFV 0xfc0ff07f
- +#define MATCH_VFWCVTRTZXUFV 0x48071057
- +#define MASK_VFWCVTRTZXUFV 0xfc0ff07f
- +#define MATCH_VFWCVTRTZXFV 0x48079057
- +#define MASK_VFWCVTRTZXFV 0xfc0ff07f
- +#define MATCH_VFNCVTXUFW 0x48081057
- +#define MASK_VFNCVTXUFW 0xfc0ff07f
- +#define MATCH_VFNCVTXFW 0x48089057
- +#define MASK_VFNCVTXFW 0xfc0ff07f
- +#define MATCH_VFNCVTFXUW 0x48091057
- +#define MASK_VFNCVTFXUW 0xfc0ff07f
- +#define MATCH_VFNCVTFXW 0x48099057
- +#define MASK_VFNCVTFXW 0xfc0ff07f
- +#define MATCH_VFNCVTFFW 0x480a1057
- +#define MASK_VFNCVTFFW 0xfc0ff07f
- +#define MATCH_VFNCVTRODFFW 0x480a9057
- +#define MASK_VFNCVTRODFFW 0xfc0ff07f
- +#define MATCH_VFNCVTRTZXUFW 0x480b1057
- +#define MASK_VFNCVTRTZXUFW 0xfc0ff07f
- +#define MATCH_VFNCVTRTZXFW 0x480b9057
- +#define MASK_VFNCVTRTZXFW 0xfc0ff07f
- +
- +#define MATCH_VREDSUMVS 0x00002057
- +#define MASK_VREDSUMVS 0xfc00707f
- +#define MATCH_VREDMAXVS 0x1c002057
- +#define MASK_VREDMAXVS 0xfc00707f
- +#define MATCH_VREDMAXUVS 0x18002057
- +#define MASK_VREDMAXUVS 0xfc00707f
- +#define MATCH_VREDMINVS 0x14002057
- +#define MASK_VREDMINVS 0xfc00707f
- +#define MATCH_VREDMINUVS 0x10002057
- +#define MASK_VREDMINUVS 0xfc00707f
- +#define MATCH_VREDANDVS 0x04002057
- +#define MASK_VREDANDVS 0xfc00707f
- +#define MATCH_VREDORVS 0x08002057
- +#define MASK_VREDORVS 0xfc00707f
- +#define MATCH_VREDXORVS 0x0c002057
- +#define MASK_VREDXORVS 0xfc00707f
- +
- +#define MATCH_VWREDSUMUVS 0xc0000057
- +#define MASK_VWREDSUMUVS 0xfc00707f
- +#define MATCH_VWREDSUMVS 0xc4000057
- +#define MASK_VWREDSUMVS 0xfc00707f
- +
- +#define MATCH_VFREDOSUMVS 0x0c001057
- +#define MASK_VFREDOSUMVS 0xfc00707f
- +#define MATCH_VFREDSUMVS 0x04001057
- +#define MASK_VFREDSUMVS 0xfc00707f
- +#define MATCH_VFREDMAXVS 0x1c001057
- +#define MASK_VFREDMAXVS 0xfc00707f
- +#define MATCH_VFREDMINVS 0x14001057
- +#define MASK_VFREDMINVS 0xfc00707f
- +
- +#define MATCH_VFWREDOSUMVS 0xcc001057
- +#define MASK_VFWREDOSUMVS 0xfc00707f
- +#define MATCH_VFWREDSUMVS 0xc4001057
- +#define MASK_VFWREDSUMVS 0xfc00707f
- +
- +#define MATCH_VMANDMM 0x66002057
- +#define MASK_VMANDMM 0xfe00707f
- +#define MATCH_VMNANDMM 0x76002057
- +#define MASK_VMNANDMM 0xfe00707f
- +#define MATCH_VMANDNOTMM 0x62002057
- +#define MASK_VMANDNOTMM 0xfe00707f
- +#define MATCH_VMXORMM 0x6e002057
- +#define MASK_VMXORMM 0xfe00707f
- +#define MATCH_VMORMM 0x6a002057
- +#define MASK_VMORMM 0xfe00707f
- +#define MATCH_VMNORMM 0x7a002057
- +#define MASK_VMNORMM 0xfe00707f
- +#define MATCH_VMORNOTMM 0x72002057
- +#define MASK_VMORNOTMM 0xfe00707f
- +#define MATCH_VMXNORMM 0x7e002057
- +#define MASK_VMXNORMM 0xfe00707f
- +
- +#define MATCH_VPOPCM 0x40082057
- +#define MASK_VPOPCM 0xfc0ff07f
- +#define MATCH_VFIRSTM 0x4008a057
- +#define MASK_VFIRSTM 0xfc0ff07f
- +
- +#define MATCH_VMSBFM 0x5000a057
- +#define MASK_VMSBFM 0xfc0ff07f
- +#define MATCH_VMSIFM 0x5001a057
- +#define MASK_VMSIFM 0xfc0ff07f
- +#define MATCH_VMSOFM 0x50012057
- +#define MASK_VMSOFM 0xfc0ff07f
- +#define MATCH_VIOTAM 0x50082057
- +#define MASK_VIOTAM 0xfc0ff07f
- +#define MATCH_VIDV 0x5008a057
- +#define MASK_VIDV 0xfdfff07f
- +
- +#define MATCH_VMVXS 0x42002057
- +#define MASK_VMVXS 0xfe0ff07f
- +#define MATCH_VMVSX 0x42006057
- +#define MASK_VMVSX 0xfff0707f
- +
- +#define MATCH_VFMVFS 0x42001057
- +#define MASK_VFMVFS 0xfe0ff07f
- +#define MATCH_VFMVSF 0x42005057
- +#define MASK_VFMVSF 0xfff0707f
- +
- +#define MATCH_VSLIDEUPVX 0x38004057
- +#define MASK_VSLIDEUPVX 0xfc00707f
- +#define MATCH_VSLIDEUPVI 0x38003057
- +#define MASK_VSLIDEUPVI 0xfc00707f
- +#define MATCH_VSLIDEDOWNVX 0x3c004057
- +#define MASK_VSLIDEDOWNVX 0xfc00707f
- +#define MATCH_VSLIDEDOWNVI 0x3c003057
- +#define MASK_VSLIDEDOWNVI 0xfc00707f
- +
- +#define MATCH_VSLIDE1UPVX 0x38006057
- +#define MASK_VSLIDE1UPVX 0xfc00707f
- +#define MATCH_VSLIDE1DOWNVX 0x3c006057
- +#define MASK_VSLIDE1DOWNVX 0xfc00707f
- +
- +#define MATCH_VFSLIDE1UPVF 0x38005057
- +#define MASK_VFSLIDE1UPVF 0xfc00707f
- +#define MATCH_VFSLIDE1DOWNVF 0x3c005057
- +#define MASK_VFSLIDE1DOWNVF 0xfc00707f
- +
- +#define MATCH_VRGATHERVV 0x30000057
- +#define MASK_VRGATHERVV 0xfc00707f
- +#define MATCH_VRGATHERVX 0x30004057
- +#define MASK_VRGATHERVX 0xfc00707f
- +#define MATCH_VRGATHERVI 0x30003057
- +#define MASK_VRGATHERVI 0xfc00707f
- +
- +#define MATCH_VCOMPRESSVM 0x5e002057
- +#define MASK_VCOMPRESSVM 0xfe00707f
- +
- +#define MATCH_VMV1RV 0x9e003057
- +#define MASK_VMV1RV 0xfe0ff07f
- +#define MATCH_VMV2RV 0x9e00b057
- +#define MASK_VMV2RV 0xfe0ff07f
- +#define MATCH_VMV4RV 0x9e01b057
- +#define MASK_VMV4RV 0xfe0ff07f
- +#define MATCH_VMV8RV 0x9e03b057
- +#define MASK_VMV8RV 0xfe0ff07f
- +
- +#define MATCH_VDOTVV 0xe4000057
- +#define MASK_VDOTVV 0xfc00707f
- +#define MATCH_VDOTUVV 0xe0000057
- +#define MASK_VDOTUVV 0xfc00707f
- +#define MATCH_VFDOTVV 0xe4001057
- +#define MASK_VFDOTVV 0xfc00707f
- +/* END RVV */
- +
- #define MATCH_CUSTOM0 0xb
- #define MASK_CUSTOM0 0x707f
- #define MATCH_CUSTOM0_RS1 0x200b
- @@ -830,6 +2954,13 @@
- #define CSR_FFLAGS 0x1
- #define CSR_FRM 0x2
- #define CSR_FCSR 0x3
- +#define CSR_VSTART 0x008
- +#define CSR_VXSAT 0x009
- +#define CSR_VXRM 0x00a
- +#define CSR_VCSR 0x00f
- +#define CSR_VL 0xc20
- +#define CSR_VTYPE 0xc21
- +#define CSR_VLENB 0xc22
- #define CSR_DCSR 0x7b0
- #define CSR_DPC 0x7b1
- #define CSR_DSCRATCH0 0x7b2
- @@ -1365,6 +3496,13 @@ DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
- DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- +DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
- diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
- index 680780a664..62049bdd23 100644
- --- a/include/opcode/riscv.h
- +++ b/include/opcode/riscv.h
- @@ -52,6 +52,34 @@ static const char * const riscv_pred_succ[16] =
- "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
- };
-
- +/* List of vsetvli vsew constants. */
- +static const char * const riscv_vsew[8] =
- +{
- + "e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024"
- +};
- +
- +/* List of vsetvli vlmul constants. */
- +static const char * const riscv_vlmul[8] =
- +{
- + "m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2"
- +};
- +
- +/* List of vsetvli vediv constants. */
- +static const char * const riscv_vediv[4] =
- +{
- + "d1", "d2", "d4", "d8"
- +};
- +
- +static const char * const riscv_vta[2] =
- +{
- + "tu", "ta"
- +};
- +
- +static const char * const riscv_vma[2] =
- +{
- + "mu", "ma"
- +};
- +
- #define RVC_JUMP_BITS 11
- #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
-
- @@ -99,6 +127,14 @@ static const char * const riscv_pred_succ[16] =
- ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
- #define EXTRACT_RVC_J_IMM(x) \
- ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
- +#define EXTRACT_RVV_VI_IMM(x) \
- + (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
- +#define EXTRACT_RVV_VI_UIMM(x) \
- + (RV_X(x, 15, 5))
- +#define EXTRACT_RVV_OFFSET(x) \
- + (RV_X(x, 29, 3))
- +#define EXTRACT_RVV_VC_IMM(x) \
- + (RV_X(x, 20, 11))
-
- #define ENCODE_ITYPE_IMM(x) \
- (RV_X(x, 0, 12) << 20)
- @@ -138,6 +174,8 @@ static const char * const riscv_pred_succ[16] =
- ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
- #define ENCODE_RVC_J_IMM(x) \
- ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
- +#define ENCODE_RVV_VC_IMM(x) \
- + (RV_X(x, 0, 11) << 20)
-
- #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
- #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
- @@ -158,6 +196,7 @@ static const char * const riscv_pred_succ[16] =
- #define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
- #define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
- #define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
- +#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
-
- #define RISCV_RTYPE(insn, rd, rs1, rs2) \
- ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
- @@ -256,6 +295,37 @@ static const char * const riscv_pred_succ[16] =
- #define OP_MASK_CFUNCT2 0x3
- #define OP_SH_CFUNCT2 5
-
- +/* RVV fields. */
- +
- +#define OP_MASK_VD 0x1f
- +#define OP_SH_VD 7
- +#define OP_MASK_VS1 0x1f
- +#define OP_SH_VS1 15
- +#define OP_MASK_VS2 0x1f
- +#define OP_SH_VS2 20
- +#define OP_MASK_VIMM 0x1f
- +#define OP_SH_VIMM 15
- +#define OP_MASK_VMASK 0x1
- +#define OP_SH_VMASK 25
- +#define OP_MASK_VFUNCT6 0x3f
- +#define OP_SH_VFUNCT6 26
- +
- +#define OP_MASK_VLMUL 0x23
- +#define OP_SH_VLMUL 0
- +#define OP_MASK_VSEW 0x7
- +#define OP_SH_VSEW 2
- +#define OP_MASK_VEDIV 0x3
- +#define OP_SH_VEDIV 8
- +#define OP_MASK_VTYPE_RES 0x1
- +#define OP_SH_VTYPE_RES 10
- +#define OP_MASK_VTA 0x1
- +#define OP_SH_VTA 6
- +#define OP_MASK_VMA 0x1
- +#define OP_SH_VMA 7
- +
- +#define OP_MASK_VWD 0x1
- +#define OP_SH_VWD 26
- +
- /* ABI names for selected x-registers. */
-
- #define X_RA 1
- @@ -269,6 +339,8 @@ static const char * const riscv_pred_succ[16] =
-
- #define NGPR 32
- #define NFPR 32
- +#define NVECR 32
- +#define NVECM 1
-
- /* These fake label defines are use by both the assembler, and
- libopcodes. The assembler uses this when it needs to generate a fake
- @@ -282,6 +354,10 @@ static const char * const riscv_pred_succ[16] =
- (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
- | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
-
- +#define INSERT_VLMUL(STRUCT, VALUE) \
- + INSERT_BITS (STRUCT, (VALUE & 0x3), (OP_MASK_VLMUL & 0x3), 0), \
- + INSERT_BITS (STRUCT, (((VALUE & 0x4) >> 2) <<5), (OP_MASK_VLMUL & 0x20), 0)
- +
- /* Extract bits MASK << SHIFT from STRUCT and shift them right
- SHIFT places. */
- #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
- @@ -291,6 +367,11 @@ static const char * const riscv_pred_succ[16] =
- #define EXTRACT_OPERAND(FIELD, INSN) \
- EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
-
- +/* Extract the vlmul value from vsetvli instrucion. */
- +#define EXTRACT_VLMUL(INSN) \
- + (((EXTRACT_OPERAND (VLMUL, INSN) >> 5) << 2) \
- + | (EXTRACT_OPERAND (VLMUL, INSN) & 0x3))
- +
- /* The maximal number of subset can be required. */
- #define MAX_SUBSET_NUM 4
-
- @@ -309,6 +390,12 @@ enum riscv_insn_class
- INSN_CLASS_D_AND_C,
- INSN_CLASS_F_AND_C,
- INSN_CLASS_Q,
- + INSN_CLASS_V,
- + INSN_CLASS_V_AND_F,
- + INSN_CLASS_V_OR_ZVAMO,
- + INSN_CLASS_V_AND_ZVEDIV,
- + INSN_CLASS_V_OR_ZVLSSEG,
- + INSN_CLASS_V_AND_ZVQMAC,
- };
-
- /* This structure holds information for a particular instruction. */
- @@ -335,8 +422,11 @@ struct riscv_opcode
- INSN_MACRO, then this field is the macro identifier. */
- insn_t mask;
- /* A function to determine if a word corresponds to this instruction.
- - Usually, this computes ((word & mask) == match). */
- - int (*match_func) (const struct riscv_opcode *op, insn_t word);
- + Usually, this computes ((word & mask) == match). If the constraints
- + checking is disable, then most of the function should check only the
- + basic encoding for the instruction. */
- + int (*match_func) (const struct riscv_opcode *op, insn_t word,
- + int constraints);
- /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
- of bits describing the instruction, notably any relevant hazard
- information. */
- @@ -375,6 +465,7 @@ enum riscv_csr_class
- CSR_CLASS_I,
- CSR_CLASS_I_32, /* rv32 only */
- CSR_CLASS_F, /* f-ext only */
- + CSR_CLASS_V, /* v-ext only */
- CSR_CLASS_DEBUG /* debug CSR */
- };
-
- @@ -478,6 +569,8 @@ enum
- M_CALL,
- M_J,
- M_LI,
- + M_VMSGE,
- + M_VMSGEU,
- M_NUM_MACROS
- };
-
- @@ -486,6 +579,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR];
- extern const char * const riscv_gpr_names_abi[NGPR];
- extern const char * const riscv_fpr_names_numeric[NFPR];
- extern const char * const riscv_fpr_names_abi[NFPR];
- +extern const char * const riscv_vecr_names_numeric[NVECR];
- +extern const char * const riscv_vecm_names_numeric[NVECM];
-
- extern const struct riscv_opcode riscv_opcodes[];
- extern const struct riscv_opcode riscv_insn_types[];
- diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
- index 655ce4ad0b..25e0a93e88 100644
- --- a/opcodes/riscv-dis.c
- +++ b/opcodes/riscv-dis.c
- @@ -43,6 +43,7 @@ struct riscv_private_data
-
- static const char * const *riscv_gpr_names;
- static const char * const *riscv_fpr_names;
- +static const char * const *riscv_vecr_names;
-
- /* Other options. */
- static int no_aliases; /* If set disassemble as most general inst. */
- @@ -52,6 +53,7 @@ set_default_riscv_dis_options (void)
- {
- riscv_gpr_names = riscv_gpr_names_abi;
- riscv_fpr_names = riscv_fpr_names_abi;
- + riscv_vecr_names = riscv_vecr_names_numeric;
- no_aliases = 0;
- }
-
- @@ -401,6 +403,88 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
- print (info->stream, "%d", rs1);
- break;
-
- + case 'V': /* RVV */
- + switch (*++d)
- + {
- + case 'd':
- + case 'f':
- + print (info->stream, "%s",
- + riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
- + break;
- +
- + case 'e':
- + if (!EXTRACT_OPERAND (VWD, l))
- + print (info->stream, "%s", riscv_gpr_names[0]);
- + else
- + print (info->stream, "%s",
- + riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
- + break;
- +
- + case 's':
- + print (info->stream, "%s",
- + riscv_vecr_names[EXTRACT_OPERAND (VS1, l)]);
- + break;
- +
- + case 't':
- + case 'u': /* VS1 == VS2 already verified at this point. */
- + case 'v': /* VD == VS1 == VS2 already verified at this point. */
- + print (info->stream, "%s",
- + riscv_vecr_names[EXTRACT_OPERAND (VS2, l)]);
- + break;
- +
- + case '0':
- + print (info->stream, "%s", riscv_vecr_names[0]);
- + break;
- +
- + case 'c':
- + {
- + int imm = EXTRACT_RVV_VC_IMM (l);
- + unsigned int imm_vlmul = EXTRACT_VLMUL (imm);
- + unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
- + unsigned int imm_vediv = EXTRACT_OPERAND (VEDIV, imm);
- + unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
- + unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
- + unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm);
- +
- + if (imm_vsew < ARRAY_SIZE (riscv_vsew)
- + && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
- + && imm_vediv < ARRAY_SIZE (riscv_vediv)
- + && imm_vta < ARRAY_SIZE (riscv_vta)
- + && imm_vma < ARRAY_SIZE (riscv_vma)
- + && ! imm_vtype_res)
- + print (info->stream, "%s,%s,%s,%s,%s", riscv_vsew[imm_vsew],
- + riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
- + riscv_vma[imm_vma], riscv_vediv[imm_vediv]);
- + else
- + print (info->stream, "%d", imm);
- + }
- + break;
- +
- + case 'i':
- + print (info->stream, "%d", (int)EXTRACT_RVV_VI_IMM (l));
- + break;
- +
- + case 'j':
- + print (info->stream, "%d", (int)EXTRACT_RVV_VI_UIMM (l));
- + break;
- +
- + case 'k':
- + print (info->stream, "%d", (int)EXTRACT_RVV_OFFSET (l));
- + break;
- +
- + case 'm':
- + if (! EXTRACT_OPERAND (VMASK, l))
- + print (info->stream, ",%s", riscv_vecm_names_numeric[0]);
- + break;
- +
- + default:
- + /* xgettext:c-format */
- + print (info->stream, _("# internal error, undefined modifier (V%c)"),
- + *d);
- + return;
- + }
- + break;
- +
- default:
- /* xgettext:c-format */
- print (info->stream, _("# internal error, undefined modifier (%c)"),
- @@ -488,7 +572,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
- for (; op->name; op++)
- {
- /* Does the opcode match? */
- - if (! (op->match_func) (op, word))
- + if (! (op->match_func) (op, word, 0))
- continue;
- /* Is this a pseudo-instruction and may we print it as such? */
- if (no_aliases && (op->pinfo & INSN_ALIAS))
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index 7ca44dc5b8..fcd87e2261 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -56,6 +56,19 @@ const char * const riscv_fpr_names_abi[NFPR] = {
- "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
- };
-
- +const char * const riscv_vecr_names_numeric[NVECR] =
- +{
- + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
- + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
- + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
- + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
- +};
- +
- +const char * const riscv_vecm_names_numeric[NVECM] =
- +{
- + "v0.t"
- +};
- +
- /* The order of overloaded instructions matters. Label arguments and
- register arguments look the same. Instructions that can have either
- for arguments must apear in the correct order in this table for the
- @@ -79,68 +92,112 @@ const char * const riscv_fpr_names_abi[NFPR] = {
- #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
- #define MASK_RL (OP_MASK_RL << OP_SH_RL)
- #define MASK_AQRL (MASK_AQ | MASK_RL)
- +#define MASK_VD (OP_MASK_VD << OP_SH_VD)
- +#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
- +#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
- +#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
-
- static int
- -match_opcode (const struct riscv_opcode *op, insn_t insn)
- +match_opcode (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- return ((insn ^ op->match) & op->mask) == 0;
- }
-
- static int
- match_never (const struct riscv_opcode *op ATTRIBUTE_UNUSED,
- - insn_t insn ATTRIBUTE_UNUSED)
- + insn_t insn ATTRIBUTE_UNUSED,
- + int constraints ATTRIBUTE_UNUSED)
- {
- return 0;
- }
-
- static int
- -match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn)
- +match_rs1_eq_rs2 (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
- int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
- - return match_opcode (op, insn) && rs1 == rs2;
- + return match_opcode (op, insn, 0) && rs1 == rs2;
- +}
- +
- +static int
- +match_vs1_eq_vs2 (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- +{
- + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- +
- + return match_opcode (op, insn, 0) && vs1 == vs2;
- +}
- +
- +static int
- +match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- +
- + return match_opcode (op, insn, 0) && vd == vs1 && vs1 == vs2;
- }
-
- static int
- -match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
- +match_rd_nonzero (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return match_opcode (op, insn) && ((insn & MASK_RD) != 0);
- + return match_opcode (op, insn, 0) && ((insn & MASK_RD) != 0);
- }
-
- static int
- -match_c_add (const struct riscv_opcode *op, insn_t insn)
- +match_c_add (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0);
- + return match_rd_nonzero (op, insn, 0) && ((insn & MASK_CRS2) != 0);
- }
-
- /* We don't allow mv zero,X to become a c.mv hint, so we need a separate
- matching function for this. */
-
- static int
- -match_c_add_with_hint (const struct riscv_opcode *op, insn_t insn)
- +match_c_add_with_hint (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0);
- + return match_opcode (op, insn, 0) && ((insn & MASK_CRS2) != 0);
- }
-
- static int
- -match_c_nop (const struct riscv_opcode *op, insn_t insn)
- +match_c_nop (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return (match_opcode (op, insn)
- + return (match_opcode (op, insn, 0)
- && (((insn & MASK_RD) >> OP_SH_RD) == 0));
- }
-
- static int
- -match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
- +match_c_addi16sp (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return (match_opcode (op, insn)
- + return (match_opcode (op, insn, 0)
- && (((insn & MASK_RD) >> OP_SH_RD) == 2)
- && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0);
- }
-
- static int
- -match_c_lui (const struct riscv_opcode *op, insn_t insn)
- +match_c_lui (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return (match_rd_nonzero (op, insn)
- + return (match_rd_nonzero (op, insn, 0)
- && (((insn & MASK_RD) >> OP_SH_RD) != 2)
- && EXTRACT_RVC_LUI_IMM (insn) != 0);
- }
- @@ -149,50 +206,275 @@ match_c_lui (const struct riscv_opcode *op, insn_t insn)
- matching function for this. */
-
- static int
- -match_c_lui_with_hint (const struct riscv_opcode *op, insn_t insn)
- +match_c_lui_with_hint (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return (match_opcode (op, insn)
- + return (match_opcode (op, insn, 0)
- && (((insn & MASK_RD) >> OP_SH_RD) != 2)
- && EXTRACT_RVC_LUI_IMM (insn) != 0);
- }
-
- static int
- -match_c_addi4spn (const struct riscv_opcode *op, insn_t insn)
- +match_c_addi4spn (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
- + return match_opcode (op, insn, 0) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
- }
-
- /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */
-
- static int
- -match_c_slli (const struct riscv_opcode *op, insn_t insn)
- +match_c_slli (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
- + return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
- }
-
- /* This requires a non-zero rd, and a non-zero shift. */
-
- static int
- -match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn)
- +match_slli_as_c_slli (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return match_rd_nonzero (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
- + return match_rd_nonzero (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
- }
-
- /* This requires a zero shift. A zero rd is a hint, so is allowed. */
-
- static int
- -match_c_slli64 (const struct riscv_opcode *op, insn_t insn)
- +match_c_slli64 (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- {
- - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) == 0;
- + return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) == 0;
- }
-
- /* This is used for both srli and srai. This requires a non-zero shift.
- A zero rd is not possible. */
-
- static int
- -match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
- +match_srxi_as_c_srxi (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints ATTRIBUTE_UNUSED)
- +{
- + return match_opcode (op, insn, 0) && EXTRACT_RVC_IMM (insn) != 0;
- +}
- +
- +/* These are used to check the vector constraints. */
- +
- +static int
- +match_widen_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- +
- + if (constraints
- + && ((vd % 2) != 0
- + || (vs1 >= vd && vs1 <= (vd + 1))
- + || (vs2 >= vd && vs2 <= (vd + 1))
- + || (!vm && vm >= vd && vm <= (vd + 1))))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_widen_vd_neq_vs1_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- +
- + if (constraints
- + && ((vd % 2) != 0
- + || (vs2 % 2) != 0
- + || (vs1 >= vd && vs1 <= (vd + 1))
- + || (!vm && vm >= vd && vm <= (vd + 1))))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_widen_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- +
- + if (constraints
- + && ((vd % 2) != 0
- + || (vs2 >= vd && vs2 <= (vd + 1))
- + || (!vm && vm >= vd && vm <= (vd + 1))))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_widen_vd_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- +
- + if (constraints
- + && ((vd % 2) != 0
- + || (vs2 % 2) != 0
- + || (!vm && vm >= vd && vm <= (vd + 1))))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_quad_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- +
- + if (constraints
- + && ((vd % 4) != 0
- + || (vs1 >= vd && vs1 <= (vd + 3))
- + || (vs2 >= vd && vs2 <= (vd + 3))
- + || (!vm && vm >= vd && vm <= (vd + 3))))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_quad_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- +
- + if (constraints
- + && ((vd % 4) != 0
- + || (vs2 >= vd && vs2 <= (vd + 3))
- + || (!vm && vm >= vd && vm <= (vd + 3))))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_narrow_vd_neq_vs2 (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- +
- + if (constraints
- + && ((vs2 % 2) != 0
- + || (vd >= vs2 && vd <= (vs2 + 1))))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- +
- + if (constraints
- + && (vs1 == vd
- + || vs2 == vd
- + || (!vm && vm == vd)))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- +
- + if (constraints
- + && (vs2 == vd
- + || (!vm && vm == vd)))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_vd_neq_vs2 (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- +
- + if (constraints && vs2 == vd)
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_vd_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- {
- - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
- +
- + if (constraints && !vm && vm == vd)
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- +}
- +
- +static int
- +match_vmv_nf_rv (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- +{
- + int vd = (insn & MASK_VD) >> OP_SH_VD;
- + int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int nf = ((insn & (0x7 << 15) ) >> 15) + 1;
- +
- + if (constraints
- + && ((vd % nf) != 0
- + || (vs2 % nf) != 0))
- + return 0;
- +
- + return match_opcode (op, insn, 0);
- }
-
- const struct riscv_opcode riscv_opcodes[] =
- @@ -780,6 +1062,954 @@ const struct riscv_opcode riscv_opcodes[] =
- {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
- {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
-
- +/* RVV */
- +{"vsetvl", 0, INSN_CLASS_V, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
- +{"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
- +
- +{"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
- +{"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
- +{"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
- +{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
- +{"vle128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128V, MASK_VLE128V, match_opcode, INSN_DREF },
- +{"vle256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256V, MASK_VLE256V, match_opcode, INSN_DREF },
- +{"vle512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512V, MASK_VLE512V, match_opcode, INSN_DREF },
- +{"vle1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024V, MASK_VLE1024V, match_opcode, INSN_DREF },
- +
- +{"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
- +{"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
- +{"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
- +{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
- +{"vse128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE128V, MASK_VSE128V, match_opcode, INSN_DREF },
- +{"vse256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE256V, MASK_VSE256V, match_opcode, INSN_DREF },
- +{"vse512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE512V, MASK_VSE512V, match_opcode, INSN_DREF },
- +{"vse1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE1024V, MASK_VSE1024V, match_opcode, INSN_DREF },
- +
- +{"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
- +{"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
- +{"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
- +{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
- +{"vlse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE128V, MASK_VLSE128V, match_opcode, INSN_DREF },
- +{"vlse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE256V, MASK_VLSE256V, match_opcode, INSN_DREF },
- +{"vlse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE512V, MASK_VLSE512V, match_opcode, INSN_DREF },
- +{"vlse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE1024V, MASK_VLSE1024V, match_opcode, INSN_DREF },
- +
- +{"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
- +{"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
- +{"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
- +{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
- +{"vsse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE128V, MASK_VSSE128V, match_opcode, INSN_DREF },
- +{"vsse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE256V, MASK_VSSE256V, match_opcode, INSN_DREF },
- +{"vsse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_opcode, INSN_DREF },
- +{"vsse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_opcode, INSN_DREF },
- +
- +{"vlxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_opcode, INSN_DREF },
- +{"vlxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_opcode, INSN_DREF },
- +{"vlxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_opcode, INSN_DREF },
- +{"vlxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_opcode, INSN_DREF },
- +{"vlxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI128V, MASK_VLXEI128V, match_opcode, INSN_DREF },
- +{"vlxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI256V, MASK_VLXEI256V, match_opcode, INSN_DREF },
- +{"vlxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI512V, MASK_VLXEI512V, match_opcode, INSN_DREF },
- +{"vlxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI1024V, MASK_VLXEI1024V, match_opcode, INSN_DREF },
- +
- +{"vsxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_opcode, INSN_DREF },
- +{"vsxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_opcode, INSN_DREF },
- +{"vsxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_opcode, INSN_DREF },
- +{"vsxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_opcode, INSN_DREF },
- +{"vsxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI128V, MASK_VSXEI128V, match_opcode, INSN_DREF },
- +{"vsxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI256V, MASK_VSXEI256V, match_opcode, INSN_DREF },
- +{"vsxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI512V, MASK_VSXEI512V, match_opcode, INSN_DREF },
- +{"vsxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI1024V, MASK_VSXEI1024V, match_opcode, INSN_DREF },
- +
- +{"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF },
- +{"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF },
- +{"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF },
- +{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF },
- +{"vsuxei128.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI128V, MASK_VSUXEI128V, match_opcode, INSN_DREF },
- +{"vsuxei256.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI256V, MASK_VSUXEI256V, match_opcode, INSN_DREF },
- +{"vsuxei512.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI512V, MASK_VSUXEI512V, match_opcode, INSN_DREF },
- +{"vsuxei1024.v",0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI1024V, MASK_VSUXEI1024V, match_opcode, INSN_DREF },
- +
- +{"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
- +{"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
- +{"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
- +{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
- +{"vle128ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128FFV, MASK_VLE128FFV, match_opcode, INSN_DREF },
- +{"vle256ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256FFV, MASK_VLE256FFV, match_opcode, INSN_DREF },
- +{"vle512ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512FFV, MASK_VLE512FFV, match_opcode, INSN_DREF },
- +{"vle1024ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024FFV, MASK_VLE1024FFV, match_opcode, INSN_DREF },
- +
- +{"vlseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF },
- +{"vlseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF },
- +{"vlseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF },
- +{"vlseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF },
- +{"vlseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF },
- +{"vlseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF },
- +{"vlseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF },
- +
- +{"vlseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF },
- +{"vlseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF },
- +{"vlseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF },
- +{"vlseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF },
- +{"vlseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF },
- +{"vlseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF },
- +{"vlseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF },
- +
- +{"vlseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF },
- +{"vlseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF },
- +{"vlseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF },
- +{"vlseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF },
- +{"vlseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF },
- +{"vlseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF },
- +{"vlseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF },
- +
- +{"vlseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF },
- +{"vlseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF },
- +{"vlseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF },
- +{"vlseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF },
- +{"vlseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF },
- +{"vlseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF },
- +{"vlseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF },
- +
- +{"vlseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E128V, MASK_VLSEG2E128V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E128V, MASK_VSSEG2E128V, match_opcode, INSN_DREF },
- +{"vlseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E128V, MASK_VLSEG3E128V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E128V, MASK_VSSEG3E128V, match_opcode, INSN_DREF },
- +{"vlseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E128V, MASK_VLSEG4E128V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E128V, MASK_VSSEG4E128V, match_opcode, INSN_DREF },
- +{"vlseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E128V, MASK_VLSEG5E128V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E128V, MASK_VSSEG5E128V, match_opcode, INSN_DREF },
- +{"vlseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E128V, MASK_VLSEG6E128V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E128V, MASK_VSSEG6E128V, match_opcode, INSN_DREF },
- +{"vlseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E128V, MASK_VLSEG7E128V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E128V, MASK_VSSEG7E128V, match_opcode, INSN_DREF },
- +{"vlseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E128V, MASK_VLSEG8E128V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E128V, MASK_VSSEG8E128V, match_opcode, INSN_DREF },
- +
- +{"vlseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E256V, MASK_VLSEG2E256V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E256V, MASK_VSSEG2E256V, match_opcode, INSN_DREF },
- +{"vlseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E256V, MASK_VLSEG3E256V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E256V, MASK_VSSEG3E256V, match_opcode, INSN_DREF },
- +{"vlseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E256V, MASK_VLSEG4E256V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E256V, MASK_VSSEG4E256V, match_opcode, INSN_DREF },
- +{"vlseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E256V, MASK_VLSEG5E256V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E256V, MASK_VSSEG5E256V, match_opcode, INSN_DREF },
- +{"vlseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E256V, MASK_VLSEG6E256V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E256V, MASK_VSSEG6E256V, match_opcode, INSN_DREF },
- +{"vlseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E256V, MASK_VLSEG7E256V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E256V, MASK_VSSEG7E256V, match_opcode, INSN_DREF },
- +{"vlseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E256V, MASK_VLSEG8E256V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E256V, MASK_VSSEG8E256V, match_opcode, INSN_DREF },
- +
- +{"vlseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E512V, MASK_VLSEG2E512V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E512V, MASK_VSSEG2E512V, match_opcode, INSN_DREF },
- +{"vlseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E512V, MASK_VLSEG3E512V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E512V, MASK_VSSEG3E512V, match_opcode, INSN_DREF },
- +{"vlseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E512V, MASK_VLSEG4E512V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E512V, MASK_VSSEG4E512V, match_opcode, INSN_DREF },
- +{"vlseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E512V, MASK_VLSEG5E512V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E512V, MASK_VSSEG5E512V, match_opcode, INSN_DREF },
- +{"vlseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E512V, MASK_VLSEG6E512V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E512V, MASK_VSSEG6E512V, match_opcode, INSN_DREF },
- +{"vlseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E512V, MASK_VLSEG7E512V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E512V, MASK_VSSEG7E512V, match_opcode, INSN_DREF },
- +{"vlseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E512V, MASK_VLSEG8E512V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E512V, MASK_VSSEG8E512V, match_opcode, INSN_DREF },
- +
- +{"vlseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E1024V, MASK_VLSEG2E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E1024V, MASK_VSSEG2E1024V, match_opcode, INSN_DREF },
- +{"vlseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E1024V, MASK_VLSEG3E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E1024V, MASK_VSSEG3E1024V, match_opcode, INSN_DREF },
- +{"vlseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E1024V, MASK_VLSEG4E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E1024V, MASK_VSSEG4E1024V, match_opcode, INSN_DREF },
- +{"vlseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E1024V, MASK_VLSEG5E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E1024V, MASK_VSSEG5E1024V, match_opcode, INSN_DREF },
- +{"vlseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E1024V, MASK_VLSEG6E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E1024V, MASK_VSSEG6E1024V, match_opcode, INSN_DREF },
- +{"vlseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E1024V, MASK_VLSEG7E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E1024V, MASK_VSSEG7E1024V, match_opcode, INSN_DREF },
- +{"vlseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024V, MASK_VLSEG8E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E1024V, MASK_VSSEG8E1024V, match_opcode, INSN_DREF },
- +
- +{"vlsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF },
- +{"vlsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF },
- +{"vlsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF },
- +{"vlsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF },
- +{"vlsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF },
- +{"vlsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF },
- +{"vlsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF },
- +
- +{"vlsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF },
- +{"vlsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF },
- +{"vlsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF },
- +{"vlsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF },
- +{"vlsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF },
- +{"vlsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF },
- +{"vlsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF },
- +
- +{"vlsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF },
- +{"vlsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF },
- +{"vlsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF },
- +{"vlsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF },
- +{"vlsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF },
- +{"vlsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF },
- +{"vlsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF },
- +
- +{"vlsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF },
- +{"vlsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF },
- +{"vlsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF },
- +{"vlsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF },
- +{"vlsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF },
- +{"vlsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF },
- +{"vlsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF },
- +
- +{"vlsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E128V, MASK_VLSSEG2E128V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E128V, MASK_VSSSEG2E128V, match_opcode, INSN_DREF },
- +{"vlsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E128V, MASK_VLSSEG3E128V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E128V, MASK_VSSSEG3E128V, match_opcode, INSN_DREF },
- +{"vlsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E128V, MASK_VLSSEG4E128V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E128V, MASK_VSSSEG4E128V, match_opcode, INSN_DREF },
- +{"vlsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E128V, MASK_VLSSEG5E128V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E128V, MASK_VSSSEG5E128V, match_opcode, INSN_DREF },
- +{"vlsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E128V, MASK_VLSSEG6E128V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E128V, MASK_VSSSEG6E128V, match_opcode, INSN_DREF },
- +{"vlsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E128V, MASK_VLSSEG7E128V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E128V, MASK_VSSSEG7E128V, match_opcode, INSN_DREF },
- +{"vlsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E128V, MASK_VLSSEG8E128V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E128V, MASK_VSSSEG8E128V, match_opcode, INSN_DREF },
- +
- +{"vlsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E256V, MASK_VLSSEG2E256V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E256V, MASK_VSSSEG2E256V, match_opcode, INSN_DREF },
- +{"vlsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E256V, MASK_VLSSEG3E256V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E256V, MASK_VSSSEG3E256V, match_opcode, INSN_DREF },
- +{"vlsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E256V, MASK_VLSSEG4E256V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E256V, MASK_VSSSEG4E256V, match_opcode, INSN_DREF },
- +{"vlsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E256V, MASK_VLSSEG5E256V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E256V, MASK_VSSSEG5E256V, match_opcode, INSN_DREF },
- +{"vlsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E256V, MASK_VLSSEG6E256V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E256V, MASK_VSSSEG6E256V, match_opcode, INSN_DREF },
- +{"vlsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E256V, MASK_VLSSEG7E256V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E256V, MASK_VSSSEG7E256V, match_opcode, INSN_DREF },
- +{"vlsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E256V, MASK_VLSSEG8E256V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E256V, MASK_VSSSEG8E256V, match_opcode, INSN_DREF },
- +
- +{"vlsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E512V, MASK_VLSSEG2E512V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E512V, MASK_VSSSEG2E512V, match_opcode, INSN_DREF },
- +{"vlsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E512V, MASK_VLSSEG3E512V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E512V, MASK_VSSSEG3E512V, match_opcode, INSN_DREF },
- +{"vlsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E512V, MASK_VLSSEG4E512V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E512V, MASK_VSSSEG4E512V, match_opcode, INSN_DREF },
- +{"vlsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E512V, MASK_VLSSEG5E512V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E512V, MASK_VSSSEG5E512V, match_opcode, INSN_DREF },
- +{"vlsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E512V, MASK_VLSSEG6E512V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E512V, MASK_VSSSEG6E512V, match_opcode, INSN_DREF },
- +{"vlsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E512V, MASK_VLSSEG7E512V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E512V, MASK_VSSSEG7E512V, match_opcode, INSN_DREF },
- +{"vlsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E512V, MASK_VLSSEG8E512V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E512V, MASK_VSSSEG8E512V, match_opcode, INSN_DREF },
- +
- +{"vlsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E1024V, MASK_VLSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E1024V, MASK_VSSSEG2E1024V, match_opcode, INSN_DREF },
- +{"vlsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E1024V, MASK_VLSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E1024V, MASK_VSSSEG3E1024V, match_opcode, INSN_DREF },
- +{"vlsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E1024V, MASK_VLSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E1024V, MASK_VSSSEG4E1024V, match_opcode, INSN_DREF },
- +{"vlsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E1024V, MASK_VLSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E1024V, MASK_VSSSEG5E1024V, match_opcode, INSN_DREF },
- +{"vlsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E1024V, MASK_VLSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E1024V, MASK_VSSSEG6E1024V, match_opcode, INSN_DREF },
- +{"vlsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E1024V, MASK_VLSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E1024V, MASK_VSSSEG7E1024V, match_opcode, INSN_DREF },
- +{"vlsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E1024V, MASK_VLSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
- +{"vssseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_opcode, INSN_DREF },
- +
- +{"vlxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI8V, MASK_VLXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI8V, MASK_VSXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI8V, MASK_VLXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI8V, MASK_VSXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI8V, MASK_VLXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI8V, MASK_VSXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI8V, MASK_VLXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI8V, MASK_VSXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI8V, MASK_VLXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI8V, MASK_VSXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI8V, MASK_VLXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI8V, MASK_VSXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI8V, MASK_VLXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI8V, MASK_VSXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vlxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI16V, MASK_VLXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI16V, MASK_VSXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI16V, MASK_VLXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI16V, MASK_VSXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI16V, MASK_VLXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI16V, MASK_VSXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI16V, MASK_VLXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI16V, MASK_VSXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI16V, MASK_VLXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI16V, MASK_VSXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI16V, MASK_VLXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI16V, MASK_VSXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI16V, MASK_VLXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI16V, MASK_VSXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vlxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI32V, MASK_VLXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI32V, MASK_VSXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI32V, MASK_VLXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI32V, MASK_VSXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI32V, MASK_VLXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI32V, MASK_VSXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI32V, MASK_VLXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI32V, MASK_VSXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI32V, MASK_VLXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI32V, MASK_VSXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI32V, MASK_VLXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI32V, MASK_VSXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI32V, MASK_VLXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI32V, MASK_VSXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vlxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI64V, MASK_VLXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI64V, MASK_VSXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI64V, MASK_VLXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI64V, MASK_VSXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI64V, MASK_VLXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI64V, MASK_VSXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI64V, MASK_VLXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI64V, MASK_VSXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI64V, MASK_VLXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI64V, MASK_VSXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI64V, MASK_VLXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI64V, MASK_VSXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI64V, MASK_VLXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI64V, MASK_VSXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vlxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI128V, MASK_VLXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg2ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI128V, MASK_VSXSEG2EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI128V, MASK_VLXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg3ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI128V, MASK_VSXSEG3EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI128V, MASK_VLXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg4ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI128V, MASK_VSXSEG4EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI128V, MASK_VLXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg5ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI128V, MASK_VSXSEG5EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI128V, MASK_VLXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg6ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI128V, MASK_VSXSEG6EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI128V, MASK_VLXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg7ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI128V, MASK_VSXSEG7EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI128V, MASK_VLXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg8ei128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI128V, MASK_VSXSEG8EI128V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vlxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI256V, MASK_VLXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg2ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI256V, MASK_VSXSEG2EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI256V, MASK_VLXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg3ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI256V, MASK_VSXSEG3EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI256V, MASK_VLXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg4ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI256V, MASK_VSXSEG4EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI256V, MASK_VLXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg5ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI256V, MASK_VSXSEG5EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI256V, MASK_VLXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg6ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI256V, MASK_VSXSEG6EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI256V, MASK_VLXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg7ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI256V, MASK_VSXSEG7EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI256V, MASK_VLXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg8ei256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI256V, MASK_VSXSEG8EI256V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vlxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI512V, MASK_VLXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg2ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI512V, MASK_VSXSEG2EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI512V, MASK_VLXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg3ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI512V, MASK_VSXSEG3EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI512V, MASK_VLXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg4ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI512V, MASK_VSXSEG4EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI512V, MASK_VLXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg5ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI512V, MASK_VSXSEG5EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI512V, MASK_VLXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg6ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI512V, MASK_VSXSEG6EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI512V, MASK_VLXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg7ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI512V, MASK_VSXSEG7EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI512V, MASK_VLXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg8ei512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI512V, MASK_VSXSEG8EI512V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vlxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI1024V, MASK_VLXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg2ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI1024V, MASK_VSXSEG2EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG3EI1024V, MASK_VLXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg3ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG3EI1024V, MASK_VSXSEG3EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG4EI1024V, MASK_VLXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg4ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG4EI1024V, MASK_VSXSEG4EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG5EI1024V, MASK_VLXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg5ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG5EI1024V, MASK_VSXSEG5EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG6EI1024V, MASK_VLXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg6ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG6EI1024V, MASK_VSXSEG6EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG7EI1024V, MASK_VLXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg7ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG7EI1024V, MASK_VSXSEG7EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vlxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG8EI1024V, MASK_VLXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +{"vsxseg8ei1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG8EI1024V, MASK_VSXSEG8EI1024V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- +
- +{"vlseg2e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg3e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg4e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg5e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg6e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg7e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg8e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_vd_neq_vm, INSN_DREF },
- +
- +{"vlseg2e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg3e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg4e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg5e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg6e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg7e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg8e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_vd_neq_vm, INSN_DREF },
- +
- +{"vlseg2e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg3e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg4e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg5e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg6e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg7e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg8e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
- +
- +{"vlseg2e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg3e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg4e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg5e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg6e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg7e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg8e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
- +
- +{"vlseg2e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E128FFV, MASK_VLSEG2E128FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg3e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E128FFV, MASK_VLSEG3E128FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg4e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E128FFV, MASK_VLSEG4E128FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg5e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E128FFV, MASK_VLSEG5E128FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg6e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E128FFV, MASK_VLSEG6E128FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg7e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E128FFV, MASK_VLSEG7E128FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg8e128ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E128FFV, MASK_VLSEG8E128FFV, match_vd_neq_vm, INSN_DREF },
- +
- +{"vlseg2e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E256FFV, MASK_VLSEG2E256FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg3e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E256FFV, MASK_VLSEG3E256FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg4e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E256FFV, MASK_VLSEG4E256FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg5e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E256FFV, MASK_VLSEG5E256FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg6e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E256FFV, MASK_VLSEG6E256FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg7e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E256FFV, MASK_VLSEG7E256FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg8e256ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E256FFV, MASK_VLSEG8E256FFV, match_vd_neq_vm, INSN_DREF },
- +
- +{"vlseg2e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E512FFV, MASK_VLSEG2E512FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg3e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E512FFV, MASK_VLSEG3E512FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg4e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E512FFV, MASK_VLSEG4E512FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg5e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E512FFV, MASK_VLSEG5E512FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg6e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E512FFV, MASK_VLSEG6E512FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg7e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E512FFV, MASK_VLSEG7E512FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg8e512ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E512FFV, MASK_VLSEG8E512FFV, match_vd_neq_vm, INSN_DREF },
- +
- +{"vlseg2e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E1024FFV, MASK_VLSEG2E1024FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg3e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E1024FFV, MASK_VLSEG3E1024FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg4e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E1024FFV, MASK_VLSEG4E1024FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg5e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E1024FFV, MASK_VLSEG5E1024FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg6e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E1024FFV, MASK_VLSEG6E1024FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg7e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E1024FFV, MASK_VLSEG7E1024FFV, match_vd_neq_vm, INSN_DREF },
- +{"vlseg8e1024ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024FFV, MASK_VLSEG8E1024FFV, match_vd_neq_vm, INSN_DREF },
- +
- +{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RV, MASK_VL1RV, match_opcode, INSN_DREF },
- +{"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF },
- +
- +{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_opcode, INSN_DREF},
- +{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_opcode, INSN_DREF},
- +{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_opcode, INSN_DREF},
- +{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_opcode, INSN_DREF},
- +{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_opcode, INSN_DREF},
- +{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_opcode, INSN_DREF},
- +{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_opcode, INSN_DREF},
- +{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_opcode, INSN_DREF},
- +{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_opcode, INSN_DREF},
- +
- +{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_opcode, INSN_DREF},
- +{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_opcode, INSN_DREF},
- +{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_opcode, INSN_DREF},
- +{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_opcode, INSN_DREF},
- +{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_opcode, INSN_DREF},
- +{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_opcode, INSN_DREF},
- +{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_opcode, INSN_DREF},
- +{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_opcode, INSN_DREF},
- +{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_opcode, INSN_DREF},
- +
- +{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_opcode, INSN_DREF},
- +{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_opcode, INSN_DREF},
- +{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_opcode, INSN_DREF},
- +{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_opcode, INSN_DREF},
- +{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_opcode, INSN_DREF},
- +{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_opcode, INSN_DREF},
- +{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_opcode, INSN_DREF},
- +{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_opcode, INSN_DREF},
- +{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_opcode, INSN_DREF},
- +
- +{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_opcode, INSN_DREF},
- +{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_opcode, INSN_DREF},
- +{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_opcode, INSN_DREF},
- +{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_opcode, INSN_DREF},
- +{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_opcode, INSN_DREF},
- +{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_opcode, INSN_DREF},
- +{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_opcode, INSN_DREF},
- +{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_opcode, INSN_DREF},
- +{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_opcode, INSN_DREF},
- +
- +{"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
- +{"vadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
- +{"vadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
- +{"vsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
- +{"vsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
- +{"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
- +{"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
- +
- +{"vwcvt.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
- +{"vwcvtu.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
- +
- +{"vwaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
- +{"vwaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
- +{"vwsubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
- +{"vwsubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
- +{"vwadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
- +{"vwadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
- +{"vwsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
- +{"vwsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
- +{"vwaddu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
- +{"vwaddu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
- +{"vwsubu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
- +{"vwsubu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
- +{"vwadd.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
- +{"vwadd.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
- +{"vwsub.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
- +{"vwsub.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
- +
- +{"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_opcode, 0 },
- +{"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_opcode, 0 },
- +{"vzext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_opcode, 0 },
- +{"vsext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_opcode, 0 },
- +{"vzext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_opcode, 0 },
- +{"vsext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_opcode, 0 },
- +
- +{"vadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_opcode, 0 },
- +{"vadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_opcode, 0 },
- +{"vadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_opcode, 0 },
- +{"vmadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
- +{"vmadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
- +{"vmadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
- +{"vmadc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
- +{"vmadc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
- +{"vmadc.vi", 0, INSN_CLASS_V, "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
- +{"vsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_opcode, 0 },
- +{"vsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_opcode, 0 },
- +{"vmsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
- +{"vmsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
- +{"vmsbc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
- +{"vmsbc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
- +
- +{"vnot.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
- +
- +{"vand.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
- +{"vand.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
- +{"vand.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
- +{"vor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
- +{"vor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
- +{"vor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
- +{"vxor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
- +{"vxor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
- +{"vxor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
- +
- +{"vsll.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
- +{"vsll.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
- +{"vsll.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
- +{"vsrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
- +{"vsrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
- +{"vsrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
- +{"vsra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
- +{"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
- +{"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
- +
- +{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2, 0 },
- +{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2, 0 },
- +{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2, 0 },
- +{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2, 0 },
- +{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2, 0 },
- +{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2, 0 },
- +
- +{"vmseq.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
- +{"vmseq.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
- +{"vmseq.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
- +{"vmsne.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
- +{"vmsne.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
- +{"vmsne.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
- +{"vmsltu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
- +{"vmsltu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
- +{"vmslt.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
- +{"vmslt.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
- +{"vmsleu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
- +{"vmsleu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
- +{"vmsleu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
- +{"vmsle.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
- +{"vmsle.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
- +{"vmsle.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
- +{"vmsgtu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
- +{"vmsgtu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
- +{"vmsgt.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
- +{"vmsgt.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
- +
- +/* These aliases are for assembly but not disassembly. */
- +{"vmsgt.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
- +{"vmsgtu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
- +{"vmsge.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
- +{"vmsgeu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
- +{"vmslt.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
- +{"vmsltu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, INSN_ALIAS },
- +{"vmsltu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
- +{"vmsge.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
- +{"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, INSN_ALIAS },
- +{"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
- +
- +{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
- +{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
- +{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
- +{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
- +
- +{"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
- +{"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
- +{"vmin.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
- +{"vmin.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
- +{"vmaxu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
- +{"vmaxu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
- +{"vmax.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
- +{"vmax.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
- +
- +{"vmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
- +{"vmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
- +{"vmulh.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
- +{"vmulh.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
- +{"vmulhu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
- +{"vmulhu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
- +{"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
- +{"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
- +
- +{"vwmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
- +{"vwmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
- +{"vwmulu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
- +{"vwmulu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
- +{"vwmulsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
- +{"vwmulsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
- +
- +{"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
- +{"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
- +{"vnmsac.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
- +{"vnmsac.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
- +{"vmadd.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
- +{"vmadd.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
- +{"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
- +{"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
- +
- +{"vwmaccu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vwmaccu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vwmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vwmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vwmaccsu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vwmaccsu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vwmaccus.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
- +
- +{"vqmaccu.vv", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,Vs,VtVm", MATCH_VQMACCUVV, MASK_VQMACCUVV, match_quad_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vqmaccu.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCUVX, MASK_VQMACCUVX, match_quad_vd_neq_vs2_neq_vm, 0},
- +{"vqmacc.vv", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,Vs,VtVm", MATCH_VQMACCVV, MASK_VQMACCVV, match_quad_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vqmacc.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCVX, MASK_VQMACCVX, match_quad_vd_neq_vs2_neq_vm, 0},
- +{"vqmaccsu.vv", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,Vs,VtVm", MATCH_VQMACCSUVV, MASK_VQMACCSUVV, match_quad_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vqmaccsu.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_quad_vd_neq_vs2_neq_vm, 0},
- +{"vqmaccus.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_quad_vd_neq_vs2_neq_vm, 0},
- +
- +{"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
- +{"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
- +{"vdiv.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
- +{"vdiv.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
- +{"vremu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
- +{"vremu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
- +{"vrem.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
- +{"vrem.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
- +
- +{"vmerge.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
- +{"vmerge.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
- +{"vmerge.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
- +
- +{"vmv.v.v", 0, INSN_CLASS_V, "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
- +{"vmv.v.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
- +{"vmv.v.i", 0, INSN_CLASS_V, "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
- +
- +{"vsaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
- +{"vsaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
- +{"vsaddu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
- +{"vsadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
- +{"vsadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
- +{"vsadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
- +{"vssubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
- +{"vssubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
- +{"vssub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
- +{"vssub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
- +
- +{"vaaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_opcode, 0 },
- +{"vaaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_opcode, 0 },
- +{"vaadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_opcode, 0 },
- +{"vaadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_opcode, 0 },
- +{"vasubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_opcode, 0 },
- +{"vasubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_opcode, 0 },
- +{"vasub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_opcode, 0 },
- +{"vasub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_opcode, 0 },
- +
- +{"vsmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
- +{"vsmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
- +
- +{"vssrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
- +{"vssrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
- +{"vssrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
- +{"vssra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
- +{"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
- +{"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
- +
- +{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2, 0 },
- +{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2, 0 },
- +{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2, 0 },
- +{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2, 0 },
- +{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2, 0 },
- +{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2, 0 },
- +
- +{"vfadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
- +{"vfadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
- +{"vfsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
- +{"vfsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
- +{"vfrsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
- +
- +{"vfwadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vfwadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vfwsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwadd.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
- +{"vfwadd.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
- +{"vfwsub.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
- +{"vfwsub.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
- +
- +{"vfmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
- +{"vfmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
- +{"vfdiv.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
- +{"vfdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
- +{"vfrdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
- +
- +{"vfwmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vfwmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
- +
- +{"vfmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
- +{"vfmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
- +{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
- +{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
- +{"vfmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
- +{"vfmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
- +{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
- +{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
- +{"vfmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
- +{"vfmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
- +{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
- +{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
- +{"vfmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
- +{"vfmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
- +{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
- +{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
- +
- +{"vfwmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vfwmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vfwmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
- +
- +{"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0},
- +
- +{"vfmin.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
- +{"vfmin.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
- +{"vfmax.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
- +{"vfmax.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
- +
- +{"vfsgnj.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
- +{"vfsgnj.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
- +{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
- +{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
- +{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
- +{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
- +
- +{"vmfeq.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
- +{"vmfeq.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
- +{"vmfne.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
- +{"vmfne.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
- +{"vmflt.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
- +{"vmflt.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
- +{"vmfle.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
- +{"vmfle.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
- +{"vmfgt.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
- +{"vmfge.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
- +
- +/* These aliases are for assembly but not disassembly. */
- +{"vmfgt.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
- +{"vmfge.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
- +
- +{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
- +
- +{"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
- +{"vfmv.v.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
- +
- +{"vfcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_opcode, 0},
- +{"vfcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_opcode, 0},
- +{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_opcode, 0},
- +{"vfcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_opcode, 0},
- +{"vfcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_opcode, 0},
- +{"vfcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_opcode, 0},
- +
- +{"vfwcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
- +{"vfwcvt.f.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
- +
- +{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2, 0},
- +{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2, 0},
- +{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2, 0},
- +{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2, 0},
- +{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2, 0},
- +{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2, 0},
- +{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2, 0},
- +{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2, 0},
- +
- +{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
- +{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
- +{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
- +{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
- +{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
- +{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
- +{"vredor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
- +{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
- +
- +{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
- +{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
- +
- +{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
- +{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
- +{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
- +{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
- +
- +{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
- +{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
- +
- +{"vmmv.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
- +{"vmcpy.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
- +{"vmclr.m", 0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
- +{"vmset.m", 0, INSN_CLASS_V, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
- +{"vmnot.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
- +
- +{"vmand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
- +{"vmnand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
- +{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
- +{"vmxor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
- +{"vmor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
- +{"vmnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
- +{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
- +{"vmxnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
- +
- +{"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
- +{"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
- +{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_opcode, 0},
- +{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_opcode, 0},
- +{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_opcode, 0},
- +{"viota.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
- +{"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_opcode, 0},
- +
- +{"vmv.x.s", 0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
- +{"vmv.s.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
- +
- +{"vfmv.f.s", 0, INSN_CLASS_V_AND_F, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
- +{"vfmv.s.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
- +
- +{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2, 0},
- +{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2, 0},
- +{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
- +{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
- +
- +{"vslide1up.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2, 0},
- +{"vslide1down.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
- +{"vfslide1up.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2, 0},
- +{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_opcode, 0},
- +
- +{"vrgather.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +{"vrgather.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
- +{"vrgather.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
- +
- +{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
- +
- +{"vmv1r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
- +{"vmv2r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
- +{"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_vmv_nf_rv, 0},
- +{"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
- +
- +{"vdot.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDOTVV, MASK_VDOTVV, match_opcode, 0},
- +{"vdotu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDOTUVV, MASK_VDOTUVV, match_opcode, 0},
- +{"vfdot.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VFDOTVV, MASK_VFDOTVV, match_opcode, 0},
- +/* END RVV */
- +
- /* Terminate the list. */
- {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
- };
- @@ -797,6 +2027,26 @@ const struct riscv_opcode riscv_insn_types[] =
- {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,T", 0, 0, match_opcode, 0 },
- {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,T", 0, 0, match_opcode, 0 },
-
- +{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,s,t", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,S,t", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,s,T", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,S,T", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V, "O4,F3,F7,d,Vs,t", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,Vs,t", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,d,Vs,T", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,Vs,T", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V, "O4,F3,F7,d,s,Vt", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,s,Vt", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,d,S,Vt", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,S,Vt", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,Vs,t", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,Vs,T", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,s,Vt", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,S,Vt", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V, "O4,F3,F7,d,Vs,Vt", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,Vs,Vt", 0, 0, match_opcode, 0 },
- +{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,Vs,Vt", 0, 0, match_opcode, 0 },
- +
- {"r", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 },
- {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 },
- {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 },
- --
- 2.33.0
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