0024-RISC-V-Update-the-vector-mask-constraints.patch 345 KB

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  1. From 74aac3ffbc31ab5640f1cf2ed0bacaeef35b4e68 Mon Sep 17 00:00:00 2001
  2. From: Nelson Chu <nelson.chu@sifive.com>
  3. Date: Thu, 13 Aug 2020 15:32:14 +0800
  4. Subject: [PATCH 24/48] RISC-V: Update the vector mask constraints.
  5. For now, the destination vector register group for most of masked vector
  6. instruction can not overlap the source mask register. Unless,
  7. 1. Comparison instruction.
  8. 2. Reduction instruction.
  9. V0 is a special case. It is a carry-in register for v[m]adc and v[m]sbc,
  10. and is used to choose vs1/rs1/frs1/imm or vs2 for v[f]merge. For vadc and
  11. vsbc, vd can not overlap the carry-in V0. I use the match_vd_neq_vm to
  12. check the constraints since V0 and VM have the same encoding.
  13. I regard vdot[u].vv as a reduction instruction, too. Therefore, I don't
  14. check the VM constraints for it.
  15. Besides, I also rewrite the vector failed testcases since their names are
  16. hard to understand and maintain.
  17. opcodes/
  18. * riscv-opc.c (match_narrow_vd_neq_vs2): Add the vm checking.
  19. Renamed to match_narrow_vd_neq_vs2_neq_vm.
  20. (match_vd_neq_vs2): Removed. Replace it with match_vd_neq_vs2_vm.
  21. (riscv_opcodes): Updated.
  22. gas/
  23. * config/tc-riscv.c (riscv_ip): Update the comment for V0.
  24. * testsuite/gas/riscv/vector-insns-fail-zvamo.d: New failed testcase
  25. for vector AMO operations.
  26. * testsuite/gas/riscv/vector-insns-fail-zvamo.l: Likewise.
  27. * testsuite/gas/riscv/vector-insns-fail-zvamo.s: Likewise.
  28. * testsuite/gas/riscv/vector-insns-fail-zvqmac.d: New failed testcase
  29. for vector quad-widening instructions.
  30. * testsuite/gas/riscv/vector-insns-fail-zvqmac.l: Likewise.
  31. * testsuite/gas/riscv/vector-insns-fail-zvqmac.s: Likewise.
  32. * testsuite/gas/riscv/vector-insns-fail-load-store.d: New failed testcase
  33. for vector load and store instructions.
  34. * testsuite/gas/riscv/vector-insns-fail-load-store.l: Likewise.
  35. * testsuite/gas/riscv/vector-insns-fail-load-store.s: Likewise.
  36. * testsuite/gas/riscv/vector-insns-fail-arith-int.d: New failed testcase
  37. for vector integer arithmetic instructions.
  38. * testsuite/gas/riscv/vector-insns-fail-arith-int.l: Likewise.
  39. * testsuite/gas/riscv/vector-insns-fail-arith-int.s: Likewise.
  40. * testsuite/gas/riscv/vector-insns-fail-arith-fixp.d: New failed testcase
  41. for vector fixed-point arithmetic instructions.
  42. * testsuite/gas/riscv/vector-insns-fail-arith-fixp.l: Likewise.
  43. * testsuite/gas/riscv/vector-insns-fail-arith-fixp.s: Likewise.
  44. * testsuite/gas/riscv/vector-insns-fail-arith-floatp.d: New failed testcase
  45. for vector floating-point arithmetic instructions.
  46. * testsuite/gas/riscv/vector-insns-fail-arith-floatp.l: Likewise.
  47. * testsuite/gas/riscv/vector-insns-fail-arith-floatp.s: Likewise.
  48. * testsuite/gas/riscv/vector-insns-fail-arith-widen.d: New failed testcase
  49. for vector widening instructions.
  50. * testsuite/gas/riscv/vector-insns-fail-arith-widen.l: Likewise.
  51. * testsuite/gas/riscv/vector-insns-fail-arith-widen.s: Likewise.
  52. * testsuite/gas/riscv/vector-insns-fail-arith-narrow.d: New failed testcase
  53. for vector narrowing instructions.
  54. * testsuite/gas/riscv/vector-insns-fail-arith-narrow.l: Likewise.
  55. * testsuite/gas/riscv/vector-insns-fail-arith-narrow.s: Likewise.
  56. * testsuite/gas/riscv/vector-insns-fail-mask.d: New failed testcase
  57. for vector mask instructions.
  58. * testsuite/gas/riscv/vector-insns-fail-mask.l: Likewise.
  59. * testsuite/gas/riscv/vector-insns-fail-mask.s: Likewise.
  60. * testsuite/gas/riscv/vector-insns-fail-permutation.d: New failed testcase
  61. for vector permutation instructions.
  62. * testsuite/gas/riscv/vector-insns-fail-permutation.l: Likewise.
  63. * testsuite/gas/riscv/vector-insns-fail-permutation.s: Likewise.
  64. * testsuite/gas/riscv/vector-insns-fail-01.d: Removed.
  65. * testsuite/gas/riscv/vector-insns-fail-01.l: Likewise.
  66. * testsuite/gas/riscv/vector-insns-fail-01.s: Likewise.
  67. * testsuite/gas/riscv/vector-insns-fail-02.d: Likewise.
  68. * testsuite/gas/riscv/vector-insns-fail-02.l: Likewise.
  69. * testsuite/gas/riscv/vector-insns-fail-02.s: Likewise.
  70. * testsuite/gas/riscv/vector-insns-fail-03.d: Likewise.
  71. * testsuite/gas/riscv/vector-insns-fail-03.l: Likewise.
  72. * testsuite/gas/riscv/vector-insns-fail-03.s: Likewise.
  73. * testsuite/gas/riscv/vector-insns-fail-04.d: Likewise.
  74. * testsuite/gas/riscv/vector-insns-fail-04.l: Likewise.
  75. * testsuite/gas/riscv/vector-insns-fail-04.s: Likewise.
  76. * testsuite/gas/riscv/vector-insns-fail-05.d: Likewise.
  77. * testsuite/gas/riscv/vector-insns-fail-05.l: Likewise.
  78. * testsuite/gas/riscv/vector-insns-fail-05.s: Likewise.
  79. * testsuite/gas/riscv/vector-insns-fail-06.d: Likewise.
  80. * testsuite/gas/riscv/vector-insns-fail-06.l: Likewise.
  81. * testsuite/gas/riscv/vector-insns-fail-06.s: Likewise.
  82. ---
  83. gas/config/tc-riscv.c | 6 +-
  84. .../gas/riscv/vector-insns-fail-01.d | 3 -
  85. .../gas/riscv/vector-insns-fail-01.l | 393 -------
  86. .../gas/riscv/vector-insns-fail-01.s | 1037 -----------------
  87. .../gas/riscv/vector-insns-fail-02.d | 3 -
  88. .../gas/riscv/vector-insns-fail-02.l | 121 --
  89. .../gas/riscv/vector-insns-fail-02.s | 162 ---
  90. .../gas/riscv/vector-insns-fail-03.d | 3 -
  91. .../gas/riscv/vector-insns-fail-03.l | 125 --
  92. .../gas/riscv/vector-insns-fail-03.s | 187 ---
  93. .../gas/riscv/vector-insns-fail-04.d | 3 -
  94. .../gas/riscv/vector-insns-fail-04.l | 49 -
  95. .../gas/riscv/vector-insns-fail-04.s | 85 --
  96. .../gas/riscv/vector-insns-fail-05.d | 3 -
  97. .../gas/riscv/vector-insns-fail-05.s | 139 ---
  98. .../gas/riscv/vector-insns-fail-06.d | 3 -
  99. .../gas/riscv/vector-insns-fail-06.l | 25 -
  100. .../gas/riscv/vector-insns-fail-06.s | 73 --
  101. .../gas/riscv/vector-insns-fail-arith-fixp.d | 3 +
  102. .../gas/riscv/vector-insns-fail-arith-fixp.l | 27 +
  103. .../gas/riscv/vector-insns-fail-arith-fixp.s | 81 ++
  104. .../riscv/vector-insns-fail-arith-floatp.d | 3 +
  105. .../riscv/vector-insns-fail-arith-floatp.l | 47 +
  106. .../riscv/vector-insns-fail-arith-floatp.s | 152 +++
  107. .../gas/riscv/vector-insns-fail-arith-int.d | 3 +
  108. .../gas/riscv/vector-insns-fail-arith-int.l | 70 ++
  109. .../gas/riscv/vector-insns-fail-arith-int.s | 210 ++++
  110. .../riscv/vector-insns-fail-arith-narrow.d | 3 +
  111. ...-05.l => vector-insns-fail-arith-narrow.l} | 45 +-
  112. .../riscv/vector-insns-fail-arith-narrow.s | 100 ++
  113. .../gas/riscv/vector-insns-fail-arith-widen.d | 3 +
  114. .../gas/riscv/vector-insns-fail-arith-widen.l | 253 ++++
  115. .../gas/riscv/vector-insns-fail-arith-widen.s | 297 +++++
  116. .../gas/riscv/vector-insns-fail-load-store.d | 3 +
  117. .../gas/riscv/vector-insns-fail-load-store.l | 557 +++++++++
  118. .../gas/riscv/vector-insns-fail-load-store.s | 610 ++++++++++
  119. .../gas/riscv/vector-insns-fail-mask.d | 3 +
  120. .../gas/riscv/vector-insns-fail-mask.l | 7 +
  121. .../gas/riscv/vector-insns-fail-mask.s | 20 +
  122. .../gas/riscv/vector-insns-fail-permutation.d | 3 +
  123. .../gas/riscv/vector-insns-fail-permutation.l | 31 +
  124. .../gas/riscv/vector-insns-fail-permutation.s | 56 +
  125. .../gas/riscv/vector-insns-fail-zvamo.d | 3 +
  126. .../gas/riscv/vector-insns-fail-zvamo.l | 109 ++
  127. .../gas/riscv/vector-insns-fail-zvamo.s | 217 ++++
  128. .../gas/riscv/vector-insns-fail-zvqmac.d | 3 +
  129. .../gas/riscv/vector-insns-fail-zvqmac.l | 35 +
  130. .../gas/riscv/vector-insns-fail-zvqmac.s | 39 +
  131. opcodes/riscv-opc.c | 817 +++++++------
  132. 49 files changed, 3391 insertions(+), 2839 deletions(-)
  133. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.d
  134. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.l
  135. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.s
  136. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.d
  137. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.l
  138. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.s
  139. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.d
  140. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.l
  141. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.s
  142. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.d
  143. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.l
  144. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.s
  145. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.d
  146. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.s
  147. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.d
  148. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.l
  149. delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.s
  150. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
  151. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
  152. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
  153. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
  154. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
  155. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
  156. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
  157. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
  158. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
  159. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
  160. rename gas/testsuite/gas/riscv/{vector-insns-fail-05.l => vector-insns-fail-arith-narrow.l} (59%)
  161. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
  162. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
  163. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
  164. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
  165. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
  166. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
  167. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
  168. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.d
  169. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.l
  170. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.s
  171. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
  172. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
  173. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
  174. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
  175. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
  176. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
  177. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d
  178. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
  179. create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s
  180. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  181. index 2dc55ca5aa..e998890b92 100644
  182. --- a/gas/config/tc-riscv.c
  183. +++ b/gas/config/tc-riscv.c
  184. @@ -2826,7 +2826,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
  185. INSERT_OPERAND (VS2, *ip, regno);
  186. continue;
  187. - case '0': /* required vector mask register without .t */
  188. + /* The `V0` is carry-in register for v[m]adc and v[m]sbc,
  189. + and is used to choose vs1/rs1/frs1/imm or vs2 for
  190. + v[f]merge. It use the same encoding as the vector mask
  191. + register. */
  192. + case '0':
  193. if (reg_lookup (&s, RCLASS_VECR, &regno) && regno == 0)
  194. continue;
  195. break;
  196. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.d b/gas/testsuite/gas/riscv/vector-insns-fail-01.d
  197. deleted file mode 100644
  198. index ade7888937..0000000000
  199. --- a/gas/testsuite/gas/riscv/vector-insns-fail-01.d
  200. +++ /dev/null
  201. @@ -1,3 +0,0 @@
  202. -#as: -march=rv32ifv -mcheck-constraints
  203. -#source: vector-insns-fail-01.s
  204. -#error_output: vector-insns-fail-01.l
  205. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.l b/gas/testsuite/gas/riscv/vector-insns-fail-01.l
  206. deleted file mode 100644
  207. index 61687938c9..0000000000
  208. --- a/gas/testsuite/gas/riscv/vector-insns-fail-01.l
  209. +++ /dev/null
  210. @@ -1,393 +0,0 @@
  211. -.*: Assembler messages:
  212. -.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
  213. -.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
  214. -.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
  215. -.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
  216. -.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
  217. -.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
  218. -.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
  219. -.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
  220. -.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
  221. -.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
  222. -.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
  223. -.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
  224. -.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
  225. -.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
  226. -.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
  227. -.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
  228. -.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
  229. -.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
  230. -.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
  231. -.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
  232. -.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
  233. -.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
  234. -.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
  235. -.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
  236. -.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
  237. -.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
  238. -.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
  239. -.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
  240. -.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
  241. -.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
  242. -.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
  243. -.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
  244. -.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
  245. -.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
  246. -.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
  247. -.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
  248. -.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
  249. -.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
  250. -.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
  251. -.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
  252. -.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
  253. -.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
  254. -.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
  255. -.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
  256. -.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
  257. -.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
  258. -.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
  259. -.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
  260. -.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
  261. -.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
  262. -.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
  263. -.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
  264. -.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
  265. -.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
  266. -.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
  267. -.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
  268. -.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
  269. -.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
  270. -.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
  271. -.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
  272. -.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
  273. -.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
  274. -.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
  275. -.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
  276. -.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
  277. -.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
  278. -.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
  279. -.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
  280. -.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
  281. -.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
  282. -.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
  283. -.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
  284. -.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
  285. -.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
  286. -.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
  287. -.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
  288. -.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
  289. -.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
  290. -.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
  291. -.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
  292. -.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
  293. -.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
  294. -.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
  295. -.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
  296. -.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
  297. -.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
  298. -.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
  299. -.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
  300. -.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
  301. -.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
  302. -.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
  303. -.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
  304. -.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
  305. -.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
  306. -.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
  307. -.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
  308. -.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
  309. -.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
  310. -.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
  311. -.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
  312. -.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
  313. -.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
  314. -.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
  315. -.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
  316. -.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
  317. -.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
  318. -.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
  319. -.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
  320. -.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
  321. -.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
  322. -.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
  323. -.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
  324. -.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
  325. -.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
  326. -.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
  327. -.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
  328. -.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
  329. -.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
  330. -.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
  331. -.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
  332. -.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
  333. -.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
  334. -.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
  335. -.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
  336. -.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
  337. -.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
  338. -.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
  339. -.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
  340. -.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
  341. -.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
  342. -.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
  343. -.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
  344. -.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
  345. -.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
  346. -.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
  347. -.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
  348. -.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
  349. -.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
  350. -.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
  351. -.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
  352. -.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
  353. -.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
  354. -.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
  355. -.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
  356. -.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
  357. -.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
  358. -.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
  359. -.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
  360. -.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
  361. -.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
  362. -.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
  363. -.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
  364. -.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
  365. -.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
  366. -.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
  367. -.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
  368. -.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
  369. -.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
  370. -.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
  371. -.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
  372. -.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
  373. -.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
  374. -.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
  375. -.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
  376. -.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
  377. -.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
  378. -.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
  379. -.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
  380. -.*Error: illegal operands `vlxseg2ei8.v v2,\(a0\),v2'
  381. -.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v2,v0.t'
  382. -.*Error: illegal operands `vsxseg2ei8.v v2,\(a0\),v2'
  383. -.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v2,v0.t'
  384. -.*Error: illegal operands `vlxseg3ei8.v v2,\(a0\),v2'
  385. -.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v2,v0.t'
  386. -.*Error: illegal operands `vsxseg3ei8.v v2,\(a0\),v2'
  387. -.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v2,v0.t'
  388. -.*Error: illegal operands `vlxseg4ei8.v v2,\(a0\),v2'
  389. -.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v2,v0.t'
  390. -.*Error: illegal operands `vsxseg4ei8.v v2,\(a0\),v2'
  391. -.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v2,v0.t'
  392. -.*Error: illegal operands `vlxseg5ei8.v v2,\(a0\),v2'
  393. -.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v2,v0.t'
  394. -.*Error: illegal operands `vsxseg5ei8.v v2,\(a0\),v2'
  395. -.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v2,v0.t'
  396. -.*Error: illegal operands `vlxseg6ei8.v v2,\(a0\),v2'
  397. -.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v2,v0.t'
  398. -.*Error: illegal operands `vsxseg6ei8.v v2,\(a0\),v2'
  399. -.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v2,v0.t'
  400. -.*Error: illegal operands `vlxseg7ei8.v v2,\(a0\),v2'
  401. -.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v2,v0.t'
  402. -.*Error: illegal operands `vsxseg7ei8.v v2,\(a0\),v2'
  403. -.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v2,v0.t'
  404. -.*Error: illegal operands `vlxseg8ei8.v v2,\(a0\),v2'
  405. -.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v2,v0.t'
  406. -.*Error: illegal operands `vsxseg8ei8.v v2,\(a0\),v2'
  407. -.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v2,v0.t'
  408. -.*Error: illegal operands `vlxseg2ei16.v v2,\(a0\),v2'
  409. -.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v2,v0.t'
  410. -.*Error: illegal operands `vsxseg2ei16.v v2,\(a0\),v2'
  411. -.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v2,v0.t'
  412. -.*Error: illegal operands `vlxseg3ei16.v v2,\(a0\),v2'
  413. -.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v2,v0.t'
  414. -.*Error: illegal operands `vsxseg3ei16.v v2,\(a0\),v2'
  415. -.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v2,v0.t'
  416. -.*Error: illegal operands `vlxseg4ei16.v v2,\(a0\),v2'
  417. -.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v2,v0.t'
  418. -.*Error: illegal operands `vsxseg4ei16.v v2,\(a0\),v2'
  419. -.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v2,v0.t'
  420. -.*Error: illegal operands `vlxseg5ei16.v v2,\(a0\),v2'
  421. -.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v2,v0.t'
  422. -.*Error: illegal operands `vsxseg5ei16.v v2,\(a0\),v2'
  423. -.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v2,v0.t'
  424. -.*Error: illegal operands `vlxseg6ei16.v v2,\(a0\),v2'
  425. -.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v2,v0.t'
  426. -.*Error: illegal operands `vsxseg6ei16.v v2,\(a0\),v2'
  427. -.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v2,v0.t'
  428. -.*Error: illegal operands `vlxseg7ei16.v v2,\(a0\),v2'
  429. -.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v2,v0.t'
  430. -.*Error: illegal operands `vsxseg7ei16.v v2,\(a0\),v2'
  431. -.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v2,v0.t'
  432. -.*Error: illegal operands `vlxseg8ei16.v v2,\(a0\),v2'
  433. -.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v2,v0.t'
  434. -.*Error: illegal operands `vsxseg8ei16.v v2,\(a0\),v2'
  435. -.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v2,v0.t'
  436. -.*Error: illegal operands `vlxseg2ei32.v v2,\(a0\),v2'
  437. -.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v2,v0.t'
  438. -.*Error: illegal operands `vsxseg2ei32.v v2,\(a0\),v2'
  439. -.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v2,v0.t'
  440. -.*Error: illegal operands `vlxseg3ei32.v v2,\(a0\),v2'
  441. -.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v2,v0.t'
  442. -.*Error: illegal operands `vsxseg3ei32.v v2,\(a0\),v2'
  443. -.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v2,v0.t'
  444. -.*Error: illegal operands `vlxseg4ei32.v v2,\(a0\),v2'
  445. -.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v2,v0.t'
  446. -.*Error: illegal operands `vsxseg4ei32.v v2,\(a0\),v2'
  447. -.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v2,v0.t'
  448. -.*Error: illegal operands `vlxseg5ei32.v v2,\(a0\),v2'
  449. -.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v2,v0.t'
  450. -.*Error: illegal operands `vsxseg5ei32.v v2,\(a0\),v2'
  451. -.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v2,v0.t'
  452. -.*Error: illegal operands `vlxseg6ei32.v v2,\(a0\),v2'
  453. -.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v2,v0.t'
  454. -.*Error: illegal operands `vsxseg6ei32.v v2,\(a0\),v2'
  455. -.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v2,v0.t'
  456. -.*Error: illegal operands `vlxseg7ei32.v v2,\(a0\),v2'
  457. -.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v2,v0.t'
  458. -.*Error: illegal operands `vsxseg7ei32.v v2,\(a0\),v2'
  459. -.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v2,v0.t'
  460. -.*Error: illegal operands `vlxseg8ei32.v v2,\(a0\),v2'
  461. -.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v2,v0.t'
  462. -.*Error: illegal operands `vsxseg8ei32.v v2,\(a0\),v2'
  463. -.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v2,v0.t'
  464. -.*Error: illegal operands `vlxseg2ei64.v v2,\(a0\),v2'
  465. -.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v2,v0.t'
  466. -.*Error: illegal operands `vsxseg2ei64.v v2,\(a0\),v2'
  467. -.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v2,v0.t'
  468. -.*Error: illegal operands `vlxseg3ei64.v v2,\(a0\),v2'
  469. -.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v2,v0.t'
  470. -.*Error: illegal operands `vsxseg3ei64.v v2,\(a0\),v2'
  471. -.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v2,v0.t'
  472. -.*Error: illegal operands `vlxseg4ei64.v v2,\(a0\),v2'
  473. -.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v2,v0.t'
  474. -.*Error: illegal operands `vsxseg4ei64.v v2,\(a0\),v2'
  475. -.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v2,v0.t'
  476. -.*Error: illegal operands `vlxseg5ei64.v v2,\(a0\),v2'
  477. -.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v2,v0.t'
  478. -.*Error: illegal operands `vsxseg5ei64.v v2,\(a0\),v2'
  479. -.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v2,v0.t'
  480. -.*Error: illegal operands `vlxseg6ei64.v v2,\(a0\),v2'
  481. -.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v2,v0.t'
  482. -.*Error: illegal operands `vsxseg6ei64.v v2,\(a0\),v2'
  483. -.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v2,v0.t'
  484. -.*Error: illegal operands `vlxseg7ei64.v v2,\(a0\),v2'
  485. -.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v2,v0.t'
  486. -.*Error: illegal operands `vsxseg7ei64.v v2,\(a0\),v2'
  487. -.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v2,v0.t'
  488. -.*Error: illegal operands `vlxseg8ei64.v v2,\(a0\),v2'
  489. -.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v2,v0.t'
  490. -.*Error: illegal operands `vsxseg8ei64.v v2,\(a0\),v2'
  491. -.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v2,v0.t'
  492. -.*Error: illegal operands `vlxseg2ei128.v v2,\(a0\),v2'
  493. -.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v2,v0.t'
  494. -.*Error: illegal operands `vsxseg2ei128.v v2,\(a0\),v2'
  495. -.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v2,v0.t'
  496. -.*Error: illegal operands `vlxseg3ei128.v v2,\(a0\),v2'
  497. -.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v2,v0.t'
  498. -.*Error: illegal operands `vsxseg3ei128.v v2,\(a0\),v2'
  499. -.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v2,v0.t'
  500. -.*Error: illegal operands `vlxseg4ei128.v v2,\(a0\),v2'
  501. -.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v2,v0.t'
  502. -.*Error: illegal operands `vsxseg4ei128.v v2,\(a0\),v2'
  503. -.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v2,v0.t'
  504. -.*Error: illegal operands `vlxseg5ei128.v v2,\(a0\),v2'
  505. -.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v2,v0.t'
  506. -.*Error: illegal operands `vsxseg5ei128.v v2,\(a0\),v2'
  507. -.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v2,v0.t'
  508. -.*Error: illegal operands `vlxseg6ei128.v v2,\(a0\),v2'
  509. -.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v2,v0.t'
  510. -.*Error: illegal operands `vsxseg6ei128.v v2,\(a0\),v2'
  511. -.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v2,v0.t'
  512. -.*Error: illegal operands `vlxseg7ei128.v v2,\(a0\),v2'
  513. -.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v2,v0.t'
  514. -.*Error: illegal operands `vsxseg7ei128.v v2,\(a0\),v2'
  515. -.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v2,v0.t'
  516. -.*Error: illegal operands `vlxseg8ei128.v v2,\(a0\),v2'
  517. -.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v2,v0.t'
  518. -.*Error: illegal operands `vsxseg8ei128.v v2,\(a0\),v2'
  519. -.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v2,v0.t'
  520. -.*Error: illegal operands `vlxseg2ei256.v v2,\(a0\),v2'
  521. -.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v2,v0.t'
  522. -.*Error: illegal operands `vsxseg2ei256.v v2,\(a0\),v2'
  523. -.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v2,v0.t'
  524. -.*Error: illegal operands `vlxseg3ei256.v v2,\(a0\),v2'
  525. -.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v2,v0.t'
  526. -.*Error: illegal operands `vsxseg3ei256.v v2,\(a0\),v2'
  527. -.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v2,v0.t'
  528. -.*Error: illegal operands `vlxseg4ei256.v v2,\(a0\),v2'
  529. -.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v2,v0.t'
  530. -.*Error: illegal operands `vsxseg4ei256.v v2,\(a0\),v2'
  531. -.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v2,v0.t'
  532. -.*Error: illegal operands `vlxseg5ei256.v v2,\(a0\),v2'
  533. -.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v2,v0.t'
  534. -.*Error: illegal operands `vsxseg5ei256.v v2,\(a0\),v2'
  535. -.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v2,v0.t'
  536. -.*Error: illegal operands `vlxseg6ei256.v v2,\(a0\),v2'
  537. -.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v2,v0.t'
  538. -.*Error: illegal operands `vsxseg6ei256.v v2,\(a0\),v2'
  539. -.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v2,v0.t'
  540. -.*Error: illegal operands `vlxseg7ei256.v v2,\(a0\),v2'
  541. -.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v2,v0.t'
  542. -.*Error: illegal operands `vsxseg7ei256.v v2,\(a0\),v2'
  543. -.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v2,v0.t'
  544. -.*Error: illegal operands `vlxseg8ei256.v v2,\(a0\),v2'
  545. -.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v2,v0.t'
  546. -.*Error: illegal operands `vsxseg8ei256.v v2,\(a0\),v2'
  547. -.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v2,v0.t'
  548. -.*Error: illegal operands `vlxseg2ei512.v v2,\(a0\),v2'
  549. -.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v2,v0.t'
  550. -.*Error: illegal operands `vsxseg2ei512.v v2,\(a0\),v2'
  551. -.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v2,v0.t'
  552. -.*Error: illegal operands `vlxseg3ei512.v v2,\(a0\),v2'
  553. -.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v2,v0.t'
  554. -.*Error: illegal operands `vsxseg3ei512.v v2,\(a0\),v2'
  555. -.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v2,v0.t'
  556. -.*Error: illegal operands `vlxseg4ei512.v v2,\(a0\),v2'
  557. -.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v2,v0.t'
  558. -.*Error: illegal operands `vsxseg4ei512.v v2,\(a0\),v2'
  559. -.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v2,v0.t'
  560. -.*Error: illegal operands `vlxseg5ei512.v v2,\(a0\),v2'
  561. -.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v2,v0.t'
  562. -.*Error: illegal operands `vsxseg5ei512.v v2,\(a0\),v2'
  563. -.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v2,v0.t'
  564. -.*Error: illegal operands `vlxseg6ei512.v v2,\(a0\),v2'
  565. -.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v2,v0.t'
  566. -.*Error: illegal operands `vsxseg6ei512.v v2,\(a0\),v2'
  567. -.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v2,v0.t'
  568. -.*Error: illegal operands `vlxseg7ei512.v v2,\(a0\),v2'
  569. -.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v2,v0.t'
  570. -.*Error: illegal operands `vsxseg7ei512.v v2,\(a0\),v2'
  571. -.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v2,v0.t'
  572. -.*Error: illegal operands `vlxseg8ei512.v v2,\(a0\),v2'
  573. -.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v2,v0.t'
  574. -.*Error: illegal operands `vsxseg8ei512.v v2,\(a0\),v2'
  575. -.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v2,v0.t'
  576. -.*Error: illegal operands `vlxseg2ei1024.v v2,\(a0\),v2'
  577. -.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v2,v0.t'
  578. -.*Error: illegal operands `vsxseg2ei1024.v v2,\(a0\),v2'
  579. -.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v2,v0.t'
  580. -.*Error: illegal operands `vlxseg3ei1024.v v2,\(a0\),v2'
  581. -.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v2,v0.t'
  582. -.*Error: illegal operands `vsxseg3ei1024.v v2,\(a0\),v2'
  583. -.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v2,v0.t'
  584. -.*Error: illegal operands `vlxseg4ei1024.v v2,\(a0\),v2'
  585. -.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v2,v0.t'
  586. -.*Error: illegal operands `vsxseg4ei1024.v v2,\(a0\),v2'
  587. -.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v2,v0.t'
  588. -.*Error: illegal operands `vlxseg5ei1024.v v2,\(a0\),v2'
  589. -.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v2,v0.t'
  590. -.*Error: illegal operands `vsxseg5ei1024.v v2,\(a0\),v2'
  591. -.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v2,v0.t'
  592. -.*Error: illegal operands `vlxseg6ei1024.v v2,\(a0\),v2'
  593. -.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v2,v0.t'
  594. -.*Error: illegal operands `vsxseg6ei1024.v v2,\(a0\),v2'
  595. -.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v2,v0.t'
  596. -.*Error: illegal operands `vlxseg7ei1024.v v2,\(a0\),v2'
  597. -.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v2,v0.t'
  598. -.*Error: illegal operands `vsxseg7ei1024.v v2,\(a0\),v2'
  599. -.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v2,v0.t'
  600. -.*Error: illegal operands `vlxseg8ei1024.v v2,\(a0\),v2'
  601. -.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v2,v0.t'
  602. -.*Error: illegal operands `vsxseg8ei1024.v v2,\(a0\),v2'
  603. -.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v2,v0.t'
  604. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.s b/gas/testsuite/gas/riscv/vector-insns-fail-01.s
  605. deleted file mode 100644
  606. index 4c1a913f2d..0000000000
  607. --- a/gas/testsuite/gas/riscv/vector-insns-fail-01.s
  608. +++ /dev/null
  609. @@ -1,1037 +0,0 @@
  610. -# Vector Unit-Stride Segment Loads and Stores
  611. -
  612. - vlseg2e8.v v0, (a0), v0.t # vd overlap vm
  613. - vlseg2e8.v v4, (a0), v0.t # OK
  614. - vsseg2e8.v v0, (a0), v0.t # OK
  615. - vsseg2e8.v v4, (a0), v0.t # OK
  616. - vlseg2e8ff.v v0, (a0), v0.t # vd overlap vm
  617. - vlseg2e8ff.v v4, (a0), v0.t # OK
  618. - vlseg3e8.v v0, (a0), v0.t # vd overlap vm
  619. - vlseg3e8.v v4, (a0), v0.t # OK
  620. - vsseg3e8.v v0, (a0), v0.t # OK
  621. - vsseg3e8.v v4, (a0), v0.t # OK
  622. - vlseg3e8ff.v v0, (a0), v0.t # vd overlap vm
  623. - vlseg3e8ff.v v4, (a0), v0.t # OK
  624. - vlseg4e8.v v0, (a0), v0.t # vd overlap vm
  625. - vlseg4e8.v v4, (a0), v0.t # OK
  626. - vsseg4e8.v v0, (a0), v0.t # OK
  627. - vsseg4e8.v v4, (a0), v0.t # OK
  628. - vlseg4e8ff.v v0, (a0), v0.t # vd overlap vm
  629. - vlseg4e8ff.v v4, (a0), v0.t # OK
  630. - vlseg5e8.v v0, (a0), v0.t # vd overlap vm
  631. - vlseg5e8.v v4, (a0), v0.t # OK
  632. - vsseg5e8.v v0, (a0), v0.t # OK
  633. - vsseg5e8.v v4, (a0), v0.t # OK
  634. - vlseg5e8ff.v v0, (a0), v0.t # vd overlap vm
  635. - vlseg5e8ff.v v4, (a0), v0.t # OK
  636. - vlseg6e8.v v0, (a0), v0.t # vd overlap vm
  637. - vlseg6e8.v v4, (a0), v0.t # OK
  638. - vsseg6e8.v v0, (a0), v0.t # OK
  639. - vsseg6e8.v v4, (a0), v0.t # OK
  640. - vlseg6e8ff.v v0, (a0), v0.t # vd overlap vm
  641. - vlseg6e8ff.v v4, (a0), v0.t # OK
  642. - vlseg7e8.v v0, (a0), v0.t # vd overlap vm
  643. - vlseg7e8.v v4, (a0), v0.t # OK
  644. - vsseg7e8.v v0, (a0), v0.t # OK
  645. - vsseg7e8.v v4, (a0), v0.t # OK
  646. - vlseg7e8ff.v v0, (a0), v0.t # vd overlap vm
  647. - vlseg7e8ff.v v4, (a0), v0.t # OK
  648. - vlseg8e8.v v0, (a0), v0.t # vd overlap vm
  649. - vlseg8e8.v v4, (a0), v0.t # OK
  650. - vsseg8e8.v v0, (a0), v0.t # OK
  651. - vsseg8e8.v v4, (a0), v0.t # OK
  652. - vlseg8e8ff.v v0, (a0), v0.t # vd overlap vm
  653. - vlseg8e8ff.v v4, (a0), v0.t # OK
  654. -
  655. - vlseg2e16.v v0, (a0), v0.t # vd overlap vm
  656. - vlseg2e16.v v4, (a0), v0.t # OK
  657. - vsseg2e16.v v0, (a0), v0.t # OK
  658. - vsseg2e16.v v4, (a0), v0.t # OK
  659. - vlseg2e16ff.v v0, (a0), v0.t # vd overlap vm
  660. - vlseg2e16ff.v v4, (a0), v0.t # OK
  661. - vlseg3e16.v v0, (a0), v0.t # vd overlap vm
  662. - vlseg3e16.v v4, (a0), v0.t # OK
  663. - vsseg3e16.v v0, (a0), v0.t # OK
  664. - vsseg3e16.v v4, (a0), v0.t # OK
  665. - vlseg3e16ff.v v0, (a0), v0.t # vd overlap vm
  666. - vlseg3e16ff.v v4, (a0), v0.t # OK
  667. - vlseg4e16.v v0, (a0), v0.t # vd overlap vm
  668. - vlseg4e16.v v4, (a0), v0.t # OK
  669. - vsseg4e16.v v0, (a0), v0.t # OK
  670. - vsseg4e16.v v4, (a0), v0.t # OK
  671. - vlseg4e16ff.v v0, (a0), v0.t # vd overlap vm
  672. - vlseg4e16ff.v v4, (a0), v0.t # OK
  673. - vlseg5e16.v v0, (a0), v0.t # vd overlap vm
  674. - vlseg5e16.v v4, (a0), v0.t # OK
  675. - vsseg5e16.v v0, (a0), v0.t # OK
  676. - vsseg5e16.v v4, (a0), v0.t # OK
  677. - vlseg5e16ff.v v0, (a0), v0.t # vd overlap vm
  678. - vlseg5e16ff.v v4, (a0), v0.t # OK
  679. - vlseg6e16.v v0, (a0), v0.t # vd overlap vm
  680. - vlseg6e16.v v4, (a0), v0.t # OK
  681. - vsseg6e16.v v0, (a0), v0.t # OK
  682. - vsseg6e16.v v4, (a0), v0.t # OK
  683. - vlseg6e16ff.v v0, (a0), v0.t # vd overlap vm
  684. - vlseg6e16ff.v v4, (a0), v0.t # OK
  685. - vlseg7e16.v v0, (a0), v0.t # vd overlap vm
  686. - vlseg7e16.v v4, (a0), v0.t # OK
  687. - vsseg7e16.v v0, (a0), v0.t # OK
  688. - vsseg7e16.v v4, (a0), v0.t # OK
  689. - vlseg7e16ff.v v0, (a0), v0.t # vd overlap vm
  690. - vlseg7e16ff.v v4, (a0), v0.t # OK
  691. - vlseg8e16.v v0, (a0), v0.t # vd overlap vm
  692. - vlseg8e16.v v4, (a0), v0.t # OK
  693. - vsseg8e16.v v0, (a0), v0.t # OK
  694. - vsseg8e16.v v4, (a0), v0.t # OK
  695. - vlseg8e16ff.v v0, (a0), v0.t # vd overlap vm
  696. - vlseg8e16ff.v v4, (a0), v0.t # OK
  697. -
  698. - vlseg2e32.v v0, (a0), v0.t # vd overlap vm
  699. - vlseg2e32.v v4, (a0), v0.t # OK
  700. - vsseg2e32.v v0, (a0), v0.t # OK
  701. - vsseg2e32.v v4, (a0), v0.t # OK
  702. - vlseg2e32ff.v v0, (a0), v0.t # vd overlap vm
  703. - vlseg2e32ff.v v4, (a0), v0.t # OK
  704. - vlseg3e32.v v0, (a0), v0.t # vd overlap vm
  705. - vlseg3e32.v v4, (a0), v0.t # OK
  706. - vsseg3e32.v v0, (a0), v0.t # OK
  707. - vsseg3e32.v v4, (a0), v0.t # OK
  708. - vlseg3e32ff.v v0, (a0), v0.t # vd overlap vm
  709. - vlseg3e32ff.v v4, (a0), v0.t # OK
  710. - vlseg4e32.v v0, (a0), v0.t # vd overlap vm
  711. - vlseg4e32.v v4, (a0), v0.t # OK
  712. - vsseg4e32.v v0, (a0), v0.t # OK
  713. - vsseg4e32.v v4, (a0), v0.t # OK
  714. - vlseg4e32ff.v v0, (a0), v0.t # vd overlap vm
  715. - vlseg4e32ff.v v4, (a0), v0.t # OK
  716. - vlseg5e32.v v0, (a0), v0.t # vd overlap vm
  717. - vlseg5e32.v v4, (a0), v0.t # OK
  718. - vsseg5e32.v v0, (a0), v0.t # OK
  719. - vsseg5e32.v v4, (a0), v0.t # OK
  720. - vlseg5e32ff.v v0, (a0), v0.t # vd overlap vm
  721. - vlseg5e32ff.v v4, (a0), v0.t # OK
  722. - vlseg6e32.v v0, (a0), v0.t # vd overlap vm
  723. - vlseg6e32.v v4, (a0), v0.t # OK
  724. - vsseg6e32.v v0, (a0), v0.t # OK
  725. - vsseg6e32.v v4, (a0), v0.t # OK
  726. - vlseg6e32ff.v v0, (a0), v0.t # vd overlap vm
  727. - vlseg6e32ff.v v4, (a0), v0.t # OK
  728. - vlseg7e32.v v0, (a0), v0.t # vd overlap vm
  729. - vlseg7e32.v v4, (a0), v0.t # OK
  730. - vsseg7e32.v v0, (a0), v0.t # OK
  731. - vsseg7e32.v v4, (a0), v0.t # OK
  732. - vlseg7e32ff.v v0, (a0), v0.t # vd overlap vm
  733. - vlseg7e32ff.v v4, (a0), v0.t # OK
  734. - vlseg8e32.v v0, (a0), v0.t # vd overlap vm
  735. - vlseg8e32.v v4, (a0), v0.t # OK
  736. - vsseg8e32.v v0, (a0), v0.t # OK
  737. - vsseg8e32.v v4, (a0), v0.t # OK
  738. - vlseg8e32ff.v v0, (a0), v0.t # vd overlap vm
  739. - vlseg8e32ff.v v4, (a0), v0.t # OK
  740. -
  741. - vlseg2e64.v v0, (a0), v0.t # vd overlap vm
  742. - vlseg2e64.v v4, (a0), v0.t # OK
  743. - vsseg2e64.v v0, (a0), v0.t # OK
  744. - vsseg2e64.v v4, (a0), v0.t # OK
  745. - vlseg2e64ff.v v0, (a0), v0.t # vd overlap vm
  746. - vlseg2e64ff.v v4, (a0), v0.t # OK
  747. - vlseg3e64.v v0, (a0), v0.t # vd overlap vm
  748. - vlseg3e64.v v4, (a0), v0.t # OK
  749. - vsseg3e64.v v0, (a0), v0.t # OK
  750. - vsseg3e64.v v4, (a0), v0.t # OK
  751. - vlseg3e64ff.v v0, (a0), v0.t # vd overlap vm
  752. - vlseg3e64ff.v v4, (a0), v0.t # OK
  753. - vlseg4e64.v v0, (a0), v0.t # vd overlap vm
  754. - vlseg4e64.v v4, (a0), v0.t # OK
  755. - vsseg4e64.v v0, (a0), v0.t # OK
  756. - vsseg4e64.v v4, (a0), v0.t # OK
  757. - vlseg4e64ff.v v0, (a0), v0.t # vd overlap vm
  758. - vlseg4e64ff.v v4, (a0), v0.t # OK
  759. - vlseg5e64.v v0, (a0), v0.t # vd overlap vm
  760. - vlseg5e64.v v4, (a0), v0.t # OK
  761. - vsseg5e64.v v0, (a0), v0.t # OK
  762. - vsseg5e64.v v4, (a0), v0.t # OK
  763. - vlseg5e64ff.v v0, (a0), v0.t # vd overlap vm
  764. - vlseg5e64ff.v v4, (a0), v0.t # OK
  765. - vlseg6e64.v v0, (a0), v0.t # vd overlap vm
  766. - vlseg6e64.v v4, (a0), v0.t # OK
  767. - vsseg6e64.v v0, (a0), v0.t # OK
  768. - vsseg6e64.v v4, (a0), v0.t # OK
  769. - vlseg6e64ff.v v0, (a0), v0.t # vd overlap vm
  770. - vlseg6e64ff.v v4, (a0), v0.t # OK
  771. - vlseg7e64.v v0, (a0), v0.t # vd overlap vm
  772. - vlseg7e64.v v4, (a0), v0.t # OK
  773. - vsseg7e64.v v0, (a0), v0.t # OK
  774. - vsseg7e64.v v4, (a0), v0.t # OK
  775. - vlseg7e64ff.v v0, (a0), v0.t # vd overlap vm
  776. - vlseg7e64ff.v v4, (a0), v0.t # OK
  777. - vlseg8e64.v v0, (a0), v0.t # vd overlap vm
  778. - vlseg8e64.v v4, (a0), v0.t # OK
  779. - vsseg8e64.v v0, (a0), v0.t # OK
  780. - vsseg8e64.v v4, (a0), v0.t # OK
  781. - vlseg8e64ff.v v0, (a0), v0.t # vd overlap vm
  782. - vlseg8e64ff.v v4, (a0), v0.t # OK
  783. -
  784. - vlseg2e128.v v0, (a0), v0.t # vd overlap vm
  785. - vlseg2e128.v v4, (a0), v0.t # OK
  786. - vsseg2e128.v v0, (a0), v0.t # OK
  787. - vsseg2e128.v v4, (a0), v0.t # OK
  788. - vlseg2e128ff.v v0, (a0), v0.t # vd overlap vm
  789. - vlseg2e128ff.v v4, (a0), v0.t # OK
  790. - vlseg3e128.v v0, (a0), v0.t # vd overlap vm
  791. - vlseg3e128.v v4, (a0), v0.t # OK
  792. - vsseg3e128.v v0, (a0), v0.t # OK
  793. - vsseg3e128.v v4, (a0), v0.t # OK
  794. - vlseg3e128ff.v v0, (a0), v0.t # vd overlap vm
  795. - vlseg3e128ff.v v4, (a0), v0.t # OK
  796. - vlseg4e128.v v0, (a0), v0.t # vd overlap vm
  797. - vlseg4e128.v v4, (a0), v0.t # OK
  798. - vsseg4e128.v v0, (a0), v0.t # OK
  799. - vsseg4e128.v v4, (a0), v0.t # OK
  800. - vlseg4e128ff.v v0, (a0), v0.t # vd overlap vm
  801. - vlseg4e128ff.v v4, (a0), v0.t # OK
  802. - vlseg5e128.v v0, (a0), v0.t # vd overlap vm
  803. - vlseg5e128.v v4, (a0), v0.t # OK
  804. - vsseg5e128.v v0, (a0), v0.t # OK
  805. - vsseg5e128.v v4, (a0), v0.t # OK
  806. - vlseg5e128ff.v v0, (a0), v0.t # vd overlap vm
  807. - vlseg5e128ff.v v4, (a0), v0.t # OK
  808. - vlseg6e128.v v0, (a0), v0.t # vd overlap vm
  809. - vlseg6e128.v v4, (a0), v0.t # OK
  810. - vsseg6e128.v v0, (a0), v0.t # OK
  811. - vsseg6e128.v v4, (a0), v0.t # OK
  812. - vlseg6e128ff.v v0, (a0), v0.t # vd overlap vm
  813. - vlseg6e128ff.v v4, (a0), v0.t # OK
  814. - vlseg7e128.v v0, (a0), v0.t # vd overlap vm
  815. - vlseg7e128.v v4, (a0), v0.t # OK
  816. - vsseg7e128.v v0, (a0), v0.t # OK
  817. - vsseg7e128.v v4, (a0), v0.t # OK
  818. - vlseg7e128ff.v v0, (a0), v0.t # vd overlap vm
  819. - vlseg7e128ff.v v4, (a0), v0.t # OK
  820. - vlseg8e128.v v0, (a0), v0.t # vd overlap vm
  821. - vlseg8e128.v v4, (a0), v0.t # OK
  822. - vsseg8e128.v v0, (a0), v0.t # OK
  823. - vsseg8e128.v v4, (a0), v0.t # OK
  824. - vlseg8e128ff.v v0, (a0), v0.t # vd overlap vm
  825. - vlseg8e128ff.v v4, (a0), v0.t # OK
  826. -
  827. - vlseg2e256.v v0, (a0), v0.t # vd overlap vm
  828. - vlseg2e256.v v4, (a0), v0.t # OK
  829. - vsseg2e256.v v0, (a0), v0.t # OK
  830. - vsseg2e256.v v4, (a0), v0.t # OK
  831. - vlseg2e256ff.v v0, (a0), v0.t # vd overlap vm
  832. - vlseg2e256ff.v v4, (a0), v0.t # OK
  833. - vlseg3e256.v v0, (a0), v0.t # vd overlap vm
  834. - vlseg3e256.v v4, (a0), v0.t # OK
  835. - vsseg3e256.v v0, (a0), v0.t # OK
  836. - vsseg3e256.v v4, (a0), v0.t # OK
  837. - vlseg3e256ff.v v0, (a0), v0.t # vd overlap vm
  838. - vlseg3e256ff.v v4, (a0), v0.t # OK
  839. - vlseg4e256.v v0, (a0), v0.t # vd overlap vm
  840. - vlseg4e256.v v4, (a0), v0.t # OK
  841. - vsseg4e256.v v0, (a0), v0.t # OK
  842. - vsseg4e256.v v4, (a0), v0.t # OK
  843. - vlseg4e256ff.v v0, (a0), v0.t # vd overlap vm
  844. - vlseg4e256ff.v v4, (a0), v0.t # OK
  845. - vlseg5e256.v v0, (a0), v0.t # vd overlap vm
  846. - vlseg5e256.v v4, (a0), v0.t # OK
  847. - vsseg5e256.v v0, (a0), v0.t # OK
  848. - vsseg5e256.v v4, (a0), v0.t # OK
  849. - vlseg5e256ff.v v0, (a0), v0.t # vd overlap vm
  850. - vlseg5e256ff.v v4, (a0), v0.t # OK
  851. - vlseg6e256.v v0, (a0), v0.t # vd overlap vm
  852. - vlseg6e256.v v4, (a0), v0.t # OK
  853. - vsseg6e256.v v0, (a0), v0.t # OK
  854. - vsseg6e256.v v4, (a0), v0.t # OK
  855. - vlseg6e256ff.v v0, (a0), v0.t # vd overlap vm
  856. - vlseg6e256ff.v v4, (a0), v0.t # OK
  857. - vlseg7e256.v v0, (a0), v0.t # vd overlap vm
  858. - vlseg7e256.v v4, (a0), v0.t # OK
  859. - vsseg7e256.v v0, (a0), v0.t # OK
  860. - vsseg7e256.v v4, (a0), v0.t # OK
  861. - vlseg7e256ff.v v0, (a0), v0.t # vd overlap vm
  862. - vlseg7e256ff.v v4, (a0), v0.t # OK
  863. - vlseg8e256.v v0, (a0), v0.t # vd overlap vm
  864. - vlseg8e256.v v4, (a0), v0.t # OK
  865. - vsseg8e256.v v0, (a0), v0.t # OK
  866. - vsseg8e256.v v4, (a0), v0.t # OK
  867. - vlseg8e256ff.v v0, (a0), v0.t # vd overlap vm
  868. - vlseg8e256ff.v v4, (a0), v0.t # OK
  869. -
  870. - vlseg2e512.v v0, (a0), v0.t # vd overlap vm
  871. - vlseg2e512.v v4, (a0), v0.t # OK
  872. - vsseg2e512.v v0, (a0), v0.t # OK
  873. - vsseg2e512.v v4, (a0), v0.t # OK
  874. - vlseg2e512ff.v v0, (a0), v0.t # vd overlap vm
  875. - vlseg2e512ff.v v4, (a0), v0.t # OK
  876. - vlseg3e512.v v0, (a0), v0.t # vd overlap vm
  877. - vlseg3e512.v v4, (a0), v0.t # OK
  878. - vsseg3e512.v v0, (a0), v0.t # OK
  879. - vsseg3e512.v v4, (a0), v0.t # OK
  880. - vlseg3e512ff.v v0, (a0), v0.t # vd overlap vm
  881. - vlseg3e512ff.v v4, (a0), v0.t # OK
  882. - vlseg4e512.v v0, (a0), v0.t # vd overlap vm
  883. - vlseg4e512.v v4, (a0), v0.t # OK
  884. - vsseg4e512.v v0, (a0), v0.t # OK
  885. - vsseg4e512.v v4, (a0), v0.t # OK
  886. - vlseg4e512ff.v v0, (a0), v0.t # vd overlap vm
  887. - vlseg4e512ff.v v4, (a0), v0.t # OK
  888. - vlseg5e512.v v0, (a0), v0.t # vd overlap vm
  889. - vlseg5e512.v v4, (a0), v0.t # OK
  890. - vsseg5e512.v v0, (a0), v0.t # OK
  891. - vsseg5e512.v v4, (a0), v0.t # OK
  892. - vlseg5e512ff.v v0, (a0), v0.t # vd overlap vm
  893. - vlseg5e512ff.v v4, (a0), v0.t # OK
  894. - vlseg6e512.v v0, (a0), v0.t # vd overlap vm
  895. - vlseg6e512.v v4, (a0), v0.t # OK
  896. - vsseg6e512.v v0, (a0), v0.t # OK
  897. - vsseg6e512.v v4, (a0), v0.t # OK
  898. - vlseg6e512ff.v v0, (a0), v0.t # vd overlap vm
  899. - vlseg6e512ff.v v4, (a0), v0.t # OK
  900. - vlseg7e512.v v0, (a0), v0.t # vd overlap vm
  901. - vlseg7e512.v v4, (a0), v0.t # OK
  902. - vsseg7e512.v v0, (a0), v0.t # OK
  903. - vsseg7e512.v v4, (a0), v0.t # OK
  904. - vlseg7e512ff.v v0, (a0), v0.t # vd overlap vm
  905. - vlseg7e512ff.v v4, (a0), v0.t # OK
  906. - vlseg8e512.v v0, (a0), v0.t # vd overlap vm
  907. - vlseg8e512.v v4, (a0), v0.t # OK
  908. - vsseg8e512.v v0, (a0), v0.t # OK
  909. - vsseg8e512.v v4, (a0), v0.t # OK
  910. - vlseg8e512ff.v v0, (a0), v0.t # vd overlap vm
  911. - vlseg8e512ff.v v4, (a0), v0.t # OK
  912. -
  913. - vlseg2e1024.v v0, (a0), v0.t # vd overlap vm
  914. - vlseg2e1024.v v4, (a0), v0.t # OK
  915. - vsseg2e1024.v v0, (a0), v0.t # OK
  916. - vsseg2e1024.v v4, (a0), v0.t # OK
  917. - vlseg2e1024ff.v v0, (a0), v0.t # vd overlap vm
  918. - vlseg2e1024ff.v v4, (a0), v0.t # OK
  919. - vlseg3e1024.v v0, (a0), v0.t # vd overlap vm
  920. - vlseg3e1024.v v4, (a0), v0.t # OK
  921. - vsseg3e1024.v v0, (a0), v0.t # OK
  922. - vsseg3e1024.v v4, (a0), v0.t # OK
  923. - vlseg3e1024ff.v v0, (a0), v0.t # vd overlap vm
  924. - vlseg3e1024ff.v v4, (a0), v0.t # OK
  925. - vlseg4e1024.v v0, (a0), v0.t # vd overlap vm
  926. - vlseg4e1024.v v4, (a0), v0.t # OK
  927. - vsseg4e1024.v v0, (a0), v0.t # OK
  928. - vsseg4e1024.v v4, (a0), v0.t # OK
  929. - vlseg4e1024ff.v v0, (a0), v0.t # vd overlap vm
  930. - vlseg4e1024ff.v v4, (a0), v0.t # OK
  931. - vlseg5e1024.v v0, (a0), v0.t # vd overlap vm
  932. - vlseg5e1024.v v4, (a0), v0.t # OK
  933. - vsseg5e1024.v v0, (a0), v0.t # OK
  934. - vsseg5e1024.v v4, (a0), v0.t # OK
  935. - vlseg5e1024ff.v v0, (a0), v0.t # vd overlap vm
  936. - vlseg5e1024ff.v v4, (a0), v0.t # OK
  937. - vlseg6e1024.v v0, (a0), v0.t # vd overlap vm
  938. - vlseg6e1024.v v4, (a0), v0.t # OK
  939. - vsseg6e1024.v v0, (a0), v0.t # OK
  940. - vsseg6e1024.v v4, (a0), v0.t # OK
  941. - vlseg6e1024ff.v v0, (a0), v0.t # vd overlap vm
  942. - vlseg6e1024ff.v v4, (a0), v0.t # OK
  943. - vlseg7e1024.v v0, (a0), v0.t # vd overlap vm
  944. - vlseg7e1024.v v4, (a0), v0.t # OK
  945. - vsseg7e1024.v v0, (a0), v0.t # OK
  946. - vsseg7e1024.v v4, (a0), v0.t # OK
  947. - vlseg7e1024ff.v v0, (a0), v0.t # vd overlap vm
  948. - vlseg7e1024ff.v v4, (a0), v0.t # OK
  949. - vlseg8e1024.v v0, (a0), v0.t # vd overlap vm
  950. - vlseg8e1024.v v4, (a0), v0.t # OK
  951. - vsseg8e1024.v v0, (a0), v0.t # OK
  952. - vsseg8e1024.v v4, (a0), v0.t # OK
  953. - vlseg8e1024ff.v v0, (a0), v0.t # vd overlap vm
  954. - vlseg8e1024ff.v v4, (a0), v0.t # OK
  955. -
  956. -# Vector Strided Segment Loads and Stores
  957. -
  958. - vlsseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
  959. - vlsseg2e8.v v4, (a0), a1, v0.t # OK
  960. - vssseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
  961. - vssseg2e8.v v4, (a0), a1, v0.t # OK
  962. - vlsseg3e8.v v0, (a0), a1, v0.t # vd overlap vm
  963. - vlsseg3e8.v v4, (a0), a1, v0.t # OK
  964. - vssseg3e8.v v0, (a0), a1, v0.t # vd overlap vm
  965. - vssseg3e8.v v4, (a0), a1, v0.t # OK
  966. - vlsseg4e8.v v0, (a0), a1, v0.t # vd overlap vm
  967. - vlsseg4e8.v v4, (a0), a1, v0.t # OK
  968. - vssseg4e8.v v0, (a0), a1, v0.t # vd overlap vm
  969. - vssseg4e8.v v4, (a0), a1, v0.t # OK
  970. - vlsseg5e8.v v0, (a0), a1, v0.t # vd overlap vm
  971. - vlsseg5e8.v v4, (a0), a1, v0.t # OK
  972. - vssseg5e8.v v0, (a0), a1, v0.t # vd overlap vm
  973. - vssseg5e8.v v4, (a0), a1, v0.t # OK
  974. - vlsseg6e8.v v0, (a0), a1, v0.t # vd overlap vm
  975. - vlsseg6e8.v v4, (a0), a1, v0.t # OK
  976. - vssseg6e8.v v0, (a0), a1, v0.t # vd overlap vm
  977. - vssseg6e8.v v4, (a0), a1, v0.t # OK
  978. - vlsseg7e8.v v0, (a0), a1, v0.t # vd overlap vm
  979. - vlsseg7e8.v v4, (a0), a1, v0.t # OK
  980. - vssseg7e8.v v0, (a0), a1, v0.t # vd overlap vm
  981. - vssseg7e8.v v4, (a0), a1, v0.t # OK
  982. - vlsseg8e8.v v0, (a0), a1, v0.t # vd overlap vm
  983. - vlsseg8e8.v v4, (a0), a1, v0.t # OK
  984. - vssseg8e8.v v0, (a0), a1, v0.t # vd overlap vm
  985. - vssseg8e8.v v4, (a0), a1, v0.t # OK
  986. -
  987. - vlsseg2e16.v v0, (a0), a1, v0.t # vd overlap vm
  988. - vlsseg2e16.v v4, (a0), a1, v0.t # OK
  989. - vssseg2e16.v v0, (a0), a1, v0.t # vd overlap vm
  990. - vssseg2e16.v v4, (a0), a1, v0.t # OK
  991. - vlsseg3e16.v v0, (a0), a1, v0.t # vd overlap vm
  992. - vlsseg3e16.v v4, (a0), a1, v0.t # OK
  993. - vssseg3e16.v v0, (a0), a1, v0.t # vd overlap vm
  994. - vssseg3e16.v v4, (a0), a1, v0.t # OK
  995. - vlsseg4e16.v v0, (a0), a1, v0.t # vd overlap vm
  996. - vlsseg4e16.v v4, (a0), a1, v0.t # OK
  997. - vssseg4e16.v v0, (a0), a1, v0.t # vd overlap vm
  998. - vssseg4e16.v v4, (a0), a1, v0.t # OK
  999. - vlsseg5e16.v v0, (a0), a1, v0.t # vd overlap vm
  1000. - vlsseg5e16.v v4, (a0), a1, v0.t # OK
  1001. - vssseg5e16.v v0, (a0), a1, v0.t # vd overlap vm
  1002. - vssseg5e16.v v4, (a0), a1, v0.t # OK
  1003. - vlsseg6e16.v v0, (a0), a1, v0.t # vd overlap vm
  1004. - vlsseg6e16.v v4, (a0), a1, v0.t # OK
  1005. - vssseg6e16.v v0, (a0), a1, v0.t # vd overlap vm
  1006. - vssseg6e16.v v4, (a0), a1, v0.t # OK
  1007. - vlsseg7e16.v v0, (a0), a1, v0.t # vd overlap vm
  1008. - vlsseg7e16.v v4, (a0), a1, v0.t # OK
  1009. - vssseg7e16.v v0, (a0), a1, v0.t # vd overlap vm
  1010. - vssseg7e16.v v4, (a0), a1, v0.t # OK
  1011. - vlsseg8e16.v v0, (a0), a1, v0.t # vd overlap vm
  1012. - vlsseg8e16.v v4, (a0), a1, v0.t # OK
  1013. - vssseg8e16.v v0, (a0), a1, v0.t # vd overlap vm
  1014. - vssseg8e16.v v4, (a0), a1, v0.t # OK
  1015. -
  1016. - vlsseg2e32.v v0, (a0), a1, v0.t # vd overlap vm
  1017. - vlsseg2e32.v v4, (a0), a1, v0.t # OK
  1018. - vssseg2e32.v v0, (a0), a1, v0.t # vd overlap vm
  1019. - vssseg2e32.v v4, (a0), a1, v0.t # OK
  1020. - vlsseg3e32.v v0, (a0), a1, v0.t # vd overlap vm
  1021. - vlsseg3e32.v v4, (a0), a1, v0.t # OK
  1022. - vssseg3e32.v v0, (a0), a1, v0.t # vd overlap vm
  1023. - vssseg3e32.v v4, (a0), a1, v0.t # OK
  1024. - vlsseg4e32.v v0, (a0), a1, v0.t # vd overlap vm
  1025. - vlsseg4e32.v v4, (a0), a1, v0.t # OK
  1026. - vssseg4e32.v v0, (a0), a1, v0.t # vd overlap vm
  1027. - vssseg4e32.v v4, (a0), a1, v0.t # OK
  1028. - vlsseg5e32.v v0, (a0), a1, v0.t # vd overlap vm
  1029. - vlsseg5e32.v v4, (a0), a1, v0.t # OK
  1030. - vssseg5e32.v v0, (a0), a1, v0.t # vd overlap vm
  1031. - vssseg5e32.v v4, (a0), a1, v0.t # OK
  1032. - vlsseg6e32.v v0, (a0), a1, v0.t # vd overlap vm
  1033. - vlsseg6e32.v v4, (a0), a1, v0.t # OK
  1034. - vssseg6e32.v v0, (a0), a1, v0.t # vd overlap vm
  1035. - vssseg6e32.v v4, (a0), a1, v0.t # OK
  1036. - vlsseg7e32.v v0, (a0), a1, v0.t # vd overlap vm
  1037. - vlsseg7e32.v v4, (a0), a1, v0.t # OK
  1038. - vssseg7e32.v v0, (a0), a1, v0.t # vd overlap vm
  1039. - vssseg7e32.v v4, (a0), a1, v0.t # OK
  1040. - vlsseg8e32.v v0, (a0), a1, v0.t # vd overlap vm
  1041. - vlsseg8e32.v v4, (a0), a1, v0.t # OK
  1042. - vssseg8e32.v v0, (a0), a1, v0.t # vd overlap vm
  1043. - vssseg8e32.v v4, (a0), a1, v0.t # OK
  1044. -
  1045. - vlsseg2e64.v v0, (a0), a1, v0.t # vd overlap vm
  1046. - vlsseg2e64.v v4, (a0), a1, v0.t # OK
  1047. - vssseg2e64.v v0, (a0), a1, v0.t # vd overlap vm
  1048. - vssseg2e64.v v4, (a0), a1, v0.t # OK
  1049. - vlsseg3e64.v v0, (a0), a1, v0.t # vd overlap vm
  1050. - vlsseg3e64.v v4, (a0), a1, v0.t # OK
  1051. - vssseg3e64.v v0, (a0), a1, v0.t # vd overlap vm
  1052. - vssseg3e64.v v4, (a0), a1, v0.t # OK
  1053. - vlsseg4e64.v v0, (a0), a1, v0.t # vd overlap vm
  1054. - vlsseg4e64.v v4, (a0), a1, v0.t # OK
  1055. - vssseg4e64.v v0, (a0), a1, v0.t # vd overlap vm
  1056. - vssseg4e64.v v4, (a0), a1, v0.t # OK
  1057. - vlsseg5e64.v v0, (a0), a1, v0.t # vd overlap vm
  1058. - vlsseg5e64.v v4, (a0), a1, v0.t # OK
  1059. - vssseg5e64.v v0, (a0), a1, v0.t # vd overlap vm
  1060. - vssseg5e64.v v4, (a0), a1, v0.t # OK
  1061. - vlsseg6e64.v v0, (a0), a1, v0.t # vd overlap vm
  1062. - vlsseg6e64.v v4, (a0), a1, v0.t # OK
  1063. - vssseg6e64.v v0, (a0), a1, v0.t # vd overlap vm
  1064. - vssseg6e64.v v4, (a0), a1, v0.t # OK
  1065. - vlsseg7e64.v v0, (a0), a1, v0.t # vd overlap vm
  1066. - vlsseg7e64.v v4, (a0), a1, v0.t # OK
  1067. - vssseg7e64.v v0, (a0), a1, v0.t # vd overlap vm
  1068. - vssseg7e64.v v4, (a0), a1, v0.t # OK
  1069. - vlsseg8e64.v v0, (a0), a1, v0.t # vd overlap vm
  1070. - vlsseg8e64.v v4, (a0), a1, v0.t # OK
  1071. - vssseg8e64.v v0, (a0), a1, v0.t # vd overlap vm
  1072. - vssseg8e64.v v4, (a0), a1, v0.t # OK
  1073. -
  1074. - vlsseg2e128.v v0, (a0), a1, v0.t # vd overlap vm
  1075. - vlsseg2e128.v v4, (a0), a1, v0.t # OK
  1076. - vssseg2e128.v v0, (a0), a1, v0.t # vd overlap vm
  1077. - vssseg2e128.v v4, (a0), a1, v0.t # OK
  1078. - vlsseg3e128.v v0, (a0), a1, v0.t # vd overlap vm
  1079. - vlsseg3e128.v v4, (a0), a1, v0.t # OK
  1080. - vssseg3e128.v v0, (a0), a1, v0.t # vd overlap vm
  1081. - vssseg3e128.v v4, (a0), a1, v0.t # OK
  1082. - vlsseg4e128.v v0, (a0), a1, v0.t # vd overlap vm
  1083. - vlsseg4e128.v v4, (a0), a1, v0.t # OK
  1084. - vssseg4e128.v v0, (a0), a1, v0.t # vd overlap vm
  1085. - vssseg4e128.v v4, (a0), a1, v0.t # OK
  1086. - vlsseg5e128.v v0, (a0), a1, v0.t # vd overlap vm
  1087. - vlsseg5e128.v v4, (a0), a1, v0.t # OK
  1088. - vssseg5e128.v v0, (a0), a1, v0.t # vd overlap vm
  1089. - vssseg5e128.v v4, (a0), a1, v0.t # OK
  1090. - vlsseg6e128.v v0, (a0), a1, v0.t # vd overlap vm
  1091. - vlsseg6e128.v v4, (a0), a1, v0.t # OK
  1092. - vssseg6e128.v v0, (a0), a1, v0.t # vd overlap vm
  1093. - vssseg6e128.v v4, (a0), a1, v0.t # OK
  1094. - vlsseg7e128.v v0, (a0), a1, v0.t # vd overlap vm
  1095. - vlsseg7e128.v v4, (a0), a1, v0.t # OK
  1096. - vssseg7e128.v v0, (a0), a1, v0.t # vd overlap vm
  1097. - vssseg7e128.v v4, (a0), a1, v0.t # OK
  1098. - vlsseg8e128.v v0, (a0), a1, v0.t # vd overlap vm
  1099. - vlsseg8e128.v v4, (a0), a1, v0.t # OK
  1100. - vssseg8e128.v v0, (a0), a1, v0.t # vd overlap vm
  1101. - vssseg8e128.v v4, (a0), a1, v0.t # OK
  1102. -
  1103. - vlsseg2e256.v v0, (a0), a1, v0.t # vd overlap vm
  1104. - vlsseg2e256.v v4, (a0), a1, v0.t # OK
  1105. - vssseg2e256.v v0, (a0), a1, v0.t # vd overlap vm
  1106. - vssseg2e256.v v4, (a0), a1, v0.t # OK
  1107. - vlsseg3e256.v v0, (a0), a1, v0.t # vd overlap vm
  1108. - vlsseg3e256.v v4, (a0), a1, v0.t # OK
  1109. - vssseg3e256.v v0, (a0), a1, v0.t # vd overlap vm
  1110. - vssseg3e256.v v4, (a0), a1, v0.t # OK
  1111. - vlsseg4e256.v v0, (a0), a1, v0.t # vd overlap vm
  1112. - vlsseg4e256.v v4, (a0), a1, v0.t # OK
  1113. - vssseg4e256.v v0, (a0), a1, v0.t # vd overlap vm
  1114. - vssseg4e256.v v4, (a0), a1, v0.t # OK
  1115. - vlsseg5e256.v v0, (a0), a1, v0.t # vd overlap vm
  1116. - vlsseg5e256.v v4, (a0), a1, v0.t # OK
  1117. - vssseg5e256.v v0, (a0), a1, v0.t # vd overlap vm
  1118. - vssseg5e256.v v4, (a0), a1, v0.t # OK
  1119. - vlsseg6e256.v v0, (a0), a1, v0.t # vd overlap vm
  1120. - vlsseg6e256.v v4, (a0), a1, v0.t # OK
  1121. - vssseg6e256.v v0, (a0), a1, v0.t # vd overlap vm
  1122. - vssseg6e256.v v4, (a0), a1, v0.t # OK
  1123. - vlsseg7e256.v v0, (a0), a1, v0.t # vd overlap vm
  1124. - vlsseg7e256.v v4, (a0), a1, v0.t # OK
  1125. - vssseg7e256.v v0, (a0), a1, v0.t # vd overlap vm
  1126. - vssseg7e256.v v4, (a0), a1, v0.t # OK
  1127. - vlsseg8e256.v v0, (a0), a1, v0.t # vd overlap vm
  1128. - vlsseg8e256.v v4, (a0), a1, v0.t # OK
  1129. - vssseg8e256.v v0, (a0), a1, v0.t # vd overlap vm
  1130. - vssseg8e256.v v4, (a0), a1, v0.t # OK
  1131. -
  1132. - vlsseg2e512.v v0, (a0), a1, v0.t # vd overlap vm
  1133. - vlsseg2e512.v v4, (a0), a1, v0.t # OK
  1134. - vssseg2e512.v v0, (a0), a1, v0.t # vd overlap vm
  1135. - vssseg2e512.v v4, (a0), a1, v0.t # OK
  1136. - vlsseg3e512.v v0, (a0), a1, v0.t # vd overlap vm
  1137. - vlsseg3e512.v v4, (a0), a1, v0.t # OK
  1138. - vssseg3e512.v v0, (a0), a1, v0.t # vd overlap vm
  1139. - vssseg3e512.v v4, (a0), a1, v0.t # OK
  1140. - vlsseg4e512.v v0, (a0), a1, v0.t # vd overlap vm
  1141. - vlsseg4e512.v v4, (a0), a1, v0.t # OK
  1142. - vssseg4e512.v v0, (a0), a1, v0.t # vd overlap vm
  1143. - vssseg4e512.v v4, (a0), a1, v0.t # OK
  1144. - vlsseg5e512.v v0, (a0), a1, v0.t # vd overlap vm
  1145. - vlsseg5e512.v v4, (a0), a1, v0.t # OK
  1146. - vssseg5e512.v v0, (a0), a1, v0.t # vd overlap vm
  1147. - vssseg5e512.v v4, (a0), a1, v0.t # OK
  1148. - vlsseg6e512.v v0, (a0), a1, v0.t # vd overlap vm
  1149. - vlsseg6e512.v v4, (a0), a1, v0.t # OK
  1150. - vssseg6e512.v v0, (a0), a1, v0.t # vd overlap vm
  1151. - vssseg6e512.v v4, (a0), a1, v0.t # OK
  1152. - vlsseg7e512.v v0, (a0), a1, v0.t # vd overlap vm
  1153. - vlsseg7e512.v v4, (a0), a1, v0.t # OK
  1154. - vssseg7e512.v v0, (a0), a1, v0.t # vd overlap vm
  1155. - vssseg7e512.v v4, (a0), a1, v0.t # OK
  1156. - vlsseg8e512.v v0, (a0), a1, v0.t # vd overlap vm
  1157. - vlsseg8e512.v v4, (a0), a1, v0.t # OK
  1158. - vssseg8e512.v v0, (a0), a1, v0.t # vd overlap vm
  1159. - vssseg8e512.v v4, (a0), a1, v0.t # OK
  1160. -
  1161. - vlsseg2e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1162. - vlsseg2e1024.v v4, (a0), a1, v0.t # OK
  1163. - vssseg2e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1164. - vssseg2e1024.v v4, (a0), a1, v0.t # OK
  1165. - vlsseg3e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1166. - vlsseg3e1024.v v4, (a0), a1, v0.t # OK
  1167. - vssseg3e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1168. - vssseg3e1024.v v4, (a0), a1, v0.t # OK
  1169. - vlsseg4e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1170. - vlsseg4e1024.v v4, (a0), a1, v0.t # OK
  1171. - vssseg4e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1172. - vssseg4e1024.v v4, (a0), a1, v0.t # OK
  1173. - vlsseg5e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1174. - vlsseg5e1024.v v4, (a0), a1, v0.t # OK
  1175. - vssseg5e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1176. - vssseg5e1024.v v4, (a0), a1, v0.t # OK
  1177. - vlsseg6e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1178. - vlsseg6e1024.v v4, (a0), a1, v0.t # OK
  1179. - vssseg6e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1180. - vssseg6e1024.v v4, (a0), a1, v0.t # OK
  1181. - vlsseg7e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1182. - vlsseg7e1024.v v4, (a0), a1, v0.t # OK
  1183. - vssseg7e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1184. - vssseg7e1024.v v4, (a0), a1, v0.t # OK
  1185. - vlsseg8e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1186. - vlsseg8e1024.v v4, (a0), a1, v0.t # OK
  1187. - vssseg8e1024.v v0, (a0), a1, v0.t # vd overlap vm
  1188. - vssseg8e1024.v v4, (a0), a1, v0.t # OK
  1189. -
  1190. -# Vector Indexed Segment Loads and Stores
  1191. -
  1192. - vlxseg2ei8.v v0, (a0), v2 # OK
  1193. - vlxseg2ei8.v v1, (a0), v2 # OK
  1194. - vlxseg2ei8.v v2, (a0), v2 # vd overlap vs2
  1195. - vlxseg2ei8.v v0, (a0), v2, v0.t # vd overlap vm
  1196. - vsxseg2ei8.v v0, (a0), v2
  1197. - vsxseg2ei8.v v1, (a0), v2
  1198. - vsxseg2ei8.v v2, (a0), v2
  1199. - vsxseg2ei8.v v0, (a0), v2, v0.t
  1200. - vlxseg3ei8.v v0, (a0), v2
  1201. - vlxseg3ei8.v v1, (a0), v2
  1202. - vlxseg3ei8.v v2, (a0), v2
  1203. - vlxseg3ei8.v v0, (a0), v2, v0.t
  1204. - vsxseg3ei8.v v0, (a0), v2
  1205. - vsxseg3ei8.v v1, (a0), v2
  1206. - vsxseg3ei8.v v2, (a0), v2
  1207. - vsxseg3ei8.v v0, (a0), v2, v0.t
  1208. - vlxseg4ei8.v v0, (a0), v2
  1209. - vlxseg4ei8.v v1, (a0), v2
  1210. - vlxseg4ei8.v v2, (a0), v2
  1211. - vlxseg4ei8.v v0, (a0), v2, v0.t
  1212. - vsxseg4ei8.v v0, (a0), v2
  1213. - vsxseg4ei8.v v1, (a0), v2
  1214. - vsxseg4ei8.v v2, (a0), v2
  1215. - vsxseg4ei8.v v0, (a0), v2, v0.t
  1216. - vlxseg5ei8.v v0, (a0), v2
  1217. - vlxseg5ei8.v v1, (a0), v2
  1218. - vlxseg5ei8.v v2, (a0), v2
  1219. - vlxseg5ei8.v v0, (a0), v2, v0.t
  1220. - vsxseg5ei8.v v0, (a0), v2
  1221. - vsxseg5ei8.v v1, (a0), v2
  1222. - vsxseg5ei8.v v2, (a0), v2
  1223. - vsxseg5ei8.v v0, (a0), v2, v0.t
  1224. - vlxseg6ei8.v v0, (a0), v2
  1225. - vlxseg6ei8.v v1, (a0), v2
  1226. - vlxseg6ei8.v v2, (a0), v2
  1227. - vlxseg6ei8.v v0, (a0), v2, v0.t
  1228. - vsxseg6ei8.v v0, (a0), v2
  1229. - vsxseg6ei8.v v1, (a0), v2
  1230. - vsxseg6ei8.v v2, (a0), v2
  1231. - vsxseg6ei8.v v0, (a0), v2, v0.t
  1232. - vlxseg7ei8.v v0, (a0), v2
  1233. - vlxseg7ei8.v v1, (a0), v2
  1234. - vlxseg7ei8.v v2, (a0), v2
  1235. - vlxseg7ei8.v v0, (a0), v2, v0.t
  1236. - vsxseg7ei8.v v0, (a0), v2
  1237. - vsxseg7ei8.v v1, (a0), v2
  1238. - vsxseg7ei8.v v2, (a0), v2
  1239. - vsxseg7ei8.v v0, (a0), v2, v0.t
  1240. - vlxseg8ei8.v v0, (a0), v2
  1241. - vlxseg8ei8.v v1, (a0), v2
  1242. - vlxseg8ei8.v v2, (a0), v2
  1243. - vlxseg8ei8.v v0, (a0), v2, v0.t
  1244. - vsxseg8ei8.v v0, (a0), v2
  1245. - vsxseg8ei8.v v1, (a0), v2
  1246. - vsxseg8ei8.v v2, (a0), v2
  1247. - vsxseg8ei8.v v0, (a0), v2, v0.t
  1248. -
  1249. - vlxseg2ei16.v v0, (a0), v2 # OK
  1250. - vlxseg2ei16.v v1, (a0), v2 # OK
  1251. - vlxseg2ei16.v v2, (a0), v2 # vd overlap vs2
  1252. - vlxseg2ei16.v v0, (a0), v2, v0.t # vd overlap vm
  1253. - vsxseg2ei16.v v0, (a0), v2
  1254. - vsxseg2ei16.v v1, (a0), v2
  1255. - vsxseg2ei16.v v2, (a0), v2
  1256. - vsxseg2ei16.v v0, (a0), v2, v0.t
  1257. - vlxseg3ei16.v v0, (a0), v2
  1258. - vlxseg3ei16.v v1, (a0), v2
  1259. - vlxseg3ei16.v v2, (a0), v2
  1260. - vlxseg3ei16.v v0, (a0), v2, v0.t
  1261. - vsxseg3ei16.v v0, (a0), v2
  1262. - vsxseg3ei16.v v1, (a0), v2
  1263. - vsxseg3ei16.v v2, (a0), v2
  1264. - vsxseg3ei16.v v0, (a0), v2, v0.t
  1265. - vlxseg4ei16.v v0, (a0), v2
  1266. - vlxseg4ei16.v v1, (a0), v2
  1267. - vlxseg4ei16.v v2, (a0), v2
  1268. - vlxseg4ei16.v v0, (a0), v2, v0.t
  1269. - vsxseg4ei16.v v0, (a0), v2
  1270. - vsxseg4ei16.v v1, (a0), v2
  1271. - vsxseg4ei16.v v2, (a0), v2
  1272. - vsxseg4ei16.v v0, (a0), v2, v0.t
  1273. - vlxseg5ei16.v v0, (a0), v2
  1274. - vlxseg5ei16.v v1, (a0), v2
  1275. - vlxseg5ei16.v v2, (a0), v2
  1276. - vlxseg5ei16.v v0, (a0), v2, v0.t
  1277. - vsxseg5ei16.v v0, (a0), v2
  1278. - vsxseg5ei16.v v1, (a0), v2
  1279. - vsxseg5ei16.v v2, (a0), v2
  1280. - vsxseg5ei16.v v0, (a0), v2, v0.t
  1281. - vlxseg6ei16.v v0, (a0), v2
  1282. - vlxseg6ei16.v v1, (a0), v2
  1283. - vlxseg6ei16.v v2, (a0), v2
  1284. - vlxseg6ei16.v v0, (a0), v2, v0.t
  1285. - vsxseg6ei16.v v0, (a0), v2
  1286. - vsxseg6ei16.v v1, (a0), v2
  1287. - vsxseg6ei16.v v2, (a0), v2
  1288. - vsxseg6ei16.v v0, (a0), v2, v0.t
  1289. - vlxseg7ei16.v v0, (a0), v2
  1290. - vlxseg7ei16.v v1, (a0), v2
  1291. - vlxseg7ei16.v v2, (a0), v2
  1292. - vlxseg7ei16.v v0, (a0), v2, v0.t
  1293. - vsxseg7ei16.v v0, (a0), v2
  1294. - vsxseg7ei16.v v1, (a0), v2
  1295. - vsxseg7ei16.v v2, (a0), v2
  1296. - vsxseg7ei16.v v0, (a0), v2, v0.t
  1297. - vlxseg8ei16.v v0, (a0), v2
  1298. - vlxseg8ei16.v v1, (a0), v2
  1299. - vlxseg8ei16.v v2, (a0), v2
  1300. - vlxseg8ei16.v v0, (a0), v2, v0.t
  1301. - vsxseg8ei16.v v0, (a0), v2
  1302. - vsxseg8ei16.v v1, (a0), v2
  1303. - vsxseg8ei16.v v2, (a0), v2
  1304. - vsxseg8ei16.v v0, (a0), v2, v0.t
  1305. -
  1306. - vlxseg2ei32.v v0, (a0), v2 # OK
  1307. - vlxseg2ei32.v v1, (a0), v2 # OK
  1308. - vlxseg2ei32.v v2, (a0), v2 # vd overlap vs2
  1309. - vlxseg2ei32.v v0, (a0), v2, v0.t # vd overlap vm
  1310. - vsxseg2ei32.v v0, (a0), v2
  1311. - vsxseg2ei32.v v1, (a0), v2
  1312. - vsxseg2ei32.v v2, (a0), v2
  1313. - vsxseg2ei32.v v0, (a0), v2, v0.t
  1314. - vlxseg3ei32.v v0, (a0), v2
  1315. - vlxseg3ei32.v v1, (a0), v2
  1316. - vlxseg3ei32.v v2, (a0), v2
  1317. - vlxseg3ei32.v v0, (a0), v2, v0.t
  1318. - vsxseg3ei32.v v0, (a0), v2
  1319. - vsxseg3ei32.v v1, (a0), v2
  1320. - vsxseg3ei32.v v2, (a0), v2
  1321. - vsxseg3ei32.v v0, (a0), v2, v0.t
  1322. - vlxseg4ei32.v v0, (a0), v2
  1323. - vlxseg4ei32.v v1, (a0), v2
  1324. - vlxseg4ei32.v v2, (a0), v2
  1325. - vlxseg4ei32.v v0, (a0), v2, v0.t
  1326. - vsxseg4ei32.v v0, (a0), v2
  1327. - vsxseg4ei32.v v1, (a0), v2
  1328. - vsxseg4ei32.v v2, (a0), v2
  1329. - vsxseg4ei32.v v0, (a0), v2, v0.t
  1330. - vlxseg5ei32.v v0, (a0), v2
  1331. - vlxseg5ei32.v v1, (a0), v2
  1332. - vlxseg5ei32.v v2, (a0), v2
  1333. - vlxseg5ei32.v v0, (a0), v2, v0.t
  1334. - vsxseg5ei32.v v0, (a0), v2
  1335. - vsxseg5ei32.v v1, (a0), v2
  1336. - vsxseg5ei32.v v2, (a0), v2
  1337. - vsxseg5ei32.v v0, (a0), v2, v0.t
  1338. - vlxseg6ei32.v v0, (a0), v2
  1339. - vlxseg6ei32.v v1, (a0), v2
  1340. - vlxseg6ei32.v v2, (a0), v2
  1341. - vlxseg6ei32.v v0, (a0), v2, v0.t
  1342. - vsxseg6ei32.v v0, (a0), v2
  1343. - vsxseg6ei32.v v1, (a0), v2
  1344. - vsxseg6ei32.v v2, (a0), v2
  1345. - vsxseg6ei32.v v0, (a0), v2, v0.t
  1346. - vlxseg7ei32.v v0, (a0), v2
  1347. - vlxseg7ei32.v v1, (a0), v2
  1348. - vlxseg7ei32.v v2, (a0), v2
  1349. - vlxseg7ei32.v v0, (a0), v2, v0.t
  1350. - vsxseg7ei32.v v0, (a0), v2
  1351. - vsxseg7ei32.v v1, (a0), v2
  1352. - vsxseg7ei32.v v2, (a0), v2
  1353. - vsxseg7ei32.v v0, (a0), v2, v0.t
  1354. - vlxseg8ei32.v v0, (a0), v2
  1355. - vlxseg8ei32.v v1, (a0), v2
  1356. - vlxseg8ei32.v v2, (a0), v2
  1357. - vlxseg8ei32.v v0, (a0), v2, v0.t
  1358. - vsxseg8ei32.v v0, (a0), v2
  1359. - vsxseg8ei32.v v1, (a0), v2
  1360. - vsxseg8ei32.v v2, (a0), v2
  1361. - vsxseg8ei32.v v0, (a0), v2, v0.t
  1362. -
  1363. - vlxseg2ei64.v v0, (a0), v2 # OK
  1364. - vlxseg2ei64.v v1, (a0), v2 # OK
  1365. - vlxseg2ei64.v v2, (a0), v2 # vd overlap vs2
  1366. - vlxseg2ei64.v v0, (a0), v2, v0.t # vd overlap vm
  1367. - vsxseg2ei64.v v0, (a0), v2
  1368. - vsxseg2ei64.v v1, (a0), v2
  1369. - vsxseg2ei64.v v2, (a0), v2
  1370. - vsxseg2ei64.v v0, (a0), v2, v0.t
  1371. - vlxseg3ei64.v v0, (a0), v2
  1372. - vlxseg3ei64.v v1, (a0), v2
  1373. - vlxseg3ei64.v v2, (a0), v2
  1374. - vlxseg3ei64.v v0, (a0), v2, v0.t
  1375. - vsxseg3ei64.v v0, (a0), v2
  1376. - vsxseg3ei64.v v1, (a0), v2
  1377. - vsxseg3ei64.v v2, (a0), v2
  1378. - vsxseg3ei64.v v0, (a0), v2, v0.t
  1379. - vlxseg4ei64.v v0, (a0), v2
  1380. - vlxseg4ei64.v v1, (a0), v2
  1381. - vlxseg4ei64.v v2, (a0), v2
  1382. - vlxseg4ei64.v v0, (a0), v2, v0.t
  1383. - vsxseg4ei64.v v0, (a0), v2
  1384. - vsxseg4ei64.v v1, (a0), v2
  1385. - vsxseg4ei64.v v2, (a0), v2
  1386. - vsxseg4ei64.v v0, (a0), v2, v0.t
  1387. - vlxseg5ei64.v v0, (a0), v2
  1388. - vlxseg5ei64.v v1, (a0), v2
  1389. - vlxseg5ei64.v v2, (a0), v2
  1390. - vlxseg5ei64.v v0, (a0), v2, v0.t
  1391. - vsxseg5ei64.v v0, (a0), v2
  1392. - vsxseg5ei64.v v1, (a0), v2
  1393. - vsxseg5ei64.v v2, (a0), v2
  1394. - vsxseg5ei64.v v0, (a0), v2, v0.t
  1395. - vlxseg6ei64.v v0, (a0), v2
  1396. - vlxseg6ei64.v v1, (a0), v2
  1397. - vlxseg6ei64.v v2, (a0), v2
  1398. - vlxseg6ei64.v v0, (a0), v2, v0.t
  1399. - vsxseg6ei64.v v0, (a0), v2
  1400. - vsxseg6ei64.v v1, (a0), v2
  1401. - vsxseg6ei64.v v2, (a0), v2
  1402. - vsxseg6ei64.v v0, (a0), v2, v0.t
  1403. - vlxseg7ei64.v v0, (a0), v2
  1404. - vlxseg7ei64.v v1, (a0), v2
  1405. - vlxseg7ei64.v v2, (a0), v2
  1406. - vlxseg7ei64.v v0, (a0), v2, v0.t
  1407. - vsxseg7ei64.v v0, (a0), v2
  1408. - vsxseg7ei64.v v1, (a0), v2
  1409. - vsxseg7ei64.v v2, (a0), v2
  1410. - vsxseg7ei64.v v0, (a0), v2, v0.t
  1411. - vlxseg8ei64.v v0, (a0), v2
  1412. - vlxseg8ei64.v v1, (a0), v2
  1413. - vlxseg8ei64.v v2, (a0), v2
  1414. - vlxseg8ei64.v v0, (a0), v2, v0.t
  1415. - vsxseg8ei64.v v0, (a0), v2
  1416. - vsxseg8ei64.v v1, (a0), v2
  1417. - vsxseg8ei64.v v2, (a0), v2
  1418. - vsxseg8ei64.v v0, (a0), v2, v0.t
  1419. -
  1420. - vlxseg2ei128.v v0, (a0), v2 # OK
  1421. - vlxseg2ei128.v v1, (a0), v2 # OK
  1422. - vlxseg2ei128.v v2, (a0), v2 # vd overlap vs2
  1423. - vlxseg2ei128.v v0, (a0), v2, v0.t # vd overlap vm
  1424. - vsxseg2ei128.v v0, (a0), v2
  1425. - vsxseg2ei128.v v1, (a0), v2
  1426. - vsxseg2ei128.v v2, (a0), v2
  1427. - vsxseg2ei128.v v0, (a0), v2, v0.t
  1428. - vlxseg3ei128.v v0, (a0), v2
  1429. - vlxseg3ei128.v v1, (a0), v2
  1430. - vlxseg3ei128.v v2, (a0), v2
  1431. - vlxseg3ei128.v v0, (a0), v2, v0.t
  1432. - vsxseg3ei128.v v0, (a0), v2
  1433. - vsxseg3ei128.v v1, (a0), v2
  1434. - vsxseg3ei128.v v2, (a0), v2
  1435. - vsxseg3ei128.v v0, (a0), v2, v0.t
  1436. - vlxseg4ei128.v v0, (a0), v2
  1437. - vlxseg4ei128.v v1, (a0), v2
  1438. - vlxseg4ei128.v v2, (a0), v2
  1439. - vlxseg4ei128.v v0, (a0), v2, v0.t
  1440. - vsxseg4ei128.v v0, (a0), v2
  1441. - vsxseg4ei128.v v1, (a0), v2
  1442. - vsxseg4ei128.v v2, (a0), v2
  1443. - vsxseg4ei128.v v0, (a0), v2, v0.t
  1444. - vlxseg5ei128.v v0, (a0), v2
  1445. - vlxseg5ei128.v v1, (a0), v2
  1446. - vlxseg5ei128.v v2, (a0), v2
  1447. - vlxseg5ei128.v v0, (a0), v2, v0.t
  1448. - vsxseg5ei128.v v0, (a0), v2
  1449. - vsxseg5ei128.v v1, (a0), v2
  1450. - vsxseg5ei128.v v2, (a0), v2
  1451. - vsxseg5ei128.v v0, (a0), v2, v0.t
  1452. - vlxseg6ei128.v v0, (a0), v2
  1453. - vlxseg6ei128.v v1, (a0), v2
  1454. - vlxseg6ei128.v v2, (a0), v2
  1455. - vlxseg6ei128.v v0, (a0), v2, v0.t
  1456. - vsxseg6ei128.v v0, (a0), v2
  1457. - vsxseg6ei128.v v1, (a0), v2
  1458. - vsxseg6ei128.v v2, (a0), v2
  1459. - vsxseg6ei128.v v0, (a0), v2, v0.t
  1460. - vlxseg7ei128.v v0, (a0), v2
  1461. - vlxseg7ei128.v v1, (a0), v2
  1462. - vlxseg7ei128.v v2, (a0), v2
  1463. - vlxseg7ei128.v v0, (a0), v2, v0.t
  1464. - vsxseg7ei128.v v0, (a0), v2
  1465. - vsxseg7ei128.v v1, (a0), v2
  1466. - vsxseg7ei128.v v2, (a0), v2
  1467. - vsxseg7ei128.v v0, (a0), v2, v0.t
  1468. - vlxseg8ei128.v v0, (a0), v2
  1469. - vlxseg8ei128.v v1, (a0), v2
  1470. - vlxseg8ei128.v v2, (a0), v2
  1471. - vlxseg8ei128.v v0, (a0), v2, v0.t
  1472. - vsxseg8ei128.v v0, (a0), v2
  1473. - vsxseg8ei128.v v1, (a0), v2
  1474. - vsxseg8ei128.v v2, (a0), v2
  1475. - vsxseg8ei128.v v0, (a0), v2, v0.t
  1476. -
  1477. - vlxseg2ei256.v v0, (a0), v2 # OK
  1478. - vlxseg2ei256.v v1, (a0), v2 # OK
  1479. - vlxseg2ei256.v v2, (a0), v2 # vd overlap vs2
  1480. - vlxseg2ei256.v v0, (a0), v2, v0.t # vd overlap vm
  1481. - vsxseg2ei256.v v0, (a0), v2
  1482. - vsxseg2ei256.v v1, (a0), v2
  1483. - vsxseg2ei256.v v2, (a0), v2
  1484. - vsxseg2ei256.v v0, (a0), v2, v0.t
  1485. - vlxseg3ei256.v v0, (a0), v2
  1486. - vlxseg3ei256.v v1, (a0), v2
  1487. - vlxseg3ei256.v v2, (a0), v2
  1488. - vlxseg3ei256.v v0, (a0), v2, v0.t
  1489. - vsxseg3ei256.v v0, (a0), v2
  1490. - vsxseg3ei256.v v1, (a0), v2
  1491. - vsxseg3ei256.v v2, (a0), v2
  1492. - vsxseg3ei256.v v0, (a0), v2, v0.t
  1493. - vlxseg4ei256.v v0, (a0), v2
  1494. - vlxseg4ei256.v v1, (a0), v2
  1495. - vlxseg4ei256.v v2, (a0), v2
  1496. - vlxseg4ei256.v v0, (a0), v2, v0.t
  1497. - vsxseg4ei256.v v0, (a0), v2
  1498. - vsxseg4ei256.v v1, (a0), v2
  1499. - vsxseg4ei256.v v2, (a0), v2
  1500. - vsxseg4ei256.v v0, (a0), v2, v0.t
  1501. - vlxseg5ei256.v v0, (a0), v2
  1502. - vlxseg5ei256.v v1, (a0), v2
  1503. - vlxseg5ei256.v v2, (a0), v2
  1504. - vlxseg5ei256.v v0, (a0), v2, v0.t
  1505. - vsxseg5ei256.v v0, (a0), v2
  1506. - vsxseg5ei256.v v1, (a0), v2
  1507. - vsxseg5ei256.v v2, (a0), v2
  1508. - vsxseg5ei256.v v0, (a0), v2, v0.t
  1509. - vlxseg6ei256.v v0, (a0), v2
  1510. - vlxseg6ei256.v v1, (a0), v2
  1511. - vlxseg6ei256.v v2, (a0), v2
  1512. - vlxseg6ei256.v v0, (a0), v2, v0.t
  1513. - vsxseg6ei256.v v0, (a0), v2
  1514. - vsxseg6ei256.v v1, (a0), v2
  1515. - vsxseg6ei256.v v2, (a0), v2
  1516. - vsxseg6ei256.v v0, (a0), v2, v0.t
  1517. - vlxseg7ei256.v v0, (a0), v2
  1518. - vlxseg7ei256.v v1, (a0), v2
  1519. - vlxseg7ei256.v v2, (a0), v2
  1520. - vlxseg7ei256.v v0, (a0), v2, v0.t
  1521. - vsxseg7ei256.v v0, (a0), v2
  1522. - vsxseg7ei256.v v1, (a0), v2
  1523. - vsxseg7ei256.v v2, (a0), v2
  1524. - vsxseg7ei256.v v0, (a0), v2, v0.t
  1525. - vlxseg8ei256.v v0, (a0), v2
  1526. - vlxseg8ei256.v v1, (a0), v2
  1527. - vlxseg8ei256.v v2, (a0), v2
  1528. - vlxseg8ei256.v v0, (a0), v2, v0.t
  1529. - vsxseg8ei256.v v0, (a0), v2
  1530. - vsxseg8ei256.v v1, (a0), v2
  1531. - vsxseg8ei256.v v2, (a0), v2
  1532. - vsxseg8ei256.v v0, (a0), v2, v0.t
  1533. -
  1534. - vlxseg2ei512.v v0, (a0), v2 # OK
  1535. - vlxseg2ei512.v v1, (a0), v2 # OK
  1536. - vlxseg2ei512.v v2, (a0), v2 # vd overlap vs2
  1537. - vlxseg2ei512.v v0, (a0), v2, v0.t # vd overlap vm
  1538. - vsxseg2ei512.v v0, (a0), v2
  1539. - vsxseg2ei512.v v1, (a0), v2
  1540. - vsxseg2ei512.v v2, (a0), v2
  1541. - vsxseg2ei512.v v0, (a0), v2, v0.t
  1542. - vlxseg3ei512.v v0, (a0), v2
  1543. - vlxseg3ei512.v v1, (a0), v2
  1544. - vlxseg3ei512.v v2, (a0), v2
  1545. - vlxseg3ei512.v v0, (a0), v2, v0.t
  1546. - vsxseg3ei512.v v0, (a0), v2
  1547. - vsxseg3ei512.v v1, (a0), v2
  1548. - vsxseg3ei512.v v2, (a0), v2
  1549. - vsxseg3ei512.v v0, (a0), v2, v0.t
  1550. - vlxseg4ei512.v v0, (a0), v2
  1551. - vlxseg4ei512.v v1, (a0), v2
  1552. - vlxseg4ei512.v v2, (a0), v2
  1553. - vlxseg4ei512.v v0, (a0), v2, v0.t
  1554. - vsxseg4ei512.v v0, (a0), v2
  1555. - vsxseg4ei512.v v1, (a0), v2
  1556. - vsxseg4ei512.v v2, (a0), v2
  1557. - vsxseg4ei512.v v0, (a0), v2, v0.t
  1558. - vlxseg5ei512.v v0, (a0), v2
  1559. - vlxseg5ei512.v v1, (a0), v2
  1560. - vlxseg5ei512.v v2, (a0), v2
  1561. - vlxseg5ei512.v v0, (a0), v2, v0.t
  1562. - vsxseg5ei512.v v0, (a0), v2
  1563. - vsxseg5ei512.v v1, (a0), v2
  1564. - vsxseg5ei512.v v2, (a0), v2
  1565. - vsxseg5ei512.v v0, (a0), v2, v0.t
  1566. - vlxseg6ei512.v v0, (a0), v2
  1567. - vlxseg6ei512.v v1, (a0), v2
  1568. - vlxseg6ei512.v v2, (a0), v2
  1569. - vlxseg6ei512.v v0, (a0), v2, v0.t
  1570. - vsxseg6ei512.v v0, (a0), v2
  1571. - vsxseg6ei512.v v1, (a0), v2
  1572. - vsxseg6ei512.v v2, (a0), v2
  1573. - vsxseg6ei512.v v0, (a0), v2, v0.t
  1574. - vlxseg7ei512.v v0, (a0), v2
  1575. - vlxseg7ei512.v v1, (a0), v2
  1576. - vlxseg7ei512.v v2, (a0), v2
  1577. - vlxseg7ei512.v v0, (a0), v2, v0.t
  1578. - vsxseg7ei512.v v0, (a0), v2
  1579. - vsxseg7ei512.v v1, (a0), v2
  1580. - vsxseg7ei512.v v2, (a0), v2
  1581. - vsxseg7ei512.v v0, (a0), v2, v0.t
  1582. - vlxseg8ei512.v v0, (a0), v2
  1583. - vlxseg8ei512.v v1, (a0), v2
  1584. - vlxseg8ei512.v v2, (a0), v2
  1585. - vlxseg8ei512.v v0, (a0), v2, v0.t
  1586. - vsxseg8ei512.v v0, (a0), v2
  1587. - vsxseg8ei512.v v1, (a0), v2
  1588. - vsxseg8ei512.v v2, (a0), v2
  1589. - vsxseg8ei512.v v0, (a0), v2, v0.t
  1590. -
  1591. - vlxseg2ei1024.v v0, (a0), v2 # OK
  1592. - vlxseg2ei1024.v v1, (a0), v2 # OK
  1593. - vlxseg2ei1024.v v2, (a0), v2 # vd overlap vs2
  1594. - vlxseg2ei1024.v v0, (a0), v2, v0.t # vd overlap vm
  1595. - vsxseg2ei1024.v v0, (a0), v2
  1596. - vsxseg2ei1024.v v1, (a0), v2
  1597. - vsxseg2ei1024.v v2, (a0), v2
  1598. - vsxseg2ei1024.v v0, (a0), v2, v0.t
  1599. - vlxseg3ei1024.v v0, (a0), v2
  1600. - vlxseg3ei1024.v v1, (a0), v2
  1601. - vlxseg3ei1024.v v2, (a0), v2
  1602. - vlxseg3ei1024.v v0, (a0), v2, v0.t
  1603. - vsxseg3ei1024.v v0, (a0), v2
  1604. - vsxseg3ei1024.v v1, (a0), v2
  1605. - vsxseg3ei1024.v v2, (a0), v2
  1606. - vsxseg3ei1024.v v0, (a0), v2, v0.t
  1607. - vlxseg4ei1024.v v0, (a0), v2
  1608. - vlxseg4ei1024.v v1, (a0), v2
  1609. - vlxseg4ei1024.v v2, (a0), v2
  1610. - vlxseg4ei1024.v v0, (a0), v2, v0.t
  1611. - vsxseg4ei1024.v v0, (a0), v2
  1612. - vsxseg4ei1024.v v1, (a0), v2
  1613. - vsxseg4ei1024.v v2, (a0), v2
  1614. - vsxseg4ei1024.v v0, (a0), v2, v0.t
  1615. - vlxseg5ei1024.v v0, (a0), v2
  1616. - vlxseg5ei1024.v v1, (a0), v2
  1617. - vlxseg5ei1024.v v2, (a0), v2
  1618. - vlxseg5ei1024.v v0, (a0), v2, v0.t
  1619. - vsxseg5ei1024.v v0, (a0), v2
  1620. - vsxseg5ei1024.v v1, (a0), v2
  1621. - vsxseg5ei1024.v v2, (a0), v2
  1622. - vsxseg5ei1024.v v0, (a0), v2, v0.t
  1623. - vlxseg6ei1024.v v0, (a0), v2
  1624. - vlxseg6ei1024.v v1, (a0), v2
  1625. - vlxseg6ei1024.v v2, (a0), v2
  1626. - vlxseg6ei1024.v v0, (a0), v2, v0.t
  1627. - vsxseg6ei1024.v v0, (a0), v2
  1628. - vsxseg6ei1024.v v1, (a0), v2
  1629. - vsxseg6ei1024.v v2, (a0), v2
  1630. - vsxseg6ei1024.v v0, (a0), v2, v0.t
  1631. - vlxseg7ei1024.v v0, (a0), v2
  1632. - vlxseg7ei1024.v v1, (a0), v2
  1633. - vlxseg7ei1024.v v2, (a0), v2
  1634. - vlxseg7ei1024.v v0, (a0), v2, v0.t
  1635. - vsxseg7ei1024.v v0, (a0), v2
  1636. - vsxseg7ei1024.v v1, (a0), v2
  1637. - vsxseg7ei1024.v v2, (a0), v2
  1638. - vsxseg7ei1024.v v0, (a0), v2, v0.t
  1639. - vlxseg8ei1024.v v0, (a0), v2
  1640. - vlxseg8ei1024.v v1, (a0), v2
  1641. - vlxseg8ei1024.v v2, (a0), v2
  1642. - vlxseg8ei1024.v v0, (a0), v2, v0.t
  1643. - vsxseg8ei1024.v v0, (a0), v2
  1644. - vsxseg8ei1024.v v1, (a0), v2
  1645. - vsxseg8ei1024.v v2, (a0), v2
  1646. - vsxseg8ei1024.v v0, (a0), v2, v0.t
  1647. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.d b/gas/testsuite/gas/riscv/vector-insns-fail-02.d
  1648. deleted file mode 100644
  1649. index 6780b8553d..0000000000
  1650. --- a/gas/testsuite/gas/riscv/vector-insns-fail-02.d
  1651. +++ /dev/null
  1652. @@ -1,3 +0,0 @@
  1653. -#as: -march=rv32ifv_zvqmac -mcheck-constraints
  1654. -#source: vector-insns-fail-02.s
  1655. -#error_output: vector-insns-fail-02.l
  1656. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.l b/gas/testsuite/gas/riscv/vector-insns-fail-02.l
  1657. deleted file mode 100644
  1658. index c015fd75fc..0000000000
  1659. --- a/gas/testsuite/gas/riscv/vector-insns-fail-02.l
  1660. +++ /dev/null
  1661. @@ -1,121 +0,0 @@
  1662. -.*: Assembler messages:
  1663. -.*Error: illegal operands `vwaddu.vv v1,v2,v4'
  1664. -.*Error: illegal operands `vwaddu.vv v2,v2,v4'
  1665. -.*Error: illegal operands `vwaddu.vv v2,v3,v4'
  1666. -.*Error: illegal operands `vwaddu.vv v4,v2,v4'
  1667. -.*Error: illegal operands `vwaddu.vv v4,v2,v5'
  1668. -.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
  1669. -.*Error: illegal operands `vwsubu.vv v1,v2,v4'
  1670. -.*Error: illegal operands `vwsubu.vv v2,v2,v4'
  1671. -.*Error: illegal operands `vwsubu.vv v2,v3,v4'
  1672. -.*Error: illegal operands `vwsubu.vv v4,v2,v4'
  1673. -.*Error: illegal operands `vwsubu.vv v4,v2,v5'
  1674. -.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
  1675. -.*Error: illegal operands `vwadd.vv v1,v2,v4'
  1676. -.*Error: illegal operands `vwadd.vv v2,v2,v4'
  1677. -.*Error: illegal operands `vwadd.vv v2,v3,v4'
  1678. -.*Error: illegal operands `vwadd.vv v4,v2,v4'
  1679. -.*Error: illegal operands `vwadd.vv v4,v2,v5'
  1680. -.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
  1681. -.*Error: illegal operands `vwsub.vv v1,v2,v4'
  1682. -.*Error: illegal operands `vwsub.vv v2,v2,v4'
  1683. -.*Error: illegal operands `vwsub.vv v2,v3,v4'
  1684. -.*Error: illegal operands `vwsub.vv v4,v2,v4'
  1685. -.*Error: illegal operands `vwsub.vv v4,v2,v5'
  1686. -.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
  1687. -.*Error: illegal operands `vwmul.vv v1,v2,v4'
  1688. -.*Error: illegal operands `vwmul.vv v2,v2,v4'
  1689. -.*Error: illegal operands `vwmul.vv v2,v3,v4'
  1690. -.*Error: illegal operands `vwmul.vv v4,v2,v4'
  1691. -.*Error: illegal operands `vwmul.vv v4,v2,v5'
  1692. -.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
  1693. -.*Error: illegal operands `vwmulu.vv v1,v2,v4'
  1694. -.*Error: illegal operands `vwmulu.vv v2,v2,v4'
  1695. -.*Error: illegal operands `vwmulu.vv v2,v3,v4'
  1696. -.*Error: illegal operands `vwmulu.vv v4,v2,v4'
  1697. -.*Error: illegal operands `vwmulu.vv v4,v2,v5'
  1698. -.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
  1699. -.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
  1700. -.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
  1701. -.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
  1702. -.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
  1703. -.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
  1704. -.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
  1705. -.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
  1706. -.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
  1707. -.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
  1708. -.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
  1709. -.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
  1710. -.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
  1711. -.*Error: illegal operands `vwmacc.vv v1,v2,v4'
  1712. -.*Error: illegal operands `vwmacc.vv v2,v2,v4'
  1713. -.*Error: illegal operands `vwmacc.vv v2,v3,v4'
  1714. -.*Error: illegal operands `vwmacc.vv v4,v2,v4'
  1715. -.*Error: illegal operands `vwmacc.vv v4,v2,v5'
  1716. -.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
  1717. -.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
  1718. -.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
  1719. -.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
  1720. -.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
  1721. -.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
  1722. -.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
  1723. -.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
  1724. -.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
  1725. -.*Error: illegal operands `vqmaccu.vv v4,v6,v8'
  1726. -.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
  1727. -.*Error: illegal operands `vqmaccu.vv v8,v4,v10'
  1728. -.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
  1729. -.*Error: illegal operands `vqmacc.vv v2,v4,v8'
  1730. -.*Error: illegal operands `vqmacc.vv v4,v4,v8'
  1731. -.*Error: illegal operands `vqmacc.vv v4,v6,v8'
  1732. -.*Error: illegal operands `vqmacc.vv v8,v4,v8'
  1733. -.*Error: illegal operands `vqmacc.vv v8,v4,v10'
  1734. -.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
  1735. -.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
  1736. -.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
  1737. -.*Error: illegal operands `vqmaccsu.vv v4,v6,v8'
  1738. -.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
  1739. -.*Error: illegal operands `vqmaccsu.vv v8,v4,v10'
  1740. -.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
  1741. -.*Error: illegal operands `vfwadd.vv v1,v2,v4'
  1742. -.*Error: illegal operands `vfwadd.vv v2,v2,v4'
  1743. -.*Error: illegal operands `vfwadd.vv v2,v3,v4'
  1744. -.*Error: illegal operands `vfwadd.vv v4,v2,v4'
  1745. -.*Error: illegal operands `vfwadd.vv v4,v2,v5'
  1746. -.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
  1747. -.*Error: illegal operands `vfwsub.vv v1,v2,v4'
  1748. -.*Error: illegal operands `vfwsub.vv v2,v2,v4'
  1749. -.*Error: illegal operands `vfwsub.vv v2,v3,v4'
  1750. -.*Error: illegal operands `vfwsub.vv v4,v2,v4'
  1751. -.*Error: illegal operands `vfwsub.vv v4,v2,v5'
  1752. -.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
  1753. -.*Error: illegal operands `vfwmul.vv v1,v2,v4'
  1754. -.*Error: illegal operands `vfwmul.vv v2,v2,v4'
  1755. -.*Error: illegal operands `vfwmul.vv v2,v3,v4'
  1756. -.*Error: illegal operands `vfwmul.vv v4,v2,v4'
  1757. -.*Error: illegal operands `vfwmul.vv v4,v2,v5'
  1758. -.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
  1759. -.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
  1760. -.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
  1761. -.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
  1762. -.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
  1763. -.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
  1764. -.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
  1765. -.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
  1766. -.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
  1767. -.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
  1768. -.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
  1769. -.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
  1770. -.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
  1771. -.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
  1772. -.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
  1773. -.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
  1774. -.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
  1775. -.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
  1776. -.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
  1777. -.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
  1778. -.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
  1779. -.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
  1780. -.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
  1781. -.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
  1782. -.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
  1783. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.s b/gas/testsuite/gas/riscv/vector-insns-fail-02.s
  1784. deleted file mode 100644
  1785. index bf493c8ddb..0000000000
  1786. --- a/gas/testsuite/gas/riscv/vector-insns-fail-02.s
  1787. +++ /dev/null
  1788. @@ -1,162 +0,0 @@
  1789. -# Widening Vector Arithmetic Instructions (VV)
  1790. -# Quad-Widening Vector Arithmetic Instructions (VV)
  1791. -
  1792. - vwaddu.vv v0, v2, v4 # OK
  1793. - vwaddu.vv v1, v2, v4 # vd should be multiple of 2
  1794. - vwaddu.vv v2, v2, v4 # vd overlap vs2
  1795. - vwaddu.vv v2, v3, v4 # vd overlap vs2
  1796. - vwaddu.vv v4, v2, v4 # vd overlap vs1
  1797. - vwaddu.vv v4, v2, v5 # vd overlap vs1
  1798. - vwaddu.vv v0, v2, v4, v0.t # vd overlap vm
  1799. -
  1800. - vwsubu.vv v0, v2, v4 # OK
  1801. - vwsubu.vv v1, v2, v4 # vd should be multiple of 2
  1802. - vwsubu.vv v2, v2, v4 # vd overlap vs2
  1803. - vwsubu.vv v2, v3, v4 # vd overlap vs2
  1804. - vwsubu.vv v4, v2, v4 # vd overlap vs1
  1805. - vwsubu.vv v4, v2, v5 # vd overlap vs1
  1806. - vwsubu.vv v0, v2, v4, v0.t # vd overlap vm
  1807. -
  1808. - vwadd.vv v0, v2, v4 # OK
  1809. - vwadd.vv v1, v2, v4 # vd should be multiple of 2
  1810. - vwadd.vv v2, v2, v4 # vd overlap vs2
  1811. - vwadd.vv v2, v3, v4 # vd overlap vs2
  1812. - vwadd.vv v4, v2, v4 # vd overlap vs1
  1813. - vwadd.vv v4, v2, v5 # vd overlap vs1
  1814. - vwadd.vv v0, v2, v4, v0.t # vd overlap vm
  1815. -
  1816. - vwsub.vv v0, v2, v4 # OK
  1817. - vwsub.vv v1, v2, v4 # vd should be multiple of 2
  1818. - vwsub.vv v2, v2, v4 # vd overlap vs2
  1819. - vwsub.vv v2, v3, v4 # vd overlap vs2
  1820. - vwsub.vv v4, v2, v4 # vd overlap vs1
  1821. - vwsub.vv v4, v2, v5 # vd overlap vs1
  1822. - vwsub.vv v0, v2, v4, v0.t # vd overlap vm
  1823. -
  1824. - vwmul.vv v0, v2, v4 # OK
  1825. - vwmul.vv v1, v2, v4 # vd should be multiple of 2
  1826. - vwmul.vv v2, v2, v4 # vd overlap vs2
  1827. - vwmul.vv v2, v3, v4 # vd overlap vs2
  1828. - vwmul.vv v4, v2, v4 # vd overlap vs1
  1829. - vwmul.vv v4, v2, v5 # vd overlap vs1
  1830. - vwmul.vv v0, v2, v4, v0.t # vd overlap vm
  1831. -
  1832. - vwmulu.vv v0, v2, v4 # OK
  1833. - vwmulu.vv v1, v2, v4 # vd should be multiple of 2
  1834. - vwmulu.vv v2, v2, v4 # vd overlap vs2
  1835. - vwmulu.vv v2, v3, v4 # vd overlap vs2
  1836. - vwmulu.vv v4, v2, v4 # vd overlap vs1
  1837. - vwmulu.vv v4, v2, v5 # vd overlap vs1
  1838. - vwmulu.vv v0, v2, v4, v0.t # vd overlap vm
  1839. -
  1840. - vwmulsu.vv v0, v2, v4 # OK
  1841. - vwmulsu.vv v1, v2, v4 # vd should be multiple of 2
  1842. - vwmulsu.vv v2, v2, v4 # vd overlap vs2
  1843. - vwmulsu.vv v2, v3, v4 # vd overlap vs2
  1844. - vwmulsu.vv v4, v2, v4 # vd overlap vs1
  1845. - vwmulsu.vv v4, v2, v5 # vd overlap vs1
  1846. - vwmulsu.vv v0, v2, v4, v0.t # vd overlap vm
  1847. -
  1848. - vwmaccu.vv v0, v2, v4 # OK
  1849. - vwmaccu.vv v1, v2, v4 # vd should be multiple of 2
  1850. - vwmaccu.vv v2, v2, v4 # vd overlap vs1
  1851. - vwmaccu.vv v2, v3, v4 # vd overlap vs1
  1852. - vwmaccu.vv v4, v2, v4 # vd overlap vs2
  1853. - vwmaccu.vv v4, v2, v5 # vd overlap vs2
  1854. - vwmaccu.vv v0, v2, v4, v0.t # vd overlap vm
  1855. -
  1856. - vwmacc.vv v0, v2, v4 # OK
  1857. - vwmacc.vv v1, v2, v4 # vd should be multiple of 2
  1858. - vwmacc.vv v2, v2, v4 # vd overlap vs1
  1859. - vwmacc.vv v2, v3, v4 # vd overlap vs1
  1860. - vwmacc.vv v4, v2, v4 # vd overlap vs2
  1861. - vwmacc.vv v4, v2, v5 # vd overlap vs2
  1862. - vwmacc.vv v0, v2, v4, v0.t # vd overlap vm
  1863. -
  1864. - vwmaccsu.vv v0, v2, v4 # OK
  1865. - vwmaccsu.vv v1, v2, v4 # vd should be multiple of 2
  1866. - vwmaccsu.vv v2, v2, v4 # vd overlap vs1
  1867. - vwmaccsu.vv v2, v3, v4 # vd overlap vs1
  1868. - vwmaccsu.vv v4, v2, v4 # vd overlap vs2
  1869. - vwmaccsu.vv v4, v2, v5 # vd overlap vs2
  1870. - vwmaccsu.vv v0, v2, v4, v0.t # vd overlap vm
  1871. -
  1872. - vqmaccu.vv v0, v4, v8 # OK
  1873. - vqmaccu.vv v2, v4, v8 # vd should be multiple of 4
  1874. - vqmaccu.vv v4, v4, v8 # vd overlap vs1
  1875. - vqmaccu.vv v4, v6, v8 # vd overlap vs1
  1876. - vqmaccu.vv v8, v4, v8 # vd overlap vs2
  1877. - vqmaccu.vv v8, v4, v10 # vd overlap vs2
  1878. - vqmaccu.vv v0, v4, v8, v0.t # vd overlap vm
  1879. -
  1880. - vqmacc.vv v0, v4, v8 # OK
  1881. - vqmacc.vv v2, v4, v8 # vd should be multiple of 4
  1882. - vqmacc.vv v4, v4, v8 # vd overlap vs1
  1883. - vqmacc.vv v4, v6, v8 # vd overlap vs1
  1884. - vqmacc.vv v8, v4, v8 # vd overlap vs2
  1885. - vqmacc.vv v8, v4, v10 # vd overlap vs2
  1886. - vqmacc.vv v0, v4, v8, v0.t # vd overlap vm
  1887. -
  1888. - vqmaccsu.vv v0, v4, v8 # OK
  1889. - vqmaccsu.vv v2, v4, v8 # vd should be multiple of 4
  1890. - vqmaccsu.vv v4, v4, v8 # vd overlap vs1
  1891. - vqmaccsu.vv v4, v6, v8 # vd overlap vs1
  1892. - vqmaccsu.vv v8, v4, v8 # vd overlap vs2
  1893. - vqmaccsu.vv v8, v4, v10 # vd overlap vs2
  1894. - vqmaccsu.vv v0, v4, v8, v0.t # vd overlap vm
  1895. -
  1896. - vfwadd.vv v0, v2, v4 # OK
  1897. - vfwadd.vv v1, v2, v4 # vd should be multiple of 2
  1898. - vfwadd.vv v2, v2, v4 # vd overlap vs2
  1899. - vfwadd.vv v2, v3, v4 # vd overlap vs2
  1900. - vfwadd.vv v4, v2, v4 # vd overlap vs1
  1901. - vfwadd.vv v4, v2, v5 # vd overlap vs1
  1902. - vfwadd.vv v0, v2, v4, v0.t # vd overlap vm
  1903. -
  1904. - vfwsub.vv v0, v2, v4 # OK
  1905. - vfwsub.vv v1, v2, v4 # vd should be multiple of 2
  1906. - vfwsub.vv v2, v2, v4 # vd overlap vs2
  1907. - vfwsub.vv v2, v3, v4 # vd overlap vs2
  1908. - vfwsub.vv v4, v2, v4 # vd overlap vs1
  1909. - vfwsub.vv v4, v2, v5 # vd overlap vs1
  1910. - vfwsub.vv v0, v2, v4, v0.t # vd overlap vm
  1911. -
  1912. - vfwmul.vv v0, v2, v4 # OK
  1913. - vfwmul.vv v1, v2, v4 # vd should be multiple of 2
  1914. - vfwmul.vv v2, v2, v4 # vd overlap vs2
  1915. - vfwmul.vv v2, v3, v4 # vd overlap vs2
  1916. - vfwmul.vv v4, v2, v4 # vd overlap vs1
  1917. - vfwmul.vv v4, v2, v5 # vd overlap vs1
  1918. - vfwmul.vv v0, v2, v4, v0.t # vd overlap vm
  1919. -
  1920. - vfwmacc.vv v0, v2, v4 # OK
  1921. - vfwmacc.vv v1, v2, v4 # vd should be multiple of 2
  1922. - vfwmacc.vv v2, v2, v4 # vd overlap vs1
  1923. - vfwmacc.vv v2, v3, v4 # vd overlap vs1
  1924. - vfwmacc.vv v4, v2, v4 # vd overlap vs2
  1925. - vfwmacc.vv v4, v2, v5 # vd overlap vs2
  1926. - vfwmacc.vv v0, v2, v4, v0.t # vd overlap vm
  1927. -
  1928. - vfwnmacc.vv v0, v2, v4 # OK
  1929. - vfwnmacc.vv v1, v2, v4 # vd should be multiple of 2
  1930. - vfwnmacc.vv v2, v2, v4 # vd overlap vs1
  1931. - vfwnmacc.vv v2, v3, v4 # vd overlap vs1
  1932. - vfwnmacc.vv v4, v2, v4 # vd overlap vs2
  1933. - vfwnmacc.vv v4, v2, v5 # vd overlap vs2
  1934. - vfwnmacc.vv v0, v2, v4, v0.t # vd overlap vm
  1935. -
  1936. - vfwmsac.vv v0, v2, v4 # OK
  1937. - vfwmsac.vv v1, v2, v4 # vd should be multiple of 2
  1938. - vfwmsac.vv v2, v2, v4 # vd overlap vs1
  1939. - vfwmsac.vv v2, v3, v4 # vd overlap vs1
  1940. - vfwmsac.vv v4, v2, v4 # vd overlap vs2
  1941. - vfwmsac.vv v4, v2, v5 # vd overlap vs2
  1942. - vfwmsac.vv v0, v2, v4, v0.t # vd overlap vm
  1943. -
  1944. - vfwnmsac.vv v0, v2, v4 # OK
  1945. - vfwnmsac.vv v1, v2, v4 # vd should be multiple of 2
  1946. - vfwnmsac.vv v2, v2, v4 # vd overlap vs1
  1947. - vfwnmsac.vv v2, v3, v4 # vd overlap vs1
  1948. - vfwnmsac.vv v4, v2, v4 # vd overlap vs2
  1949. - vfwnmsac.vv v4, v2, v5 # vd overlap vs2
  1950. - vfwnmsac.vv v0, v2, v4, v0.t # vd overlap vm
  1951. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.d b/gas/testsuite/gas/riscv/vector-insns-fail-03.d
  1952. deleted file mode 100644
  1953. index 1bfe441872..0000000000
  1954. --- a/gas/testsuite/gas/riscv/vector-insns-fail-03.d
  1955. +++ /dev/null
  1956. @@ -1,3 +0,0 @@
  1957. -#as: -march=rv32ifv_zvqmac -mcheck-constraints
  1958. -#source: vector-insns-fail-03.s
  1959. -#error_output: vector-insns-fail-03.l
  1960. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.l b/gas/testsuite/gas/riscv/vector-insns-fail-03.l
  1961. deleted file mode 100644
  1962. index 128e22726d..0000000000
  1963. --- a/gas/testsuite/gas/riscv/vector-insns-fail-03.l
  1964. +++ /dev/null
  1965. @@ -1,125 +0,0 @@
  1966. -.*: Assembler messages:
  1967. -.*Error: illegal operands `vwcvt.x.x.v v1,v2'
  1968. -.*Error: illegal operands `vwcvt.x.x.v v2,v2'
  1969. -.*Error: illegal operands `vwcvt.x.x.v v2,v3'
  1970. -.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
  1971. -.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
  1972. -.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
  1973. -.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
  1974. -.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
  1975. -.*Error: illegal operands `vwaddu.vx v1,v2,a1'
  1976. -.*Error: illegal operands `vwaddu.vx v2,v2,a1'
  1977. -.*Error: illegal operands `vwaddu.vx v2,v3,a1'
  1978. -.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
  1979. -.*Error: illegal operands `vwsubu.vx v1,v2,a1'
  1980. -.*Error: illegal operands `vwsubu.vx v2,v2,a1'
  1981. -.*Error: illegal operands `vwsubu.vx v2,v3,a1'
  1982. -.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
  1983. -.*Error: illegal operands `vwadd.vx v1,v2,a1'
  1984. -.*Error: illegal operands `vwadd.vx v2,v2,a1'
  1985. -.*Error: illegal operands `vwadd.vx v2,v3,a1'
  1986. -.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
  1987. -.*Error: illegal operands `vwsub.vx v1,v2,a1'
  1988. -.*Error: illegal operands `vwsub.vx v2,v2,a1'
  1989. -.*Error: illegal operands `vwsub.vx v2,v3,a1'
  1990. -.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
  1991. -.*Error: illegal operands `vwmul.vx v1,v2,a1'
  1992. -.*Error: illegal operands `vwmul.vx v2,v2,a1'
  1993. -.*Error: illegal operands `vwmul.vx v2,v3,a1'
  1994. -.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
  1995. -.*Error: illegal operands `vwmulu.vx v1,v2,a1'
  1996. -.*Error: illegal operands `vwmulu.vx v2,v2,a1'
  1997. -.*Error: illegal operands `vwmulu.vx v2,v3,a1'
  1998. -.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
  1999. -.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
  2000. -.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
  2001. -.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
  2002. -.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
  2003. -.*Error: illegal operands `vwmaccu.vx v1,a1,v4'
  2004. -.*Error: illegal operands `vwmaccu.vx v4,a1,v4'
  2005. -.*Error: illegal operands `vwmaccu.vx v4,a1,v5'
  2006. -.*Error: illegal operands `vwmaccu.vx v0,a1,v4,v0.t'
  2007. -.*Error: illegal operands `vwmacc.vx v1,a1,v4'
  2008. -.*Error: illegal operands `vwmacc.vx v4,a1,v4'
  2009. -.*Error: illegal operands `vwmacc.vx v4,a1,v5'
  2010. -.*Error: illegal operands `vwmacc.vx v0,a1,v4,v0.t'
  2011. -.*Error: illegal operands `vwmaccsu.vx v1,a1,v4'
  2012. -.*Error: illegal operands `vwmaccsu.vx v4,a1,v4'
  2013. -.*Error: illegal operands `vwmaccsu.vx v4,a1,v5'
  2014. -.*Error: illegal operands `vwmaccsu.vx v0,a1,v4,v0.t'
  2015. -.*Error: illegal operands `vwmaccus.vx v1,a1,v4'
  2016. -.*Error: illegal operands `vwmaccus.vx v4,a1,v4'
  2017. -.*Error: illegal operands `vwmaccus.vx v4,a1,v5'
  2018. -.*Error: illegal operands `vwmaccus.vx v0,a1,v4,v0.t'
  2019. -.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
  2020. -.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
  2021. -.*Error: illegal operands `vqmaccu.vx v4,a1,v6'
  2022. -.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
  2023. -.*Error: illegal operands `vqmacc.vx v2,a1,v4'
  2024. -.*Error: illegal operands `vqmacc.vx v4,a1,v4'
  2025. -.*Error: illegal operands `vqmacc.vx v4,a1,v6'
  2026. -.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
  2027. -.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
  2028. -.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
  2029. -.*Error: illegal operands `vqmaccsu.vx v4,a1,v6'
  2030. -.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
  2031. -.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
  2032. -.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
  2033. -.*Error: illegal operands `vqmaccus.vx v4,a1,v6'
  2034. -.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
  2035. -.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
  2036. -.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
  2037. -.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
  2038. -.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
  2039. -.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
  2040. -.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
  2041. -.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
  2042. -.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
  2043. -.*Error: illegal operands `vfwmul.vf v1,v2,fa1'
  2044. -.*Error: illegal operands `vfwmul.vf v2,v2,fa1'
  2045. -.*Error: illegal operands `vfwmul.vf v2,v3,fa1'
  2046. -.*Error: illegal operands `vfwmul.vf v0,v2,fa1,v0.t'
  2047. -.*Error: illegal operands `vfwmacc.vf v1,fa1,v4'
  2048. -.*Error: illegal operands `vfwmacc.vf v4,fa1,v4'
  2049. -.*Error: illegal operands `vfwmacc.vf v4,fa1,v5'
  2050. -.*Error: illegal operands `vfwmacc.vf v0,fa1,v4,v0.t'
  2051. -.*Error: illegal operands `vfwnmacc.vf v1,fa1,v4'
  2052. -.*Error: illegal operands `vfwnmacc.vf v4,fa1,v4'
  2053. -.*Error: illegal operands `vfwnmacc.vf v4,fa1,v5'
  2054. -.*Error: illegal operands `vfwnmacc.vf v0,fa1,v4,v0.t'
  2055. -.*Error: illegal operands `vfwmsac.vf v1,fa1,v4'
  2056. -.*Error: illegal operands `vfwmsac.vf v4,fa1,v4'
  2057. -.*Error: illegal operands `vfwmsac.vf v4,fa1,v5'
  2058. -.*Error: illegal operands `vfwmsac.vf v0,fa1,v4,v0.t'
  2059. -.*Error: illegal operands `vfwnmsac.vf v1,fa1,v4'
  2060. -.*Error: illegal operands `vfwnmsac.vf v4,fa1,v4'
  2061. -.*Error: illegal operands `vfwnmsac.vf v4,fa1,v5'
  2062. -.*Error: illegal operands `vfwnmsac.vf v0,fa1,v4,v0.t'
  2063. -.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
  2064. -.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
  2065. -.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
  2066. -.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
  2067. -.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
  2068. -.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
  2069. -.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
  2070. -.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
  2071. -.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
  2072. -.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
  2073. -.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
  2074. -.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
  2075. -.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
  2076. -.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
  2077. -.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
  2078. -.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
  2079. -.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
  2080. -.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
  2081. -.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
  2082. -.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
  2083. -.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
  2084. -.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
  2085. -.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
  2086. -.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
  2087. -.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
  2088. -.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
  2089. -.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
  2090. -.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
  2091. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.s b/gas/testsuite/gas/riscv/vector-insns-fail-03.s
  2092. deleted file mode 100644
  2093. index 9450b9ceb0..0000000000
  2094. --- a/gas/testsuite/gas/riscv/vector-insns-fail-03.s
  2095. +++ /dev/null
  2096. @@ -1,187 +0,0 @@
  2097. -# Widening Vector Arithmetic Instructions (V[X|F])
  2098. -
  2099. - vwcvt.x.x.v v0, v2 # OK
  2100. - vwcvt.x.x.v v1, v2 # vd should be multiple of 2
  2101. - vwcvt.x.x.v v2, v2 # vd overlap vs2
  2102. - vwcvt.x.x.v v2, v3 # vd overlap vs2
  2103. - vwcvt.x.x.v v0, v2, v0.t # vd overlap vm
  2104. -
  2105. - vwcvtu.x.x.v v0, v2 # OK
  2106. - vwcvtu.x.x.v v1, v2 # vd should be multiple of 2
  2107. - vwcvtu.x.x.v v2, v2 # vd overlap vs2
  2108. - vwcvtu.x.x.v v2, v3 # vd overlap vs2
  2109. - vwcvtu.x.x.v v0, v2, v0.t # vd overlap vm
  2110. -
  2111. - vwaddu.vx v0, v2, a1 # OK
  2112. - vwaddu.vx v1, v2, a1 # vd should be multiple of 2
  2113. - vwaddu.vx v2, v2, a1 # vd overlap vs2
  2114. - vwaddu.vx v2, v3, a1 # vd overlap vs2
  2115. - vwaddu.vx v0, v2, a1, v0.t # vd overlap vm
  2116. -
  2117. - vwsubu.vx v0, v2, a1 # OK
  2118. - vwsubu.vx v1, v2, a1 # vd should be multiple of 2
  2119. - vwsubu.vx v2, v2, a1 # vd overlap vs2
  2120. - vwsubu.vx v2, v3, a1 # vd overlap vs2
  2121. - vwsubu.vx v0, v2, a1, v0.t # vd overlap vm
  2122. -
  2123. - vwadd.vx v0, v2, a1 # OK
  2124. - vwadd.vx v1, v2, a1 # vd should be multiple of 2
  2125. - vwadd.vx v2, v2, a1 # vd overlap vs2
  2126. - vwadd.vx v2, v3, a1 # vd overlap vs2
  2127. - vwadd.vx v0, v2, a1, v0.t # vd overlap vm
  2128. -
  2129. - vwsub.vx v0, v2, a1 # OK
  2130. - vwsub.vx v1, v2, a1 # vd should be multiple of 2
  2131. - vwsub.vx v2, v2, a1 # vd overlap vs2
  2132. - vwsub.vx v2, v3, a1 # vd overlap vs2
  2133. - vwsub.vx v0, v2, a1, v0.t # vd overlap vm
  2134. -
  2135. - vwmul.vx v0, v2, a1 # OK
  2136. - vwmul.vx v1, v2, a1 # vd should be multiple of 2
  2137. - vwmul.vx v2, v2, a1 # vd overlap vs2
  2138. - vwmul.vx v2, v3, a1 # vd overlap vs2
  2139. - vwmul.vx v0, v2, a1, v0.t # vd overlap vm
  2140. -
  2141. - vwmulu.vx v0, v2, a1 # OK
  2142. - vwmulu.vx v1, v2, a1 # vd should be multiple of 2
  2143. - vwmulu.vx v2, v2, a1 # vd overlap vs2
  2144. - vwmulu.vx v2, v3, a1 # vd overlap vs2
  2145. - vwmulu.vx v0, v2, a1, v0.t # vd overlap vm
  2146. -
  2147. - vwmulsu.vx v0, v2, a1 # OK
  2148. - vwmulsu.vx v1, v2, a1 # vd should be multiple of 2
  2149. - vwmulsu.vx v2, v2, a1 # vd overlap vs2
  2150. - vwmulsu.vx v2, v3, a1 # vd overlap vs2
  2151. - vwmulsu.vx v0, v2, a1, v0.t # vd overlap vm
  2152. -
  2153. - vwmaccu.vx v0, a1, v4 # OK
  2154. - vwmaccu.vx v1, a1, v4 # vd should be multiple of 2
  2155. - vwmaccu.vx v4, a1, v4 # vd overlap vs2
  2156. - vwmaccu.vx v4, a1, v5 # vd overlap vs2
  2157. - vwmaccu.vx v0, a1, v4, v0.t # vd overlap vm
  2158. -
  2159. - vwmacc.vx v0, a1, v4 # OK
  2160. - vwmacc.vx v1, a1, v4 # vd should be multiple of 2
  2161. - vwmacc.vx v4, a1, v4 # vd overlap vs2
  2162. - vwmacc.vx v4, a1, v5 # vd overlap vs2
  2163. - vwmacc.vx v0, a1, v4, v0.t # vd overlap vm
  2164. -
  2165. - vwmaccsu.vx v0, a1, v4 # OK
  2166. - vwmaccsu.vx v1, a1, v4 # vd should be multiple of 2
  2167. - vwmaccsu.vx v4, a1, v4 # vd overlap vs2
  2168. - vwmaccsu.vx v4, a1, v5 # vd overlap vs2
  2169. - vwmaccsu.vx v0, a1, v4, v0.t # vd overlap vm
  2170. -
  2171. - vwmaccus.vx v0, a1, v4 # OK
  2172. - vwmaccus.vx v1, a1, v4 # vd should be multiple of 2
  2173. - vwmaccus.vx v4, a1, v4 # vd overlap vs2
  2174. - vwmaccus.vx v4, a1, v5 # vd overlap vs2
  2175. - vwmaccus.vx v0, a1, v4, v0.t # vd overlap vm
  2176. -
  2177. - vqmaccu.vx v0, a1, v4 # OK
  2178. - vqmaccu.vx v2, a1, v4 # vd should be multiple of 4
  2179. - vqmaccu.vx v4, a1, v4 # vd overlap vs2
  2180. - vqmaccu.vx v4, a1, v6 # vd overlap vs2
  2181. - vqmaccu.vx v0, a1, v4, v0.t # vd overlap vm
  2182. -
  2183. - vqmacc.vx v0, a1, v4 # OK
  2184. - vqmacc.vx v2, a1, v4 # vd should be multiple of 4
  2185. - vqmacc.vx v4, a1, v4 # vd overlap vs2
  2186. - vqmacc.vx v4, a1, v6 # vd overlap vs2
  2187. - vqmacc.vx v0, a1, v4, v0.t # vd overlap vm
  2188. -
  2189. - vqmaccsu.vx v0, a1, v4 # OK
  2190. - vqmaccsu.vx v2, a1, v4 # vd should be multiple of 4
  2191. - vqmaccsu.vx v4, a1, v4 # vd overlap vs2
  2192. - vqmaccsu.vx v4, a1, v6 # vd overlap vs2
  2193. - vqmaccsu.vx v0, a1, v4, v0.t # vd overlap vm
  2194. -
  2195. - vqmaccus.vx v0, a1, v4 # OK
  2196. - vqmaccus.vx v2, a1, v4 # vd should be multiple of 4
  2197. - vqmaccus.vx v4, a1, v4 # vd overlap vs2
  2198. - vqmaccus.vx v4, a1, v6 # vd overlap vs2
  2199. - vqmaccus.vx v0, a1, v4, v0.t # vd overlap vm
  2200. -
  2201. - vfwadd.vf v0, v2, fa1 # OK
  2202. - vfwadd.vf v1, v2, fa1 # vd should be multiple of 2
  2203. - vfwadd.vf v2, v2, fa1 # vd overlap vs2
  2204. - vfwadd.vf v2, v3, fa1 # vd overlap vs2
  2205. - vfwadd.vf v0, v2, fa1, v0.t # vd overlap vm
  2206. -
  2207. - vfwsub.vf v0, v2, fa1 # OK
  2208. - vfwsub.vf v1, v2, fa1 # vd should be multiple of 2
  2209. - vfwsub.vf v2, v2, fa1 # vd overlap vs2
  2210. - vfwsub.vf v2, v3, fa1 # vd overlap vs2
  2211. - vfwsub.vf v0, v2, fa1, v0.t # vd overlap vm
  2212. -
  2213. - vfwmul.vf v0, v2, fa1 # OK
  2214. - vfwmul.vf v1, v2, fa1 # vd should be multiple of 2
  2215. - vfwmul.vf v2, v2, fa1 # vd overlap vs2
  2216. - vfwmul.vf v2, v3, fa1 # vd overlap vs2
  2217. - vfwmul.vf v0, v2, fa1, v0.t # vd overlap vm
  2218. -
  2219. - vfwmacc.vf v0, fa1, v4 # OK
  2220. - vfwmacc.vf v1, fa1, v4 # vd should be multiple of 2
  2221. - vfwmacc.vf v4, fa1, v4 # vd overlap vs2
  2222. - vfwmacc.vf v4, fa1, v5 # vd overlap vs2
  2223. - vfwmacc.vf v0, fa1, v4, v0.t # vd overlap vm
  2224. -
  2225. - vfwnmacc.vf v0, fa1, v4 # OK
  2226. - vfwnmacc.vf v1, fa1, v4 # vd should be multiple of 2
  2227. - vfwnmacc.vf v4, fa1, v4 # vd overlap vs2
  2228. - vfwnmacc.vf v4, fa1, v5 # vd overlap vs2
  2229. - vfwnmacc.vf v0, fa1, v4, v0.t # vd overlap vm
  2230. -
  2231. - vfwmsac.vf v0, fa1, v4 # OK
  2232. - vfwmsac.vf v1, fa1, v4 # vd should be multiple of 2
  2233. - vfwmsac.vf v4, fa1, v4 # vd overlap vs2
  2234. - vfwmsac.vf v4, fa1, v5 # vd overlap vs2
  2235. - vfwmsac.vf v0, fa1, v4, v0.t # vd overlap vm
  2236. -
  2237. - vfwnmsac.vf v0, fa1, v4 # OK
  2238. - vfwnmsac.vf v1, fa1, v4 # vd should be multiple of 2
  2239. - vfwnmsac.vf v4, fa1, v4 # vd overlap vs2
  2240. - vfwnmsac.vf v4, fa1, v5 # vd overlap vs2
  2241. - vfwnmsac.vf v0, fa1, v4, v0.t # vd overlap vm
  2242. -
  2243. - vfwcvt.xu.f.v v0, v2 # OK
  2244. - vfwcvt.xu.f.v v1, v2 # vd should be multiple of 2
  2245. - vfwcvt.xu.f.v v2, v2 # vd overlap vs2
  2246. - vfwcvt.xu.f.v v2, v3 # vd overlap vs2
  2247. - vfwcvt.xu.f.v v0, v2, v0.t # vd overlap vm
  2248. -
  2249. - vfwcvt.x.f.v v0, v2 # OK
  2250. - vfwcvt.x.f.v v1, v2 # vd should be multiple of 2
  2251. - vfwcvt.x.f.v v2, v2 # vd overlap vs2
  2252. - vfwcvt.x.f.v v2, v3 # vd overlap vs2
  2253. - vfwcvt.x.f.v v0, v2, v0.t # vd overlap vm
  2254. -
  2255. - vfwcvt.rtz.xu.f.v v0, v2 # OK
  2256. - vfwcvt.rtz.xu.f.v v1, v2 # vd should be multiple of 2
  2257. - vfwcvt.rtz.xu.f.v v2, v2 # vd overlap vs2
  2258. - vfwcvt.rtz.xu.f.v v2, v3 # vd overlap vs2
  2259. - vfwcvt.rtz.xu.f.v v0, v2, v0.t # vd overlap vm
  2260. -
  2261. - vfwcvt.rtz.x.f.v v0, v2 # OK
  2262. - vfwcvt.rtz.x.f.v v1, v2 # vd should be multiple of 2
  2263. - vfwcvt.rtz.x.f.v v2, v2 # vd overlap vs2
  2264. - vfwcvt.rtz.x.f.v v2, v3 # vd overlap vs2
  2265. - vfwcvt.rtz.x.f.v v0, v2, v0.t # vd overlap vm
  2266. -
  2267. - vfwcvt.f.xu.v v0, v2 # OK
  2268. - vfwcvt.f.xu.v v1, v2 # vd should be multiple of 2
  2269. - vfwcvt.f.xu.v v2, v2 # vd overlap vs2
  2270. - vfwcvt.f.xu.v v2, v3 # vd overlap vs2
  2271. - vfwcvt.f.xu.v v0, v2, v0.t # vd overlap vm
  2272. -
  2273. - vfwcvt.f.x.v v0, v2 # OK
  2274. - vfwcvt.f.x.v v1, v2 # vd should be multiple of 2
  2275. - vfwcvt.f.x.v v2, v2 # vd overlap vs2
  2276. - vfwcvt.f.x.v v2, v3 # vd overlap vs2
  2277. - vfwcvt.f.x.v v0, v2, v0.t # vd overlap vm
  2278. -
  2279. - vfwcvt.f.f.v v0, v2 # OK
  2280. - vfwcvt.f.f.v v1, v2 # vd should be multiple of 2
  2281. - vfwcvt.f.f.v v2, v2 # vd overlap vs2
  2282. - vfwcvt.f.f.v v2, v3 # vd overlap vs2
  2283. - vfwcvt.f.f.v v0, v2, v0.t # vd overlap vm
  2284. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.d b/gas/testsuite/gas/riscv/vector-insns-fail-04.d
  2285. deleted file mode 100644
  2286. index d483884544..0000000000
  2287. --- a/gas/testsuite/gas/riscv/vector-insns-fail-04.d
  2288. +++ /dev/null
  2289. @@ -1,3 +0,0 @@
  2290. -#as: -march=rv32ifv -mcheck-constraints
  2291. -#source: vector-insns-fail-04.s
  2292. -#error_output: vector-insns-fail-04.l
  2293. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.l b/gas/testsuite/gas/riscv/vector-insns-fail-04.l
  2294. deleted file mode 100644
  2295. index 9a9c76c19d..0000000000
  2296. --- a/gas/testsuite/gas/riscv/vector-insns-fail-04.l
  2297. +++ /dev/null
  2298. @@ -1,49 +0,0 @@
  2299. -.*: Assembler messages:
  2300. -.*Error: illegal operands `vwaddu.wv v1,v2,v4'
  2301. -.*Error: illegal operands `vwaddu.wv v2,v3,v4'
  2302. -.*Error: illegal operands `vwaddu.wv v4,v2,v4'
  2303. -.*Error: illegal operands `vwaddu.wv v4,v2,v5'
  2304. -.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
  2305. -.*Error: illegal operands `vwsubu.wv v1,v2,v4'
  2306. -.*Error: illegal operands `vwsubu.wv v2,v3,v4'
  2307. -.*Error: illegal operands `vwsubu.wv v4,v2,v4'
  2308. -.*Error: illegal operands `vwsubu.wv v4,v2,v5'
  2309. -.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
  2310. -.*Error: illegal operands `vwadd.wv v1,v2,v4'
  2311. -.*Error: illegal operands `vwadd.wv v2,v3,v4'
  2312. -.*Error: illegal operands `vwadd.wv v4,v2,v4'
  2313. -.*Error: illegal operands `vwadd.wv v4,v2,v5'
  2314. -.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
  2315. -.*Error: illegal operands `vwsub.wv v1,v2,v4'
  2316. -.*Error: illegal operands `vwsub.wv v2,v3,v4'
  2317. -.*Error: illegal operands `vwsub.wv v4,v2,v4'
  2318. -.*Error: illegal operands `vwsub.wv v4,v2,v5'
  2319. -.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
  2320. -.*Error: illegal operands `vfwadd.wv v1,v2,v4'
  2321. -.*Error: illegal operands `vfwadd.wv v2,v3,v4'
  2322. -.*Error: illegal operands `vfwadd.wv v4,v2,v4'
  2323. -.*Error: illegal operands `vfwadd.wv v4,v2,v5'
  2324. -.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
  2325. -.*Error: illegal operands `vfwsub.wv v1,v2,v4'
  2326. -.*Error: illegal operands `vfwsub.wv v2,v3,v4'
  2327. -.*Error: illegal operands `vfwsub.wv v4,v2,v4'
  2328. -.*Error: illegal operands `vfwsub.wv v4,v2,v5'
  2329. -.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
  2330. -.*Error: illegal operands `vwaddu.wx v1,v2,a1'
  2331. -.*Error: illegal operands `vwaddu.wx v2,v3,a1'
  2332. -.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
  2333. -.*Error: illegal operands `vwsubu.wx v1,v2,a1'
  2334. -.*Error: illegal operands `vwsubu.wx v2,v3,a1'
  2335. -.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
  2336. -.*Error: illegal operands `vwadd.wx v1,v2,a1'
  2337. -.*Error: illegal operands `vwadd.wx v2,v3,a1'
  2338. -.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
  2339. -.*Error: illegal operands `vwsub.wx v1,v2,a1'
  2340. -.*Error: illegal operands `vwsub.wx v2,v3,a1'
  2341. -.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
  2342. -.*Error: illegal operands `vfwadd.wf v1,v2,fa1'
  2343. -.*Error: illegal operands `vfwadd.wf v2,v3,fa1'
  2344. -.*Error: illegal operands `vfwadd.wf v0,v2,fa1,v0.t'
  2345. -.*Error: illegal operands `vfwsub.wf v1,v2,fa1'
  2346. -.*Error: illegal operands `vfwsub.wf v2,v3,fa1'
  2347. -.*Error: illegal operands `vfwsub.wf v0,v2,fa1,v0.t'
  2348. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.s b/gas/testsuite/gas/riscv/vector-insns-fail-04.s
  2349. deleted file mode 100644
  2350. index e1db16d53b..0000000000
  2351. --- a/gas/testsuite/gas/riscv/vector-insns-fail-04.s
  2352. +++ /dev/null
  2353. @@ -1,85 +0,0 @@
  2354. -# Widening Vector Arithmetic Instructions (W[V|X])
  2355. -
  2356. - vwaddu.wv v0, v2, v4 # OK
  2357. - vwaddu.wv v1, v2, v4 # vd should be multiple of 2
  2358. - vwaddu.wv v2, v2, v4 # OK
  2359. - vwaddu.wv v2, v3, v4 # vs2 should be multiple of 2
  2360. - vwaddu.wv v4, v2, v4 # vd overlap vs1
  2361. - vwaddu.wv v4, v2, v5 # vd overlap vs1
  2362. - vwaddu.wv v0, v2, v4, v0.t # vd overlap vm
  2363. -
  2364. - vwsubu.wv v0, v2, v4 # OK
  2365. - vwsubu.wv v1, v2, v4 # vd should be multiple of 2
  2366. - vwsubu.wv v2, v2, v4 # OK
  2367. - vwsubu.wv v2, v3, v4 # vs2 should be multiple of 2
  2368. - vwsubu.wv v4, v2, v4 # vd overlap vs1
  2369. - vwsubu.wv v4, v2, v5 # vd overlap vs1
  2370. - vwsubu.wv v0, v2, v4, v0.t # vd overlap vm
  2371. -
  2372. - vwadd.wv v0, v2, v4 # OK
  2373. - vwadd.wv v1, v2, v4 # vd should be multiple of 2
  2374. - vwadd.wv v2, v2, v4 # OK
  2375. - vwadd.wv v2, v3, v4 # vs2 should be multiple of 2
  2376. - vwadd.wv v4, v2, v4 # vd overlap vs1
  2377. - vwadd.wv v4, v2, v5 # vd overlap vs1
  2378. - vwadd.wv v0, v2, v4, v0.t # vd overlap vm
  2379. -
  2380. - vwsub.wv v0, v2, v4 # OK
  2381. - vwsub.wv v1, v2, v4 # vd should be multiple of 2
  2382. - vwsub.wv v2, v2, v4 # OK
  2383. - vwsub.wv v2, v3, v4 # vs2 should be multiple of 2
  2384. - vwsub.wv v4, v2, v4 # vd overlap vs1
  2385. - vwsub.wv v4, v2, v5 # vd overlap vs1
  2386. - vwsub.wv v0, v2, v4, v0.t # vd overlap vm
  2387. -
  2388. - vfwadd.wv v0, v2, v4 # OK
  2389. - vfwadd.wv v1, v2, v4 # vd should be multiple of 2
  2390. - vfwadd.wv v2, v2, v4 # OK
  2391. - vfwadd.wv v2, v3, v4 # vs2 should be multiple of 2
  2392. - vfwadd.wv v4, v2, v4 # vd overlap vs1
  2393. - vfwadd.wv v4, v2, v5 # vd overlap vs1
  2394. - vfwadd.wv v0, v2, v4, v0.t # vd overlap vm
  2395. -
  2396. - vfwsub.wv v0, v2, v4 # OK
  2397. - vfwsub.wv v1, v2, v4 # vd should be multiple of 2
  2398. - vfwsub.wv v2, v2, v4 # OK
  2399. - vfwsub.wv v2, v3, v4 # vs2 should be multiple of 2
  2400. - vfwsub.wv v4, v2, v4 # vd overlap vs1
  2401. - vfwsub.wv v4, v2, v5 # vd overlap vs1
  2402. - vfwsub.wv v0, v2, v4, v0.t # vd overlap vm
  2403. -
  2404. - vwaddu.wx v0, v2, a1 # OK
  2405. - vwaddu.wx v1, v2, a1 # vd should be multiple of 2
  2406. - vwaddu.wx v2, v2, a1 # OK
  2407. - vwaddu.wx v2, v3, a1 # vs2 should be multiple of 2
  2408. - vwaddu.wx v0, v2, a1, v0.t # vd overlap vm
  2409. -
  2410. - vwsubu.wx v0, v2, a1 # OK
  2411. - vwsubu.wx v1, v2, a1 # vd should be multiple of 2
  2412. - vwsubu.wx v2, v2, a1 # OK
  2413. - vwsubu.wx v2, v3, a1 # vs2 should be multiple of 2
  2414. - vwsubu.wx v0, v2, a1, v0.t # vd overlap vm
  2415. -
  2416. - vwadd.wx v0, v2, a1 # OK
  2417. - vwadd.wx v1, v2, a1 # vd should be multiple of 2
  2418. - vwadd.wx v2, v2, a1 # OK
  2419. - vwadd.wx v2, v3, a1 # vs2 should be multiple of 2
  2420. - vwadd.wx v0, v2, a1, v0.t # vd overlap vm
  2421. -
  2422. - vwsub.wx v0, v2, a1 # OK
  2423. - vwsub.wx v1, v2, a1 # vd should be multiple of 2
  2424. - vwsub.wx v2, v2, a1 # OK
  2425. - vwsub.wx v2, v3, a1 # vs2 should be multiple of 2
  2426. - vwsub.wx v0, v2, a1, v0.t # vd overlap vm
  2427. -
  2428. - vfwadd.wf v0, v2, fa1 # OK
  2429. - vfwadd.wf v1, v2, fa1 # vd should be multiple of 2
  2430. - vfwadd.wf v2, v2, fa1 # OK
  2431. - vfwadd.wf v2, v3, fa1 # vs2 should be multiple of 2
  2432. - vfwadd.wf v0, v2, fa1, v0.t # vd overlap vm
  2433. -
  2434. - vfwsub.wf v0, v2, fa1 # OK
  2435. - vfwsub.wf v1, v2, fa1 # vd should be multiple of 2
  2436. - vfwsub.wf v2, v2, fa1 # OK
  2437. - vfwsub.wf v2, v3, fa1 # vs2 should be multiple of 2
  2438. - vfwsub.wf v0, v2, fa1, v0.t # vd overlap vm
  2439. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.d b/gas/testsuite/gas/riscv/vector-insns-fail-05.d
  2440. deleted file mode 100644
  2441. index b13053ab06..0000000000
  2442. --- a/gas/testsuite/gas/riscv/vector-insns-fail-05.d
  2443. +++ /dev/null
  2444. @@ -1,3 +0,0 @@
  2445. -#as: -march=rv32ifv -mcheck-constraints
  2446. -#source: vector-insns-fail-05.s
  2447. -#error_output: vector-insns-fail-05.l
  2448. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.s b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
  2449. deleted file mode 100644
  2450. index 6b68680fd9..0000000000
  2451. --- a/gas/testsuite/gas/riscv/vector-insns-fail-05.s
  2452. +++ /dev/null
  2453. @@ -1,139 +0,0 @@
  2454. -# Narrowing Vector Arithmetic Instructions
  2455. -
  2456. - vncvt.x.x.v v0, v2 # OK
  2457. - vncvt.x.x.v v2, v2 # vd overlap vs2
  2458. - vncvt.x.x.v v2, v3 # vs2 should be multiple of 2
  2459. - vncvt.x.x.v v3, v2 # vd overlap vs2
  2460. - vncvt.x.x.v v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  2461. -
  2462. - vnsrl.wv v0, v2, v4 # OK
  2463. - vnsrl.wv v2, v2, v4 # vd overlap vs2
  2464. - vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
  2465. - vnsrl.wv v3, v2, v4 # vd overlap vs2
  2466. - vnsrl.wv v4, v2, v4 # OK
  2467. - vnsrl.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
  2468. -
  2469. - vnsrl.wx v0, v2, a1 # OK
  2470. - vnsrl.wx v2, v2, a1 # vd overlap vs2
  2471. - vnsrl.wx v2, v3, a1 # vs2 should be multiple of 2
  2472. - vnsrl.wx v3, v2, a1 # vd overlap vs2
  2473. - vnsrl.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
  2474. -
  2475. - vnsrl.wi v0, v2, 1 # OK
  2476. - vnsrl.wi v2, v2, 1 # vd overlap vs2
  2477. - vnsrl.wi v2, v3, 1 # vs2 should be multiple of 2
  2478. - vnsrl.wi v3, v2, 1 # vd overlap vs2
  2479. - vnsrl.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
  2480. -
  2481. - vnsra.wv v0, v2, v4 # OK
  2482. - vnsra.wv v2, v2, v4 # vd overlap vs2
  2483. - vnsra.wv v2, v3, v4 # vs2 should be multiple of 2
  2484. - vnsra.wv v3, v2, v4 # vd overlap vs2
  2485. - vnsra.wv v4, v2, v4 # OK
  2486. - vnsra.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
  2487. -
  2488. - vnsra.wx v0, v2, a1 # OK
  2489. - vnsra.wx v2, v2, a1 # vd overlap vs2
  2490. - vnsra.wx v2, v3, a1 # vs2 should be multiple of 2
  2491. - vnsra.wx v3, v2, a1 # vd overlap vs2
  2492. - vnsra.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
  2493. -
  2494. - vnsra.wi v0, v2, 1 # OK
  2495. - vnsra.wi v2, v2, 1 # vd overlap vs2
  2496. - vnsra.wi v2, v3, 1 # vs2 should be multiple of 2
  2497. - vnsra.wi v3, v2, 1 # vd overlap vs2
  2498. - vnsra.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
  2499. -
  2500. - vnclipu.wv v0, v2, v4 # OK
  2501. - vnclipu.wv v2, v2, v4 # vd overlap vs2
  2502. - vnclipu.wv v2, v3, v4 # vs2 should be multiple of 2
  2503. - vnclipu.wv v3, v2, v4 # vd overlap vs2
  2504. - vnclipu.wv v4, v2, v4 # OK
  2505. - vnclipu.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
  2506. -
  2507. - vnclipu.wx v0, v2, a1 # OK
  2508. - vnclipu.wx v2, v2, a1 # vd overlap vs2
  2509. - vnclipu.wx v2, v3, a1 # vs2 should be multiple of 2
  2510. - vnclipu.wx v3, v2, a1 # vd overlap vs2
  2511. - vnclipu.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
  2512. -
  2513. - vnclipu.wi v0, v2, 1 # OK
  2514. - vnclipu.wi v2, v2, 1 # vd overlap vs2
  2515. - vnclipu.wi v2, v3, 1 # vs2 should be multiple of 2
  2516. - vnclipu.wi v3, v2, 1 # vd overlap vs2
  2517. - vnclipu.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
  2518. -
  2519. - vnclip.wv v0, v2, v4 # OK
  2520. - vnclip.wv v2, v2, v4 # vd overlap vs2
  2521. - vnclip.wv v2, v3, v4 # vs2 should be multiple of 2
  2522. - vnclip.wv v3, v2, v4 # vd overlap vs2
  2523. - vnclip.wv v4, v2, v4 # OK
  2524. - vnclip.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
  2525. -
  2526. - vnclip.wx v0, v2, a1 # OK
  2527. - vnclip.wx v2, v2, a1 # vd overlap vs2
  2528. - vnclip.wx v2, v3, a1 # vs2 should be multiple of 2
  2529. - vnclip.wx v3, v2, a1 # vd overlap vs2
  2530. - vnclip.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
  2531. -
  2532. - vnclip.wi v0, v2, 1 # OK
  2533. - vnclip.wi v2, v2, 1 # vd overlap vs2
  2534. - vnclip.wi v2, v3, 1 # vs2 should be multiple of 2
  2535. - vnclip.wi v3, v2, 1 # vd overlap vs2
  2536. - vnclip.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
  2537. -
  2538. - vfncvt.xu.f.w v0, v2 # OK
  2539. - vfncvt.xu.f.w v2, v2 # vd overlap vs2
  2540. - vfncvt.xu.f.w v2, v3 # vs2 should be multiple of 2
  2541. - vfncvt.xu.f.w v3, v2 # vd overlap vs2
  2542. - vfncvt.xu.f.w v4, v2 # OK
  2543. - vfncvt.xu.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  2544. -
  2545. - vfncvt.x.f.w v0, v2 # OK
  2546. - vfncvt.x.f.w v2, v2 # vd overlap vs2
  2547. - vfncvt.x.f.w v2, v3 # vs2 should be multiple of 2
  2548. - vfncvt.x.f.w v3, v2 # vd overlap vs2
  2549. - vfncvt.x.f.w v4, v2 # OK
  2550. - vfncvt.x.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  2551. -
  2552. - vfncvt.rtz.xu.f.w v0, v2 # OK
  2553. - vfncvt.rtz.xu.f.w v2, v2 # vd overlap vs2
  2554. - vfncvt.rtz.xu.f.w v2, v3 # vs2 should be multiple of 2
  2555. - vfncvt.rtz.xu.f.w v3, v2 # vd overlap vs2
  2556. - vfncvt.rtz.xu.f.w v4, v2 # OK
  2557. - vfncvt.rtz.xu.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  2558. -
  2559. - vfncvt.rtz.x.f.w v0, v2 # OK
  2560. - vfncvt.rtz.x.f.w v2, v2 # vd overlap vs2
  2561. - vfncvt.rtz.x.f.w v2, v3 # vs2 should be multiple of 2
  2562. - vfncvt.rtz.x.f.w v3, v2 # vd overlap vs2
  2563. - vfncvt.rtz.x.f.w v4, v2 # OK
  2564. - vfncvt.rtz.x.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  2565. -
  2566. - vfncvt.f.xu.w v0, v2 # OK
  2567. - vfncvt.f.xu.w v2, v2 # vd overlap vs2
  2568. - vfncvt.f.xu.w v2, v3 # vs2 should be multiple of 2
  2569. - vfncvt.f.xu.w v3, v2 # vd overlap vs2
  2570. - vfncvt.f.xu.w v4, v2 # OK
  2571. - vfncvt.f.xu.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  2572. -
  2573. - vfncvt.f.x.w v0, v2 # OK
  2574. - vfncvt.f.x.w v2, v2 # vd overlap vs2
  2575. - vfncvt.f.x.w v2, v3 # vs2 should be multiple of 2
  2576. - vfncvt.f.x.w v3, v2 # vd overlap vs2
  2577. - vfncvt.f.x.w v4, v2 # OK
  2578. - vfncvt.f.x.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  2579. -
  2580. - vfncvt.f.f.w v0, v2 # OK
  2581. - vfncvt.f.f.w v2, v2 # vd overlap vs2
  2582. - vfncvt.f.f.w v2, v3 # vs2 should be multiple of 2
  2583. - vfncvt.f.f.w v3, v2 # vd overlap vs2
  2584. - vfncvt.f.f.w v4, v2 # OK
  2585. - vfncvt.f.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  2586. -
  2587. - vfncvt.rod.f.f.w v0, v2 # OK
  2588. - vfncvt.rod.f.f.w v2, v2 # vd overlap vs2
  2589. - vfncvt.rod.f.f.w v2, v3 # vs2 should be multiple of 2
  2590. - vfncvt.rod.f.f.w v3, v2 # vd overlap vs2
  2591. - vfncvt.rod.f.f.w v4, v2 # OK
  2592. - vfncvt.rod.f.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
  2593. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.d b/gas/testsuite/gas/riscv/vector-insns-fail-06.d
  2594. deleted file mode 100644
  2595. index a2a2220d68..0000000000
  2596. --- a/gas/testsuite/gas/riscv/vector-insns-fail-06.d
  2597. +++ /dev/null
  2598. @@ -1,3 +0,0 @@
  2599. -#as: -march=rv32ifv -mcheck-constraints
  2600. -#source: vector-insns-fail-06.s
  2601. -#error_output: vector-insns-fail-06.l
  2602. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.l b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
  2603. deleted file mode 100644
  2604. index 4c540eb272..0000000000
  2605. --- a/gas/testsuite/gas/riscv/vector-insns-fail-06.l
  2606. +++ /dev/null
  2607. @@ -1,25 +0,0 @@
  2608. -.*: Assembler messages:
  2609. -.*Error: illegal operands `viota.m v2,v2'
  2610. -.*Error: illegal operands `viota.m v0,v2,v0.t'
  2611. -.*Error: illegal operands `vslideup.vx v2,v2,a4'
  2612. -.*Error: illegal operands `vslideup.vi v2,v2,1'
  2613. -.*Error: illegal operands `vslide1up.vx v2,v2,a4'
  2614. -.*Error: illegal operands `vfslide1up.vf v2,v2,fa4'
  2615. -.*Error: illegal operands `vrgather.vv v2,v2,v4'
  2616. -.*Error: illegal operands `vrgather.vv v4,v2,v4'
  2617. -.*Error: illegal operands `vrgather.vv v0,v2,v4,v0.t'
  2618. -.*Error: illegal operands `vrgather.vx v2,v2,a4'
  2619. -.*Error: illegal operands `vrgather.vx v0,v2,a4,v0.t'
  2620. -.*Error: illegal operands `vrgather.vi v2,v2,1'
  2621. -.*Error: illegal operands `vrgather.vi v0,v2,1,v0.t'
  2622. -.*Error: illegal operands `vrgatherei16.vv v2,v2,v4'
  2623. -.*Error: illegal operands `vrgatherei16.vv v4,v2,v4'
  2624. -.*Error: illegal operands `vrgatherei16.vv v0,v2,v4,v0.t'
  2625. -.*Error: illegal operands `vcompress.vm v2,v2,v4'
  2626. -.*Error: illegal operands `vcompress.vm v4,v2,v4'
  2627. -.*Error: illegal operands `vmv2r.v v1,v2'
  2628. -.*Error: illegal operands `vmv2r.v v2,v3'
  2629. -.*Error: illegal operands `vmv4r.v v2,v4'
  2630. -.*Error: illegal operands `vmv4r.v v4,v7'
  2631. -.*Error: illegal operands `vmv8r.v v6,v8'
  2632. -.*Error: illegal operands `vmv8r.v v8,v12'
  2633. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.s b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
  2634. deleted file mode 100644
  2635. index 3a35aadb49..0000000000
  2636. --- a/gas/testsuite/gas/riscv/vector-insns-fail-06.s
  2637. +++ /dev/null
  2638. @@ -1,73 +0,0 @@
  2639. -# Vector Iota Instruction
  2640. -# Vector Slideup Instructions
  2641. -# Vector Slide1up
  2642. -# Vector Register Gather Instruction
  2643. -# Vector Compress Instruction
  2644. -# Vector Load/Store Whole Register Instructions
  2645. -# Whole Vector Register Move
  2646. -
  2647. - viota.m v0, v2 # OK
  2648. - viota.m v2, v2 # vd overlap vs2
  2649. - viota.m v0, v2, v0.t # vd overlap vm
  2650. -
  2651. - vslideup.vx v0, v2, a4 # OK
  2652. - vslideup.vx v1, v2, a4 # OK
  2653. - vslideup.vx v2, v2, a4 # vd overlap vs2
  2654. - vslideup.vx v0, v2, a4, v0.t # vd overlap vm
  2655. -
  2656. - vslideup.vi v0, v2, 1 # OK
  2657. - vslideup.vi v1, v2, 1 # OK
  2658. - vslideup.vi v2, v2, 1 # vd overlap vs2
  2659. - vslideup.vi v0, v2, 1, v0.t # vd overlap vm
  2660. -
  2661. - vslide1up.vx v0, v2, a4 # OK
  2662. - vslide1up.vx v1, v2, a4 # OK
  2663. - vslide1up.vx v2, v2, a4 # vd overlap vs2
  2664. - vslide1up.vx v0, v2, a4, v0.t # vd overlap vm
  2665. -
  2666. - vfslide1up.vf v0, v2, fa4 # OK
  2667. - vfslide1up.vf v1, v2, fa4 # OK
  2668. - vfslide1up.vf v2, v2, fa4 # vd overlap vs2
  2669. - vfslide1up.vf v0, v2, fa4, v0.t # vd overlap vm
  2670. -
  2671. - vrgather.vv v0, v2, v4 # OK
  2672. - vrgather.vv v1, v2, v4 # OK
  2673. - vrgather.vv v2, v2, v4 # vd overlap vs2
  2674. - vrgather.vv v4, v2, v4 # vd overlap vs1
  2675. - vrgather.vv v0, v2, v4, v0.t # vd overlap vm
  2676. -
  2677. - vrgather.vx v0, v2, a4 # OK
  2678. - vrgather.vx v1, v2, a4 # OK
  2679. - vrgather.vx v2, v2, a4 # vd overlap vs2
  2680. - vrgather.vx v0, v2, a4, v0.t # vd overlap vm
  2681. -
  2682. - vrgather.vi v0, v2, 1 # OK
  2683. - vrgather.vi v1, v2, 1 # OK
  2684. - vrgather.vi v2, v2, 1 # vd overlap vs2
  2685. - vrgather.vi v0, v2, 1, v0.t # vd overlap vm
  2686. -
  2687. - vrgatherei16.vv v0, v2, v4 # OK
  2688. - vrgatherei16.vv v1, v2, v4 # OK
  2689. - vrgatherei16.vv v2, v2, v4 # vd overlap vs2
  2690. - vrgatherei16.vv v4, v2, v4 # vd overlap vs1
  2691. - vrgatherei16.vv v0, v2, v4, v0.t# vd overlap vm
  2692. -
  2693. - vcompress.vm v0, v2, v4 # OK
  2694. - vcompress.vm v1, v2, v4 # OK
  2695. - vcompress.vm v2, v2, v4 # vd overlap vs2
  2696. - vcompress.vm v4, v2, v4 # vd overlap vs1
  2697. -
  2698. - vmv1r.v v0, v1 # OK
  2699. - vmv1r.v v2, v3 # OK
  2700. -
  2701. - vmv2r.v v0, v2 # OK
  2702. - vmv2r.v v1, v2 # vd must be aligned to 2
  2703. - vmv2r.v v2, v3 # vs2 must be aligned to 2
  2704. -
  2705. - vmv4r.v v0, v4 # OK
  2706. - vmv4r.v v2, v4 # vd must be aligned to 4
  2707. - vmv4r.v v4, v7 # vs2 must be aligned to 4
  2708. -
  2709. - vmv8r.v v0, v8 # OK
  2710. - vmv8r.v v6, v8 # vd must be aligned to 8
  2711. - vmv8r.v v8, v12 # vs2 must be aligned to 8
  2712. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
  2713. new file mode 100644
  2714. index 0000000000..df48418486
  2715. --- /dev/null
  2716. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
  2717. @@ -0,0 +1,3 @@
  2718. +#as: -march=rv32iv -mcheck-constraints
  2719. +#source: vector-insns-fail-arith-fixp.s
  2720. +#error_output: vector-insns-fail-arith-fixp.l
  2721. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
  2722. new file mode 100644
  2723. index 0000000000..a3c126d8ec
  2724. --- /dev/null
  2725. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
  2726. @@ -0,0 +1,27 @@
  2727. +.*: Assembler messages:
  2728. +.*Error: illegal operands `vsaddu.vv v0,v4,v8,v0.t'
  2729. +.*Error: illegal operands `vsaddu.vx v0,v4,a1,v0.t'
  2730. +.*Error: illegal operands `vsaddu.vi v0,v4,15,v0.t'
  2731. +.*Error: illegal operands `vsadd.vv v0,v4,v8,v0.t'
  2732. +.*Error: illegal operands `vsadd.vx v0,v4,a1,v0.t'
  2733. +.*Error: illegal operands `vsadd.vi v0,v4,15,v0.t'
  2734. +.*Error: illegal operands `vssubu.vv v0,v4,v8,v0.t'
  2735. +.*Error: illegal operands `vssubu.vx v0,v4,a1,v0.t'
  2736. +.*Error: illegal operands `vssub.vv v0,v4,v8,v0.t'
  2737. +.*Error: illegal operands `vssub.vx v0,v4,a1,v0.t'
  2738. +.*Error: illegal operands `vaaddu.vv v0,v4,v8,v0.t'
  2739. +.*Error: illegal operands `vaaddu.vx v0,v4,a1,v0.t'
  2740. +.*Error: illegal operands `vaadd.vv v0,v4,v8,v0.t'
  2741. +.*Error: illegal operands `vaadd.vx v0,v4,a1,v0.t'
  2742. +.*Error: illegal operands `vasubu.vv v0,v4,v8,v0.t'
  2743. +.*Error: illegal operands `vasubu.vx v0,v4,a1,v0.t'
  2744. +.*Error: illegal operands `vasub.vv v0,v4,v8,v0.t'
  2745. +.*Error: illegal operands `vasub.vx v0,v4,a1,v0.t'
  2746. +.*Error: illegal operands `vsmul.vv v0,v4,v8,v0.t'
  2747. +.*Error: illegal operands `vsmul.vx v0,v4,a1,v0.t'
  2748. +.*Error: illegal operands `vssrl.vv v0,v4,v8,v0.t'
  2749. +.*Error: illegal operands `vssrl.vx v0,v4,a1,v0.t'
  2750. +.*Error: illegal operands `vssrl.vi v0,v4,31,v0.t'
  2751. +.*Error: illegal operands `vssra.vv v0,v4,v8,v0.t'
  2752. +.*Error: illegal operands `vssra.vx v0,v4,a1,v0.t'
  2753. +.*Error: illegal operands `vssra.vi v0,v4,31,v0.t'
  2754. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
  2755. new file mode 100644
  2756. index 0000000000..1fbcb601ea
  2757. --- /dev/null
  2758. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
  2759. @@ -0,0 +1,81 @@
  2760. +# Vector Single-Width Saturating Add and Subtract
  2761. +
  2762. + vsaddu.vv v4, v4, v8 # OK
  2763. + vsaddu.vv v8, v4, v8 # OK
  2764. + vsaddu.vv v0, v4, v8, v0.t # vd overlap vm
  2765. + vsaddu.vx v4, v4, a1 # OK
  2766. + vsaddu.vx v0, v4, a1, v0.t # vd overlap vm
  2767. + vsaddu.vi v4, v4, 15 # OK
  2768. + vsaddu.vi v0, v4, 15, v0.t # vd overlap vm
  2769. +
  2770. + vsadd.vv v4, v4, v8
  2771. + vsadd.vv v8, v4, v8
  2772. + vsadd.vv v0, v4, v8, v0.t
  2773. + vsadd.vx v4, v4, a1
  2774. + vsadd.vx v0, v4, a1, v0.t
  2775. + vsadd.vi v4, v4, 15
  2776. + vsadd.vi v0, v4, 15, v0.t
  2777. +
  2778. + vssubu.vv v4, v4, v8 # OK
  2779. + vssubu.vv v8, v4, v8 # OK
  2780. + vssubu.vv v0, v4, v8, v0.t # vd overlap vm
  2781. + vssubu.vx v4, v4, a1 # OK
  2782. + vssubu.vx v0, v4, a1, v0.t # vd overlap vm
  2783. +
  2784. + vssub.vv v4, v4, v8
  2785. + vssub.vv v8, v4, v8
  2786. + vssub.vv v0, v4, v8, v0.t
  2787. + vssub.vx v4, v4, a1
  2788. + vssub.vx v0, v4, a1, v0.t
  2789. +
  2790. +# Vector Single-Width Averaging Add and Subtract
  2791. +
  2792. + vaaddu.vv v4, v4, v8 # OK
  2793. + vaaddu.vv v8, v4, v8 # OK
  2794. + vaaddu.vv v0, v4, v8, v0.t # vd overlap vm
  2795. + vaaddu.vx v4, v4, a1 # OK
  2796. + vaaddu.vx v0, v4, a1, v0.t # vd overlap vm
  2797. +
  2798. + vaadd.vv v4, v4, v8
  2799. + vaadd.vv v8, v4, v8
  2800. + vaadd.vv v0, v4, v8, v0.t
  2801. + vaadd.vx v4, v4, a1
  2802. + vaadd.vx v0, v4, a1, v0.t
  2803. +
  2804. + vasubu.vv v4, v4, v8
  2805. + vasubu.vv v8, v4, v8
  2806. + vasubu.vv v0, v4, v8, v0.t
  2807. + vasubu.vx v4, v4, a1
  2808. + vasubu.vx v0, v4, a1, v0.t
  2809. +
  2810. + vasub.vv v4, v4, v8
  2811. + vasub.vv v8, v4, v8
  2812. + vasub.vv v0, v4, v8, v0.t
  2813. + vasub.vx v4, v4, a1
  2814. + vasub.vx v0, v4, a1, v0.t
  2815. +
  2816. +# Vector Single-Width Fractional Multiply with Rounding and Saturation
  2817. +
  2818. + vsmul.vv v4, v4, v8 # OK
  2819. + vsmul.vv v8, v4, v8 # OK
  2820. + vsmul.vv v0, v4, v8, v0.t # vd overlap vm
  2821. + vsmul.vx v4, v4, a1 # OK
  2822. + vsmul.vx v0, v4, a1, v0.t # vd overlap vm
  2823. +
  2824. +# Vector Single-Width Scaling Shift Instructions
  2825. +
  2826. + vssrl.vv v4, v4, v8 # OK
  2827. + vssrl.vv v8, v4, v8 # OK
  2828. + vssrl.vv v0, v4, v8, v0.t # vd overlap vm
  2829. + vssrl.vx v4, v4, a1 # OK
  2830. + vssrl.vx v0, v4, a1, v0.t # vd overlap vm
  2831. + vssrl.vi v4, v4, 31 # OK
  2832. + vssrl.vi v0, v4, 31, v0.t # vd overlap vm
  2833. +
  2834. + vssra.vv v4, v4, v8
  2835. + vssra.vv v8, v4, v8
  2836. + vssra.vv v0, v4, v8, v0.t
  2837. + vssra.vx v4, v4, a1
  2838. + vssra.vx v0, v4, a1, v0.t
  2839. + vssra.vi v4, v4, 31
  2840. + vssra.vi v0, v4, 31, v0.t
  2841. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
  2842. new file mode 100644
  2843. index 0000000000..796f7e2ded
  2844. --- /dev/null
  2845. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
  2846. @@ -0,0 +1,3 @@
  2847. +#as: -march=rv32ifv -mcheck-constraints
  2848. +#source: vector-insns-fail-arith-floatp.s
  2849. +#error_output: vector-insns-fail-arith-floatp.l
  2850. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
  2851. new file mode 100644
  2852. index 0000000000..0fc28a82d7
  2853. --- /dev/null
  2854. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
  2855. @@ -0,0 +1,47 @@
  2856. +.*: Assembler messages:
  2857. +.*Error: illegal operands `vfadd.vv v0,v4,v8,v0.t'
  2858. +.*Error: illegal operands `vfadd.vf v0,v4,fa1,v0.t'
  2859. +.*Error: illegal operands `vfsub.vv v0,v4,v8,v0.t'
  2860. +.*Error: illegal operands `vfsub.vf v0,v4,fa1,v0.t'
  2861. +.*Error: illegal operands `vfrsub.vf v0,v4,fa1,v0.t'
  2862. +.*Error: illegal operands `vfmul.vv v0,v4,v8,v0.t'
  2863. +.*Error: illegal operands `vfmul.vf v0,v4,fa1,v0.t'
  2864. +.*Error: illegal operands `vfdiv.vv v0,v4,v8,v0.t'
  2865. +.*Error: illegal operands `vfdiv.vf v0,v4,fa1,v0.t'
  2866. +.*Error: illegal operands `vfrdiv.vf v0,v4,fa1,v0.t'
  2867. +.*Error: illegal operands `vfmacc.vv v0,v4,v8,v0.t'
  2868. +.*Error: illegal operands `vfmacc.vf v0,fa1,v4,v0.t'
  2869. +.*Error: illegal operands `vfnmacc.vv v0,v4,v8,v0.t'
  2870. +.*Error: illegal operands `vfnmacc.vf v0,fa1,v4,v0.t'
  2871. +.*Error: illegal operands `vfmsac.vv v0,v4,v8,v0.t'
  2872. +.*Error: illegal operands `vfmsac.vf v0,fa1,v4,v0.t'
  2873. +.*Error: illegal operands `vfnmsac.vv v0,v4,v8,v0.t'
  2874. +.*Error: illegal operands `vfnmsac.vf v0,fa1,v4,v0.t'
  2875. +.*Error: illegal operands `vfmadd.vv v0,v4,v8,v0.t'
  2876. +.*Error: illegal operands `vfmadd.vf v0,fa1,v4,v0.t'
  2877. +.*Error: illegal operands `vfnmadd.vv v0,v4,v8,v0.t'
  2878. +.*Error: illegal operands `vfnmadd.vf v0,fa1,v4,v0.t'
  2879. +.*Error: illegal operands `vfmsub.vv v0,v4,v8,v0.t'
  2880. +.*Error: illegal operands `vfmsub.vf v0,fa1,v4,v0.t'
  2881. +.*Error: illegal operands `vfnmsub.vv v0,v4,v8,v0.t'
  2882. +.*Error: illegal operands `vfnmsub.vf v0,fa1,v4,v0.t'
  2883. +.*Error: illegal operands `vfsqrt.v v0,v4,v0.t'
  2884. +.*Error: illegal operands `vfrece7.v v0,v4,v0.t'
  2885. +.*Error: illegal operands `vfrsqrte7.v v0,v4,v0.t'
  2886. +.*Error: illegal operands `vfclass.v v0,v4,v0.t'
  2887. +.*Error: illegal operands `vfmin.vv v0,v4,v8,v0.t'
  2888. +.*Error: illegal operands `vfmin.vf v0,v4,fa1,v0.t'
  2889. +.*Error: illegal operands `vfmax.vv v0,v4,v8,v0.t'
  2890. +.*Error: illegal operands `vfmax.vf v0,v4,fa1,v0.t'
  2891. +.*Error: illegal operands `vfsgnj.vv v0,v4,v8,v0.t'
  2892. +.*Error: illegal operands `vfsgnj.vf v0,v4,fa1,v0.t'
  2893. +.*Error: illegal operands `vfsgnjn.vv v0,v4,v8,v0.t'
  2894. +.*Error: illegal operands `vfsgnjn.vf v0,v4,fa1,v0.t'
  2895. +.*Error: illegal operands `vfsgnjx.vv v0,v4,v8,v0.t'
  2896. +.*Error: illegal operands `vfsgnjx.vf v0,v4,fa1,v0.t'
  2897. +.*Error: illegal operands `vfcvt.xu.f.v v0,v4,v0.t'
  2898. +.*Error: illegal operands `vfcvt.x.f.v v0,v4,v0.t'
  2899. +.*Error: illegal operands `vfcvt.rtz.xu.f.v v0,v4,v0.t'
  2900. +.*Error: illegal operands `vfcvt.rtz.x.f.v v0,v4,v0.t'
  2901. +.*Error: illegal operands `vfcvt.f.xu.v v0,v4,v0.t'
  2902. +.*Error: illegal operands `vfcvt.f.x.v v0,v4,v0.t'
  2903. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
  2904. new file mode 100644
  2905. index 0000000000..3231c35ada
  2906. --- /dev/null
  2907. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
  2908. @@ -0,0 +1,152 @@
  2909. +# Vector Single-Width Floating-Point Add/Subtract Instructions
  2910. +
  2911. + vfadd.vv v4, v4, v8 # OK
  2912. + vfadd.vv v8, v4, v8 # OK
  2913. + vfadd.vv v0, v4, v8, v0.t # vd overlap vm
  2914. + vfadd.vf v4, v4, fa1 # OK
  2915. + vfadd.vf v0, v4, fa1, v0.t # vd overlap vm
  2916. +
  2917. + vfsub.vv v4, v4, v8
  2918. + vfsub.vv v8, v4, v8
  2919. + vfsub.vv v0, v4, v8, v0.t
  2920. + vfsub.vf v4, v4, fa1
  2921. + vfsub.vf v0, v4, fa1, v0.t
  2922. +
  2923. + vfrsub.vf v4, v4, fa1 # OK
  2924. + vfrsub.vf v0, v4, fa1, v0.t # vd overlap vm
  2925. +
  2926. +# Vector Single-Width Floating-Point Multiply/Divide Instructions
  2927. +
  2928. + vfmul.vv v4, v4, v8 # OK
  2929. + vfmul.vv v8, v4, v8 # OK
  2930. + vfmul.vv v0, v4, v8, v0.t # vd overlap vm
  2931. + vfmul.vf v4, v4, fa1 # OK
  2932. + vfmul.vf v0, v4, fa1, v0.t # vd overlap vm
  2933. +
  2934. + vfdiv.vv v4, v4, v8
  2935. + vfdiv.vv v8, v4, v8
  2936. + vfdiv.vv v0, v4, v8, v0.t
  2937. + vfdiv.vf v4, v4, fa1
  2938. + vfdiv.vf v0, v4, fa1, v0.t
  2939. +
  2940. + vfrdiv.vf v4, v4, fa1 # OK
  2941. + vfrdiv.vf v0, v4, fa1, v0.t # vd overlap vm
  2942. +
  2943. +# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
  2944. +
  2945. + vfmacc.vv v4, v4, v8 # OK
  2946. + vfmacc.vv v8, v4, v8 # OK
  2947. + vfmacc.vv v0, v4, v8, v0.t # vd overlap vm
  2948. + vfmacc.vf v4, fa1, v4 # OK
  2949. + vfmacc.vf v0, fa1, v4, v0.t # vd overlap vm
  2950. +
  2951. + vfnmacc.vv v4, v4, v8
  2952. + vfnmacc.vv v8, v4, v8
  2953. + vfnmacc.vv v0, v4, v8, v0.t
  2954. + vfnmacc.vf v4, fa1, v4
  2955. + vfnmacc.vf v0, fa1, v4, v0.t
  2956. +
  2957. + vfmsac.vv v4, v4, v8
  2958. + vfmsac.vv v8, v4, v8
  2959. + vfmsac.vv v0, v4, v8, v0.t
  2960. + vfmsac.vf v4, fa1, v4
  2961. + vfmsac.vf v0, fa1, v4, v0.t
  2962. +
  2963. + vfnmsac.vv v4, v4, v8
  2964. + vfnmsac.vv v8, v4, v8
  2965. + vfnmsac.vv v0, v4, v8, v0.t
  2966. + vfnmsac.vf v4, fa1, v4
  2967. + vfnmsac.vf v0, fa1, v4, v0.t
  2968. +
  2969. + vfmadd.vv v4, v4, v8
  2970. + vfmadd.vv v8, v4, v8
  2971. + vfmadd.vv v0, v4, v8, v0.t
  2972. + vfmadd.vf v4, fa1, v4
  2973. + vfmadd.vf v0, fa1, v4, v0.t
  2974. +
  2975. + vfnmadd.vv v4, v4, v8
  2976. + vfnmadd.vv v8, v4, v8
  2977. + vfnmadd.vv v0, v4, v8, v0.t
  2978. + vfnmadd.vf v4, fa1, v4
  2979. + vfnmadd.vf v0, fa1, v4, v0.t
  2980. +
  2981. + vfmsub.vv v4, v4, v8
  2982. + vfmsub.vv v8, v4, v8
  2983. + vfmsub.vv v0, v4, v8, v0.t
  2984. + vfmsub.vf v4, fa1, v4
  2985. + vfmsub.vf v0, fa1, v4, v0.t
  2986. +
  2987. + vfnmsub.vv v4, v4, v8
  2988. + vfnmsub.vv v8, v4, v8
  2989. + vfnmsub.vv v0, v4, v8, v0.t
  2990. + vfnmsub.vf v4, fa1, v4
  2991. + vfnmsub.vf v0, fa1, v4, v0.t
  2992. +
  2993. +# Vector Floating-Point Square-Root Instruction
  2994. +
  2995. + vfsqrt.v v4, v4 # OK
  2996. + vfsqrt.v v0, v4, v0.t # vd overlap vm
  2997. +
  2998. +# Vector Floating-Point Reciprocal Estimate Instruction
  2999. +
  3000. + vfrece7.v v4, v4 # OK
  3001. + vfrece7.v v0, v4, v0.t # vd overlap vm
  3002. +
  3003. +# Vector Floating-Point Reciprocal Square-Root Estimate Instruction
  3004. +
  3005. + vfrsqrte7.v v4, v4 # OK
  3006. + vfrsqrte7.v v0, v4, v0.t # vd overlap vm
  3007. +
  3008. +# Vector Floating-Point Classify Instruction
  3009. +
  3010. + vfclass.v v4, v4 # OK
  3011. + vfclass.v v0, v4, v0.t # vd overlap vm
  3012. +
  3013. +# Vector Floating-Point MIN/MAX Instructions
  3014. +
  3015. + vfmin.vv v4, v4, v8 # OK
  3016. + vfmin.vv v8, v4, v8 # OK
  3017. + vfmin.vv v0, v4, v8, v0.t # vd overlap vm
  3018. + vfmin.vf v4, v4, fa1 # OK
  3019. + vfmin.vf v0, v4, fa1, v0.t # vd overlap vm
  3020. +
  3021. + vfmax.vv v4, v4, v8
  3022. + vfmax.vv v8, v4, v8
  3023. + vfmax.vv v0, v4, v8, v0.t
  3024. + vfmax.vf v4, v4, fa1
  3025. + vfmax.vf v0, v4, fa1, v0.t
  3026. +
  3027. +# Vector Floating-Point Sign-Injection Instructions
  3028. +
  3029. + vfsgnj.vv v4, v4, v8 # OK
  3030. + vfsgnj.vv v8, v4, v8 # OK
  3031. + vfsgnj.vv v0, v4, v8, v0.t # vd overlap vm
  3032. + vfsgnj.vf v4, v4, fa1 # OK
  3033. + vfsgnj.vf v0, v4, fa1, v0.t # vd overlap vm
  3034. +
  3035. + vfsgnjn.vv v4, v4, v8
  3036. + vfsgnjn.vv v8, v4, v8
  3037. + vfsgnjn.vv v0, v4, v8, v0.t
  3038. + vfsgnjn.vf v4, v4, fa1
  3039. + vfsgnjn.vf v0, v4, fa1, v0.t
  3040. +
  3041. + vfsgnjx.vv v4, v4, v8
  3042. + vfsgnjx.vv v8, v4, v8
  3043. + vfsgnjx.vv v0, v4, v8, v0.t
  3044. + vfsgnjx.vf v4, v4, fa1
  3045. + vfsgnjx.vf v0, v4, fa1, v0.t
  3046. +
  3047. +# Single-Width Floating-Point/Integer Type-Convert Instructions
  3048. +
  3049. + vfcvt.xu.f.v v4, v4 # OK
  3050. + vfcvt.xu.f.v v0, v4, v0.t # vd overlap vm
  3051. + vfcvt.x.f.v v4, v4
  3052. + vfcvt.x.f.v v0, v4, v0.t
  3053. + vfcvt.rtz.xu.f.v v4, v4
  3054. + vfcvt.rtz.xu.f.v v0, v4, v0.t
  3055. + vfcvt.rtz.x.f.v v4, v4
  3056. + vfcvt.rtz.x.f.v v0, v4, v0.t
  3057. + vfcvt.f.xu.v v4, v4
  3058. + vfcvt.f.xu.v v0, v4, v0.t
  3059. + vfcvt.f.x.v v4, v4
  3060. + vfcvt.f.x.v v0, v4, v0.t
  3061. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
  3062. new file mode 100644
  3063. index 0000000000..55b350bc85
  3064. --- /dev/null
  3065. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
  3066. @@ -0,0 +1,3 @@
  3067. +#as: -march=rv32iv -mcheck-constraints
  3068. +#source: vector-insns-fail-arith-int.s
  3069. +#error_output: vector-insns-fail-arith-int.l
  3070. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
  3071. new file mode 100644
  3072. index 0000000000..480406af93
  3073. --- /dev/null
  3074. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
  3075. @@ -0,0 +1,70 @@
  3076. +.*: Assembler messages:
  3077. +.*Error: illegal operands `vadd.vv v0,v4,v8,v0.t'
  3078. +.*Error: illegal operands `vadd.vx v0,v4,a1,v0.t'
  3079. +.*Error: illegal operands `vadd.vi v0,v4,15,v0.t'
  3080. +.*Error: illegal operands `vsub.vv v0,v4,v8,v0.t'
  3081. +.*Error: illegal operands `vsub.vx v0,v4,a1,v0.t'
  3082. +.*Error: illegal operands `vrsub.vx v0,v4,a1,v0.t'
  3083. +.*Error: illegal operands `vrsub.vi v0,v4,15,v0.t'
  3084. +.*Error: illegal operands `vzext.vf2 v0,v4,v0.t'
  3085. +.*Error: illegal operands `vsext.vf2 v0,v4,v0.t'
  3086. +.*Error: illegal operands `vzext.vf4 v0,v4,v0.t'
  3087. +.*Error: illegal operands `vsext.vf4 v0,v4,v0.t'
  3088. +.*Error: illegal operands `vzext.vf8 v0,v4,v0.t'
  3089. +.*Error: illegal operands `vsext.vf8 v0,v4,v0.t'
  3090. +.*Error: illegal operands `vadc.vvm v0,v4,v8,v0'
  3091. +.*Error: illegal operands `vadc.vxm v0,v4,a1,v0'
  3092. +.*Error: illegal operands `vadc.vim v0,v4,15,v0'
  3093. +.*Error: illegal operands `vsbc.vvm v0,v4,v8,v0'
  3094. +.*Error: illegal operands `vsbc.vxm v0,v4,a1,v0'
  3095. +.*Error: illegal operands `vnot.v v0,v4,v0.t'
  3096. +.*Error: illegal operands `vand.vv v0,v4,v8,v0.t'
  3097. +.*Error: illegal operands `vand.vx v0,v4,a1,v0.t'
  3098. +.*Error: illegal operands `vand.vi v0,v4,15,v0.t'
  3099. +.*Error: illegal operands `vor.vv v0,v4,v8,v0.t'
  3100. +.*Error: illegal operands `vor.vx v0,v4,a1,v0.t'
  3101. +.*Error: illegal operands `vor.vi v0,v4,15,v0.t'
  3102. +.*Error: illegal operands `vxor.vv v0,v4,v8,v0.t'
  3103. +.*Error: illegal operands `vxor.vx v0,v4,a1,v0.t'
  3104. +.*Error: illegal operands `vxor.vi v0,v4,15,v0.t'
  3105. +.*Error: illegal operands `vsll.vv v0,v4,v8,v0.t'
  3106. +.*Error: illegal operands `vsll.vx v0,v4,a1,v0.t'
  3107. +.*Error: illegal operands `vsll.vi v0,v4,31,v0.t'
  3108. +.*Error: illegal operands `vsrl.vv v0,v4,v8,v0.t'
  3109. +.*Error: illegal operands `vsrl.vx v0,v4,a1,v0.t'
  3110. +.*Error: illegal operands `vsrl.vi v0,v4,31,v0.t'
  3111. +.*Error: illegal operands `vsra.vv v0,v4,v8,v0.t'
  3112. +.*Error: illegal operands `vsra.vx v0,v4,a1,v0.t'
  3113. +.*Error: illegal operands `vsra.vi v0,v4,31,v0.t'
  3114. +.*Error: illegal operands `vminu.vv v0,v4,v8,v0.t'
  3115. +.*Error: illegal operands `vminu.vx v0,v4,a1,v0.t'
  3116. +.*Error: illegal operands `vmin.vv v0,v4,v8,v0.t'
  3117. +.*Error: illegal operands `vmin.vx v0,v4,a1,v0.t'
  3118. +.*Error: illegal operands `vmaxu.vv v0,v4,v8,v0.t'
  3119. +.*Error: illegal operands `vmaxu.vx v0,v4,a1,v0.t'
  3120. +.*Error: illegal operands `vmax.vv v0,v4,v8,v0.t'
  3121. +.*Error: illegal operands `vmax.vx v0,v4,a1,v0.t'
  3122. +.*Error: illegal operands `vmul.vv v0,v4,v8,v0.t'
  3123. +.*Error: illegal operands `vmul.vx v0,v4,a1,v0.t'
  3124. +.*Error: illegal operands `vmulh.vv v0,v4,v8,v0.t'
  3125. +.*Error: illegal operands `vmulh.vx v0,v4,a1,v0.t'
  3126. +.*Error: illegal operands `vmulhu.vv v0,v4,v8,v0.t'
  3127. +.*Error: illegal operands `vmulhu.vx v0,v4,a1,v0.t'
  3128. +.*Error: illegal operands `vmulhsu.vv v0,v4,v8,v0.t'
  3129. +.*Error: illegal operands `vmulhsu.vx v0,v4,a1,v0.t'
  3130. +.*Error: illegal operands `vdivu.vv v0,v4,v8,v0.t'
  3131. +.*Error: illegal operands `vdivu.vx v0,v4,a1,v0.t'
  3132. +.*Error: illegal operands `vdiv.vv v0,v4,v8,v0.t'
  3133. +.*Error: illegal operands `vdiv.vx v0,v4,a1,v0.t'
  3134. +.*Error: illegal operands `vremu.vv v0,v4,v8,v0.t'
  3135. +.*Error: illegal operands `vremu.vx v0,v4,a1,v0.t'
  3136. +.*Error: illegal operands `vrem.vv v0,v4,v8,v0.t'
  3137. +.*Error: illegal operands `vrem.vx v0,v4,a1,v0.t'
  3138. +.*Error: illegal operands `vmacc.vv v0,v4,v8,v0.t'
  3139. +.*Error: illegal operands `vmacc.vx v0,a1,v4,v0.t'
  3140. +.*Error: illegal operands `vnmsac.vv v0,v4,v8,v0.t'
  3141. +.*Error: illegal operands `vnmsac.vx v0,a1,v4,v0.t'
  3142. +.*Error: illegal operands `vmadd.vv v0,v4,v8,v0.t'
  3143. +.*Error: illegal operands `vmadd.vx v0,a1,v4,v0.t'
  3144. +.*Error: illegal operands `vnmsub.vv v0,v4,v8,v0.t'
  3145. +.*Error: illegal operands `vnmsub.vx v0,a1,v4,v0.t'
  3146. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
  3147. new file mode 100644
  3148. index 0000000000..e014125c29
  3149. --- /dev/null
  3150. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
  3151. @@ -0,0 +1,210 @@
  3152. +# Vector Single-Width Integer Add and Subtract
  3153. +
  3154. + vadd.vv v4, v4, v8 # OK
  3155. + vadd.vv v8, v4, v8 # OK
  3156. + vadd.vv v0, v4, v8, v0.t # vd overlap vm
  3157. + vadd.vx v4, v4, a1 # OK
  3158. + vadd.vx v0, v4, a1, v0.t # vd overlap vm
  3159. + vadd.vi v4, v4, 15 # OK
  3160. + vadd.vi v0, v4, 15, v0.t # vd overlap vm
  3161. +
  3162. + vsub.vv v4, v4, v8 # OK
  3163. + vsub.vv v8, v4, v8 # OK
  3164. + vsub.vv v0, v4, v8, v0.t # vd overlap vm
  3165. + vsub.vx v4, v4, a1 # OK
  3166. + vsub.vx v0, v4, a1, v0.t # vd overlap vm
  3167. +
  3168. + vrsub.vx v4, v4, a1 # OK
  3169. + vrsub.vx v0, v4, a1, v0.t # vd overlap vm
  3170. + vrsub.vi v4, v4, 15 # OK
  3171. + vrsub.vi v0, v4, 15, v0.t # vd overlap vm
  3172. +
  3173. +# Vector Integer Extension
  3174. +
  3175. + vzext.vf2 v4, v4 # OK
  3176. + vzext.vf2 v0, v4, v0.t # vd overlap vm
  3177. + vsext.vf2 v4, v4
  3178. + vsext.vf2 v0, v4, v0.t
  3179. + vzext.vf4 v4, v4
  3180. + vzext.vf4 v0, v4, v0.t
  3181. + vsext.vf4 v4, v4
  3182. + vsext.vf4 v0, v4, v0.t
  3183. + vzext.vf8 v4, v4
  3184. + vzext.vf8 v0, v4, v0.t
  3185. + vsext.vf8 v4, v4
  3186. + vsext.vf8 v0, v4, v0.t
  3187. +
  3188. +# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
  3189. +
  3190. + vadc.vvm v4, v4, v8, v0 # OK
  3191. + vadc.vvm v8, v4, v8, v0 # OK
  3192. + vadc.vvm v0, v4, v8, v0 # vd overlap vm
  3193. + vadc.vxm v4, v4, a1, v0 # OK
  3194. + vadc.vxm v0, v4, a1, v0 # vd overlap vm
  3195. + vadc.vim v4, v4, 15, v0 # OK
  3196. + vadc.vim v0, v4, 15, v0 # vd overlap vm
  3197. +
  3198. + vsbc.vvm v4, v4, v8, v0 # OK
  3199. + vsbc.vvm v8, v4, v8, v0 # OK
  3200. + vsbc.vvm v0, v4, v8, v0 # vd overlap vm
  3201. + vsbc.vxm v4, v4, a1, v0 # OK
  3202. + vsbc.vxm v0, v4, a1, v0 # vd overlap vm
  3203. +
  3204. +# Vector Bitwise Logical Instructions
  3205. +
  3206. + vnot.v v4, v4 # OK
  3207. + vnot.v v0, v4, v0.t # vd overlap vm
  3208. +
  3209. + vand.vv v4, v4, v8 # OK
  3210. + vand.vv v8, v4, v8 # OK
  3211. + vand.vv v0, v4, v8, v0.t # vd overlap vm
  3212. + vand.vx v4, v4, a1 # OK
  3213. + vand.vx v0, v4, a1, v0.t # vd overlap vm
  3214. + vand.vi v4, v4, 15 # OK
  3215. + vand.vi v0, v4, 15, v0.t # vd overlap vm
  3216. +
  3217. + vor.vv v4, v4, v8
  3218. + vor.vv v8, v4, v8
  3219. + vor.vv v0, v4, v8, v0.t
  3220. + vor.vx v4, v4, a1
  3221. + vor.vx v0, v4, a1, v0.t
  3222. + vor.vi v4, v4, 15
  3223. + vor.vi v0, v4, 15, v0.t
  3224. +
  3225. + vxor.vv v4, v4, v8
  3226. + vxor.vv v8, v4, v8
  3227. + vxor.vv v0, v4, v8, v0.t
  3228. + vxor.vx v4, v4, a1
  3229. + vxor.vx v0, v4, a1, v0.t
  3230. + vxor.vi v4, v4, 15
  3231. + vxor.vi v0, v4, 15, v0.t
  3232. +
  3233. +# Vector Single-Width Bit Shift Instructions
  3234. +
  3235. + vsll.vv v4, v4, v8 # OK
  3236. + vsll.vv v8, v4, v8 # OK
  3237. + vsll.vv v0, v4, v8, v0.t # vd overlap vm
  3238. + vsll.vx v4, v4, a1 # OK
  3239. + vsll.vx v0, v4, a1, v0.t # vd overlap vm
  3240. + vsll.vi v4, v4, 31 # OK
  3241. + vsll.vi v0, v4, 31, v0.t # vd overlap vm
  3242. +
  3243. + vsrl.vv v4, v4, v8
  3244. + vsrl.vv v8, v4, v8
  3245. + vsrl.vv v0, v4, v8, v0.t
  3246. + vsrl.vx v4, v4, a1
  3247. + vsrl.vx v0, v4, a1, v0.t
  3248. + vsrl.vi v4, v4, 31
  3249. + vsrl.vi v0, v4, 31, v0.t
  3250. +
  3251. + vsra.vv v4, v4, v8
  3252. + vsra.vv v8, v4, v8
  3253. + vsra.vv v0, v4, v8, v0.t
  3254. + vsra.vx v4, v4, a1
  3255. + vsra.vx v0, v4, a1, v0.t
  3256. + vsra.vi v4, v4, 31
  3257. + vsra.vi v0, v4, 31, v0.t
  3258. +
  3259. +# Vector Integer Min/Max Instructions
  3260. +
  3261. + vminu.vv v4, v4, v8 # OK
  3262. + vminu.vv v8, v4, v8 # OK
  3263. + vminu.vv v0, v4, v8, v0.t # vd overlap vm
  3264. + vminu.vx v4, v4, a1 # OK
  3265. + vminu.vx v0, v4, a1, v0.t # vd overlap vm
  3266. +
  3267. + vmin.vv v4, v4, v8
  3268. + vmin.vv v8, v4, v8
  3269. + vmin.vv v0, v4, v8, v0.t
  3270. + vmin.vx v4, v4, a1
  3271. + vmin.vx v0, v4, a1, v0.t
  3272. +
  3273. + vmaxu.vv v4, v4, v8
  3274. + vmaxu.vv v8, v4, v8
  3275. + vmaxu.vv v0, v4, v8, v0.t
  3276. + vmaxu.vx v4, v4, a1
  3277. + vmaxu.vx v0, v4, a1, v0.t
  3278. +
  3279. + vmax.vv v4, v4, v8
  3280. + vmax.vv v8, v4, v8
  3281. + vmax.vv v0, v4, v8, v0.t
  3282. + vmax.vx v4, v4, a1
  3283. + vmax.vx v0, v4, a1, v0.t
  3284. +
  3285. +# Vector Single-Width Integer Multiply Instructions
  3286. +
  3287. + vmul.vv v4, v4, v8 # OK
  3288. + vmul.vv v8, v4, v8 # OK
  3289. + vmul.vv v0, v4, v8, v0.t # vd overlap vm
  3290. + vmul.vx v4, v4, a1 # OK
  3291. + vmul.vx v0, v4, a1, v0.t # vd overlap vm
  3292. +
  3293. + vmulh.vv v4, v4, v8
  3294. + vmulh.vv v8, v4, v8
  3295. + vmulh.vv v0, v4, v8, v0.t
  3296. + vmulh.vx v4, v4, a1
  3297. + vmulh.vx v0, v4, a1, v0.t
  3298. +
  3299. + vmulhu.vv v4, v4, v8
  3300. + vmulhu.vv v8, v4, v8
  3301. + vmulhu.vv v0, v4, v8, v0.t
  3302. + vmulhu.vx v4, v4, a1
  3303. + vmulhu.vx v0, v4, a1, v0.t
  3304. +
  3305. + vmulhsu.vv v4, v4, v8
  3306. + vmulhsu.vv v8, v4, v8
  3307. + vmulhsu.vv v0, v4, v8, v0.t
  3308. + vmulhsu.vx v4, v4, a1
  3309. + vmulhsu.vx v0, v4, a1, v0.t
  3310. +
  3311. +# Vector Integer Divide Instructions
  3312. +
  3313. + vdivu.vv v4, v4, v8 # OK
  3314. + vdivu.vv v8, v4, v8 # OK
  3315. + vdivu.vv v0, v4, v8, v0.t # vd overlap vm
  3316. + vdivu.vx v4, v4, a1 # OK
  3317. + vdivu.vx v0, v4, a1, v0.t # vd overlap vm
  3318. +
  3319. + vdiv.vv v4, v4, v8
  3320. + vdiv.vv v8, v4, v8
  3321. + vdiv.vv v0, v4, v8, v0.t
  3322. + vdiv.vx v4, v4, a1
  3323. + vdiv.vx v0, v4, a1, v0.t
  3324. +
  3325. + vremu.vv v4, v4, v8
  3326. + vremu.vv v8, v4, v8
  3327. + vremu.vv v0, v4, v8, v0.t
  3328. + vremu.vx v4, v4, a1
  3329. + vremu.vx v0, v4, a1, v0.t
  3330. +
  3331. + vrem.vv v4, v4, v8
  3332. + vrem.vv v8, v4, v8
  3333. + vrem.vv v0, v4, v8, v0.t
  3334. + vrem.vx v4, v4, a1
  3335. + vrem.vx v0, v4, a1, v0.t
  3336. +
  3337. +# Vector Single-Width Integer Multiply-Add Instructions
  3338. +
  3339. + vmacc.vv v4, v4, v8 # OK
  3340. + vmacc.vv v8, v4, v8 # OK
  3341. + vmacc.vv v0, v4, v8, v0.t # vd overlap vm
  3342. + vmacc.vx v4, a1, v4 # OK
  3343. + vmacc.vx v0, a1, v4, v0.t # vd overlap vm
  3344. +
  3345. + vnmsac.vv v4, v4, v8
  3346. + vnmsac.vv v8, v4, v8
  3347. + vnmsac.vv v0, v4, v8, v0.t
  3348. + vnmsac.vx v4, a1, v4
  3349. + vnmsac.vx v0, a1, v4, v0.t
  3350. +
  3351. + vmadd.vv v4, v4, v8
  3352. + vmadd.vv v8, v4, v8
  3353. + vmadd.vv v0, v4, v8, v0.t
  3354. + vmadd.vx v4, a1, v4
  3355. + vmadd.vx v0, a1, v4, v0.t
  3356. +
  3357. + vnmsub.vv v4, v4, v8
  3358. + vnmsub.vv v8, v4, v8
  3359. + vnmsub.vv v0, v4, v8, v0.t
  3360. + vnmsub.vx v4, a1, v4
  3361. + vnmsub.vx v0, a1, v4, v0.t
  3362. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
  3363. new file mode 100644
  3364. index 0000000000..e7a4d4e00c
  3365. --- /dev/null
  3366. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
  3367. @@ -0,0 +1,3 @@
  3368. +#as: -march=rv32ifv -mcheck-constraints
  3369. +#source: vector-insns-fail-arith-narrow.s
  3370. +#error_output: vector-insns-fail-arith-narrow.l
  3371. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
  3372. similarity index 59%
  3373. rename from gas/testsuite/gas/riscv/vector-insns-fail-05.l
  3374. rename to gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
  3375. index f2bee3d1e0..dcbe3b3f79 100644
  3376. --- a/gas/testsuite/gas/riscv/vector-insns-fail-05.l
  3377. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
  3378. @@ -2,63 +2,84 @@
  3379. .*Error: illegal operands `vncvt.x.x.v v2,v2'
  3380. .*Error: illegal operands `vncvt.x.x.v v2,v3'
  3381. .*Error: illegal operands `vncvt.x.x.v v3,v2'
  3382. +.*Error: illegal operands `vncvt.x.x.v v0,v2,v0.t'
  3383. .*Error: illegal operands `vnsrl.wv v2,v2,v4'
  3384. .*Error: illegal operands `vnsrl.wv v2,v3,v4'
  3385. .*Error: illegal operands `vnsrl.wv v3,v2,v4'
  3386. +.*Error: illegal operands `vnsrl.wv v0,v2,v4,v0.t'
  3387. .*Error: illegal operands `vnsrl.wx v2,v2,a1'
  3388. .*Error: illegal operands `vnsrl.wx v2,v3,a1'
  3389. .*Error: illegal operands `vnsrl.wx v3,v2,a1'
  3390. -.*Error: illegal operands `vnsrl.wi v2,v2,1'
  3391. -.*Error: illegal operands `vnsrl.wi v2,v3,1'
  3392. -.*Error: illegal operands `vnsrl.wi v3,v2,1'
  3393. +.*Error: illegal operands `vnsrl.wx v0,v2,a1,v0.t'
  3394. +.*Error: illegal operands `vnsrl.wi v2,v2,31'
  3395. +.*Error: illegal operands `vnsrl.wi v2,v3,31'
  3396. +.*Error: illegal operands `vnsrl.wi v3,v2,31'
  3397. +.*Error: illegal operands `vnsrl.wi v0,v2,31,v0.t'
  3398. .*Error: illegal operands `vnsra.wv v2,v2,v4'
  3399. .*Error: illegal operands `vnsra.wv v2,v3,v4'
  3400. .*Error: illegal operands `vnsra.wv v3,v2,v4'
  3401. +.*Error: illegal operands `vnsra.wv v0,v2,v4,v0.t'
  3402. .*Error: illegal operands `vnsra.wx v2,v2,a1'
  3403. .*Error: illegal operands `vnsra.wx v2,v3,a1'
  3404. .*Error: illegal operands `vnsra.wx v3,v2,a1'
  3405. -.*Error: illegal operands `vnsra.wi v2,v2,1'
  3406. -.*Error: illegal operands `vnsra.wi v2,v3,1'
  3407. -.*Error: illegal operands `vnsra.wi v3,v2,1'
  3408. +.*Error: illegal operands `vnsra.wx v0,v2,a1,v0.t'
  3409. +.*Error: illegal operands `vnsra.wi v2,v2,31'
  3410. +.*Error: illegal operands `vnsra.wi v2,v3,31'
  3411. +.*Error: illegal operands `vnsra.wi v3,v2,31'
  3412. +.*Error: illegal operands `vnsra.wi v0,v2,31,v0.t'
  3413. .*Error: illegal operands `vnclipu.wv v2,v2,v4'
  3414. .*Error: illegal operands `vnclipu.wv v2,v3,v4'
  3415. .*Error: illegal operands `vnclipu.wv v3,v2,v4'
  3416. +.*Error: illegal operands `vnclipu.wv v0,v2,v4,v0.t'
  3417. .*Error: illegal operands `vnclipu.wx v2,v2,a1'
  3418. .*Error: illegal operands `vnclipu.wx v2,v3,a1'
  3419. .*Error: illegal operands `vnclipu.wx v3,v2,a1'
  3420. -.*Error: illegal operands `vnclipu.wi v2,v2,1'
  3421. -.*Error: illegal operands `vnclipu.wi v2,v3,1'
  3422. -.*Error: illegal operands `vnclipu.wi v3,v2,1'
  3423. +.*Error: illegal operands `vnclipu.wx v0,v2,a1,v0.t'
  3424. +.*Error: illegal operands `vnclipu.wi v2,v2,31'
  3425. +.*Error: illegal operands `vnclipu.wi v2,v3,31'
  3426. +.*Error: illegal operands `vnclipu.wi v3,v2,31'
  3427. +.*Error: illegal operands `vnclipu.wi v0,v2,31,v0.t'
  3428. .*Error: illegal operands `vnclip.wv v2,v2,v4'
  3429. .*Error: illegal operands `vnclip.wv v2,v3,v4'
  3430. .*Error: illegal operands `vnclip.wv v3,v2,v4'
  3431. +.*Error: illegal operands `vnclip.wv v0,v2,v4,v0.t'
  3432. .*Error: illegal operands `vnclip.wx v2,v2,a1'
  3433. .*Error: illegal operands `vnclip.wx v2,v3,a1'
  3434. .*Error: illegal operands `vnclip.wx v3,v2,a1'
  3435. -.*Error: illegal operands `vnclip.wi v2,v2,1'
  3436. -.*Error: illegal operands `vnclip.wi v2,v3,1'
  3437. -.*Error: illegal operands `vnclip.wi v3,v2,1'
  3438. +.*Error: illegal operands `vnclip.wx v0,v2,a1,v0.t'
  3439. +.*Error: illegal operands `vnclip.wi v2,v2,31'
  3440. +.*Error: illegal operands `vnclip.wi v2,v3,31'
  3441. +.*Error: illegal operands `vnclip.wi v3,v2,31'
  3442. +.*Error: illegal operands `vnclip.wi v0,v2,31,v0.t'
  3443. .*Error: illegal operands `vfncvt.xu.f.w v2,v2'
  3444. .*Error: illegal operands `vfncvt.xu.f.w v2,v3'
  3445. .*Error: illegal operands `vfncvt.xu.f.w v3,v2'
  3446. +.*Error: illegal operands `vfncvt.xu.f.w v0,v2,v0.t'
  3447. .*Error: illegal operands `vfncvt.x.f.w v2,v2'
  3448. .*Error: illegal operands `vfncvt.x.f.w v2,v3'
  3449. .*Error: illegal operands `vfncvt.x.f.w v3,v2'
  3450. +.*Error: illegal operands `vfncvt.x.f.w v0,v2,v0.t'
  3451. .*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v2'
  3452. .*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v3'
  3453. .*Error: illegal operands `vfncvt.rtz.xu.f.w v3,v2'
  3454. +.*Error: illegal operands `vfncvt.rtz.xu.f.w v0,v2,v0.t'
  3455. .*Error: illegal operands `vfncvt.rtz.x.f.w v2,v2'
  3456. .*Error: illegal operands `vfncvt.rtz.x.f.w v2,v3'
  3457. .*Error: illegal operands `vfncvt.rtz.x.f.w v3,v2'
  3458. +.*Error: illegal operands `vfncvt.rtz.x.f.w v0,v2,v0.t'
  3459. .*Error: illegal operands `vfncvt.f.xu.w v2,v2'
  3460. .*Error: illegal operands `vfncvt.f.xu.w v2,v3'
  3461. .*Error: illegal operands `vfncvt.f.xu.w v3,v2'
  3462. +.*Error: illegal operands `vfncvt.f.xu.w v0,v2,v0.t'
  3463. .*Error: illegal operands `vfncvt.f.x.w v2,v2'
  3464. .*Error: illegal operands `vfncvt.f.x.w v2,v3'
  3465. .*Error: illegal operands `vfncvt.f.x.w v3,v2'
  3466. +.*Error: illegal operands `vfncvt.f.x.w v0,v2,v0.t'
  3467. .*Error: illegal operands `vfncvt.f.f.w v2,v2'
  3468. .*Error: illegal operands `vfncvt.f.f.w v2,v3'
  3469. .*Error: illegal operands `vfncvt.f.f.w v3,v2'
  3470. +.*Error: illegal operands `vfncvt.f.f.w v0,v2,v0.t'
  3471. .*Error: illegal operands `vfncvt.rod.f.f.w v2,v2'
  3472. .*Error: illegal operands `vfncvt.rod.f.f.w v2,v3'
  3473. .*Error: illegal operands `vfncvt.rod.f.f.w v3,v2'
  3474. +.*Error: illegal operands `vfncvt.rod.f.f.w v0,v2,v0.t'
  3475. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
  3476. new file mode 100644
  3477. index 0000000000..a843d076ff
  3478. --- /dev/null
  3479. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
  3480. @@ -0,0 +1,100 @@
  3481. +# Vector Narrowing Integer Right Shift Instructions
  3482. +
  3483. + # vncvt.x.x.v vd,vs,vm = vnsrl.wx vd,vs,x0,vm
  3484. + vncvt.x.x.v v2, v2 # vd overlap vs2
  3485. + vncvt.x.x.v v2, v3 # vs2 should be multiple of 2
  3486. + vncvt.x.x.v v3, v2 # vd overlap vs2
  3487. + vncvt.x.x.v v0, v2, v0.t # vd overlap vm
  3488. +
  3489. + vnsrl.wv v2, v2, v4 # vd overlap vs2
  3490. + vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
  3491. + vnsrl.wv v3, v2, v4 # vd overlap vs2
  3492. + vnsrl.wv v4, v2, v4 # OK
  3493. + vnsrl.wv v0, v2, v4, v0.t # vd overlap vm
  3494. + vnsrl.wx v2, v2, a1 # vd overlap vs2
  3495. + vnsrl.wx v2, v3, a1 # vs2 should be multiple of 2
  3496. + vnsrl.wx v3, v2, a1 # vd overlap vs2
  3497. + vnsrl.wx v0, v2, a1, v0.t # vd overlap vm
  3498. + vnsrl.wi v2, v2, 31 # vd overlap vs2
  3499. + vnsrl.wi v2, v3, 31 # vs2 should be multiple of 2
  3500. + vnsrl.wi v3, v2, 31 # vd overlap vs2
  3501. + vnsrl.wi v0, v2, 31, v0.t # vd overlap vm
  3502. +
  3503. + vnsra.wv v2, v2, v4
  3504. + vnsra.wv v2, v3, v4
  3505. + vnsra.wv v3, v2, v4
  3506. + vnsra.wv v4, v2, v4
  3507. + vnsra.wv v0, v2, v4, v0.t
  3508. + vnsra.wx v2, v2, a1
  3509. + vnsra.wx v2, v3, a1
  3510. + vnsra.wx v3, v2, a1
  3511. + vnsra.wx v0, v2, a1, v0.t
  3512. + vnsra.wi v2, v2, 31
  3513. + vnsra.wi v2, v3, 31
  3514. + vnsra.wi v3, v2, 31
  3515. + vnsra.wi v0, v2, 31, v0.t
  3516. +
  3517. +# Vector Narrowing Fixed-Point Clip Instructions
  3518. +
  3519. + vnclipu.wv v2, v2, v4 # vd overlap vs2
  3520. + vnclipu.wv v2, v3, v4 # vs2 should be multiple of 2
  3521. + vnclipu.wv v3, v2, v4 # vd overlap vs2
  3522. + vnclipu.wv v4, v2, v4 # OK
  3523. + vnclipu.wv v0, v2, v4, v0.t # vd overlap vm
  3524. + vnclipu.wx v2, v2, a1 # vd overlap vs2
  3525. + vnclipu.wx v2, v3, a1 # vs2 should be multiple of 2
  3526. + vnclipu.wx v3, v2, a1 # vd overlap vs2
  3527. + vnclipu.wx v0, v2, a1, v0.t # vd overlap vm
  3528. + vnclipu.wi v2, v2, 31 # vd overlap vs2
  3529. + vnclipu.wi v2, v3, 31 # vs2 should be multiple of 2
  3530. + vnclipu.wi v3, v2, 31 # vd overlap vs2
  3531. + vnclipu.wi v0, v2, 31, v0.t # vd overlap vm
  3532. +
  3533. + vnclip.wv v2, v2, v4
  3534. + vnclip.wv v2, v3, v4
  3535. + vnclip.wv v3, v2, v4
  3536. + vnclip.wv v4, v2, v4
  3537. + vnclip.wv v0, v2, v4, v0.t
  3538. + vnclip.wx v2, v2, a1
  3539. + vnclip.wx v2, v3, a1
  3540. + vnclip.wx v3, v2, a1
  3541. + vnclip.wx v0, v2, a1, v0.t
  3542. + vnclip.wi v2, v2, 31
  3543. + vnclip.wi v2, v3, 31
  3544. + vnclip.wi v3, v2, 31
  3545. + vnclip.wi v0, v2, 31, v0.t
  3546. +
  3547. +# Narrowing Floating-Point/Integer Type-Convert Instructions
  3548. +
  3549. + vfncvt.xu.f.w v2, v2 # vd overlap vs2
  3550. + vfncvt.xu.f.w v2, v3 # vs2 should be multiple of 2
  3551. + vfncvt.xu.f.w v3, v2 # vd overlap vs2
  3552. + vfncvt.xu.f.w v0, v2, v0.t # vd overlap vm
  3553. + vfncvt.x.f.w v2, v2
  3554. + vfncvt.x.f.w v2, v3
  3555. + vfncvt.x.f.w v3, v2
  3556. + vfncvt.x.f.w v0, v2, v0.t
  3557. + vfncvt.rtz.xu.f.w v2, v2
  3558. + vfncvt.rtz.xu.f.w v2, v3
  3559. + vfncvt.rtz.xu.f.w v3, v2
  3560. + vfncvt.rtz.xu.f.w v0, v2, v0.t
  3561. + vfncvt.rtz.x.f.w v2, v2
  3562. + vfncvt.rtz.x.f.w v2, v3
  3563. + vfncvt.rtz.x.f.w v3, v2
  3564. + vfncvt.rtz.x.f.w v0, v2, v0.t
  3565. + vfncvt.f.xu.w v2, v2
  3566. + vfncvt.f.xu.w v2, v3
  3567. + vfncvt.f.xu.w v3, v2
  3568. + vfncvt.f.xu.w v0, v2, v0.t
  3569. + vfncvt.f.x.w v2, v2
  3570. + vfncvt.f.x.w v2, v3
  3571. + vfncvt.f.x.w v3, v2
  3572. + vfncvt.f.x.w v0, v2, v0.t
  3573. + vfncvt.f.f.w v2, v2
  3574. + vfncvt.f.f.w v2, v3
  3575. + vfncvt.f.f.w v3, v2
  3576. + vfncvt.f.f.w v0, v2, v0.t
  3577. + vfncvt.rod.f.f.w v2, v2
  3578. + vfncvt.rod.f.f.w v2, v3
  3579. + vfncvt.rod.f.f.w v3, v2
  3580. + vfncvt.rod.f.f.w v0, v2, v0.t
  3581. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
  3582. new file mode 100644
  3583. index 0000000000..e5f034882c
  3584. --- /dev/null
  3585. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
  3586. @@ -0,0 +1,3 @@
  3587. +#as: -march=rv32ifv -mcheck-constraints
  3588. +#source: vector-insns-fail-arith-widen.s
  3589. +#error_output: vector-insns-fail-arith-widen.l
  3590. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
  3591. new file mode 100644
  3592. index 0000000000..5684601697
  3593. --- /dev/null
  3594. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
  3595. @@ -0,0 +1,253 @@
  3596. +.*: Assembler messages:
  3597. +.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
  3598. +.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
  3599. +.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
  3600. +.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
  3601. +.*Error: illegal operands `vwcvt.x.x.v v1,v2'
  3602. +.*Error: illegal operands `vwcvt.x.x.v v2,v2'
  3603. +.*Error: illegal operands `vwcvt.x.x.v v2,v3'
  3604. +.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
  3605. +.*Error: illegal operands `vwaddu.vv v1,v2,v4'
  3606. +.*Error: illegal operands `vwaddu.vv v2,v2,v4'
  3607. +.*Error: illegal operands `vwaddu.vv v2,v3,v4'
  3608. +.*Error: illegal operands `vwaddu.vv v4,v2,v4'
  3609. +.*Error: illegal operands `vwaddu.vv v4,v2,v5'
  3610. +.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
  3611. +.*Error: illegal operands `vwaddu.vx v1,v2,a1'
  3612. +.*Error: illegal operands `vwaddu.vx v2,v2,a1'
  3613. +.*Error: illegal operands `vwaddu.vx v2,v3,a1'
  3614. +.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
  3615. +.*Error: illegal operands `vwaddu.wv v1,v2,v4'
  3616. +.*Error: illegal operands `vwaddu.wv v2,v3,v4'
  3617. +.*Error: illegal operands `vwaddu.wv v4,v2,v4'
  3618. +.*Error: illegal operands `vwaddu.wv v4,v2,v5'
  3619. +.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
  3620. +.*Error: illegal operands `vwaddu.wx v1,v2,a1'
  3621. +.*Error: illegal operands `vwaddu.wx v2,v3,a1'
  3622. +.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
  3623. +.*Error: illegal operands `vwsubu.vv v1,v2,v4'
  3624. +.*Error: illegal operands `vwsubu.vv v2,v2,v4'
  3625. +.*Error: illegal operands `vwsubu.vv v2,v3,v4'
  3626. +.*Error: illegal operands `vwsubu.vv v4,v2,v4'
  3627. +.*Error: illegal operands `vwsubu.vv v4,v2,v5'
  3628. +.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
  3629. +.*Error: illegal operands `vwsubu.vx v1,v2,a1'
  3630. +.*Error: illegal operands `vwsubu.vx v2,v2,a1'
  3631. +.*Error: illegal operands `vwsubu.vx v2,v3,a1'
  3632. +.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
  3633. +.*Error: illegal operands `vwsubu.wv v1,v2,v4'
  3634. +.*Error: illegal operands `vwsubu.wv v2,v3,v4'
  3635. +.*Error: illegal operands `vwsubu.wv v4,v2,v4'
  3636. +.*Error: illegal operands `vwsubu.wv v4,v2,v5'
  3637. +.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
  3638. +.*Error: illegal operands `vwsubu.wx v1,v2,a1'
  3639. +.*Error: illegal operands `vwsubu.wx v2,v3,a1'
  3640. +.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
  3641. +.*Error: illegal operands `vwadd.vv v1,v2,v4'
  3642. +.*Error: illegal operands `vwadd.vv v2,v2,v4'
  3643. +.*Error: illegal operands `vwadd.vv v2,v3,v4'
  3644. +.*Error: illegal operands `vwadd.vv v4,v2,v4'
  3645. +.*Error: illegal operands `vwadd.vv v4,v2,v5'
  3646. +.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
  3647. +.*Error: illegal operands `vwadd.vx v1,v2,a1'
  3648. +.*Error: illegal operands `vwadd.vx v2,v2,a1'
  3649. +.*Error: illegal operands `vwadd.vx v2,v3,a1'
  3650. +.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
  3651. +.*Error: illegal operands `vwadd.wv v1,v2,v4'
  3652. +.*Error: illegal operands `vwadd.wv v2,v3,v4'
  3653. +.*Error: illegal operands `vwadd.wv v4,v2,v4'
  3654. +.*Error: illegal operands `vwadd.wv v4,v2,v5'
  3655. +.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
  3656. +.*Error: illegal operands `vwadd.wx v1,v2,a1'
  3657. +.*Error: illegal operands `vwadd.wx v2,v3,a1'
  3658. +.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
  3659. +.*Error: illegal operands `vwsub.vv v1,v2,v4'
  3660. +.*Error: illegal operands `vwsub.vv v2,v2,v4'
  3661. +.*Error: illegal operands `vwsub.vv v2,v3,v4'
  3662. +.*Error: illegal operands `vwsub.vv v4,v2,v4'
  3663. +.*Error: illegal operands `vwsub.vv v4,v2,v5'
  3664. +.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
  3665. +.*Error: illegal operands `vwsub.vx v1,v2,a1'
  3666. +.*Error: illegal operands `vwsub.vx v2,v2,a1'
  3667. +.*Error: illegal operands `vwsub.vx v2,v3,a1'
  3668. +.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
  3669. +.*Error: illegal operands `vwsub.wv v1,v2,v4'
  3670. +.*Error: illegal operands `vwsub.wv v2,v3,v4'
  3671. +.*Error: illegal operands `vwsub.wv v4,v2,v4'
  3672. +.*Error: illegal operands `vwsub.wv v4,v2,v5'
  3673. +.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
  3674. +.*Error: illegal operands `vwsub.wx v1,v2,a1'
  3675. +.*Error: illegal operands `vwsub.wx v2,v3,a1'
  3676. +.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
  3677. +.*Error: illegal operands `vwmul.vv v1,v2,v4'
  3678. +.*Error: illegal operands `vwmul.vv v2,v2,v4'
  3679. +.*Error: illegal operands `vwmul.vv v2,v3,v4'
  3680. +.*Error: illegal operands `vwmul.vv v4,v2,v4'
  3681. +.*Error: illegal operands `vwmul.vv v4,v2,v5'
  3682. +.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
  3683. +.*Error: illegal operands `vwmul.vx v1,v2,a1'
  3684. +.*Error: illegal operands `vwmul.vx v2,v2,a1'
  3685. +.*Error: illegal operands `vwmul.vx v2,v3,a1'
  3686. +.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
  3687. +.*Error: illegal operands `vwmulu.vv v1,v2,v4'
  3688. +.*Error: illegal operands `vwmulu.vv v2,v2,v4'
  3689. +.*Error: illegal operands `vwmulu.vv v2,v3,v4'
  3690. +.*Error: illegal operands `vwmulu.vv v4,v2,v4'
  3691. +.*Error: illegal operands `vwmulu.vv v4,v2,v5'
  3692. +.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
  3693. +.*Error: illegal operands `vwmulu.vx v1,v2,a1'
  3694. +.*Error: illegal operands `vwmulu.vx v2,v2,a1'
  3695. +.*Error: illegal operands `vwmulu.vx v2,v3,a1'
  3696. +.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
  3697. +.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
  3698. +.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
  3699. +.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
  3700. +.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
  3701. +.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
  3702. +.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
  3703. +.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
  3704. +.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
  3705. +.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
  3706. +.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
  3707. +.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
  3708. +.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
  3709. +.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
  3710. +.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
  3711. +.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
  3712. +.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
  3713. +.*Error: illegal operands `vwmaccu.vx v1,a1,v2'
  3714. +.*Error: illegal operands `vwmaccu.vx v2,a1,v2'
  3715. +.*Error: illegal operands `vwmaccu.vx v2,a1,v3'
  3716. +.*Error: illegal operands `vwmaccu.vx v0,a1,v2,v0.t'
  3717. +.*Error: illegal operands `vwmacc.vv v1,v2,v4'
  3718. +.*Error: illegal operands `vwmacc.vv v2,v2,v4'
  3719. +.*Error: illegal operands `vwmacc.vv v2,v3,v4'
  3720. +.*Error: illegal operands `vwmacc.vv v4,v2,v4'
  3721. +.*Error: illegal operands `vwmacc.vv v4,v2,v5'
  3722. +.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
  3723. +.*Error: illegal operands `vwmacc.vx v1,a1,v2'
  3724. +.*Error: illegal operands `vwmacc.vx v2,a1,v2'
  3725. +.*Error: illegal operands `vwmacc.vx v2,a1,v3'
  3726. +.*Error: illegal operands `vwmacc.vx v0,a1,v2,v0.t'
  3727. +.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
  3728. +.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
  3729. +.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
  3730. +.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
  3731. +.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
  3732. +.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
  3733. +.*Error: illegal operands `vwmaccsu.vx v1,a1,v2'
  3734. +.*Error: illegal operands `vwmaccsu.vx v2,a1,v2'
  3735. +.*Error: illegal operands `vwmaccsu.vx v2,a1,v3'
  3736. +.*Error: illegal operands `vwmaccsu.vx v0,a1,v2,v0.t'
  3737. +.*Error: illegal operands `vwmaccus.vx v1,a1,v2'
  3738. +.*Error: illegal operands `vwmaccus.vx v2,a1,v2'
  3739. +.*Error: illegal operands `vwmaccus.vx v2,a1,v3'
  3740. +.*Error: illegal operands `vwmaccus.vx v0,a1,v2,v0.t'
  3741. +.*Error: illegal operands `vfwadd.vv v1,v2,v4'
  3742. +.*Error: illegal operands `vfwadd.vv v2,v2,v4'
  3743. +.*Error: illegal operands `vfwadd.vv v2,v3,v4'
  3744. +.*Error: illegal operands `vfwadd.vv v4,v2,v4'
  3745. +.*Error: illegal operands `vfwadd.vv v4,v2,v5'
  3746. +.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
  3747. +.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
  3748. +.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
  3749. +.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
  3750. +.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
  3751. +.*Error: illegal operands `vfwadd.wv v1,v2,v4'
  3752. +.*Error: illegal operands `vfwadd.wv v2,v3,v4'
  3753. +.*Error: illegal operands `vfwadd.wv v4,v2,v4'
  3754. +.*Error: illegal operands `vfwadd.wv v4,v2,v5'
  3755. +.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
  3756. +.*Error: illegal operands `vfwsub.vv v1,v2,v4'
  3757. +.*Error: illegal operands `vfwsub.vv v2,v2,v4'
  3758. +.*Error: illegal operands `vfwsub.vv v2,v3,v4'
  3759. +.*Error: illegal operands `vfwsub.vv v4,v2,v4'
  3760. +.*Error: illegal operands `vfwsub.vv v4,v2,v5'
  3761. +.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
  3762. +.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
  3763. +.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
  3764. +.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
  3765. +.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
  3766. +.*Error: illegal operands `vfwsub.wv v1,v2,v4'
  3767. +.*Error: illegal operands `vfwsub.wv v2,v3,v4'
  3768. +.*Error: illegal operands `vfwsub.wv v4,v2,v4'
  3769. +.*Error: illegal operands `vfwsub.wv v4,v2,v5'
  3770. +.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
  3771. +.*Error: illegal operands `vfwmul.vv v1,v2,v4'
  3772. +.*Error: illegal operands `vfwmul.vv v2,v2,v4'
  3773. +.*Error: illegal operands `vfwmul.vv v2,v3,v4'
  3774. +.*Error: illegal operands `vfwmul.vv v4,v2,v4'
  3775. +.*Error: illegal operands `vfwmul.vv v4,v2,v5'
  3776. +.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
  3777. +.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
  3778. +.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
  3779. +.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
  3780. +.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
  3781. +.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
  3782. +.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
  3783. +.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
  3784. +.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
  3785. +.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
  3786. +.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
  3787. +.*Error: illegal operands `vfwmacc.vf v1,fa1,v2'
  3788. +.*Error: illegal operands `vfwmacc.vf v2,fa1,v2'
  3789. +.*Error: illegal operands `vfwmacc.vf v2,fa1,v3'
  3790. +.*Error: illegal operands `vfwmacc.vf v0,fa1,v2,v0.t'
  3791. +.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
  3792. +.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
  3793. +.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
  3794. +.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
  3795. +.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
  3796. +.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
  3797. +.*Error: illegal operands `vfwnmacc.vf v1,fa1,v2'
  3798. +.*Error: illegal operands `vfwnmacc.vf v2,fa1,v2'
  3799. +.*Error: illegal operands `vfwnmacc.vf v2,fa1,v3'
  3800. +.*Error: illegal operands `vfwnmacc.vf v0,fa1,v2,v0.t'
  3801. +.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
  3802. +.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
  3803. +.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
  3804. +.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
  3805. +.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
  3806. +.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
  3807. +.*Error: illegal operands `vfwmsac.vf v1,fa1,v2'
  3808. +.*Error: illegal operands `vfwmsac.vf v2,fa1,v2'
  3809. +.*Error: illegal operands `vfwmsac.vf v2,fa1,v3'
  3810. +.*Error: illegal operands `vfwmsac.vf v0,fa1,v2,v0.t'
  3811. +.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
  3812. +.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
  3813. +.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
  3814. +.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
  3815. +.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
  3816. +.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
  3817. +.*Error: illegal operands `vfwnmsac.vf v1,fa1,v2'
  3818. +.*Error: illegal operands `vfwnmsac.vf v2,fa1,v2'
  3819. +.*Error: illegal operands `vfwnmsac.vf v2,fa1,v3'
  3820. +.*Error: illegal operands `vfwnmsac.vf v0,fa1,v2,v0.t'
  3821. +.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
  3822. +.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
  3823. +.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
  3824. +.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
  3825. +.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
  3826. +.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
  3827. +.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
  3828. +.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
  3829. +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
  3830. +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
  3831. +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
  3832. +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
  3833. +.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
  3834. +.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
  3835. +.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
  3836. +.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
  3837. +.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
  3838. +.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
  3839. +.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
  3840. +.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
  3841. +.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
  3842. +.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
  3843. +.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
  3844. +.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
  3845. +.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
  3846. +.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
  3847. +.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
  3848. +.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
  3849. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
  3850. new file mode 100644
  3851. index 0000000000..addedd4dc2
  3852. --- /dev/null
  3853. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
  3854. @@ -0,0 +1,297 @@
  3855. +# Vector Widening Integer Add/Subtract
  3856. +
  3857. + # vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm
  3858. + vwcvtu.x.x.v v1, v2 # vd should be multiple of 2
  3859. + vwcvtu.x.x.v v2, v2 # vd overlap vs2
  3860. + vwcvtu.x.x.v v2, v3 # vd overlap vs2
  3861. + vwcvtu.x.x.v v0, v2, v0.t # vd overlap vm
  3862. +
  3863. + # vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm
  3864. + vwcvt.x.x.v v1, v2
  3865. + vwcvt.x.x.v v2, v2
  3866. + vwcvt.x.x.v v2, v3
  3867. + vwcvt.x.x.v v0, v2, v0.t
  3868. +
  3869. + vwaddu.vv v1, v2, v4 # vd should be multiple of 2
  3870. + vwaddu.vv v2, v2, v4 # vd overlap vs2
  3871. + vwaddu.vv v2, v3, v4 # vd overlap vs2
  3872. + vwaddu.vv v4, v2, v4 # vd overlap vs1
  3873. + vwaddu.vv v4, v2, v5 # vd overlap vs1
  3874. + vwaddu.vv v0, v2, v4, v0.t # vd overlap vm
  3875. + vwaddu.vx v1, v2, a1 # vd should be multiple of 2
  3876. + vwaddu.vx v2, v2, a1 # vd overlap vs2
  3877. + vwaddu.vx v2, v3, a1 # vd overlap vs2
  3878. + vwaddu.vx v0, v2, a1, v0.t # vd overlap vm
  3879. + vwaddu.wv v1, v2, v4 # vd should be multiple of 2
  3880. + vwaddu.wv v2, v2, v4 # OK
  3881. + vwaddu.wv v2, v3, v4 # vs2 should be multiple of 2
  3882. + vwaddu.wv v4, v2, v4 # vd overlap vs1
  3883. + vwaddu.wv v4, v2, v5 # vd overlap vs1
  3884. + vwaddu.wv v0, v2, v4, v0.t # vd overlap vm
  3885. + vwaddu.wx v1, v2, a1 # vd should be multiple of 2
  3886. + vwaddu.wx v2, v2, a1 # OK
  3887. + vwaddu.wx v2, v3, a1 # vs2 should be multiple of 2
  3888. + vwaddu.wx v0, v2, a1, v0.t # vd overlap vm
  3889. +
  3890. + vwsubu.vv v1, v2, v4
  3891. + vwsubu.vv v2, v2, v4
  3892. + vwsubu.vv v2, v3, v4
  3893. + vwsubu.vv v4, v2, v4
  3894. + vwsubu.vv v4, v2, v5
  3895. + vwsubu.vv v0, v2, v4, v0.t
  3896. + vwsubu.vx v1, v2, a1
  3897. + vwsubu.vx v2, v2, a1
  3898. + vwsubu.vx v2, v3, a1
  3899. + vwsubu.vx v0, v2, a1, v0.t
  3900. + vwsubu.wv v1, v2, v4
  3901. + vwsubu.wv v2, v2, v4
  3902. + vwsubu.wv v2, v3, v4
  3903. + vwsubu.wv v4, v2, v4
  3904. + vwsubu.wv v4, v2, v5
  3905. + vwsubu.wv v0, v2, v4, v0.t
  3906. + vwsubu.wx v1, v2, a1
  3907. + vwsubu.wx v2, v2, a1
  3908. + vwsubu.wx v2, v3, a1
  3909. + vwsubu.wx v0, v2, a1, v0.t
  3910. +
  3911. + vwadd.vv v1, v2, v4
  3912. + vwadd.vv v2, v2, v4
  3913. + vwadd.vv v2, v3, v4
  3914. + vwadd.vv v4, v2, v4
  3915. + vwadd.vv v4, v2, v5
  3916. + vwadd.vv v0, v2, v4, v0.t
  3917. + vwadd.vx v1, v2, a1
  3918. + vwadd.vx v2, v2, a1
  3919. + vwadd.vx v2, v3, a1
  3920. + vwadd.vx v0, v2, a1, v0.t
  3921. + vwadd.wv v1, v2, v4
  3922. + vwadd.wv v2, v2, v4
  3923. + vwadd.wv v2, v3, v4
  3924. + vwadd.wv v4, v2, v4
  3925. + vwadd.wv v4, v2, v5
  3926. + vwadd.wv v0, v2, v4, v0.t
  3927. + vwadd.wx v1, v2, a1
  3928. + vwadd.wx v2, v2, a1
  3929. + vwadd.wx v2, v3, a1
  3930. + vwadd.wx v0, v2, a1, v0.t
  3931. +
  3932. + vwsub.vv v1, v2, v4
  3933. + vwsub.vv v2, v2, v4
  3934. + vwsub.vv v2, v3, v4
  3935. + vwsub.vv v4, v2, v4
  3936. + vwsub.vv v4, v2, v5
  3937. + vwsub.vv v0, v2, v4, v0.t
  3938. + vwsub.vx v1, v2, a1
  3939. + vwsub.vx v2, v2, a1
  3940. + vwsub.vx v2, v3, a1
  3941. + vwsub.vx v0, v2, a1, v0.t
  3942. + vwsub.wv v1, v2, v4
  3943. + vwsub.wv v2, v2, v4
  3944. + vwsub.wv v2, v3, v4
  3945. + vwsub.wv v4, v2, v4
  3946. + vwsub.wv v4, v2, v5
  3947. + vwsub.wv v0, v2, v4, v0.t
  3948. + vwsub.wx v1, v2, a1
  3949. + vwsub.wx v2, v2, a1
  3950. + vwsub.wx v2, v3, a1
  3951. + vwsub.wx v0, v2, a1, v0.t
  3952. +
  3953. +# Vector Widening Integer Multiply Instructions
  3954. +
  3955. + vwmul.vv v1, v2, v4 # vd should be multiple of 2
  3956. + vwmul.vv v2, v2, v4 # vd overlap vs2
  3957. + vwmul.vv v2, v3, v4 # vd overlap vs2
  3958. + vwmul.vv v4, v2, v4 # vd overlap vs1
  3959. + vwmul.vv v4, v2, v5 # vd overlap vs1
  3960. + vwmul.vv v0, v2, v4, v0.t # vd overlap vm
  3961. + vwmul.vx v1, v2, a1 # vd should be multiple of 2
  3962. + vwmul.vx v2, v2, a1 # vd overlap vs2
  3963. + vwmul.vx v2, v3, a1 # vd overlap vs2
  3964. + vwmul.vx v0, v2, a1, v0.t # vd overlap vm
  3965. +
  3966. + vwmulu.vv v1, v2, v4
  3967. + vwmulu.vv v2, v2, v4
  3968. + vwmulu.vv v2, v3, v4
  3969. + vwmulu.vv v4, v2, v4
  3970. + vwmulu.vv v4, v2, v5
  3971. + vwmulu.vv v0, v2, v4, v0.t
  3972. + vwmulu.vx v1, v2, a1
  3973. + vwmulu.vx v2, v2, a1
  3974. + vwmulu.vx v2, v3, a1
  3975. + vwmulu.vx v0, v2, a1, v0.t
  3976. +
  3977. + vwmulsu.vv v1, v2, v4
  3978. + vwmulsu.vv v2, v2, v4
  3979. + vwmulsu.vv v2, v3, v4
  3980. + vwmulsu.vv v4, v2, v4
  3981. + vwmulsu.vv v4, v2, v5
  3982. + vwmulsu.vv v0, v2, v4, v0.t
  3983. + vwmulsu.vx v1, v2, a1
  3984. + vwmulsu.vx v2, v2, a1
  3985. + vwmulsu.vx v2, v3, a1
  3986. + vwmulsu.vx v0, v2, a1, v0.t
  3987. +
  3988. +# Vector Widening Integer Multiply-Add Instructions
  3989. +
  3990. + vwmaccu.vv v1, v2, v4 # vd should be multiple of 2
  3991. + vwmaccu.vv v2, v2, v4 # vd overlap vs1
  3992. + vwmaccu.vv v2, v3, v4 # vd overlap vs1
  3993. + vwmaccu.vv v4, v2, v4 # vd overlap vs2
  3994. + vwmaccu.vv v4, v2, v5 # vd overlap vs2
  3995. + vwmaccu.vv v0, v2, v4, v0.t # vd overlap vm
  3996. + vwmaccu.vx v1, a1, v2 # vd should be multiple of 2
  3997. + vwmaccu.vx v2, a1, v2 # vd overlap vs2
  3998. + vwmaccu.vx v2, a1, v3 # vd overlap vs2
  3999. + vwmaccu.vx v0, a1, v2, v0.t # vd overlap vm
  4000. +
  4001. + vwmacc.vv v1, v2, v4
  4002. + vwmacc.vv v2, v2, v4
  4003. + vwmacc.vv v2, v3, v4
  4004. + vwmacc.vv v4, v2, v4
  4005. + vwmacc.vv v4, v2, v5
  4006. + vwmacc.vv v0, v2, v4, v0.t
  4007. + vwmacc.vx v1, a1, v2
  4008. + vwmacc.vx v2, a1, v2
  4009. + vwmacc.vx v2, a1, v3
  4010. + vwmacc.vx v0, a1, v2, v0.t
  4011. +
  4012. + vwmaccsu.vv v1, v2, v4
  4013. + vwmaccsu.vv v2, v2, v4
  4014. + vwmaccsu.vv v2, v3, v4
  4015. + vwmaccsu.vv v4, v2, v4
  4016. + vwmaccsu.vv v4, v2, v5
  4017. + vwmaccsu.vv v0, v2, v4, v0.t
  4018. + vwmaccsu.vx v1, a1, v2
  4019. + vwmaccsu.vx v2, a1, v2
  4020. + vwmaccsu.vx v2, a1, v3
  4021. + vwmaccsu.vx v0, a1, v2, v0.t
  4022. +
  4023. + vwmaccus.vx v1, a1, v2 # vd should be multiple of 2
  4024. + vwmaccus.vx v2, a1, v2 # vd overlap vs2
  4025. + vwmaccus.vx v2, a1, v3 # vd overlap vs2
  4026. + vwmaccus.vx v0, a1, v2, v0.t # vd overlap vm
  4027. +
  4028. +# Vector Widening Floating-Point Add/Subtract Instructions
  4029. +
  4030. + vfwadd.vv v1, v2, v4 # vd should be multiple of 2
  4031. + vfwadd.vv v2, v2, v4 # vd overlap vs2
  4032. + vfwadd.vv v2, v3, v4 # vd overlap vs2
  4033. + vfwadd.vv v4, v2, v4 # vd overlap vs1
  4034. + vfwadd.vv v4, v2, v5 # vd overlap vs1
  4035. + vfwadd.vv v0, v2, v4, v0.t # vd overlap vm
  4036. + vfwadd.vf v1, v2, fa1 # vd should be multiple of 2
  4037. + vfwadd.vf v2, v2, fa1 # vd overlap vs2
  4038. + vfwadd.vf v2, v3, fa1 # vd overlap vs2
  4039. + vfwadd.vf v0, v2, fa1, v0.t # vd overlap vm
  4040. + vfwadd.wv v1, v2, v4 # vd should be multiple of 2
  4041. + vfwadd.wv v2, v2, v4 # OK
  4042. + vfwadd.wv v2, v3, v4 # vs2 should be multiple of 2
  4043. + vfwadd.wv v4, v2, v4 # vd overlap vs1
  4044. + vfwadd.wv v4, v2, v5 # vd overlap vs1
  4045. + vfwadd.wv v0, v2, v4, v0.t # vd overlap vm
  4046. +
  4047. + vfwsub.vv v1, v2, v4
  4048. + vfwsub.vv v2, v2, v4
  4049. + vfwsub.vv v2, v3, v4
  4050. + vfwsub.vv v4, v2, v4
  4051. + vfwsub.vv v4, v2, v5
  4052. + vfwsub.vv v0, v2, v4, v0.t
  4053. + vfwsub.vf v1, v2, fa1
  4054. + vfwsub.vf v2, v2, fa1
  4055. + vfwsub.vf v2, v3, fa1
  4056. + vfwsub.vf v0, v2, fa1, v0.t
  4057. + vfwsub.wv v1, v2, v4
  4058. + vfwsub.wv v2, v2, v4
  4059. + vfwsub.wv v2, v3, v4
  4060. + vfwsub.wv v4, v2, v4
  4061. + vfwsub.wv v4, v2, v5
  4062. + vfwsub.wv v0, v2, v4, v0.t
  4063. +
  4064. +# Vector Widening Floating-Point Multiply
  4065. +
  4066. + vfwmul.vv v1, v2, v4 # vd should be multiple of 2
  4067. + vfwmul.vv v2, v2, v4 # vd overlap vs2
  4068. + vfwmul.vv v2, v3, v4 # vd overlap vs2
  4069. + vfwmul.vv v4, v2, v4 # vd overlap vs1
  4070. + vfwmul.vv v4, v2, v5 # vd overlap vs1
  4071. + vfwmul.vv v0, v2, v4, v0.t # vd overlap vm
  4072. + vfwsub.vf v1, v2, fa1 # vd should be multiple of 2
  4073. + vfwsub.vf v2, v2, fa1 # vd overlap vs2
  4074. + vfwsub.vf v2, v3, fa1 # vd overlap vs2
  4075. + vfwsub.vf v0, v2, fa1, v0.t # vd overlap vm
  4076. +
  4077. +# Vector Widening Floating-Point Fused Multiply-Add Instructions
  4078. + vfwmacc.vv v1, v2, v4 # vd should be multiple of 2
  4079. + vfwmacc.vv v2, v2, v4 # vd overlap vs1
  4080. + vfwmacc.vv v2, v3, v4 # vd overlap vs1
  4081. + vfwmacc.vv v4, v2, v4 # vd overlap vs2
  4082. + vfwmacc.vv v4, v2, v5 # vd overlap vs2
  4083. + vfwmacc.vv v0, v2, v4, v0.t # vd overlap vm
  4084. + vfwmacc.vf v1, fa1, v2 # vd should be multiple of 2
  4085. + vfwmacc.vf v2, fa1, v2 # vd overlap vs2
  4086. + vfwmacc.vf v2, fa1, v3 # vd overlap vs2
  4087. + vfwmacc.vf v0, fa1, v2, v0.t # vd overlap vm
  4088. +
  4089. + vfwnmacc.vv v1, v2, v4
  4090. + vfwnmacc.vv v2, v2, v4
  4091. + vfwnmacc.vv v2, v3, v4
  4092. + vfwnmacc.vv v4, v2, v4
  4093. + vfwnmacc.vv v4, v2, v5
  4094. + vfwnmacc.vv v0, v2, v4, v0.t
  4095. + vfwnmacc.vf v1, fa1, v2
  4096. + vfwnmacc.vf v2, fa1, v2
  4097. + vfwnmacc.vf v2, fa1, v3
  4098. + vfwnmacc.vf v0, fa1, v2, v0.t
  4099. +
  4100. + vfwmsac.vv v1, v2, v4
  4101. + vfwmsac.vv v2, v2, v4
  4102. + vfwmsac.vv v2, v3, v4
  4103. + vfwmsac.vv v4, v2, v4
  4104. + vfwmsac.vv v4, v2, v5
  4105. + vfwmsac.vv v0, v2, v4, v0.t
  4106. + vfwmsac.vf v1, fa1, v2
  4107. + vfwmsac.vf v2, fa1, v2
  4108. + vfwmsac.vf v2, fa1, v3
  4109. + vfwmsac.vf v0, fa1, v2, v0.t
  4110. +
  4111. + vfwnmsac.vv v1, v2, v4
  4112. + vfwnmsac.vv v2, v2, v4
  4113. + vfwnmsac.vv v2, v3, v4
  4114. + vfwnmsac.vv v4, v2, v4
  4115. + vfwnmsac.vv v4, v2, v5
  4116. + vfwnmsac.vv v0, v2, v4, v0.t
  4117. + vfwnmsac.vf v1, fa1, v2
  4118. + vfwnmsac.vf v2, fa1, v2
  4119. + vfwnmsac.vf v2, fa1, v3
  4120. + vfwnmsac.vf v0, fa1, v2, v0.t
  4121. +
  4122. +# Widening Floating-Point/Integer Type-Convert Instructions
  4123. +
  4124. + vfwcvt.xu.f.v v1, v2 # vd should be multiple of 2
  4125. + vfwcvt.xu.f.v v2, v2 # vd overlap vs2
  4126. + vfwcvt.xu.f.v v2, v3 # vd overlap vs2
  4127. + vfwcvt.xu.f.v v0, v2, v0.t # vd overlap vm
  4128. + vfwcvt.x.f.v v1, v2
  4129. + vfwcvt.x.f.v v2, v2
  4130. + vfwcvt.x.f.v v2, v3
  4131. + vfwcvt.x.f.v v0, v2, v0.t
  4132. + vfwcvt.rtz.xu.f.v v1, v2
  4133. + vfwcvt.rtz.xu.f.v v2, v2
  4134. + vfwcvt.rtz.xu.f.v v2, v3
  4135. + vfwcvt.rtz.xu.f.v v0, v2, v0.t
  4136. + vfwcvt.rtz.x.f.v v1, v2
  4137. + vfwcvt.rtz.x.f.v v2, v2
  4138. + vfwcvt.rtz.x.f.v v2, v3
  4139. + vfwcvt.rtz.x.f.v v0, v2, v0.t
  4140. + vfwcvt.f.xu.v v1, v2
  4141. + vfwcvt.f.xu.v v2, v2
  4142. + vfwcvt.f.xu.v v2, v3
  4143. + vfwcvt.f.xu.v v0, v2, v0.t
  4144. + vfwcvt.f.x.v v1, v2
  4145. + vfwcvt.f.x.v v2, v2
  4146. + vfwcvt.f.x.v v2, v3
  4147. + vfwcvt.f.x.v v0, v2, v0.t
  4148. + vfwcvt.f.f.v v1, v2
  4149. + vfwcvt.f.f.v v2, v2
  4150. + vfwcvt.f.f.v v2, v3
  4151. + vfwcvt.f.f.v v0, v2, v0.t
  4152. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
  4153. new file mode 100644
  4154. index 0000000000..763191f31e
  4155. --- /dev/null
  4156. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
  4157. @@ -0,0 +1,3 @@
  4158. +#as: -march=rv32iv -mcheck-constraints
  4159. +#source: vector-insns-fail-load-store.s
  4160. +#error_output: vector-insns-fail-load-store.l
  4161. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
  4162. new file mode 100644
  4163. index 0000000000..bd04cbb263
  4164. --- /dev/null
  4165. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
  4166. @@ -0,0 +1,557 @@
  4167. +.*: Assembler messages:
  4168. +.*Error: illegal operands `vle8.v v0,\(a0\),v0.t'
  4169. +.*Error: illegal operands `vle8ff.v v0,\(a0\),v0.t'
  4170. +.*Error: illegal operands `vle16.v v0,\(a0\),v0.t'
  4171. +.*Error: illegal operands `vle16ff.v v0,\(a0\),v0.t'
  4172. +.*Error: illegal operands `vle32.v v0,\(a0\),v0.t'
  4173. +.*Error: illegal operands `vle32ff.v v0,\(a0\),v0.t'
  4174. +.*Error: illegal operands `vle64.v v0,\(a0\),v0.t'
  4175. +.*Error: illegal operands `vle64ff.v v0,\(a0\),v0.t'
  4176. +.*Error: illegal operands `vle128.v v0,\(a0\),v0.t'
  4177. +.*Error: illegal operands `vle128ff.v v0,\(a0\),v0.t'
  4178. +.*Error: illegal operands `vle256.v v0,\(a0\),v0.t'
  4179. +.*Error: illegal operands `vle256ff.v v0,\(a0\),v0.t'
  4180. +.*Error: illegal operands `vle512.v v0,\(a0\),v0.t'
  4181. +.*Error: illegal operands `vle512ff.v v0,\(a0\),v0.t'
  4182. +.*Error: illegal operands `vle1024.v v0,\(a0\),v0.t'
  4183. +.*Error: illegal operands `vle1024ff.v v0,\(a0\),v0.t'
  4184. +.*Error: illegal operands `vse8.v v0,\(a0\),v0.t'
  4185. +.*Error: illegal operands `vse16.v v0,\(a0\),v0.t'
  4186. +.*Error: illegal operands `vse32.v v0,\(a0\),v0.t'
  4187. +.*Error: illegal operands `vse64.v v0,\(a0\),v0.t'
  4188. +.*Error: illegal operands `vse128.v v0,\(a0\),v0.t'
  4189. +.*Error: illegal operands `vse256.v v0,\(a0\),v0.t'
  4190. +.*Error: illegal operands `vse512.v v0,\(a0\),v0.t'
  4191. +.*Error: illegal operands `vse1024.v v0,\(a0\),v0.t'
  4192. +.*Error: illegal operands `vlse8.v v0,\(a0\),a1,v0.t'
  4193. +.*Error: illegal operands `vlse16.v v0,\(a0\),a1,v0.t'
  4194. +.*Error: illegal operands `vlse32.v v0,\(a0\),a1,v0.t'
  4195. +.*Error: illegal operands `vlse64.v v0,\(a0\),a1,v0.t'
  4196. +.*Error: illegal operands `vlse128.v v0,\(a0\),a1,v0.t'
  4197. +.*Error: illegal operands `vlse256.v v0,\(a0\),a1,v0.t'
  4198. +.*Error: illegal operands `vlse512.v v0,\(a0\),a1,v0.t'
  4199. +.*Error: illegal operands `vlse1024.v v0,\(a0\),a1,v0.t'
  4200. +.*Error: illegal operands `vsse8.v v0,\(a0\),a1,v0.t'
  4201. +.*Error: illegal operands `vsse16.v v0,\(a0\),a1,v0.t'
  4202. +.*Error: illegal operands `vsse32.v v0,\(a0\),a1,v0.t'
  4203. +.*Error: illegal operands `vsse64.v v0,\(a0\),a1,v0.t'
  4204. +.*Error: illegal operands `vsse128.v v0,\(a0\),a1,v0.t'
  4205. +.*Error: illegal operands `vsse256.v v0,\(a0\),a1,v0.t'
  4206. +.*Error: illegal operands `vsse512.v v0,\(a0\),a1,v0.t'
  4207. +.*Error: illegal operands `vsse1024.v v0,\(a0\),a1,v0.t'
  4208. +.*Error: illegal operands `vlxei8.v v0,\(a0\),v4,v0.t'
  4209. +.*Error: illegal operands `vlxei16.v v0,\(a0\),v4,v0.t'
  4210. +.*Error: illegal operands `vlxei32.v v0,\(a0\),v4,v0.t'
  4211. +.*Error: illegal operands `vlxei64.v v0,\(a0\),v4,v0.t'
  4212. +.*Error: illegal operands `vsxei8.v v0,\(a0\),v4,v0.t'
  4213. +.*Error: illegal operands `vsxei16.v v0,\(a0\),v4,v0.t'
  4214. +.*Error: illegal operands `vsxei32.v v0,\(a0\),v4,v0.t'
  4215. +.*Error: illegal operands `vsxei64.v v0,\(a0\),v4,v0.t'
  4216. +.*Error: illegal operands `vsuxei8.v v0,\(a0\),v4,v0.t'
  4217. +.*Error: illegal operands `vsuxei16.v v0,\(a0\),v4,v0.t'
  4218. +.*Error: illegal operands `vsuxei32.v v0,\(a0\),v4,v0.t'
  4219. +.*Error: illegal operands `vsuxei64.v v0,\(a0\),v4,v0.t'
  4220. +.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
  4221. +.*Error: illegal operands `vsseg2e8.v v0,\(a0\),v0.t'
  4222. +.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
  4223. +.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
  4224. +.*Error: illegal operands `vsseg3e8.v v0,\(a0\),v0.t'
  4225. +.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
  4226. +.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
  4227. +.*Error: illegal operands `vsseg4e8.v v0,\(a0\),v0.t'
  4228. +.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
  4229. +.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
  4230. +.*Error: illegal operands `vsseg5e8.v v0,\(a0\),v0.t'
  4231. +.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
  4232. +.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
  4233. +.*Error: illegal operands `vsseg6e8.v v0,\(a0\),v0.t'
  4234. +.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
  4235. +.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
  4236. +.*Error: illegal operands `vsseg7e8.v v0,\(a0\),v0.t'
  4237. +.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
  4238. +.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
  4239. +.*Error: illegal operands `vsseg8e8.v v0,\(a0\),v0.t'
  4240. +.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
  4241. +.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
  4242. +.*Error: illegal operands `vsseg2e16.v v0,\(a0\),v0.t'
  4243. +.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
  4244. +.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
  4245. +.*Error: illegal operands `vsseg3e16.v v0,\(a0\),v0.t'
  4246. +.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
  4247. +.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
  4248. +.*Error: illegal operands `vsseg4e16.v v0,\(a0\),v0.t'
  4249. +.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
  4250. +.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
  4251. +.*Error: illegal operands `vsseg5e16.v v0,\(a0\),v0.t'
  4252. +.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
  4253. +.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
  4254. +.*Error: illegal operands `vsseg6e16.v v0,\(a0\),v0.t'
  4255. +.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
  4256. +.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
  4257. +.*Error: illegal operands `vsseg7e16.v v0,\(a0\),v0.t'
  4258. +.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
  4259. +.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
  4260. +.*Error: illegal operands `vsseg8e16.v v0,\(a0\),v0.t'
  4261. +.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
  4262. +.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
  4263. +.*Error: illegal operands `vsseg2e32.v v0,\(a0\),v0.t'
  4264. +.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
  4265. +.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
  4266. +.*Error: illegal operands `vsseg3e32.v v0,\(a0\),v0.t'
  4267. +.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
  4268. +.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
  4269. +.*Error: illegal operands `vsseg4e32.v v0,\(a0\),v0.t'
  4270. +.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
  4271. +.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
  4272. +.*Error: illegal operands `vsseg5e32.v v0,\(a0\),v0.t'
  4273. +.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
  4274. +.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
  4275. +.*Error: illegal operands `vsseg6e32.v v0,\(a0\),v0.t'
  4276. +.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
  4277. +.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
  4278. +.*Error: illegal operands `vsseg7e32.v v0,\(a0\),v0.t'
  4279. +.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
  4280. +.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
  4281. +.*Error: illegal operands `vsseg8e32.v v0,\(a0\),v0.t'
  4282. +.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
  4283. +.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
  4284. +.*Error: illegal operands `vsseg2e64.v v0,\(a0\),v0.t'
  4285. +.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
  4286. +.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
  4287. +.*Error: illegal operands `vsseg3e64.v v0,\(a0\),v0.t'
  4288. +.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
  4289. +.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
  4290. +.*Error: illegal operands `vsseg4e64.v v0,\(a0\),v0.t'
  4291. +.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
  4292. +.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
  4293. +.*Error: illegal operands `vsseg5e64.v v0,\(a0\),v0.t'
  4294. +.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
  4295. +.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
  4296. +.*Error: illegal operands `vsseg6e64.v v0,\(a0\),v0.t'
  4297. +.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
  4298. +.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
  4299. +.*Error: illegal operands `vsseg7e64.v v0,\(a0\),v0.t'
  4300. +.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
  4301. +.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
  4302. +.*Error: illegal operands `vsseg8e64.v v0,\(a0\),v0.t'
  4303. +.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
  4304. +.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
  4305. +.*Error: illegal operands `vsseg2e128.v v0,\(a0\),v0.t'
  4306. +.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
  4307. +.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
  4308. +.*Error: illegal operands `vsseg3e128.v v0,\(a0\),v0.t'
  4309. +.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
  4310. +.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
  4311. +.*Error: illegal operands `vsseg4e128.v v0,\(a0\),v0.t'
  4312. +.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
  4313. +.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
  4314. +.*Error: illegal operands `vsseg5e128.v v0,\(a0\),v0.t'
  4315. +.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
  4316. +.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
  4317. +.*Error: illegal operands `vsseg6e128.v v0,\(a0\),v0.t'
  4318. +.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
  4319. +.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
  4320. +.*Error: illegal operands `vsseg7e128.v v0,\(a0\),v0.t'
  4321. +.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
  4322. +.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
  4323. +.*Error: illegal operands `vsseg8e128.v v0,\(a0\),v0.t'
  4324. +.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
  4325. +.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
  4326. +.*Error: illegal operands `vsseg2e256.v v0,\(a0\),v0.t'
  4327. +.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
  4328. +.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
  4329. +.*Error: illegal operands `vsseg3e256.v v0,\(a0\),v0.t'
  4330. +.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
  4331. +.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
  4332. +.*Error: illegal operands `vsseg4e256.v v0,\(a0\),v0.t'
  4333. +.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
  4334. +.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
  4335. +.*Error: illegal operands `vsseg5e256.v v0,\(a0\),v0.t'
  4336. +.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
  4337. +.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
  4338. +.*Error: illegal operands `vsseg6e256.v v0,\(a0\),v0.t'
  4339. +.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
  4340. +.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
  4341. +.*Error: illegal operands `vsseg7e256.v v0,\(a0\),v0.t'
  4342. +.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
  4343. +.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
  4344. +.*Error: illegal operands `vsseg8e256.v v0,\(a0\),v0.t'
  4345. +.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
  4346. +.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
  4347. +.*Error: illegal operands `vsseg2e512.v v0,\(a0\),v0.t'
  4348. +.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
  4349. +.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
  4350. +.*Error: illegal operands `vsseg3e512.v v0,\(a0\),v0.t'
  4351. +.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
  4352. +.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
  4353. +.*Error: illegal operands `vsseg4e512.v v0,\(a0\),v0.t'
  4354. +.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
  4355. +.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
  4356. +.*Error: illegal operands `vsseg5e512.v v0,\(a0\),v0.t'
  4357. +.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
  4358. +.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
  4359. +.*Error: illegal operands `vsseg6e512.v v0,\(a0\),v0.t'
  4360. +.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
  4361. +.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
  4362. +.*Error: illegal operands `vsseg7e512.v v0,\(a0\),v0.t'
  4363. +.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
  4364. +.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
  4365. +.*Error: illegal operands `vsseg8e512.v v0,\(a0\),v0.t'
  4366. +.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
  4367. +.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
  4368. +.*Error: illegal operands `vsseg2e1024.v v0,\(a0\),v0.t'
  4369. +.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
  4370. +.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
  4371. +.*Error: illegal operands `vsseg3e1024.v v0,\(a0\),v0.t'
  4372. +.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
  4373. +.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
  4374. +.*Error: illegal operands `vsseg4e1024.v v0,\(a0\),v0.t'
  4375. +.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
  4376. +.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
  4377. +.*Error: illegal operands `vsseg5e1024.v v0,\(a0\),v0.t'
  4378. +.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
  4379. +.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
  4380. +.*Error: illegal operands `vsseg6e1024.v v0,\(a0\),v0.t'
  4381. +.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
  4382. +.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
  4383. +.*Error: illegal operands `vsseg7e1024.v v0,\(a0\),v0.t'
  4384. +.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
  4385. +.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
  4386. +.*Error: illegal operands `vsseg8e1024.v v0,\(a0\),v0.t'
  4387. +.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
  4388. +.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
  4389. +.*Error: illegal operands `vssseg2e8.v v0,\(a0\),a1,v0.t'
  4390. +.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
  4391. +.*Error: illegal operands `vssseg3e8.v v0,\(a0\),a1,v0.t'
  4392. +.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
  4393. +.*Error: illegal operands `vssseg4e8.v v0,\(a0\),a1,v0.t'
  4394. +.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
  4395. +.*Error: illegal operands `vssseg5e8.v v0,\(a0\),a1,v0.t'
  4396. +.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
  4397. +.*Error: illegal operands `vssseg6e8.v v0,\(a0\),a1,v0.t'
  4398. +.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
  4399. +.*Error: illegal operands `vssseg7e8.v v0,\(a0\),a1,v0.t'
  4400. +.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
  4401. +.*Error: illegal operands `vssseg8e8.v v0,\(a0\),a1,v0.t'
  4402. +.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
  4403. +.*Error: illegal operands `vssseg2e16.v v0,\(a0\),a1,v0.t'
  4404. +.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
  4405. +.*Error: illegal operands `vssseg3e16.v v0,\(a0\),a1,v0.t'
  4406. +.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
  4407. +.*Error: illegal operands `vssseg4e16.v v0,\(a0\),a1,v0.t'
  4408. +.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
  4409. +.*Error: illegal operands `vssseg5e16.v v0,\(a0\),a1,v0.t'
  4410. +.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
  4411. +.*Error: illegal operands `vssseg6e16.v v0,\(a0\),a1,v0.t'
  4412. +.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
  4413. +.*Error: illegal operands `vssseg7e16.v v0,\(a0\),a1,v0.t'
  4414. +.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
  4415. +.*Error: illegal operands `vssseg8e16.v v0,\(a0\),a1,v0.t'
  4416. +.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
  4417. +.*Error: illegal operands `vssseg2e32.v v0,\(a0\),a1,v0.t'
  4418. +.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
  4419. +.*Error: illegal operands `vssseg3e32.v v0,\(a0\),a1,v0.t'
  4420. +.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
  4421. +.*Error: illegal operands `vssseg4e32.v v0,\(a0\),a1,v0.t'
  4422. +.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
  4423. +.*Error: illegal operands `vssseg5e32.v v0,\(a0\),a1,v0.t'
  4424. +.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
  4425. +.*Error: illegal operands `vssseg6e32.v v0,\(a0\),a1,v0.t'
  4426. +.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
  4427. +.*Error: illegal operands `vssseg7e32.v v0,\(a0\),a1,v0.t'
  4428. +.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
  4429. +.*Error: illegal operands `vssseg8e32.v v0,\(a0\),a1,v0.t'
  4430. +.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
  4431. +.*Error: illegal operands `vssseg2e64.v v0,\(a0\),a1,v0.t'
  4432. +.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
  4433. +.*Error: illegal operands `vssseg3e64.v v0,\(a0\),a1,v0.t'
  4434. +.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
  4435. +.*Error: illegal operands `vssseg4e64.v v0,\(a0\),a1,v0.t'
  4436. +.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
  4437. +.*Error: illegal operands `vssseg5e64.v v0,\(a0\),a1,v0.t'
  4438. +.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
  4439. +.*Error: illegal operands `vssseg6e64.v v0,\(a0\),a1,v0.t'
  4440. +.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
  4441. +.*Error: illegal operands `vssseg7e64.v v0,\(a0\),a1,v0.t'
  4442. +.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
  4443. +.*Error: illegal operands `vssseg8e64.v v0,\(a0\),a1,v0.t'
  4444. +.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
  4445. +.*Error: illegal operands `vssseg2e128.v v0,\(a0\),a1,v0.t'
  4446. +.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
  4447. +.*Error: illegal operands `vssseg3e128.v v0,\(a0\),a1,v0.t'
  4448. +.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
  4449. +.*Error: illegal operands `vssseg4e128.v v0,\(a0\),a1,v0.t'
  4450. +.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
  4451. +.*Error: illegal operands `vssseg5e128.v v0,\(a0\),a1,v0.t'
  4452. +.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
  4453. +.*Error: illegal operands `vssseg6e128.v v0,\(a0\),a1,v0.t'
  4454. +.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
  4455. +.*Error: illegal operands `vssseg7e128.v v0,\(a0\),a1,v0.t'
  4456. +.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
  4457. +.*Error: illegal operands `vssseg8e128.v v0,\(a0\),a1,v0.t'
  4458. +.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
  4459. +.*Error: illegal operands `vssseg2e256.v v0,\(a0\),a1,v0.t'
  4460. +.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
  4461. +.*Error: illegal operands `vssseg3e256.v v0,\(a0\),a1,v0.t'
  4462. +.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
  4463. +.*Error: illegal operands `vssseg4e256.v v0,\(a0\),a1,v0.t'
  4464. +.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
  4465. +.*Error: illegal operands `vssseg5e256.v v0,\(a0\),a1,v0.t'
  4466. +.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
  4467. +.*Error: illegal operands `vssseg6e256.v v0,\(a0\),a1,v0.t'
  4468. +.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
  4469. +.*Error: illegal operands `vssseg7e256.v v0,\(a0\),a1,v0.t'
  4470. +.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
  4471. +.*Error: illegal operands `vssseg8e256.v v0,\(a0\),a1,v0.t'
  4472. +.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
  4473. +.*Error: illegal operands `vssseg2e512.v v0,\(a0\),a1,v0.t'
  4474. +.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
  4475. +.*Error: illegal operands `vssseg3e512.v v0,\(a0\),a1,v0.t'
  4476. +.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
  4477. +.*Error: illegal operands `vssseg4e512.v v0,\(a0\),a1,v0.t'
  4478. +.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
  4479. +.*Error: illegal operands `vssseg5e512.v v0,\(a0\),a1,v0.t'
  4480. +.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
  4481. +.*Error: illegal operands `vssseg6e512.v v0,\(a0\),a1,v0.t'
  4482. +.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
  4483. +.*Error: illegal operands `vssseg7e512.v v0,\(a0\),a1,v0.t'
  4484. +.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
  4485. +.*Error: illegal operands `vssseg8e512.v v0,\(a0\),a1,v0.t'
  4486. +.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
  4487. +.*Error: illegal operands `vssseg2e1024.v v0,\(a0\),a1,v0.t'
  4488. +.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
  4489. +.*Error: illegal operands `vssseg3e1024.v v0,\(a0\),a1,v0.t'
  4490. +.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
  4491. +.*Error: illegal operands `vssseg4e1024.v v0,\(a0\),a1,v0.t'
  4492. +.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
  4493. +.*Error: illegal operands `vssseg5e1024.v v0,\(a0\),a1,v0.t'
  4494. +.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
  4495. +.*Error: illegal operands `vssseg6e1024.v v0,\(a0\),a1,v0.t'
  4496. +.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
  4497. +.*Error: illegal operands `vssseg7e1024.v v0,\(a0\),a1,v0.t'
  4498. +.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
  4499. +.*Error: illegal operands `vssseg8e1024.v v0,\(a0\),a1,v0.t'
  4500. +.*Error: illegal operands `vlxseg2ei8.v v4,\(a0\),v4'
  4501. +.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v4,v0.t'
  4502. +.*Error: illegal operands `vsxseg2ei8.v v4,\(a0\),v4'
  4503. +.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v4,v0.t'
  4504. +.*Error: illegal operands `vlxseg3ei8.v v4,\(a0\),v4'
  4505. +.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v4,v0.t'
  4506. +.*Error: illegal operands `vsxseg3ei8.v v4,\(a0\),v4'
  4507. +.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v4,v0.t'
  4508. +.*Error: illegal operands `vlxseg4ei8.v v4,\(a0\),v4'
  4509. +.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v4,v0.t'
  4510. +.*Error: illegal operands `vsxseg4ei8.v v4,\(a0\),v4'
  4511. +.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v4,v0.t'
  4512. +.*Error: illegal operands `vlxseg5ei8.v v4,\(a0\),v4'
  4513. +.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v4,v0.t'
  4514. +.*Error: illegal operands `vsxseg5ei8.v v4,\(a0\),v4'
  4515. +.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v4,v0.t'
  4516. +.*Error: illegal operands `vlxseg6ei8.v v4,\(a0\),v4'
  4517. +.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v4,v0.t'
  4518. +.*Error: illegal operands `vsxseg6ei8.v v4,\(a0\),v4'
  4519. +.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v4,v0.t'
  4520. +.*Error: illegal operands `vlxseg7ei8.v v4,\(a0\),v4'
  4521. +.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v4,v0.t'
  4522. +.*Error: illegal operands `vsxseg7ei8.v v4,\(a0\),v4'
  4523. +.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v4,v0.t'
  4524. +.*Error: illegal operands `vlxseg8ei8.v v4,\(a0\),v4'
  4525. +.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v4,v0.t'
  4526. +.*Error: illegal operands `vsxseg8ei8.v v4,\(a0\),v4'
  4527. +.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v4,v0.t'
  4528. +.*Error: illegal operands `vlxseg2ei16.v v4,\(a0\),v4'
  4529. +.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v4,v0.t'
  4530. +.*Error: illegal operands `vsxseg2ei16.v v4,\(a0\),v4'
  4531. +.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v4,v0.t'
  4532. +.*Error: illegal operands `vlxseg3ei16.v v4,\(a0\),v4'
  4533. +.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v4,v0.t'
  4534. +.*Error: illegal operands `vsxseg3ei16.v v4,\(a0\),v4'
  4535. +.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v4,v0.t'
  4536. +.*Error: illegal operands `vlxseg4ei16.v v4,\(a0\),v4'
  4537. +.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v4,v0.t'
  4538. +.*Error: illegal operands `vsxseg4ei16.v v4,\(a0\),v4'
  4539. +.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v4,v0.t'
  4540. +.*Error: illegal operands `vlxseg5ei16.v v4,\(a0\),v4'
  4541. +.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v4,v0.t'
  4542. +.*Error: illegal operands `vsxseg5ei16.v v4,\(a0\),v4'
  4543. +.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v4,v0.t'
  4544. +.*Error: illegal operands `vlxseg6ei16.v v4,\(a0\),v4'
  4545. +.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v4,v0.t'
  4546. +.*Error: illegal operands `vsxseg6ei16.v v4,\(a0\),v4'
  4547. +.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v4,v0.t'
  4548. +.*Error: illegal operands `vlxseg7ei16.v v4,\(a0\),v4'
  4549. +.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v4,v0.t'
  4550. +.*Error: illegal operands `vsxseg7ei16.v v4,\(a0\),v4'
  4551. +.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v4,v0.t'
  4552. +.*Error: illegal operands `vlxseg8ei16.v v4,\(a0\),v4'
  4553. +.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v4,v0.t'
  4554. +.*Error: illegal operands `vsxseg8ei16.v v4,\(a0\),v4'
  4555. +.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v4,v0.t'
  4556. +.*Error: illegal operands `vlxseg2ei32.v v4,\(a0\),v4'
  4557. +.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v4,v0.t'
  4558. +.*Error: illegal operands `vsxseg2ei32.v v4,\(a0\),v4'
  4559. +.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v4,v0.t'
  4560. +.*Error: illegal operands `vlxseg3ei32.v v4,\(a0\),v4'
  4561. +.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v4,v0.t'
  4562. +.*Error: illegal operands `vsxseg3ei32.v v4,\(a0\),v4'
  4563. +.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v4,v0.t'
  4564. +.*Error: illegal operands `vlxseg4ei32.v v4,\(a0\),v4'
  4565. +.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v4,v0.t'
  4566. +.*Error: illegal operands `vsxseg4ei32.v v4,\(a0\),v4'
  4567. +.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v4,v0.t'
  4568. +.*Error: illegal operands `vlxseg5ei32.v v4,\(a0\),v4'
  4569. +.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v4,v0.t'
  4570. +.*Error: illegal operands `vsxseg5ei32.v v4,\(a0\),v4'
  4571. +.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v4,v0.t'
  4572. +.*Error: illegal operands `vlxseg6ei32.v v4,\(a0\),v4'
  4573. +.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v4,v0.t'
  4574. +.*Error: illegal operands `vsxseg6ei32.v v4,\(a0\),v4'
  4575. +.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v4,v0.t'
  4576. +.*Error: illegal operands `vlxseg7ei32.v v4,\(a0\),v4'
  4577. +.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v4,v0.t'
  4578. +.*Error: illegal operands `vsxseg7ei32.v v4,\(a0\),v4'
  4579. +.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v4,v0.t'
  4580. +.*Error: illegal operands `vlxseg8ei32.v v4,\(a0\),v4'
  4581. +.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v4,v0.t'
  4582. +.*Error: illegal operands `vsxseg8ei32.v v4,\(a0\),v4'
  4583. +.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v4,v0.t'
  4584. +.*Error: illegal operands `vlxseg2ei64.v v4,\(a0\),v4'
  4585. +.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v4,v0.t'
  4586. +.*Error: illegal operands `vsxseg2ei64.v v4,\(a0\),v4'
  4587. +.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v4,v0.t'
  4588. +.*Error: illegal operands `vlxseg3ei64.v v4,\(a0\),v4'
  4589. +.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v4,v0.t'
  4590. +.*Error: illegal operands `vsxseg3ei64.v v4,\(a0\),v4'
  4591. +.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v4,v0.t'
  4592. +.*Error: illegal operands `vlxseg4ei64.v v4,\(a0\),v4'
  4593. +.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v4,v0.t'
  4594. +.*Error: illegal operands `vsxseg4ei64.v v4,\(a0\),v4'
  4595. +.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v4,v0.t'
  4596. +.*Error: illegal operands `vlxseg5ei64.v v4,\(a0\),v4'
  4597. +.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v4,v0.t'
  4598. +.*Error: illegal operands `vsxseg5ei64.v v4,\(a0\),v4'
  4599. +.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v4,v0.t'
  4600. +.*Error: illegal operands `vlxseg6ei64.v v4,\(a0\),v4'
  4601. +.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v4,v0.t'
  4602. +.*Error: illegal operands `vsxseg6ei64.v v4,\(a0\),v4'
  4603. +.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v4,v0.t'
  4604. +.*Error: illegal operands `vlxseg7ei64.v v4,\(a0\),v4'
  4605. +.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v4,v0.t'
  4606. +.*Error: illegal operands `vsxseg7ei64.v v4,\(a0\),v4'
  4607. +.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v4,v0.t'
  4608. +.*Error: illegal operands `vlxseg8ei64.v v4,\(a0\),v4'
  4609. +.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v4,v0.t'
  4610. +.*Error: illegal operands `vsxseg8ei64.v v4,\(a0\),v4'
  4611. +.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v4,v0.t'
  4612. +.*Error: illegal operands `vlxseg2ei128.v v4,\(a0\),v4'
  4613. +.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v4,v0.t'
  4614. +.*Error: illegal operands `vsxseg2ei128.v v4,\(a0\),v4'
  4615. +.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v4,v0.t'
  4616. +.*Error: illegal operands `vlxseg3ei128.v v4,\(a0\),v4'
  4617. +.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v4,v0.t'
  4618. +.*Error: illegal operands `vsxseg3ei128.v v4,\(a0\),v4'
  4619. +.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v4,v0.t'
  4620. +.*Error: illegal operands `vlxseg4ei128.v v4,\(a0\),v4'
  4621. +.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v4,v0.t'
  4622. +.*Error: illegal operands `vsxseg4ei128.v v4,\(a0\),v4'
  4623. +.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v4,v0.t'
  4624. +.*Error: illegal operands `vlxseg5ei128.v v4,\(a0\),v4'
  4625. +.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v4,v0.t'
  4626. +.*Error: illegal operands `vsxseg5ei128.v v4,\(a0\),v4'
  4627. +.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v4,v0.t'
  4628. +.*Error: illegal operands `vlxseg6ei128.v v4,\(a0\),v4'
  4629. +.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v4,v0.t'
  4630. +.*Error: illegal operands `vsxseg6ei128.v v4,\(a0\),v4'
  4631. +.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v4,v0.t'
  4632. +.*Error: illegal operands `vlxseg7ei128.v v4,\(a0\),v4'
  4633. +.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v4,v0.t'
  4634. +.*Error: illegal operands `vsxseg7ei128.v v4,\(a0\),v4'
  4635. +.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v4,v0.t'
  4636. +.*Error: illegal operands `vlxseg8ei128.v v4,\(a0\),v4'
  4637. +.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v4,v0.t'
  4638. +.*Error: illegal operands `vsxseg8ei128.v v4,\(a0\),v4'
  4639. +.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v4,v0.t'
  4640. +.*Error: illegal operands `vlxseg2ei256.v v4,\(a0\),v4'
  4641. +.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v4,v0.t'
  4642. +.*Error: illegal operands `vsxseg2ei256.v v4,\(a0\),v4'
  4643. +.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v4,v0.t'
  4644. +.*Error: illegal operands `vlxseg3ei256.v v4,\(a0\),v4'
  4645. +.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v4,v0.t'
  4646. +.*Error: illegal operands `vsxseg3ei256.v v4,\(a0\),v4'
  4647. +.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v4,v0.t'
  4648. +.*Error: illegal operands `vlxseg4ei256.v v4,\(a0\),v4'
  4649. +.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v4,v0.t'
  4650. +.*Error: illegal operands `vsxseg4ei256.v v4,\(a0\),v4'
  4651. +.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v4,v0.t'
  4652. +.*Error: illegal operands `vlxseg5ei256.v v4,\(a0\),v4'
  4653. +.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v4,v0.t'
  4654. +.*Error: illegal operands `vsxseg5ei256.v v4,\(a0\),v4'
  4655. +.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v4,v0.t'
  4656. +.*Error: illegal operands `vlxseg6ei256.v v4,\(a0\),v4'
  4657. +.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v4,v0.t'
  4658. +.*Error: illegal operands `vsxseg6ei256.v v4,\(a0\),v4'
  4659. +.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v4,v0.t'
  4660. +.*Error: illegal operands `vlxseg7ei256.v v4,\(a0\),v4'
  4661. +.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v4,v0.t'
  4662. +.*Error: illegal operands `vsxseg7ei256.v v4,\(a0\),v4'
  4663. +.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v4,v0.t'
  4664. +.*Error: illegal operands `vlxseg8ei256.v v4,\(a0\),v4'
  4665. +.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v4,v0.t'
  4666. +.*Error: illegal operands `vsxseg8ei256.v v4,\(a0\),v4'
  4667. +.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v4,v0.t'
  4668. +.*Error: illegal operands `vlxseg2ei512.v v4,\(a0\),v4'
  4669. +.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v4,v0.t'
  4670. +.*Error: illegal operands `vsxseg2ei512.v v4,\(a0\),v4'
  4671. +.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v4,v0.t'
  4672. +.*Error: illegal operands `vlxseg3ei512.v v4,\(a0\),v4'
  4673. +.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v4,v0.t'
  4674. +.*Error: illegal operands `vsxseg3ei512.v v4,\(a0\),v4'
  4675. +.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v4,v0.t'
  4676. +.*Error: illegal operands `vlxseg4ei512.v v4,\(a0\),v4'
  4677. +.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v4,v0.t'
  4678. +.*Error: illegal operands `vsxseg4ei512.v v4,\(a0\),v4'
  4679. +.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v4,v0.t'
  4680. +.*Error: illegal operands `vlxseg5ei512.v v4,\(a0\),v4'
  4681. +.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v4,v0.t'
  4682. +.*Error: illegal operands `vsxseg5ei512.v v4,\(a0\),v4'
  4683. +.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v4,v0.t'
  4684. +.*Error: illegal operands `vlxseg6ei512.v v4,\(a0\),v4'
  4685. +.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v4,v0.t'
  4686. +.*Error: illegal operands `vsxseg6ei512.v v4,\(a0\),v4'
  4687. +.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v4,v0.t'
  4688. +.*Error: illegal operands `vlxseg7ei512.v v4,\(a0\),v4'
  4689. +.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v4,v0.t'
  4690. +.*Error: illegal operands `vsxseg7ei512.v v4,\(a0\),v4'
  4691. +.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v4,v0.t'
  4692. +.*Error: illegal operands `vlxseg8ei512.v v4,\(a0\),v4'
  4693. +.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v4,v0.t'
  4694. +.*Error: illegal operands `vsxseg8ei512.v v4,\(a0\),v4'
  4695. +.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v4,v0.t'
  4696. +.*Error: illegal operands `vlxseg2ei1024.v v4,\(a0\),v4'
  4697. +.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v4,v0.t'
  4698. +.*Error: illegal operands `vsxseg2ei1024.v v4,\(a0\),v4'
  4699. +.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v4,v0.t'
  4700. +.*Error: illegal operands `vlxseg3ei1024.v v4,\(a0\),v4'
  4701. +.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v4,v0.t'
  4702. +.*Error: illegal operands `vsxseg3ei1024.v v4,\(a0\),v4'
  4703. +.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v4,v0.t'
  4704. +.*Error: illegal operands `vlxseg4ei1024.v v4,\(a0\),v4'
  4705. +.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v4,v0.t'
  4706. +.*Error: illegal operands `vsxseg4ei1024.v v4,\(a0\),v4'
  4707. +.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v4,v0.t'
  4708. +.*Error: illegal operands `vlxseg5ei1024.v v4,\(a0\),v4'
  4709. +.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v4,v0.t'
  4710. +.*Error: illegal operands `vsxseg5ei1024.v v4,\(a0\),v4'
  4711. +.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v4,v0.t'
  4712. +.*Error: illegal operands `vlxseg6ei1024.v v4,\(a0\),v4'
  4713. +.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v4,v0.t'
  4714. +.*Error: illegal operands `vsxseg6ei1024.v v4,\(a0\),v4'
  4715. +.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v4,v0.t'
  4716. +.*Error: illegal operands `vlxseg7ei1024.v v4,\(a0\),v4'
  4717. +.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v4,v0.t'
  4718. +.*Error: illegal operands `vsxseg7ei1024.v v4,\(a0\),v4'
  4719. +.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v4,v0.t'
  4720. +.*Error: illegal operands `vlxseg8ei1024.v v4,\(a0\),v4'
  4721. +.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v4,v0.t'
  4722. +.*Error: illegal operands `vsxseg8ei1024.v v4,\(a0\),v4'
  4723. +.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v4,v0.t'
  4724. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
  4725. new file mode 100644
  4726. index 0000000000..05f9358aed
  4727. --- /dev/null
  4728. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
  4729. @@ -0,0 +1,610 @@
  4730. +# Vector Unit-Stride Loads and Stores
  4731. +
  4732. + vle8.v v0, (a0), v0.t # vd overlap vm
  4733. + vle8ff.v v0, (a0), v0.t # vd overlap vm
  4734. + vle16.v v0, (a0), v0.t
  4735. + vle16ff.v v0, (a0), v0.t
  4736. + vle32.v v0, (a0), v0.t
  4737. + vle32ff.v v0, (a0), v0.t
  4738. + vle64.v v0, (a0), v0.t
  4739. + vle64ff.v v0, (a0), v0.t
  4740. + vle128.v v0, (a0), v0.t
  4741. + vle128ff.v v0, (a0), v0.t
  4742. + vle256.v v0, (a0), v0.t
  4743. + vle256ff.v v0, (a0), v0.t
  4744. + vle512.v v0, (a0), v0.t
  4745. + vle512ff.v v0, (a0), v0.t
  4746. + vle1024.v v0, (a0), v0.t
  4747. + vle1024ff.v v0, (a0), v0.t
  4748. +
  4749. + vse8.v v0, (a0), v0.t # vd overlap vm
  4750. + vse16.v v0, (a0), v0.t
  4751. + vse32.v v0, (a0), v0.t
  4752. + vse64.v v0, (a0), v0.t
  4753. + vse128.v v0, (a0), v0.t
  4754. + vse256.v v0, (a0), v0.t
  4755. + vse512.v v0, (a0), v0.t
  4756. + vse1024.v v0, (a0), v0.t
  4757. +
  4758. +# Vector Strided Loads and Stores
  4759. +
  4760. + vlse8.v v0, (a0), a1, v0.t # vd overlap vm
  4761. + vlse16.v v0, (a0), a1, v0.t
  4762. + vlse32.v v0, (a0), a1, v0.t
  4763. + vlse64.v v0, (a0), a1, v0.t
  4764. + vlse128.v v0, (a0), a1, v0.t
  4765. + vlse256.v v0, (a0), a1, v0.t
  4766. + vlse512.v v0, (a0), a1, v0.t
  4767. + vlse1024.v v0, (a0), a1, v0.t
  4768. +
  4769. + vsse8.v v0, (a0), a1, v0.t
  4770. + vsse16.v v0, (a0), a1, v0.t
  4771. + vsse32.v v0, (a0), a1, v0.t
  4772. + vsse64.v v0, (a0), a1, v0.t
  4773. + vsse128.v v0, (a0), a1, v0.t
  4774. + vsse256.v v0, (a0), a1, v0.t
  4775. + vsse512.v v0, (a0), a1, v0.t
  4776. + vsse1024.v v0, (a0), a1, v0.t
  4777. +
  4778. +# Vector Indexed Loads and Stores
  4779. +
  4780. + vlxei8.v v4, (a0), v4 # OK
  4781. + vlxei8.v v0, (a0), v4, v0.t # vd overlap vm
  4782. + vlxei16.v v4, (a0), v4
  4783. + vlxei16.v v0, (a0), v4, v0.t
  4784. + vlxei32.v v4, (a0), v4
  4785. + vlxei32.v v0, (a0), v4, v0.t
  4786. + vlxei64.v v4, (a0), v4
  4787. + vlxei64.v v0, (a0), v4, v0.t
  4788. +
  4789. + vsxei8.v v4, (a0), v4
  4790. + vsxei8.v v0, (a0), v4, v0.t
  4791. + vsxei16.v v4, (a0), v4
  4792. + vsxei16.v v0, (a0), v4, v0.t
  4793. + vsxei32.v v4, (a0), v4
  4794. + vsxei32.v v0, (a0), v4, v0.t
  4795. + vsxei64.v v4, (a0), v4
  4796. + vsxei64.v v0, (a0), v4, v0.t
  4797. +
  4798. + vsuxei8.v v4, (a0), v4
  4799. + vsuxei8.v v0, (a0), v4, v0.t
  4800. + vsuxei16.v v4, (a0), v4
  4801. + vsuxei16.v v0, (a0), v4, v0.t
  4802. + vsuxei32.v v4, (a0), v4
  4803. + vsuxei32.v v0, (a0), v4, v0.t
  4804. + vsuxei64.v v4, (a0), v4
  4805. + vsuxei64.v v0, (a0), v4, v0.t
  4806. +
  4807. +# Vector Unit-Stride Segment Loads and Stores
  4808. +
  4809. + vlseg2e8.v v0, (a0), v0.t # vd overlap vm
  4810. + vsseg2e8.v v0, (a0), v0.t # vd overlap vm
  4811. + vlseg2e8ff.v v0, (a0), v0.t # vd overlap vm
  4812. + vlseg3e8.v v0, (a0), v0.t
  4813. + vsseg3e8.v v0, (a0), v0.t
  4814. + vlseg3e8ff.v v0, (a0), v0.t
  4815. + vlseg4e8.v v0, (a0), v0.t
  4816. + vsseg4e8.v v0, (a0), v0.t
  4817. + vlseg4e8ff.v v0, (a0), v0.t
  4818. + vlseg5e8.v v0, (a0), v0.t
  4819. + vsseg5e8.v v0, (a0), v0.t
  4820. + vlseg5e8ff.v v0, (a0), v0.t
  4821. + vlseg6e8.v v0, (a0), v0.t
  4822. + vsseg6e8.v v0, (a0), v0.t
  4823. + vlseg6e8ff.v v0, (a0), v0.t
  4824. + vlseg7e8.v v0, (a0), v0.t
  4825. + vsseg7e8.v v0, (a0), v0.t
  4826. + vlseg7e8ff.v v0, (a0), v0.t
  4827. + vlseg8e8.v v0, (a0), v0.t
  4828. + vsseg8e8.v v0, (a0), v0.t
  4829. + vlseg8e8ff.v v0, (a0), v0.t
  4830. +
  4831. + vlseg2e16.v v0, (a0), v0.t
  4832. + vsseg2e16.v v0, (a0), v0.t
  4833. + vlseg2e16ff.v v0, (a0), v0.t
  4834. + vlseg3e16.v v0, (a0), v0.t
  4835. + vsseg3e16.v v0, (a0), v0.t
  4836. + vlseg3e16ff.v v0, (a0), v0.t
  4837. + vlseg4e16.v v0, (a0), v0.t
  4838. + vsseg4e16.v v0, (a0), v0.t
  4839. + vlseg4e16ff.v v0, (a0), v0.t
  4840. + vlseg5e16.v v0, (a0), v0.t
  4841. + vsseg5e16.v v0, (a0), v0.t
  4842. + vlseg5e16ff.v v0, (a0), v0.t
  4843. + vlseg6e16.v v0, (a0), v0.t
  4844. + vsseg6e16.v v0, (a0), v0.t
  4845. + vlseg6e16ff.v v0, (a0), v0.t
  4846. + vlseg7e16.v v0, (a0), v0.t
  4847. + vsseg7e16.v v0, (a0), v0.t
  4848. + vlseg7e16ff.v v0, (a0), v0.t
  4849. + vlseg8e16.v v0, (a0), v0.t
  4850. + vsseg8e16.v v0, (a0), v0.t
  4851. + vlseg8e16ff.v v0, (a0), v0.t
  4852. +
  4853. + vlseg2e32.v v0, (a0), v0.t
  4854. + vsseg2e32.v v0, (a0), v0.t
  4855. + vlseg2e32ff.v v0, (a0), v0.t
  4856. + vlseg3e32.v v0, (a0), v0.t
  4857. + vsseg3e32.v v0, (a0), v0.t
  4858. + vlseg3e32ff.v v0, (a0), v0.t
  4859. + vlseg4e32.v v0, (a0), v0.t
  4860. + vsseg4e32.v v0, (a0), v0.t
  4861. + vlseg4e32ff.v v0, (a0), v0.t
  4862. + vlseg5e32.v v0, (a0), v0.t
  4863. + vsseg5e32.v v0, (a0), v0.t
  4864. + vlseg5e32ff.v v0, (a0), v0.t
  4865. + vlseg6e32.v v0, (a0), v0.t
  4866. + vsseg6e32.v v0, (a0), v0.t
  4867. + vlseg6e32ff.v v0, (a0), v0.t
  4868. + vlseg7e32.v v0, (a0), v0.t
  4869. + vsseg7e32.v v0, (a0), v0.t
  4870. + vlseg7e32ff.v v0, (a0), v0.t
  4871. + vlseg8e32.v v0, (a0), v0.t
  4872. + vsseg8e32.v v0, (a0), v0.t
  4873. + vlseg8e32ff.v v0, (a0), v0.t
  4874. +
  4875. + vlseg2e64.v v0, (a0), v0.t
  4876. + vsseg2e64.v v0, (a0), v0.t
  4877. + vlseg2e64ff.v v0, (a0), v0.t
  4878. + vlseg3e64.v v0, (a0), v0.t
  4879. + vsseg3e64.v v0, (a0), v0.t
  4880. + vlseg3e64ff.v v0, (a0), v0.t
  4881. + vlseg4e64.v v0, (a0), v0.t
  4882. + vsseg4e64.v v0, (a0), v0.t
  4883. + vlseg4e64ff.v v0, (a0), v0.t
  4884. + vlseg5e64.v v0, (a0), v0.t
  4885. + vsseg5e64.v v0, (a0), v0.t
  4886. + vlseg5e64ff.v v0, (a0), v0.t
  4887. + vlseg6e64.v v0, (a0), v0.t
  4888. + vsseg6e64.v v0, (a0), v0.t
  4889. + vlseg6e64ff.v v0, (a0), v0.t
  4890. + vlseg7e64.v v0, (a0), v0.t
  4891. + vsseg7e64.v v0, (a0), v0.t
  4892. + vlseg7e64ff.v v0, (a0), v0.t
  4893. + vlseg8e64.v v0, (a0), v0.t
  4894. + vsseg8e64.v v0, (a0), v0.t
  4895. + vlseg8e64ff.v v0, (a0), v0.t
  4896. +
  4897. + vlseg2e128.v v0, (a0), v0.t
  4898. + vsseg2e128.v v0, (a0), v0.t
  4899. + vlseg2e128ff.v v0, (a0), v0.t
  4900. + vlseg3e128.v v0, (a0), v0.t
  4901. + vsseg3e128.v v0, (a0), v0.t
  4902. + vlseg3e128ff.v v0, (a0), v0.t
  4903. + vlseg4e128.v v0, (a0), v0.t
  4904. + vsseg4e128.v v0, (a0), v0.t
  4905. + vlseg4e128ff.v v0, (a0), v0.t
  4906. + vlseg5e128.v v0, (a0), v0.t
  4907. + vsseg5e128.v v0, (a0), v0.t
  4908. + vlseg5e128ff.v v0, (a0), v0.t
  4909. + vlseg6e128.v v0, (a0), v0.t
  4910. + vsseg6e128.v v0, (a0), v0.t
  4911. + vlseg6e128ff.v v0, (a0), v0.t
  4912. + vlseg7e128.v v0, (a0), v0.t
  4913. + vsseg7e128.v v0, (a0), v0.t
  4914. + vlseg7e128ff.v v0, (a0), v0.t
  4915. + vlseg8e128.v v0, (a0), v0.t
  4916. + vsseg8e128.v v0, (a0), v0.t
  4917. + vlseg8e128ff.v v0, (a0), v0.t
  4918. +
  4919. + vlseg2e256.v v0, (a0), v0.t
  4920. + vsseg2e256.v v0, (a0), v0.t
  4921. + vlseg2e256ff.v v0, (a0), v0.t
  4922. + vlseg3e256.v v0, (a0), v0.t
  4923. + vsseg3e256.v v0, (a0), v0.t
  4924. + vlseg3e256ff.v v0, (a0), v0.t
  4925. + vlseg4e256.v v0, (a0), v0.t
  4926. + vsseg4e256.v v0, (a0), v0.t
  4927. + vlseg4e256ff.v v0, (a0), v0.t
  4928. + vlseg5e256.v v0, (a0), v0.t
  4929. + vsseg5e256.v v0, (a0), v0.t
  4930. + vlseg5e256ff.v v0, (a0), v0.t
  4931. + vlseg6e256.v v0, (a0), v0.t
  4932. + vsseg6e256.v v0, (a0), v0.t
  4933. + vlseg6e256ff.v v0, (a0), v0.t
  4934. + vlseg7e256.v v0, (a0), v0.t
  4935. + vsseg7e256.v v0, (a0), v0.t
  4936. + vlseg7e256ff.v v0, (a0), v0.t
  4937. + vlseg8e256.v v0, (a0), v0.t
  4938. + vsseg8e256.v v0, (a0), v0.t
  4939. + vlseg8e256ff.v v0, (a0), v0.t
  4940. +
  4941. + vlseg2e512.v v0, (a0), v0.t
  4942. + vsseg2e512.v v0, (a0), v0.t
  4943. + vlseg2e512ff.v v0, (a0), v0.t
  4944. + vlseg3e512.v v0, (a0), v0.t
  4945. + vsseg3e512.v v0, (a0), v0.t
  4946. + vlseg3e512ff.v v0, (a0), v0.t
  4947. + vlseg4e512.v v0, (a0), v0.t
  4948. + vsseg4e512.v v0, (a0), v0.t
  4949. + vlseg4e512ff.v v0, (a0), v0.t
  4950. + vlseg5e512.v v0, (a0), v0.t
  4951. + vsseg5e512.v v0, (a0), v0.t
  4952. + vlseg5e512ff.v v0, (a0), v0.t
  4953. + vlseg6e512.v v0, (a0), v0.t
  4954. + vsseg6e512.v v0, (a0), v0.t
  4955. + vlseg6e512ff.v v0, (a0), v0.t
  4956. + vlseg7e512.v v0, (a0), v0.t
  4957. + vsseg7e512.v v0, (a0), v0.t
  4958. + vlseg7e512ff.v v0, (a0), v0.t
  4959. + vlseg8e512.v v0, (a0), v0.t
  4960. + vsseg8e512.v v0, (a0), v0.t
  4961. + vlseg8e512ff.v v0, (a0), v0.t
  4962. +
  4963. + vlseg2e1024.v v0, (a0), v0.t
  4964. + vsseg2e1024.v v0, (a0), v0.t
  4965. + vlseg2e1024ff.v v0, (a0), v0.t
  4966. + vlseg3e1024.v v0, (a0), v0.t
  4967. + vsseg3e1024.v v0, (a0), v0.t
  4968. + vlseg3e1024ff.v v0, (a0), v0.t
  4969. + vlseg4e1024.v v0, (a0), v0.t
  4970. + vsseg4e1024.v v0, (a0), v0.t
  4971. + vlseg4e1024ff.v v0, (a0), v0.t
  4972. + vlseg5e1024.v v0, (a0), v0.t
  4973. + vsseg5e1024.v v0, (a0), v0.t
  4974. + vlseg5e1024ff.v v0, (a0), v0.t
  4975. + vlseg6e1024.v v0, (a0), v0.t
  4976. + vsseg6e1024.v v0, (a0), v0.t
  4977. + vlseg6e1024ff.v v0, (a0), v0.t
  4978. + vlseg7e1024.v v0, (a0), v0.t
  4979. + vsseg7e1024.v v0, (a0), v0.t
  4980. + vlseg7e1024ff.v v0, (a0), v0.t
  4981. + vlseg8e1024.v v0, (a0), v0.t
  4982. + vsseg8e1024.v v0, (a0), v0.t
  4983. + vlseg8e1024ff.v v0, (a0), v0.t
  4984. +
  4985. +# Vector Strided Segment Loads and Stores
  4986. +
  4987. + vlsseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
  4988. + vssseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
  4989. + vlsseg3e8.v v0, (a0), a1, v0.t
  4990. + vssseg3e8.v v0, (a0), a1, v0.t
  4991. + vlsseg4e8.v v0, (a0), a1, v0.t
  4992. + vssseg4e8.v v0, (a0), a1, v0.t
  4993. + vlsseg5e8.v v0, (a0), a1, v0.t
  4994. + vssseg5e8.v v0, (a0), a1, v0.t
  4995. + vlsseg6e8.v v0, (a0), a1, v0.t
  4996. + vssseg6e8.v v0, (a0), a1, v0.t
  4997. + vlsseg7e8.v v0, (a0), a1, v0.t
  4998. + vssseg7e8.v v0, (a0), a1, v0.t
  4999. + vlsseg8e8.v v0, (a0), a1, v0.t
  5000. + vssseg8e8.v v0, (a0), a1, v0.t
  5001. +
  5002. + vlsseg2e16.v v0, (a0), a1, v0.t
  5003. + vssseg2e16.v v0, (a0), a1, v0.t
  5004. + vlsseg3e16.v v0, (a0), a1, v0.t
  5005. + vssseg3e16.v v0, (a0), a1, v0.t
  5006. + vlsseg4e16.v v0, (a0), a1, v0.t
  5007. + vssseg4e16.v v0, (a0), a1, v0.t
  5008. + vlsseg5e16.v v0, (a0), a1, v0.t
  5009. + vssseg5e16.v v0, (a0), a1, v0.t
  5010. + vlsseg6e16.v v0, (a0), a1, v0.t
  5011. + vssseg6e16.v v0, (a0), a1, v0.t
  5012. + vlsseg7e16.v v0, (a0), a1, v0.t
  5013. + vssseg7e16.v v0, (a0), a1, v0.t
  5014. + vlsseg8e16.v v0, (a0), a1, v0.t
  5015. + vssseg8e16.v v0, (a0), a1, v0.t
  5016. +
  5017. + vlsseg2e32.v v0, (a0), a1, v0.t
  5018. + vssseg2e32.v v0, (a0), a1, v0.t
  5019. + vlsseg3e32.v v0, (a0), a1, v0.t
  5020. + vssseg3e32.v v0, (a0), a1, v0.t
  5021. + vlsseg4e32.v v0, (a0), a1, v0.t
  5022. + vssseg4e32.v v0, (a0), a1, v0.t
  5023. + vlsseg5e32.v v0, (a0), a1, v0.t
  5024. + vssseg5e32.v v0, (a0), a1, v0.t
  5025. + vlsseg6e32.v v0, (a0), a1, v0.t
  5026. + vssseg6e32.v v0, (a0), a1, v0.t
  5027. + vlsseg7e32.v v0, (a0), a1, v0.t
  5028. + vssseg7e32.v v0, (a0), a1, v0.t
  5029. + vlsseg8e32.v v0, (a0), a1, v0.t
  5030. + vssseg8e32.v v0, (a0), a1, v0.t
  5031. +
  5032. + vlsseg2e64.v v0, (a0), a1, v0.t
  5033. + vssseg2e64.v v0, (a0), a1, v0.t
  5034. + vlsseg3e64.v v0, (a0), a1, v0.t
  5035. + vssseg3e64.v v0, (a0), a1, v0.t
  5036. + vlsseg4e64.v v0, (a0), a1, v0.t
  5037. + vssseg4e64.v v0, (a0), a1, v0.t
  5038. + vlsseg5e64.v v0, (a0), a1, v0.t
  5039. + vssseg5e64.v v0, (a0), a1, v0.t
  5040. + vlsseg6e64.v v0, (a0), a1, v0.t
  5041. + vssseg6e64.v v0, (a0), a1, v0.t
  5042. + vlsseg7e64.v v0, (a0), a1, v0.t
  5043. + vssseg7e64.v v0, (a0), a1, v0.t
  5044. + vlsseg8e64.v v0, (a0), a1, v0.t
  5045. + vssseg8e64.v v0, (a0), a1, v0.t
  5046. +
  5047. + vlsseg2e128.v v0, (a0), a1, v0.t
  5048. + vssseg2e128.v v0, (a0), a1, v0.t
  5049. + vlsseg3e128.v v0, (a0), a1, v0.t
  5050. + vssseg3e128.v v0, (a0), a1, v0.t
  5051. + vlsseg4e128.v v0, (a0), a1, v0.t
  5052. + vssseg4e128.v v0, (a0), a1, v0.t
  5053. + vlsseg5e128.v v0, (a0), a1, v0.t
  5054. + vssseg5e128.v v0, (a0), a1, v0.t
  5055. + vlsseg6e128.v v0, (a0), a1, v0.t
  5056. + vssseg6e128.v v0, (a0), a1, v0.t
  5057. + vlsseg7e128.v v0, (a0), a1, v0.t
  5058. + vssseg7e128.v v0, (a0), a1, v0.t
  5059. + vlsseg8e128.v v0, (a0), a1, v0.t
  5060. + vssseg8e128.v v0, (a0), a1, v0.t
  5061. +
  5062. + vlsseg2e256.v v0, (a0), a1, v0.t
  5063. + vssseg2e256.v v0, (a0), a1, v0.t
  5064. + vlsseg3e256.v v0, (a0), a1, v0.t
  5065. + vssseg3e256.v v0, (a0), a1, v0.t
  5066. + vlsseg4e256.v v0, (a0), a1, v0.t
  5067. + vssseg4e256.v v0, (a0), a1, v0.t
  5068. + vlsseg5e256.v v0, (a0), a1, v0.t
  5069. + vssseg5e256.v v0, (a0), a1, v0.t
  5070. + vlsseg6e256.v v0, (a0), a1, v0.t
  5071. + vssseg6e256.v v0, (a0), a1, v0.t
  5072. + vlsseg7e256.v v0, (a0), a1, v0.t
  5073. + vssseg7e256.v v0, (a0), a1, v0.t
  5074. + vlsseg8e256.v v0, (a0), a1, v0.t
  5075. + vssseg8e256.v v0, (a0), a1, v0.t
  5076. +
  5077. + vlsseg2e512.v v0, (a0), a1, v0.t
  5078. + vssseg2e512.v v0, (a0), a1, v0.t
  5079. + vlsseg3e512.v v0, (a0), a1, v0.t
  5080. + vssseg3e512.v v0, (a0), a1, v0.t
  5081. + vlsseg4e512.v v0, (a0), a1, v0.t
  5082. + vssseg4e512.v v0, (a0), a1, v0.t
  5083. + vlsseg5e512.v v0, (a0), a1, v0.t
  5084. + vssseg5e512.v v0, (a0), a1, v0.t
  5085. + vlsseg6e512.v v0, (a0), a1, v0.t
  5086. + vssseg6e512.v v0, (a0), a1, v0.t
  5087. + vlsseg7e512.v v0, (a0), a1, v0.t
  5088. + vssseg7e512.v v0, (a0), a1, v0.t
  5089. + vlsseg8e512.v v0, (a0), a1, v0.t
  5090. + vssseg8e512.v v0, (a0), a1, v0.t
  5091. +
  5092. + vlsseg2e1024.v v0, (a0), a1, v0.t
  5093. + vssseg2e1024.v v0, (a0), a1, v0.t
  5094. + vlsseg3e1024.v v0, (a0), a1, v0.t
  5095. + vssseg3e1024.v v0, (a0), a1, v0.t
  5096. + vlsseg4e1024.v v0, (a0), a1, v0.t
  5097. + vssseg4e1024.v v0, (a0), a1, v0.t
  5098. + vlsseg5e1024.v v0, (a0), a1, v0.t
  5099. + vssseg5e1024.v v0, (a0), a1, v0.t
  5100. + vlsseg6e1024.v v0, (a0), a1, v0.t
  5101. + vssseg6e1024.v v0, (a0), a1, v0.t
  5102. + vlsseg7e1024.v v0, (a0), a1, v0.t
  5103. + vssseg7e1024.v v0, (a0), a1, v0.t
  5104. + vlsseg8e1024.v v0, (a0), a1, v0.t
  5105. + vssseg8e1024.v v0, (a0), a1, v0.t
  5106. +
  5107. +# Vector Indexed Segment Loads and Stores
  5108. +
  5109. + vlxseg2ei8.v v4, (a0), v4 # vd overlap vs2
  5110. + vlxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
  5111. + vsxseg2ei8.v v4, (a0), v4 # vd overlap vs2
  5112. + vsxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
  5113. + vlxseg3ei8.v v4, (a0), v4
  5114. + vlxseg3ei8.v v0, (a0), v4, v0.t
  5115. + vsxseg3ei8.v v4, (a0), v4
  5116. + vsxseg3ei8.v v0, (a0), v4, v0.t
  5117. + vlxseg4ei8.v v4, (a0), v4
  5118. + vlxseg4ei8.v v0, (a0), v4, v0.t
  5119. + vsxseg4ei8.v v4, (a0), v4
  5120. + vsxseg4ei8.v v0, (a0), v4, v0.t
  5121. + vlxseg5ei8.v v4, (a0), v4
  5122. + vlxseg5ei8.v v0, (a0), v4, v0.t
  5123. + vsxseg5ei8.v v4, (a0), v4
  5124. + vsxseg5ei8.v v0, (a0), v4, v0.t
  5125. + vlxseg6ei8.v v4, (a0), v4
  5126. + vlxseg6ei8.v v0, (a0), v4, v0.t
  5127. + vsxseg6ei8.v v4, (a0), v4
  5128. + vsxseg6ei8.v v0, (a0), v4, v0.t
  5129. + vlxseg7ei8.v v4, (a0), v4
  5130. + vlxseg7ei8.v v0, (a0), v4, v0.t
  5131. + vsxseg7ei8.v v4, (a0), v4
  5132. + vsxseg7ei8.v v0, (a0), v4, v0.t
  5133. + vlxseg8ei8.v v4, (a0), v4
  5134. + vlxseg8ei8.v v0, (a0), v4, v0.t
  5135. + vsxseg8ei8.v v4, (a0), v4
  5136. + vsxseg8ei8.v v0, (a0), v4, v0.t
  5137. +
  5138. + vlxseg2ei16.v v4, (a0), v4
  5139. + vlxseg2ei16.v v0, (a0), v4, v0.t
  5140. + vsxseg2ei16.v v4, (a0), v4
  5141. + vsxseg2ei16.v v0, (a0), v4, v0.t
  5142. + vlxseg3ei16.v v4, (a0), v4
  5143. + vlxseg3ei16.v v0, (a0), v4, v0.t
  5144. + vsxseg3ei16.v v4, (a0), v4
  5145. + vsxseg3ei16.v v0, (a0), v4, v0.t
  5146. + vlxseg4ei16.v v4, (a0), v4
  5147. + vlxseg4ei16.v v0, (a0), v4, v0.t
  5148. + vsxseg4ei16.v v4, (a0), v4
  5149. + vsxseg4ei16.v v0, (a0), v4, v0.t
  5150. + vlxseg5ei16.v v4, (a0), v4
  5151. + vlxseg5ei16.v v0, (a0), v4, v0.t
  5152. + vsxseg5ei16.v v4, (a0), v4
  5153. + vsxseg5ei16.v v0, (a0), v4, v0.t
  5154. + vlxseg6ei16.v v4, (a0), v4
  5155. + vlxseg6ei16.v v0, (a0), v4, v0.t
  5156. + vsxseg6ei16.v v4, (a0), v4
  5157. + vsxseg6ei16.v v0, (a0), v4, v0.t
  5158. + vlxseg7ei16.v v4, (a0), v4
  5159. + vlxseg7ei16.v v0, (a0), v4, v0.t
  5160. + vsxseg7ei16.v v4, (a0), v4
  5161. + vsxseg7ei16.v v0, (a0), v4, v0.t
  5162. + vlxseg8ei16.v v4, (a0), v4
  5163. + vlxseg8ei16.v v0, (a0), v4, v0.t
  5164. + vsxseg8ei16.v v4, (a0), v4
  5165. + vsxseg8ei16.v v0, (a0), v4, v0.t
  5166. +
  5167. + vlxseg2ei32.v v4, (a0), v4
  5168. + vlxseg2ei32.v v0, (a0), v4, v0.t
  5169. + vsxseg2ei32.v v4, (a0), v4
  5170. + vsxseg2ei32.v v0, (a0), v4, v0.t
  5171. + vlxseg3ei32.v v4, (a0), v4
  5172. + vlxseg3ei32.v v0, (a0), v4, v0.t
  5173. + vsxseg3ei32.v v4, (a0), v4
  5174. + vsxseg3ei32.v v0, (a0), v4, v0.t
  5175. + vlxseg4ei32.v v4, (a0), v4
  5176. + vlxseg4ei32.v v0, (a0), v4, v0.t
  5177. + vsxseg4ei32.v v4, (a0), v4
  5178. + vsxseg4ei32.v v0, (a0), v4, v0.t
  5179. + vlxseg5ei32.v v4, (a0), v4
  5180. + vlxseg5ei32.v v0, (a0), v4, v0.t
  5181. + vsxseg5ei32.v v4, (a0), v4
  5182. + vsxseg5ei32.v v0, (a0), v4, v0.t
  5183. + vlxseg6ei32.v v4, (a0), v4
  5184. + vlxseg6ei32.v v0, (a0), v4, v0.t
  5185. + vsxseg6ei32.v v4, (a0), v4
  5186. + vsxseg6ei32.v v0, (a0), v4, v0.t
  5187. + vlxseg7ei32.v v4, (a0), v4
  5188. + vlxseg7ei32.v v0, (a0), v4, v0.t
  5189. + vsxseg7ei32.v v4, (a0), v4
  5190. + vsxseg7ei32.v v0, (a0), v4, v0.t
  5191. + vlxseg8ei32.v v4, (a0), v4
  5192. + vlxseg8ei32.v v0, (a0), v4, v0.t
  5193. + vsxseg8ei32.v v4, (a0), v4
  5194. + vsxseg8ei32.v v0, (a0), v4, v0.t
  5195. +
  5196. + vlxseg2ei64.v v4, (a0), v4
  5197. + vlxseg2ei64.v v0, (a0), v4, v0.t
  5198. + vsxseg2ei64.v v4, (a0), v4
  5199. + vsxseg2ei64.v v0, (a0), v4, v0.t
  5200. + vlxseg3ei64.v v4, (a0), v4
  5201. + vlxseg3ei64.v v0, (a0), v4, v0.t
  5202. + vsxseg3ei64.v v4, (a0), v4
  5203. + vsxseg3ei64.v v0, (a0), v4, v0.t
  5204. + vlxseg4ei64.v v4, (a0), v4
  5205. + vlxseg4ei64.v v0, (a0), v4, v0.t
  5206. + vsxseg4ei64.v v4, (a0), v4
  5207. + vsxseg4ei64.v v0, (a0), v4, v0.t
  5208. + vlxseg5ei64.v v4, (a0), v4
  5209. + vlxseg5ei64.v v0, (a0), v4, v0.t
  5210. + vsxseg5ei64.v v4, (a0), v4
  5211. + vsxseg5ei64.v v0, (a0), v4, v0.t
  5212. + vlxseg6ei64.v v4, (a0), v4
  5213. + vlxseg6ei64.v v0, (a0), v4, v0.t
  5214. + vsxseg6ei64.v v4, (a0), v4
  5215. + vsxseg6ei64.v v0, (a0), v4, v0.t
  5216. + vlxseg7ei64.v v4, (a0), v4
  5217. + vlxseg7ei64.v v0, (a0), v4, v0.t
  5218. + vsxseg7ei64.v v4, (a0), v4
  5219. + vsxseg7ei64.v v0, (a0), v4, v0.t
  5220. + vlxseg8ei64.v v4, (a0), v4
  5221. + vlxseg8ei64.v v0, (a0), v4, v0.t
  5222. + vsxseg8ei64.v v4, (a0), v4
  5223. + vsxseg8ei64.v v0, (a0), v4, v0.t
  5224. +
  5225. + vlxseg2ei128.v v4, (a0), v4
  5226. + vlxseg2ei128.v v0, (a0), v4, v0.t
  5227. + vsxseg2ei128.v v4, (a0), v4
  5228. + vsxseg2ei128.v v0, (a0), v4, v0.t
  5229. + vlxseg3ei128.v v4, (a0), v4
  5230. + vlxseg3ei128.v v0, (a0), v4, v0.t
  5231. + vsxseg3ei128.v v4, (a0), v4
  5232. + vsxseg3ei128.v v0, (a0), v4, v0.t
  5233. + vlxseg4ei128.v v4, (a0), v4
  5234. + vlxseg4ei128.v v0, (a0), v4, v0.t
  5235. + vsxseg4ei128.v v4, (a0), v4
  5236. + vsxseg4ei128.v v0, (a0), v4, v0.t
  5237. + vlxseg5ei128.v v4, (a0), v4
  5238. + vlxseg5ei128.v v0, (a0), v4, v0.t
  5239. + vsxseg5ei128.v v4, (a0), v4
  5240. + vsxseg5ei128.v v0, (a0), v4, v0.t
  5241. + vlxseg6ei128.v v4, (a0), v4
  5242. + vlxseg6ei128.v v0, (a0), v4, v0.t
  5243. + vsxseg6ei128.v v4, (a0), v4
  5244. + vsxseg6ei128.v v0, (a0), v4, v0.t
  5245. + vlxseg7ei128.v v4, (a0), v4
  5246. + vlxseg7ei128.v v0, (a0), v4, v0.t
  5247. + vsxseg7ei128.v v4, (a0), v4
  5248. + vsxseg7ei128.v v0, (a0), v4, v0.t
  5249. + vlxseg8ei128.v v4, (a0), v4
  5250. + vlxseg8ei128.v v0, (a0), v4, v0.t
  5251. + vsxseg8ei128.v v4, (a0), v4
  5252. + vsxseg8ei128.v v0, (a0), v4, v0.t
  5253. +
  5254. + vlxseg2ei256.v v4, (a0), v4
  5255. + vlxseg2ei256.v v0, (a0), v4, v0.t
  5256. + vsxseg2ei256.v v4, (a0), v4
  5257. + vsxseg2ei256.v v0, (a0), v4, v0.t
  5258. + vlxseg3ei256.v v4, (a0), v4
  5259. + vlxseg3ei256.v v0, (a0), v4, v0.t
  5260. + vsxseg3ei256.v v4, (a0), v4
  5261. + vsxseg3ei256.v v0, (a0), v4, v0.t
  5262. + vlxseg4ei256.v v4, (a0), v4
  5263. + vlxseg4ei256.v v0, (a0), v4, v0.t
  5264. + vsxseg4ei256.v v4, (a0), v4
  5265. + vsxseg4ei256.v v0, (a0), v4, v0.t
  5266. + vlxseg5ei256.v v4, (a0), v4
  5267. + vlxseg5ei256.v v0, (a0), v4, v0.t
  5268. + vsxseg5ei256.v v4, (a0), v4
  5269. + vsxseg5ei256.v v0, (a0), v4, v0.t
  5270. + vlxseg6ei256.v v4, (a0), v4
  5271. + vlxseg6ei256.v v0, (a0), v4, v0.t
  5272. + vsxseg6ei256.v v4, (a0), v4
  5273. + vsxseg6ei256.v v0, (a0), v4, v0.t
  5274. + vlxseg7ei256.v v4, (a0), v4
  5275. + vlxseg7ei256.v v0, (a0), v4, v0.t
  5276. + vsxseg7ei256.v v4, (a0), v4
  5277. + vsxseg7ei256.v v0, (a0), v4, v0.t
  5278. + vlxseg8ei256.v v4, (a0), v4
  5279. + vlxseg8ei256.v v0, (a0), v4, v0.t
  5280. + vsxseg8ei256.v v4, (a0), v4
  5281. + vsxseg8ei256.v v0, (a0), v4, v0.t
  5282. +
  5283. + vlxseg2ei512.v v4, (a0), v4
  5284. + vlxseg2ei512.v v0, (a0), v4, v0.t
  5285. + vsxseg2ei512.v v4, (a0), v4
  5286. + vsxseg2ei512.v v0, (a0), v4, v0.t
  5287. + vlxseg3ei512.v v4, (a0), v4
  5288. + vlxseg3ei512.v v0, (a0), v4, v0.t
  5289. + vsxseg3ei512.v v4, (a0), v4
  5290. + vsxseg3ei512.v v0, (a0), v4, v0.t
  5291. + vlxseg4ei512.v v4, (a0), v4
  5292. + vlxseg4ei512.v v0, (a0), v4, v0.t
  5293. + vsxseg4ei512.v v4, (a0), v4
  5294. + vsxseg4ei512.v v0, (a0), v4, v0.t
  5295. + vlxseg5ei512.v v4, (a0), v4
  5296. + vlxseg5ei512.v v0, (a0), v4, v0.t
  5297. + vsxseg5ei512.v v4, (a0), v4
  5298. + vsxseg5ei512.v v0, (a0), v4, v0.t
  5299. + vlxseg6ei512.v v4, (a0), v4
  5300. + vlxseg6ei512.v v0, (a0), v4, v0.t
  5301. + vsxseg6ei512.v v4, (a0), v4
  5302. + vsxseg6ei512.v v0, (a0), v4, v0.t
  5303. + vlxseg7ei512.v v4, (a0), v4
  5304. + vlxseg7ei512.v v0, (a0), v4, v0.t
  5305. + vsxseg7ei512.v v4, (a0), v4
  5306. + vsxseg7ei512.v v0, (a0), v4, v0.t
  5307. + vlxseg8ei512.v v4, (a0), v4
  5308. + vlxseg8ei512.v v0, (a0), v4, v0.t
  5309. + vsxseg8ei512.v v4, (a0), v4
  5310. + vsxseg8ei512.v v0, (a0), v4, v0.t
  5311. +
  5312. + vlxseg2ei1024.v v4, (a0), v4
  5313. + vlxseg2ei1024.v v0, (a0), v4, v0.t
  5314. + vsxseg2ei1024.v v4, (a0), v4
  5315. + vsxseg2ei1024.v v0, (a0), v4, v0.t
  5316. + vlxseg3ei1024.v v4, (a0), v4
  5317. + vlxseg3ei1024.v v0, (a0), v4, v0.t
  5318. + vsxseg3ei1024.v v4, (a0), v4
  5319. + vsxseg3ei1024.v v0, (a0), v4, v0.t
  5320. + vlxseg4ei1024.v v4, (a0), v4
  5321. + vlxseg4ei1024.v v0, (a0), v4, v0.t
  5322. + vsxseg4ei1024.v v4, (a0), v4
  5323. + vsxseg4ei1024.v v0, (a0), v4, v0.t
  5324. + vlxseg5ei1024.v v4, (a0), v4
  5325. + vlxseg5ei1024.v v0, (a0), v4, v0.t
  5326. + vsxseg5ei1024.v v4, (a0), v4
  5327. + vsxseg5ei1024.v v0, (a0), v4, v0.t
  5328. + vlxseg6ei1024.v v4, (a0), v4
  5329. + vlxseg6ei1024.v v0, (a0), v4, v0.t
  5330. + vsxseg6ei1024.v v4, (a0), v4
  5331. + vsxseg6ei1024.v v0, (a0), v4, v0.t
  5332. + vlxseg7ei1024.v v4, (a0), v4
  5333. + vlxseg7ei1024.v v0, (a0), v4, v0.t
  5334. + vsxseg7ei1024.v v4, (a0), v4
  5335. + vsxseg7ei1024.v v0, (a0), v4, v0.t
  5336. + vlxseg8ei1024.v v4, (a0), v4
  5337. + vlxseg8ei1024.v v0, (a0), v4, v0.t
  5338. + vsxseg8ei1024.v v4, (a0), v4
  5339. + vsxseg8ei1024.v v0, (a0), v4, v0.t
  5340. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.d b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
  5341. new file mode 100644
  5342. index 0000000000..35f9e2c32c
  5343. --- /dev/null
  5344. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
  5345. @@ -0,0 +1,3 @@
  5346. +#as: -march=rv32iv -mcheck-constraints
  5347. +#source: vector-insns-fail-mask.s
  5348. +#error_output: vector-insns-fail-mask.l
  5349. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
  5350. new file mode 100644
  5351. index 0000000000..5c4e881489
  5352. --- /dev/null
  5353. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
  5354. @@ -0,0 +1,7 @@
  5355. +.*: Assembler messages:
  5356. +.*Error: illegal operands `vmsbf.m v0,v4,v0.t'
  5357. +.*Error: illegal operands `vmsif.m v0,v4,v0.t'
  5358. +.*Error: illegal operands `vmsof.m v0,v4,v0.t'
  5359. +.*Error: illegal operands `viota.m v4,v4'
  5360. +.*Error: illegal operands `viota.m v0,v4,v0.t'
  5361. +.*Error: illegal operands `vid.v v0,v0.t'
  5362. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
  5363. new file mode 100644
  5364. index 0000000000..580b101c77
  5365. --- /dev/null
  5366. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
  5367. @@ -0,0 +1,20 @@
  5368. +# Vector Set-before-first Mask Bit
  5369. +
  5370. + vmsbf.m v0, v4, v0.t # vd overlap vm
  5371. +
  5372. +# Vector Set-including-first Mask Bit
  5373. +
  5374. + vmsif.m v0, v4, v0.t # vd overlap vm
  5375. +
  5376. +# Vector Set-only-first Mask Bit
  5377. +
  5378. + vmsof.m v0, v4, v0.t # vd overlap vm
  5379. +
  5380. +# Vector Iota Instruction
  5381. +
  5382. + viota.m v4, v4 # vd overlap vs2
  5383. + viota.m v0, v4, v0.t # vd overlap vm
  5384. +
  5385. +# Vector Element Index Instruction
  5386. +
  5387. + vid.v v0, v0.t # vd overlap vm
  5388. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
  5389. new file mode 100644
  5390. index 0000000000..9822e2919a
  5391. --- /dev/null
  5392. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
  5393. @@ -0,0 +1,3 @@
  5394. +#as: -march=rv32ifv -mcheck-constraints
  5395. +#source: vector-insns-fail-permutation.s
  5396. +#error_output: vector-insns-fail-permutation.l
  5397. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
  5398. new file mode 100644
  5399. index 0000000000..c208f5710f
  5400. --- /dev/null
  5401. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
  5402. @@ -0,0 +1,31 @@
  5403. +.*: Assembler messages:
  5404. +.*Error: illegal operands `vslideup.vx v4,v4,a1'
  5405. +.*Error: illegal operands `vslideup.vx v0,v4,a1,v0.t'
  5406. +.*Error: illegal operands `vslideup.vi v4,v4,31'
  5407. +.*Error: illegal operands `vslideup.vi v0,v4,31,v0.t'
  5408. +.*Error: illegal operands `vslidedown.vx v0,v4,a1,v0.t'
  5409. +.*Error: illegal operands `vslidedown.vi v0,v4,31,v0.t'
  5410. +.*Error: illegal operands `vslide1up.vx v4,v4,a1'
  5411. +.*Error: illegal operands `vslide1up.vx v0,v4,a1,v0.t'
  5412. +.*Error: illegal operands `vfslide1up.vf v4,v4,fa1'
  5413. +.*Error: illegal operands `vfslide1up.vf v0,v4,fa1,v0.t'
  5414. +.*Error: illegal operands `vslide1down.vx v0,v4,a1,v0.t'
  5415. +.*Error: illegal operands `vfslide1down.vf v0,v4,fa1,v0.t'
  5416. +.*Error: illegal operands `vrgather.vv v4,v4,v8'
  5417. +.*Error: illegal operands `vrgather.vv v8,v4,v8'
  5418. +.*Error: illegal operands `vrgather.vv v0,v4,v8,v0.t'
  5419. +.*Error: illegal operands `vrgather.vx v4,v4,a1'
  5420. +.*Error: illegal operands `vrgather.vx v0,v4,a1,v0.t'
  5421. +.*Error: illegal operands `vrgather.vi v4,v4,31'
  5422. +.*Error: illegal operands `vrgather.vi v0,v4,31,v0.t'
  5423. +.*Error: illegal operands `vrgatherei16.vv v4,v4,v8'
  5424. +.*Error: illegal operands `vrgatherei16.vv v8,v4,v8'
  5425. +.*Error: illegal operands `vrgatherei16.vv v0,v4,v8,v0.t'
  5426. +.*Error: illegal operands `vcompress.vm v4,v4,v8'
  5427. +.*Error: illegal operands `vcompress.vm v8,v4,v8'
  5428. +.*Error: illegal operands `vmv2r.v v30,v31'
  5429. +.*Error: illegal operands `vmv2r.v v31,v30'
  5430. +.*Error: illegal operands `vmv4r.v v28,v30'
  5431. +.*Error: illegal operands `vmv4r.v v30,v28'
  5432. +.*Error: illegal operands `vmv8r.v v24,v26'
  5433. +.*Error: illegal operands `vmv8r.v v26,v24'
  5434. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
  5435. new file mode 100644
  5436. index 0000000000..85116457ff
  5437. --- /dev/null
  5438. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
  5439. @@ -0,0 +1,56 @@
  5440. +# Vector Slideup Instructions
  5441. +
  5442. + vslideup.vx v4, v4, a1 # vd overlap vs2
  5443. + vslideup.vx v0, v4, a1, v0.t # vd overlap vm
  5444. + vslideup.vi v4, v4, 31 # vd overlap vs2
  5445. + vslideup.vi v0, v4, 31, v0.t # vd overlap vm
  5446. +
  5447. + vslidedown.vx v4, v4, a1 # OK
  5448. + vslidedown.vx v0, v4, a1, v0.t # vd overlap vm
  5449. + vslidedown.vi v4, v4, 31 # OK
  5450. + vslidedown.vi v0, v4, 31, v0.t # vd overlap vm
  5451. +
  5452. + vslide1up.vx v4, v4, a1 # vd overlap vs2
  5453. + vslide1up.vx v0, v4, a1, v0.t # vd overlap vm
  5454. + vfslide1up.vf v4, v4, fa1 # vd overlap vs2
  5455. + vfslide1up.vf v0, v4, fa1, v0.t # vd overlap vm
  5456. +
  5457. + vslide1down.vx v4, v4, a1 # OK
  5458. + vslide1down.vx v0, v4, a1, v0.t # vd overlap vm
  5459. + vfslide1down.vf v4, v4, fa1 # OK
  5460. + vfslide1down.vf v0, v4, fa1, v0.t # vd overlap vm
  5461. +
  5462. +# Vector Register Gather Instructions
  5463. +
  5464. + vrgather.vv v4, v4, v8 # vd overlap vs2
  5465. + vrgather.vv v8, v4, v8 # vd overlap vs1
  5466. + vrgather.vv v0, v4, v8, v0.t # vd overlap vm
  5467. + vrgather.vx v4, v4, a1 # vd overlap vs2
  5468. + vrgather.vx v0, v4, a1, v0.t # vd overlap vm
  5469. + vrgather.vi v4, v4, 31 # vd overlap vs2
  5470. + vrgather.vi v0, v4, 31, v0.t # vd overlap vm
  5471. +
  5472. + vrgatherei16.vv v4, v4, v8 # vd overlap vs2
  5473. + vrgatherei16.vv v8, v4, v8 # vd overlap vs1
  5474. + vrgatherei16.vv v0, v4, v8, v0.t # vd overlap vm
  5475. +
  5476. +# Vector Compress Instruction
  5477. +
  5478. + vcompress.vm v4, v4, v8 # vd overlap vs2
  5479. + vcompress.vm v8, v4, v8 # vd overlap vs1
  5480. +
  5481. +# Whole Vector Register Move
  5482. +
  5483. + vmv1r.v v31, v31 # OK, HINT
  5484. +
  5485. + vmv2r.v v30, v30 # OK, HINT
  5486. + vmv2r.v v30, v31 # vs2 must be aligned to 2
  5487. + vmv2r.v v31, v30 # vd must be aligned to 2
  5488. +
  5489. + vmv4r.v v28, v28 # OK, HINT
  5490. + vmv4r.v v28, v30 # vs2 must be aligned to 4
  5491. + vmv4r.v v30, v28 # vd must be aligned to 4
  5492. +
  5493. + vmv8r.v v24, v24 # OK, HINT
  5494. + vmv8r.v v24, v26 # vs2 must be aligned to 8
  5495. + vmv8r.v v26, v24 # vd must be aligned to 8
  5496. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
  5497. new file mode 100644
  5498. index 0000000000..5749449bd0
  5499. --- /dev/null
  5500. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
  5501. @@ -0,0 +1,3 @@
  5502. +#as: -march=rv32iav -mcheck-constraints
  5503. +#source: vector-insns-fail-zvamo.s
  5504. +#error_output: vector-insns-fail-zvamo.l
  5505. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
  5506. new file mode 100644
  5507. index 0000000000..6207fb2fee
  5508. --- /dev/null
  5509. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
  5510. @@ -0,0 +1,109 @@
  5511. +.*: Assembler messages:
  5512. +.*Error: illegal operands `vamoaddei8.v v4,\(a1\),v4,v0'
  5513. +.*Error: illegal operands `vamoaddei8.v v0,\(a1\),v4,v0,v0.t'
  5514. +.*Error: illegal operands `vamoaddei8.v x0,\(a1\),v4,v0,v0.t'
  5515. +.*Error: illegal operands `vamoswapei8.v v4,\(a1\),v4,v0'
  5516. +.*Error: illegal operands `vamoswapei8.v v0,\(a1\),v4,v0,v0.t'
  5517. +.*Error: illegal operands `vamoswapei8.v x0,\(a1\),v4,v0,v0.t'
  5518. +.*Error: illegal operands `vamoxorei8.v v4,\(a1\),v4,v0'
  5519. +.*Error: illegal operands `vamoxorei8.v v0,\(a1\),v4,v0,v0.t'
  5520. +.*Error: illegal operands `vamoxorei8.v x0,\(a1\),v4,v0,v0.t'
  5521. +.*Error: illegal operands `vamoandei8.v v4,\(a1\),v4,v0'
  5522. +.*Error: illegal operands `vamoandei8.v v0,\(a1\),v4,v0,v0.t'
  5523. +.*Error: illegal operands `vamoandei8.v x0,\(a1\),v4,v0,v0.t'
  5524. +.*Error: illegal operands `vamoorei8.v v4,\(a1\),v4,v0'
  5525. +.*Error: illegal operands `vamoorei8.v v0,\(a1\),v4,v0,v0.t'
  5526. +.*Error: illegal operands `vamoorei8.v x0,\(a1\),v4,v0,v0.t'
  5527. +.*Error: illegal operands `vamominei8.v v4,\(a1\),v4,v0'
  5528. +.*Error: illegal operands `vamominei8.v v0,\(a1\),v4,v0,v0.t'
  5529. +.*Error: illegal operands `vamominei8.v x0,\(a1\),v4,v0,v0.t'
  5530. +.*Error: illegal operands `vamomaxei8.v v4,\(a1\),v4,v0'
  5531. +.*Error: illegal operands `vamomaxei8.v v0,\(a1\),v4,v0,v0.t'
  5532. +.*Error: illegal operands `vamomaxei8.v x0,\(a1\),v4,v0,v0.t'
  5533. +.*Error: illegal operands `vamominuei8.v v4,\(a1\),v4,v0'
  5534. +.*Error: illegal operands `vamominuei8.v v0,\(a1\),v4,v0,v0.t'
  5535. +.*Error: illegal operands `vamominuei8.v x0,\(a1\),v4,v0,v0.t'
  5536. +.*Error: illegal operands `vamomaxuei8.v v4,\(a1\),v4,v0'
  5537. +.*Error: illegal operands `vamomaxuei8.v v0,\(a1\),v4,v0,v0.t'
  5538. +.*Error: illegal operands `vamomaxuei8.v x0,\(a1\),v4,v0,v0.t'
  5539. +.*Error: illegal operands `vamoaddei16.v v4,\(a1\),v4,v0'
  5540. +.*Error: illegal operands `vamoaddei16.v v0,\(a1\),v4,v0,v0.t'
  5541. +.*Error: illegal operands `vamoaddei16.v x0,\(a1\),v4,v0,v0.t'
  5542. +.*Error: illegal operands `vamoswapei16.v v0,\(a1\),v4,v0,v0.t'
  5543. +.*Error: illegal operands `vamoswapei16.v v4,\(a1\),v4,v0'
  5544. +.*Error: illegal operands `vamoswapei16.v x0,\(a1\),v4,v0,v0.t'
  5545. +.*Error: illegal operands `vamoxorei16.v v0,\(a1\),v4,v0,v0.t'
  5546. +.*Error: illegal operands `vamoxorei16.v v4,\(a1\),v4,v0'
  5547. +.*Error: illegal operands `vamoxorei16.v x0,\(a1\),v4,v0,v0.t'
  5548. +.*Error: illegal operands `vamoandei16.v v0,\(a1\),v4,v0,v0.t'
  5549. +.*Error: illegal operands `vamoandei16.v v4,\(a1\),v4,v0'
  5550. +.*Error: illegal operands `vamoandei16.v x0,\(a1\),v4,v0,v0.t'
  5551. +.*Error: illegal operands `vamoorei16.v v0,\(a1\),v4,v0,v0.t'
  5552. +.*Error: illegal operands `vamoorei16.v v4,\(a1\),v4,v0'
  5553. +.*Error: illegal operands `vamoorei16.v x0,\(a1\),v4,v0,v0.t'
  5554. +.*Error: illegal operands `vamominei16.v v0,\(a1\),v4,v0,v0.t'
  5555. +.*Error: illegal operands `vamominei16.v v4,\(a1\),v4,v0'
  5556. +.*Error: illegal operands `vamominei16.v x0,\(a1\),v4,v0,v0.t'
  5557. +.*Error: illegal operands `vamomaxei16.v v0,\(a1\),v4,v0,v0.t'
  5558. +.*Error: illegal operands `vamomaxei16.v v4,\(a1\),v4,v0'
  5559. +.*Error: illegal operands `vamomaxei16.v x0,\(a1\),v4,v0,v0.t'
  5560. +.*Error: illegal operands `vamominuei16.v v0,\(a1\),v4,v0,v0.t'
  5561. +.*Error: illegal operands `vamominuei16.v v4,\(a1\),v4,v0'
  5562. +.*Error: illegal operands `vamominuei16.v x0,\(a1\),v4,v0,v0.t'
  5563. +.*Error: illegal operands `vamomaxuei16.v v0,\(a1\),v4,v0,v0.t'
  5564. +.*Error: illegal operands `vamomaxuei16.v v4,\(a1\),v4,v0'
  5565. +.*Error: illegal operands `vamomaxuei16.v x0,\(a1\),v4,v0,v0.t'
  5566. +.*Error: illegal operands `vamoaddei32.v v0,\(a1\),v4,v0,v0.t'
  5567. +.*Error: illegal operands `vamoaddei32.v v4,\(a1\),v4,v0'
  5568. +.*Error: illegal operands `vamoaddei32.v x0,\(a1\),v4,v0,v0.t'
  5569. +.*Error: illegal operands `vamoswapei32.v v4,\(a1\),v4,v0'
  5570. +.*Error: illegal operands `vamoswapei32.v v0,\(a1\),v4,v0,v0.t'
  5571. +.*Error: illegal operands `vamoswapei32.v x0,\(a1\),v4,v0,v0.t'
  5572. +.*Error: illegal operands `vamoxorei32.v v4,\(a1\),v4,v0'
  5573. +.*Error: illegal operands `vamoxorei32.v v0,\(a1\),v4,v0,v0.t'
  5574. +.*Error: illegal operands `vamoxorei32.v x0,\(a1\),v4,v0,v0.t'
  5575. +.*Error: illegal operands `vamoandei32.v v4,\(a1\),v4,v0'
  5576. +.*Error: illegal operands `vamoandei32.v v0,\(a1\),v4,v0,v0.t'
  5577. +.*Error: illegal operands `vamoandei32.v x0,\(a1\),v4,v0,v0.t'
  5578. +.*Error: illegal operands `vamoorei32.v v4,\(a1\),v4,v0'
  5579. +.*Error: illegal operands `vamoorei32.v v0,\(a1\),v4,v0,v0.t'
  5580. +.*Error: illegal operands `vamoorei32.v x0,\(a1\),v4,v0,v0.t'
  5581. +.*Error: illegal operands `vamominei32.v v4,\(a1\),v4,v0'
  5582. +.*Error: illegal operands `vamominei32.v v0,\(a1\),v4,v0,v0.t'
  5583. +.*Error: illegal operands `vamominei32.v x0,\(a1\),v4,v0,v0.t'
  5584. +.*Error: illegal operands `vamomaxei32.v v4,\(a1\),v4,v0'
  5585. +.*Error: illegal operands `vamomaxei32.v v0,\(a1\),v4,v0,v0.t'
  5586. +.*Error: illegal operands `vamomaxei32.v x0,\(a1\),v4,v0,v0.t'
  5587. +.*Error: illegal operands `vamominuei32.v v4,\(a1\),v4,v0'
  5588. +.*Error: illegal operands `vamominuei32.v v0,\(a1\),v4,v0,v0.t'
  5589. +.*Error: illegal operands `vamominuei32.v x0,\(a1\),v4,v0,v0.t'
  5590. +.*Error: illegal operands `vamomaxuei32.v v4,\(a1\),v4,v0'
  5591. +.*Error: illegal operands `vamomaxuei32.v v0,\(a1\),v4,v0,v0.t'
  5592. +.*Error: illegal operands `vamomaxuei32.v x0,\(a1\),v4,v0,v0.t'
  5593. +.*Error: illegal operands `vamoaddei64.v v4,\(a1\),v4,v0'
  5594. +.*Error: illegal operands `vamoaddei64.v v0,\(a1\),v4,v0,v0.t'
  5595. +.*Error: illegal operands `vamoaddei64.v x0,\(a1\),v4,v0,v0.t'
  5596. +.*Error: illegal operands `vamoswapei64.v v4,\(a1\),v4,v0'
  5597. +.*Error: illegal operands `vamoswapei64.v v0,\(a1\),v4,v0,v0.t'
  5598. +.*Error: illegal operands `vamoswapei64.v x0,\(a1\),v4,v0,v0.t'
  5599. +.*Error: illegal operands `vamoxorei64.v v4,\(a1\),v4,v0'
  5600. +.*Error: illegal operands `vamoxorei64.v v0,\(a1\),v4,v0,v0.t'
  5601. +.*Error: illegal operands `vamoxorei64.v x0,\(a1\),v4,v0,v0.t'
  5602. +.*Error: illegal operands `vamoandei64.v v4,\(a1\),v4,v0'
  5603. +.*Error: illegal operands `vamoandei64.v v0,\(a1\),v4,v0,v0.t'
  5604. +.*Error: illegal operands `vamoandei64.v x0,\(a1\),v4,v0,v0.t'
  5605. +.*Error: illegal operands `vamoorei64.v v4,\(a1\),v4,v0'
  5606. +.*Error: illegal operands `vamoorei64.v v0,\(a1\),v4,v0,v0.t'
  5607. +.*Error: illegal operands `vamoorei64.v x0,\(a1\),v4,v0,v0.t'
  5608. +.*Error: illegal operands `vamominei64.v v4,\(a1\),v4,v0'
  5609. +.*Error: illegal operands `vamominei64.v v0,\(a1\),v4,v0,v0.t'
  5610. +.*Error: illegal operands `vamominei64.v x0,\(a1\),v4,v0,v0.t'
  5611. +.*Error: illegal operands `vamomaxei64.v v4,\(a1\),v4,v0'
  5612. +.*Error: illegal operands `vamomaxei64.v v0,\(a1\),v4,v0,v0.t'
  5613. +.*Error: illegal operands `vamomaxei64.v x0,\(a1\),v4,v0,v0.t'
  5614. +.*Error: illegal operands `vamominuei64.v v4,\(a1\),v4,v0'
  5615. +.*Error: illegal operands `vamominuei64.v v0,\(a1\),v4,v0,v0.t'
  5616. +.*Error: illegal operands `vamominuei64.v x0,\(a1\),v4,v0,v0.t'
  5617. +.*Error: illegal operands `vamomaxuei64.v v4,\(a1\),v4,v0'
  5618. +.*Error: illegal operands `vamomaxuei64.v v0,\(a1\),v4,v0,v0.t'
  5619. +.*Error: illegal operands `vamomaxuei64.v x0,\(a1\),v4,v0,v0.t'
  5620. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
  5621. new file mode 100644
  5622. index 0000000000..0fd3c26a58
  5623. --- /dev/null
  5624. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
  5625. @@ -0,0 +1,217 @@
  5626. +# Vector AMO Operations
  5627. +
  5628. + vamoaddei8.v v0, (a1), v4, v0 # OK
  5629. + vamoaddei8.v v4, (a1), v4, v0 # vd must match vs3
  5630. + vamoaddei8.v v0, (a1), v4, v0, v0.t # vd overlap vm
  5631. + vamoaddei8.v x0, (a1), v4, v0 # OK
  5632. + vamoaddei8.v x0, (a1), v4, v0, v0.t # vs3 overlap vm
  5633. +
  5634. + vamoswapei8.v v0, (a1), v4, v0
  5635. + vamoswapei8.v v4, (a1), v4, v0
  5636. + vamoswapei8.v v0, (a1), v4, v0, v0.t
  5637. + vamoswapei8.v x0, (a1), v4, v0
  5638. + vamoswapei8.v x0, (a1), v4, v0, v0.t
  5639. +
  5640. + vamoxorei8.v v0, (a1), v4, v0
  5641. + vamoxorei8.v v4, (a1), v4, v0
  5642. + vamoxorei8.v v0, (a1), v4, v0, v0.t
  5643. + vamoxorei8.v x0, (a1), v4, v0
  5644. + vamoxorei8.v x0, (a1), v4, v0, v0.t
  5645. +
  5646. + vamoandei8.v v0, (a1), v4, v0
  5647. + vamoandei8.v v4, (a1), v4, v0
  5648. + vamoandei8.v v0, (a1), v4, v0, v0.t
  5649. + vamoandei8.v x0, (a1), v4, v0
  5650. + vamoandei8.v x0, (a1), v4, v0, v0.t
  5651. +
  5652. + vamoorei8.v v0, (a1), v4, v0
  5653. + vamoorei8.v v4, (a1), v4, v0
  5654. + vamoorei8.v v0, (a1), v4, v0, v0.t
  5655. + vamoorei8.v x0, (a1), v4, v0
  5656. + vamoorei8.v x0, (a1), v4, v0, v0.t
  5657. +
  5658. + vamominei8.v v0, (a1), v4, v0
  5659. + vamominei8.v v4, (a1), v4, v0
  5660. + vamominei8.v v0, (a1), v4, v0, v0.t
  5661. + vamominei8.v x0, (a1), v4, v0
  5662. + vamominei8.v x0, (a1), v4, v0, v0.t
  5663. +
  5664. + vamomaxei8.v v0, (a1), v4, v0
  5665. + vamomaxei8.v v4, (a1), v4, v0
  5666. + vamomaxei8.v v0, (a1), v4, v0, v0.t
  5667. + vamomaxei8.v x0, (a1), v4, v0
  5668. + vamomaxei8.v x0, (a1), v4, v0, v0.t
  5669. +
  5670. + vamominuei8.v v0, (a1), v4, v0
  5671. + vamominuei8.v v4, (a1), v4, v0
  5672. + vamominuei8.v v0, (a1), v4, v0, v0.t
  5673. + vamominuei8.v x0, (a1), v4, v0
  5674. + vamominuei8.v x0, (a1), v4, v0, v0.t
  5675. +
  5676. + vamomaxuei8.v v0, (a1), v4, v0
  5677. + vamomaxuei8.v v4, (a1), v4, v0
  5678. + vamomaxuei8.v v0, (a1), v4, v0, v0.t
  5679. + vamomaxuei8.v x0, (a1), v4, v0
  5680. + vamomaxuei8.v x0, (a1), v4, v0, v0.t
  5681. +
  5682. + vamoaddei16.v v0, (a1), v4, v0
  5683. + vamoaddei16.v v4, (a1), v4, v0
  5684. + vamoaddei16.v v0, (a1), v4, v0, v0.t
  5685. + vamoaddei16.v x0, (a1), v4, v0
  5686. + vamoaddei16.v x0, (a1), v4, v0, v0.t
  5687. +
  5688. + vamoswapei16.v v0, (a1), v4, v0
  5689. + vamoswapei16.v v0, (a1), v4, v0, v0.t
  5690. + vamoswapei16.v v4, (a1), v4, v0
  5691. + vamoswapei16.v x0, (a1), v4, v0
  5692. + vamoswapei16.v x0, (a1), v4, v0, v0.t
  5693. +
  5694. + vamoxorei16.v v0, (a1), v4, v0
  5695. + vamoxorei16.v v0, (a1), v4, v0, v0.t
  5696. + vamoxorei16.v v4, (a1), v4, v0
  5697. + vamoxorei16.v x0, (a1), v4, v0
  5698. + vamoxorei16.v x0, (a1), v4, v0, v0.t
  5699. +
  5700. + vamoandei16.v v0, (a1), v4, v0
  5701. + vamoandei16.v v0, (a1), v4, v0, v0.t
  5702. + vamoandei16.v v4, (a1), v4, v0
  5703. + vamoandei16.v x0, (a1), v4, v0
  5704. + vamoandei16.v x0, (a1), v4, v0, v0.t
  5705. +
  5706. + vamoorei16.v v0, (a1), v4, v0
  5707. + vamoorei16.v v0, (a1), v4, v0, v0.t
  5708. + vamoorei16.v v4, (a1), v4, v0
  5709. + vamoorei16.v x0, (a1), v4, v0
  5710. + vamoorei16.v x0, (a1), v4, v0, v0.t
  5711. +
  5712. + vamominei16.v v0, (a1), v4, v0
  5713. + vamominei16.v v0, (a1), v4, v0, v0.t
  5714. + vamominei16.v v4, (a1), v4, v0
  5715. + vamominei16.v x0, (a1), v4, v0
  5716. + vamominei16.v x0, (a1), v4, v0, v0.t
  5717. +
  5718. + vamomaxei16.v v0, (a1), v4, v0
  5719. + vamomaxei16.v v0, (a1), v4, v0, v0.t
  5720. + vamomaxei16.v v4, (a1), v4, v0
  5721. + vamomaxei16.v x0, (a1), v4, v0
  5722. + vamomaxei16.v x0, (a1), v4, v0, v0.t
  5723. +
  5724. + vamominuei16.v v0, (a1), v4, v0
  5725. + vamominuei16.v v0, (a1), v4, v0, v0.t
  5726. + vamominuei16.v v4, (a1), v4, v0
  5727. + vamominuei16.v x0, (a1), v4, v0
  5728. + vamominuei16.v x0, (a1), v4, v0, v0.t
  5729. +
  5730. + vamomaxuei16.v v0, (a1), v4, v0
  5731. + vamomaxuei16.v v0, (a1), v4, v0, v0.t
  5732. + vamomaxuei16.v v4, (a1), v4, v0
  5733. + vamomaxuei16.v x0, (a1), v4, v0
  5734. + vamomaxuei16.v x0, (a1), v4, v0, v0.t
  5735. +
  5736. + vamoaddei32.v v0, (a1), v4, v0
  5737. + vamoaddei32.v v0, (a1), v4, v0, v0.t
  5738. + vamoaddei32.v v4, (a1), v4, v0
  5739. + vamoaddei32.v x0, (a1), v4, v0
  5740. + vamoaddei32.v x0, (a1), v4, v0, v0.t
  5741. +
  5742. + vamoswapei32.v v0, (a1), v4, v0
  5743. + vamoswapei32.v v4, (a1), v4, v0
  5744. + vamoswapei32.v v0, (a1), v4, v0, v0.t
  5745. + vamoswapei32.v x0, (a1), v4, v0
  5746. + vamoswapei32.v x0, (a1), v4, v0, v0.t
  5747. +
  5748. + vamoxorei32.v v0, (a1), v4, v0
  5749. + vamoxorei32.v v4, (a1), v4, v0
  5750. + vamoxorei32.v v0, (a1), v4, v0, v0.t
  5751. + vamoxorei32.v x0, (a1), v4, v0
  5752. + vamoxorei32.v x0, (a1), v4, v0, v0.t
  5753. +
  5754. + vamoandei32.v v0, (a1), v4, v0
  5755. + vamoandei32.v v4, (a1), v4, v0
  5756. + vamoandei32.v v0, (a1), v4, v0, v0.t
  5757. + vamoandei32.v x0, (a1), v4, v0
  5758. + vamoandei32.v x0, (a1), v4, v0, v0.t
  5759. +
  5760. + vamoorei32.v v0, (a1), v4, v0
  5761. + vamoorei32.v v4, (a1), v4, v0
  5762. + vamoorei32.v v0, (a1), v4, v0, v0.t
  5763. + vamoorei32.v x0, (a1), v4, v0
  5764. + vamoorei32.v x0, (a1), v4, v0, v0.t
  5765. +
  5766. + vamominei32.v v0, (a1), v4, v0
  5767. + vamominei32.v v4, (a1), v4, v0
  5768. + vamominei32.v v0, (a1), v4, v0, v0.t
  5769. + vamominei32.v x0, (a1), v4, v0
  5770. + vamominei32.v x0, (a1), v4, v0, v0.t
  5771. +
  5772. + vamomaxei32.v v0, (a1), v4, v0
  5773. + vamomaxei32.v v4, (a1), v4, v0
  5774. + vamomaxei32.v v0, (a1), v4, v0, v0.t
  5775. + vamomaxei32.v x0, (a1), v4, v0
  5776. + vamomaxei32.v x0, (a1), v4, v0, v0.t
  5777. +
  5778. + vamominuei32.v v0, (a1), v4, v0
  5779. + vamominuei32.v v4, (a1), v4, v0
  5780. + vamominuei32.v v0, (a1), v4, v0, v0.t
  5781. + vamominuei32.v x0, (a1), v4, v0
  5782. + vamominuei32.v x0, (a1), v4, v0, v0.t
  5783. +
  5784. + vamomaxuei32.v v0, (a1), v4, v0
  5785. + vamomaxuei32.v v4, (a1), v4, v0
  5786. + vamomaxuei32.v v0, (a1), v4, v0, v0.t
  5787. + vamomaxuei32.v x0, (a1), v4, v0
  5788. + vamomaxuei32.v x0, (a1), v4, v0, v0.t
  5789. +
  5790. + vamoaddei64.v v0, (a1), v4, v0
  5791. + vamoaddei64.v v4, (a1), v4, v0
  5792. + vamoaddei64.v v0, (a1), v4, v0, v0.t
  5793. + vamoaddei64.v x0, (a1), v4, v0
  5794. + vamoaddei64.v x0, (a1), v4, v0, v0.t
  5795. +
  5796. + vamoswapei64.v v0, (a1), v4, v0
  5797. + vamoswapei64.v v4, (a1), v4, v0
  5798. + vamoswapei64.v v0, (a1), v4, v0, v0.t
  5799. + vamoswapei64.v x0, (a1), v4, v0
  5800. + vamoswapei64.v x0, (a1), v4, v0, v0.t
  5801. +
  5802. + vamoxorei64.v v0, (a1), v4, v0
  5803. + vamoxorei64.v v4, (a1), v4, v0
  5804. + vamoxorei64.v v0, (a1), v4, v0, v0.t
  5805. + vamoxorei64.v x0, (a1), v4, v0
  5806. + vamoxorei64.v x0, (a1), v4, v0, v0.t
  5807. +
  5808. + vamoandei64.v v0, (a1), v4, v0
  5809. + vamoandei64.v v4, (a1), v4, v0
  5810. + vamoandei64.v v0, (a1), v4, v0, v0.t
  5811. + vamoandei64.v x0, (a1), v4, v0
  5812. + vamoandei64.v x0, (a1), v4, v0, v0.t
  5813. +
  5814. + vamoorei64.v v0, (a1), v4, v0
  5815. + vamoorei64.v v4, (a1), v4, v0
  5816. + vamoorei64.v v0, (a1), v4, v0, v0.t
  5817. + vamoorei64.v x0, (a1), v4, v0
  5818. + vamoorei64.v x0, (a1), v4, v0, v0.t
  5819. +
  5820. + vamominei64.v v0, (a1), v4, v0
  5821. + vamominei64.v v4, (a1), v4, v0
  5822. + vamominei64.v v0, (a1), v4, v0, v0.t
  5823. + vamominei64.v x0, (a1), v4, v0
  5824. + vamominei64.v x0, (a1), v4, v0, v0.t
  5825. +
  5826. + vamomaxei64.v v0, (a1), v4, v0
  5827. + vamomaxei64.v v4, (a1), v4, v0
  5828. + vamomaxei64.v v0, (a1), v4, v0, v0.t
  5829. + vamomaxei64.v x0, (a1), v4, v0
  5830. + vamomaxei64.v x0, (a1), v4, v0, v0.t
  5831. +
  5832. + vamominuei64.v v0, (a1), v4, v0
  5833. + vamominuei64.v v4, (a1), v4, v0
  5834. + vamominuei64.v v0, (a1), v4, v0, v0.t
  5835. + vamominuei64.v x0, (a1), v4, v0
  5836. + vamominuei64.v x0, (a1), v4, v0, v0.t
  5837. +
  5838. + vamomaxuei64.v v0, (a1), v4, v0
  5839. + vamomaxuei64.v v4, (a1), v4, v0
  5840. + vamomaxuei64.v v0, (a1), v4, v0, v0.t
  5841. + vamomaxuei64.v x0, (a1), v4, v0
  5842. + vamomaxuei64.v x0, (a1), v4, v0, v0.t
  5843. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d
  5844. new file mode 100644
  5845. index 0000000000..912408ed06
  5846. --- /dev/null
  5847. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d
  5848. @@ -0,0 +1,3 @@
  5849. +#as: -march=rv32iv_zvqmac -mcheck-constraints
  5850. +#source: vector-insns-fail-zvqmac.s
  5851. +#error_output: vector-insns-fail-zvqmac.l
  5852. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
  5853. new file mode 100644
  5854. index 0000000000..e5c157fd89
  5855. --- /dev/null
  5856. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
  5857. @@ -0,0 +1,35 @@
  5858. +.*: Assembler messages:
  5859. +.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
  5860. +.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
  5861. +.*Error: illegal operands `vqmaccu.vv v4,v7,v8'
  5862. +.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
  5863. +.*Error: illegal operands `vqmaccu.vv v8,v4,v11'
  5864. +.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
  5865. +.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
  5866. +.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
  5867. +.*Error: illegal operands `vqmaccu.vx v4,a1,v7'
  5868. +.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
  5869. +.*Error: illegal operands `vqmacc.vv v2,v4,v8'
  5870. +.*Error: illegal operands `vqmacc.vv v4,v4,v8'
  5871. +.*Error: illegal operands `vqmacc.vv v4,v7,v8'
  5872. +.*Error: illegal operands `vqmacc.vv v8,v4,v8'
  5873. +.*Error: illegal operands `vqmacc.vv v8,v4,v11'
  5874. +.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
  5875. +.*Error: illegal operands `vqmacc.vx v2,a1,v4'
  5876. +.*Error: illegal operands `vqmacc.vx v4,a1,v4'
  5877. +.*Error: illegal operands `vqmacc.vx v4,a1,v7'
  5878. +.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
  5879. +.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
  5880. +.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
  5881. +.*Error: illegal operands `vqmaccsu.vv v4,v7,v8'
  5882. +.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
  5883. +.*Error: illegal operands `vqmaccsu.vv v8,v4,v11'
  5884. +.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
  5885. +.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
  5886. +.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
  5887. +.*Error: illegal operands `vqmaccsu.vx v4,a1,v7'
  5888. +.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
  5889. +.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
  5890. +.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
  5891. +.*Error: illegal operands `vqmaccus.vx v4,a1,v7'
  5892. +.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
  5893. diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s
  5894. new file mode 100644
  5895. index 0000000000..930e211dae
  5896. --- /dev/null
  5897. +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s
  5898. @@ -0,0 +1,39 @@
  5899. +# Quad-Widening Vector Arithmetic Instructions
  5900. +
  5901. + vqmaccu.vv v2, v4, v8 # vd should be multiple of 4
  5902. + vqmaccu.vv v4, v4, v8 # vd overlap vs1
  5903. + vqmaccu.vv v4, v7, v8 # vd overlap vs1
  5904. + vqmaccu.vv v8, v4, v8 # vd overlap vs2
  5905. + vqmaccu.vv v8, v4, v11 # vd overlap vs2
  5906. + vqmaccu.vv v0, v4, v8, v0.t # vd overlap vm
  5907. + vqmaccu.vx v2, a1, v4 # vd should be multiple of 4
  5908. + vqmaccu.vx v4, a1, v4 # vd overlap vs2
  5909. + vqmaccu.vx v4, a1, v7 # vd overlap vs2
  5910. + vqmaccu.vx v0, a1, v4, v0.t # vd overlap vm
  5911. +
  5912. + vqmacc.vv v2, v4, v8
  5913. + vqmacc.vv v4, v4, v8
  5914. + vqmacc.vv v4, v7, v8
  5915. + vqmacc.vv v8, v4, v8
  5916. + vqmacc.vv v8, v4, v11
  5917. + vqmacc.vv v0, v4, v8, v0.t
  5918. + vqmacc.vx v2, a1, v4
  5919. + vqmacc.vx v4, a1, v4
  5920. + vqmacc.vx v4, a1, v7
  5921. + vqmacc.vx v0, a1, v4, v0.t
  5922. +
  5923. + vqmaccsu.vv v2, v4, v8
  5924. + vqmaccsu.vv v4, v4, v8
  5925. + vqmaccsu.vv v4, v7, v8
  5926. + vqmaccsu.vv v8, v4, v8
  5927. + vqmaccsu.vv v8, v4, v11
  5928. + vqmaccsu.vv v0, v4, v8, v0.t
  5929. + vqmaccsu.vx v2, a1, v4
  5930. + vqmaccsu.vx v4, a1, v4
  5931. + vqmaccsu.vx v4, a1, v7
  5932. + vqmaccsu.vx v0, a1, v4, v0.t
  5933. +
  5934. + vqmaccus.vx v2, a1, v4 # vd should be multiple of 4
  5935. + vqmaccus.vx v4, a1, v4 # vd overlap vs2
  5936. + vqmaccus.vx v4, a1, v7 # vd overlap vs2
  5937. + vqmaccus.vx v0, a1, v4, v0.t # vd overlap vm
  5938. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  5939. index c7ecb7c965..58190fd7c9 100644
  5940. --- a/opcodes/riscv-opc.c
  5941. +++ b/opcodes/riscv-opc.c
  5942. @@ -381,16 +381,18 @@ match_quad_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
  5943. }
  5944. static int
  5945. -match_narrow_vd_neq_vs2 (const struct riscv_opcode *op,
  5946. - insn_t insn,
  5947. - int constraints)
  5948. +match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
  5949. + insn_t insn,
  5950. + int constraints)
  5951. {
  5952. int vd = (insn & MASK_VD) >> OP_SH_VD;
  5953. int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  5954. + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
  5955. if (constraints
  5956. && ((vs2 % 2) != 0
  5957. - || (vd >= vs2 && vd <= (vs2 + 1))))
  5958. + || (vd >= vs2 && vd <= (vs2 + 1))
  5959. + || (!vm && vd >= vm && vd <= (vm + 1))))
  5960. return 0;
  5961. return match_opcode (op, insn, 0);
  5962. @@ -432,19 +434,10 @@ match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
  5963. return match_opcode (op, insn, 0);
  5964. }
  5965. -static int
  5966. -match_vd_neq_vs2 (const struct riscv_opcode *op,
  5967. - insn_t insn,
  5968. - int constraints)
  5969. -{
  5970. - int vd = (insn & MASK_VD) >> OP_SH_VD;
  5971. - int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
  5972. -
  5973. - if (constraints && vs2 == vd)
  5974. - return 0;
  5975. -
  5976. - return match_opcode (op, insn, 0);
  5977. -}
  5978. +/* v[m]adc and v[m]sbc use the vm encoding to encode the
  5979. + carry-in v0 register. The carry-in v0 register can not
  5980. + overlap with the vd, too. Therefore, we use the same
  5981. + match_vd_neq_vm to check the overlap constraints. */
  5982. static int
  5983. match_vd_neq_vm (const struct riscv_opcode *op,
  5984. @@ -1066,305 +1059,305 @@ const struct riscv_opcode riscv_opcodes[] =
  5985. {"vsetvl", 0, INSN_CLASS_V, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
  5986. {"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
  5987. -{"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
  5988. -{"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
  5989. -{"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
  5990. -{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
  5991. -{"vle128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128V, MASK_VLE128V, match_opcode, INSN_DREF },
  5992. -{"vle256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256V, MASK_VLE256V, match_opcode, INSN_DREF },
  5993. -{"vle512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512V, MASK_VLE512V, match_opcode, INSN_DREF },
  5994. -{"vle1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024V, MASK_VLE1024V, match_opcode, INSN_DREF },
  5995. -
  5996. -{"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
  5997. -{"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
  5998. -{"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
  5999. -{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
  6000. -{"vse128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE128V, MASK_VSE128V, match_opcode, INSN_DREF },
  6001. -{"vse256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE256V, MASK_VSE256V, match_opcode, INSN_DREF },
  6002. -{"vse512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE512V, MASK_VSE512V, match_opcode, INSN_DREF },
  6003. -{"vse1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE1024V, MASK_VSE1024V, match_opcode, INSN_DREF },
  6004. -
  6005. -{"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
  6006. -{"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
  6007. -{"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
  6008. -{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
  6009. -{"vlse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE128V, MASK_VLSE128V, match_opcode, INSN_DREF },
  6010. -{"vlse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE256V, MASK_VLSE256V, match_opcode, INSN_DREF },
  6011. -{"vlse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE512V, MASK_VLSE512V, match_opcode, INSN_DREF },
  6012. -{"vlse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE1024V, MASK_VLSE1024V, match_opcode, INSN_DREF },
  6013. -
  6014. -{"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
  6015. -{"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
  6016. -{"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
  6017. -{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
  6018. -{"vsse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE128V, MASK_VSSE128V, match_opcode, INSN_DREF },
  6019. -{"vsse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE256V, MASK_VSSE256V, match_opcode, INSN_DREF },
  6020. -{"vsse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_opcode, INSN_DREF },
  6021. -{"vsse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_opcode, INSN_DREF },
  6022. -
  6023. -{"vlxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_opcode, INSN_DREF },
  6024. -{"vlxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_opcode, INSN_DREF },
  6025. -{"vlxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_opcode, INSN_DREF },
  6026. -{"vlxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_opcode, INSN_DREF },
  6027. -
  6028. -{"vsxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_opcode, INSN_DREF },
  6029. -{"vsxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_opcode, INSN_DREF },
  6030. -{"vsxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_opcode, INSN_DREF },
  6031. -{"vsxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_opcode, INSN_DREF },
  6032. -
  6033. -{"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF },
  6034. -{"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF },
  6035. -{"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF },
  6036. -{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF },
  6037. -
  6038. -{"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
  6039. -{"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
  6040. -{"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
  6041. -{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
  6042. -{"vle128ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128FFV, MASK_VLE128FFV, match_opcode, INSN_DREF },
  6043. -{"vle256ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256FFV, MASK_VLE256FFV, match_opcode, INSN_DREF },
  6044. -{"vle512ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512FFV, MASK_VLE512FFV, match_opcode, INSN_DREF },
  6045. -{"vle1024ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024FFV, MASK_VLE1024FFV, match_opcode, INSN_DREF },
  6046. +{"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
  6047. +{"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
  6048. +{"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_vd_neq_vm, INSN_DREF },
  6049. +{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_vd_neq_vm, INSN_DREF },
  6050. +{"vle128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128V, MASK_VLE128V, match_vd_neq_vm, INSN_DREF },
  6051. +{"vle256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256V, MASK_VLE256V, match_vd_neq_vm, INSN_DREF },
  6052. +{"vle512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512V, MASK_VLE512V, match_vd_neq_vm, INSN_DREF },
  6053. +{"vle1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024V, MASK_VLE1024V, match_vd_neq_vm, INSN_DREF },
  6054. +
  6055. +{"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_vd_neq_vm, INSN_DREF },
  6056. +{"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_vd_neq_vm, INSN_DREF },
  6057. +{"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_vd_neq_vm, INSN_DREF },
  6058. +{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_vd_neq_vm, INSN_DREF },
  6059. +{"vse128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE128V, MASK_VSE128V, match_vd_neq_vm, INSN_DREF },
  6060. +{"vse256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE256V, MASK_VSE256V, match_vd_neq_vm, INSN_DREF },
  6061. +{"vse512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE512V, MASK_VSE512V, match_vd_neq_vm, INSN_DREF },
  6062. +{"vse1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE1024V, MASK_VSE1024V, match_vd_neq_vm, INSN_DREF },
  6063. +
  6064. +{"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_vd_neq_vm, INSN_DREF },
  6065. +{"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_vd_neq_vm, INSN_DREF },
  6066. +{"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_vd_neq_vm, INSN_DREF },
  6067. +{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_vd_neq_vm, INSN_DREF },
  6068. +{"vlse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE128V, MASK_VLSE128V, match_vd_neq_vm, INSN_DREF },
  6069. +{"vlse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE256V, MASK_VLSE256V, match_vd_neq_vm, INSN_DREF },
  6070. +{"vlse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE512V, MASK_VLSE512V, match_vd_neq_vm, INSN_DREF },
  6071. +{"vlse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE1024V, MASK_VLSE1024V, match_vd_neq_vm, INSN_DREF },
  6072. +
  6073. +{"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_vd_neq_vm, INSN_DREF },
  6074. +{"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_vd_neq_vm, INSN_DREF },
  6075. +{"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_vd_neq_vm, INSN_DREF },
  6076. +{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_vd_neq_vm, INSN_DREF },
  6077. +{"vsse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE128V, MASK_VSSE128V, match_vd_neq_vm, INSN_DREF },
  6078. +{"vsse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE256V, MASK_VSSE256V, match_vd_neq_vm, INSN_DREF },
  6079. +{"vsse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_vd_neq_vm, INSN_DREF },
  6080. +{"vsse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_vd_neq_vm, INSN_DREF },
  6081. +
  6082. +{"vlxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_vd_neq_vm, INSN_DREF },
  6083. +{"vlxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_vd_neq_vm, INSN_DREF },
  6084. +{"vlxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_vd_neq_vm, INSN_DREF },
  6085. +{"vlxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_vd_neq_vm, INSN_DREF },
  6086. +
  6087. +{"vsxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_vd_neq_vm, INSN_DREF },
  6088. +{"vsxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_vd_neq_vm, INSN_DREF },
  6089. +{"vsxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_vd_neq_vm, INSN_DREF },
  6090. +{"vsxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_vd_neq_vm, INSN_DREF },
  6091. +
  6092. +{"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
  6093. +{"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
  6094. +{"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
  6095. +{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
  6096. +
  6097. +{"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
  6098. +{"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
  6099. +{"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
  6100. +{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
  6101. +{"vle128ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128FFV, MASK_VLE128FFV, match_vd_neq_vm, INSN_DREF },
  6102. +{"vle256ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256FFV, MASK_VLE256FFV, match_vd_neq_vm, INSN_DREF },
  6103. +{"vle512ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512FFV, MASK_VLE512FFV, match_vd_neq_vm, INSN_DREF },
  6104. +{"vle1024ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024FFV, MASK_VLE1024FFV, match_vd_neq_vm, INSN_DREF },
  6105. {"vlseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
  6106. -{"vsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF },
  6107. +{"vsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
  6108. {"vlseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
  6109. -{"vsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF },
  6110. +{"vsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_vd_neq_vm, INSN_DREF },
  6111. {"vlseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
  6112. -{"vsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF },
  6113. +{"vsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_vd_neq_vm, INSN_DREF },
  6114. {"vlseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
  6115. -{"vsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF },
  6116. +{"vsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_vd_neq_vm, INSN_DREF },
  6117. {"vlseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
  6118. -{"vsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF },
  6119. +{"vsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_vd_neq_vm, INSN_DREF },
  6120. {"vlseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
  6121. -{"vsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF },
  6122. +{"vsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_vd_neq_vm, INSN_DREF },
  6123. {"vlseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
  6124. -{"vsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF },
  6125. +{"vsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_vd_neq_vm, INSN_DREF },
  6126. {"vlseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
  6127. -{"vsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF },
  6128. +{"vsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_vd_neq_vm, INSN_DREF },
  6129. {"vlseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
  6130. -{"vsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF },
  6131. +{"vsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_vd_neq_vm, INSN_DREF },
  6132. {"vlseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
  6133. -{"vsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF },
  6134. +{"vsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_vd_neq_vm, INSN_DREF },
  6135. {"vlseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
  6136. -{"vsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF },
  6137. +{"vsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_vd_neq_vm, INSN_DREF },
  6138. {"vlseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
  6139. -{"vsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF },
  6140. +{"vsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_vd_neq_vm, INSN_DREF },
  6141. {"vlseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
  6142. -{"vsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF },
  6143. +{"vsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_vd_neq_vm, INSN_DREF },
  6144. {"vlseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
  6145. -{"vsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF },
  6146. +{"vsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_vd_neq_vm, INSN_DREF },
  6147. {"vlseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
  6148. -{"vsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF },
  6149. +{"vsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_vd_neq_vm, INSN_DREF },
  6150. {"vlseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
  6151. -{"vsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF },
  6152. +{"vsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_vd_neq_vm, INSN_DREF },
  6153. {"vlseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
  6154. -{"vsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF },
  6155. +{"vsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_vd_neq_vm, INSN_DREF },
  6156. {"vlseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
  6157. -{"vsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF },
  6158. +{"vsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_vd_neq_vm, INSN_DREF },
  6159. {"vlseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
  6160. -{"vsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF },
  6161. +{"vsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_vd_neq_vm, INSN_DREF },
  6162. {"vlseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
  6163. -{"vsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF },
  6164. +{"vsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_vd_neq_vm, INSN_DREF },
  6165. {"vlseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
  6166. -{"vsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF },
  6167. +{"vsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
  6168. {"vlseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
  6169. -{"vsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF },
  6170. +{"vsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
  6171. {"vlseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
  6172. -{"vsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF },
  6173. +{"vsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
  6174. {"vlseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
  6175. -{"vsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF },
  6176. +{"vsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
  6177. {"vlseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
  6178. -{"vsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF },
  6179. +{"vsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
  6180. {"vlseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
  6181. -{"vsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF },
  6182. +{"vsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
  6183. {"vlseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
  6184. -{"vsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF },
  6185. +{"vsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
  6186. {"vlseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
  6187. -{"vsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF },
  6188. +{"vsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
  6189. {"vlseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E128V, MASK_VLSEG2E128V, match_vd_neq_vm, INSN_DREF },
  6190. -{"vsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E128V, MASK_VSSEG2E128V, match_opcode, INSN_DREF },
  6191. +{"vsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E128V, MASK_VSSEG2E128V, match_vd_neq_vm, INSN_DREF },
  6192. {"vlseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E128V, MASK_VLSEG3E128V, match_vd_neq_vm, INSN_DREF },
  6193. -{"vsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E128V, MASK_VSSEG3E128V, match_opcode, INSN_DREF },
  6194. +{"vsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E128V, MASK_VSSEG3E128V, match_vd_neq_vm, INSN_DREF },
  6195. {"vlseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E128V, MASK_VLSEG4E128V, match_vd_neq_vm, INSN_DREF },
  6196. -{"vsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E128V, MASK_VSSEG4E128V, match_opcode, INSN_DREF },
  6197. +{"vsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E128V, MASK_VSSEG4E128V, match_vd_neq_vm, INSN_DREF },
  6198. {"vlseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E128V, MASK_VLSEG5E128V, match_vd_neq_vm, INSN_DREF },
  6199. -{"vsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E128V, MASK_VSSEG5E128V, match_opcode, INSN_DREF },
  6200. +{"vsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E128V, MASK_VSSEG5E128V, match_vd_neq_vm, INSN_DREF },
  6201. {"vlseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E128V, MASK_VLSEG6E128V, match_vd_neq_vm, INSN_DREF },
  6202. -{"vsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E128V, MASK_VSSEG6E128V, match_opcode, INSN_DREF },
  6203. +{"vsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E128V, MASK_VSSEG6E128V, match_vd_neq_vm, INSN_DREF },
  6204. {"vlseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E128V, MASK_VLSEG7E128V, match_vd_neq_vm, INSN_DREF },
  6205. -{"vsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E128V, MASK_VSSEG7E128V, match_opcode, INSN_DREF },
  6206. +{"vsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E128V, MASK_VSSEG7E128V, match_vd_neq_vm, INSN_DREF },
  6207. {"vlseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E128V, MASK_VLSEG8E128V, match_vd_neq_vm, INSN_DREF },
  6208. -{"vsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E128V, MASK_VSSEG8E128V, match_opcode, INSN_DREF },
  6209. +{"vsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E128V, MASK_VSSEG8E128V, match_vd_neq_vm, INSN_DREF },
  6210. {"vlseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E256V, MASK_VLSEG2E256V, match_vd_neq_vm, INSN_DREF },
  6211. -{"vsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E256V, MASK_VSSEG2E256V, match_opcode, INSN_DREF },
  6212. +{"vsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E256V, MASK_VSSEG2E256V, match_vd_neq_vm, INSN_DREF },
  6213. {"vlseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E256V, MASK_VLSEG3E256V, match_vd_neq_vm, INSN_DREF },
  6214. -{"vsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E256V, MASK_VSSEG3E256V, match_opcode, INSN_DREF },
  6215. +{"vsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E256V, MASK_VSSEG3E256V, match_vd_neq_vm, INSN_DREF },
  6216. {"vlseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E256V, MASK_VLSEG4E256V, match_vd_neq_vm, INSN_DREF },
  6217. -{"vsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E256V, MASK_VSSEG4E256V, match_opcode, INSN_DREF },
  6218. +{"vsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E256V, MASK_VSSEG4E256V, match_vd_neq_vm, INSN_DREF },
  6219. {"vlseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E256V, MASK_VLSEG5E256V, match_vd_neq_vm, INSN_DREF },
  6220. -{"vsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E256V, MASK_VSSEG5E256V, match_opcode, INSN_DREF },
  6221. +{"vsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E256V, MASK_VSSEG5E256V, match_vd_neq_vm, INSN_DREF },
  6222. {"vlseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E256V, MASK_VLSEG6E256V, match_vd_neq_vm, INSN_DREF },
  6223. -{"vsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E256V, MASK_VSSEG6E256V, match_opcode, INSN_DREF },
  6224. +{"vsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E256V, MASK_VSSEG6E256V, match_vd_neq_vm, INSN_DREF },
  6225. {"vlseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E256V, MASK_VLSEG7E256V, match_vd_neq_vm, INSN_DREF },
  6226. -{"vsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E256V, MASK_VSSEG7E256V, match_opcode, INSN_DREF },
  6227. +{"vsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E256V, MASK_VSSEG7E256V, match_vd_neq_vm, INSN_DREF },
  6228. {"vlseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E256V, MASK_VLSEG8E256V, match_vd_neq_vm, INSN_DREF },
  6229. -{"vsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E256V, MASK_VSSEG8E256V, match_opcode, INSN_DREF },
  6230. +{"vsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E256V, MASK_VSSEG8E256V, match_vd_neq_vm, INSN_DREF },
  6231. {"vlseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E512V, MASK_VLSEG2E512V, match_vd_neq_vm, INSN_DREF },
  6232. -{"vsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E512V, MASK_VSSEG2E512V, match_opcode, INSN_DREF },
  6233. +{"vsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E512V, MASK_VSSEG2E512V, match_vd_neq_vm, INSN_DREF },
  6234. {"vlseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E512V, MASK_VLSEG3E512V, match_vd_neq_vm, INSN_DREF },
  6235. -{"vsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E512V, MASK_VSSEG3E512V, match_opcode, INSN_DREF },
  6236. +{"vsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E512V, MASK_VSSEG3E512V, match_vd_neq_vm, INSN_DREF },
  6237. {"vlseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E512V, MASK_VLSEG4E512V, match_vd_neq_vm, INSN_DREF },
  6238. -{"vsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E512V, MASK_VSSEG4E512V, match_opcode, INSN_DREF },
  6239. +{"vsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E512V, MASK_VSSEG4E512V, match_vd_neq_vm, INSN_DREF },
  6240. {"vlseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E512V, MASK_VLSEG5E512V, match_vd_neq_vm, INSN_DREF },
  6241. -{"vsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E512V, MASK_VSSEG5E512V, match_opcode, INSN_DREF },
  6242. +{"vsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E512V, MASK_VSSEG5E512V, match_vd_neq_vm, INSN_DREF },
  6243. {"vlseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E512V, MASK_VLSEG6E512V, match_vd_neq_vm, INSN_DREF },
  6244. -{"vsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E512V, MASK_VSSEG6E512V, match_opcode, INSN_DREF },
  6245. +{"vsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E512V, MASK_VSSEG6E512V, match_vd_neq_vm, INSN_DREF },
  6246. {"vlseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E512V, MASK_VLSEG7E512V, match_vd_neq_vm, INSN_DREF },
  6247. -{"vsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E512V, MASK_VSSEG7E512V, match_opcode, INSN_DREF },
  6248. +{"vsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E512V, MASK_VSSEG7E512V, match_vd_neq_vm, INSN_DREF },
  6249. {"vlseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E512V, MASK_VLSEG8E512V, match_vd_neq_vm, INSN_DREF },
  6250. -{"vsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E512V, MASK_VSSEG8E512V, match_opcode, INSN_DREF },
  6251. +{"vsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E512V, MASK_VSSEG8E512V, match_vd_neq_vm, INSN_DREF },
  6252. {"vlseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E1024V, MASK_VLSEG2E1024V, match_vd_neq_vm, INSN_DREF },
  6253. -{"vsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E1024V, MASK_VSSEG2E1024V, match_opcode, INSN_DREF },
  6254. +{"vsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E1024V, MASK_VSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
  6255. {"vlseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E1024V, MASK_VLSEG3E1024V, match_vd_neq_vm, INSN_DREF },
  6256. -{"vsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E1024V, MASK_VSSEG3E1024V, match_opcode, INSN_DREF },
  6257. +{"vsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E1024V, MASK_VSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
  6258. {"vlseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E1024V, MASK_VLSEG4E1024V, match_vd_neq_vm, INSN_DREF },
  6259. -{"vsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E1024V, MASK_VSSEG4E1024V, match_opcode, INSN_DREF },
  6260. +{"vsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E1024V, MASK_VSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
  6261. {"vlseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E1024V, MASK_VLSEG5E1024V, match_vd_neq_vm, INSN_DREF },
  6262. -{"vsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E1024V, MASK_VSSEG5E1024V, match_opcode, INSN_DREF },
  6263. +{"vsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E1024V, MASK_VSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
  6264. {"vlseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E1024V, MASK_VLSEG6E1024V, match_vd_neq_vm, INSN_DREF },
  6265. -{"vsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E1024V, MASK_VSSEG6E1024V, match_opcode, INSN_DREF },
  6266. +{"vsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E1024V, MASK_VSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
  6267. {"vlseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E1024V, MASK_VLSEG7E1024V, match_vd_neq_vm, INSN_DREF },
  6268. -{"vsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E1024V, MASK_VSSEG7E1024V, match_opcode, INSN_DREF },
  6269. +{"vsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E1024V, MASK_VSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
  6270. {"vlseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024V, MASK_VLSEG8E1024V, match_vd_neq_vm, INSN_DREF },
  6271. -{"vsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E1024V, MASK_VSSEG8E1024V, match_opcode, INSN_DREF },
  6272. +{"vsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E1024V, MASK_VSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
  6273. {"vlsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
  6274. -{"vssseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF },
  6275. +{"vssseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
  6276. {"vlsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
  6277. -{"vssseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF },
  6278. +{"vssseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_vd_neq_vm, INSN_DREF },
  6279. {"vlsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
  6280. -{"vssseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF },
  6281. +{"vssseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_vd_neq_vm, INSN_DREF },
  6282. {"vlsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
  6283. -{"vssseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF },
  6284. +{"vssseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_vd_neq_vm, INSN_DREF },
  6285. {"vlsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
  6286. -{"vssseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF },
  6287. +{"vssseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_vd_neq_vm, INSN_DREF },
  6288. {"vlsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
  6289. -{"vssseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF },
  6290. +{"vssseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_vd_neq_vm, INSN_DREF },
  6291. {"vlsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
  6292. -{"vssseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF },
  6293. +{"vssseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_vd_neq_vm, INSN_DREF },
  6294. {"vlsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
  6295. -{"vssseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF },
  6296. +{"vssseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_vd_neq_vm, INSN_DREF },
  6297. {"vlsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
  6298. -{"vssseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF },
  6299. +{"vssseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_vd_neq_vm, INSN_DREF },
  6300. {"vlsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
  6301. -{"vssseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF },
  6302. +{"vssseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_vd_neq_vm, INSN_DREF },
  6303. {"vlsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
  6304. -{"vssseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF },
  6305. +{"vssseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_vd_neq_vm, INSN_DREF },
  6306. {"vlsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
  6307. -{"vssseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF },
  6308. +{"vssseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_vd_neq_vm, INSN_DREF },
  6309. {"vlsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
  6310. -{"vssseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF },
  6311. +{"vssseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_vd_neq_vm, INSN_DREF },
  6312. {"vlsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
  6313. -{"vssseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF },
  6314. +{"vssseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_vd_neq_vm, INSN_DREF },
  6315. {"vlsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
  6316. -{"vssseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF },
  6317. +{"vssseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_vd_neq_vm, INSN_DREF },
  6318. {"vlsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
  6319. -{"vssseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF },
  6320. +{"vssseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_vd_neq_vm, INSN_DREF },
  6321. {"vlsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
  6322. -{"vssseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF },
  6323. +{"vssseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_vd_neq_vm, INSN_DREF },
  6324. {"vlsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
  6325. -{"vssseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF },
  6326. +{"vssseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_vd_neq_vm, INSN_DREF },
  6327. {"vlsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
  6328. -{"vssseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF },
  6329. +{"vssseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_vd_neq_vm, INSN_DREF },
  6330. {"vlsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
  6331. -{"vssseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF },
  6332. +{"vssseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_vd_neq_vm, INSN_DREF },
  6333. {"vlsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
  6334. -{"vssseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF },
  6335. +{"vssseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
  6336. {"vlsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
  6337. -{"vssseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF },
  6338. +{"vssseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
  6339. {"vlsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
  6340. -{"vssseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF },
  6341. +{"vssseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
  6342. {"vlsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
  6343. -{"vssseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF },
  6344. +{"vssseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
  6345. {"vlsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
  6346. -{"vssseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF },
  6347. +{"vssseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
  6348. {"vlsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
  6349. -{"vssseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF },
  6350. +{"vssseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
  6351. {"vlsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
  6352. -{"vssseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF },
  6353. +{"vssseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
  6354. {"vlsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
  6355. -{"vssseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF },
  6356. +{"vssseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
  6357. {"vlsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E128V, MASK_VLSSEG2E128V, match_vd_neq_vm, INSN_DREF },
  6358. -{"vssseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E128V, MASK_VSSSEG2E128V, match_opcode, INSN_DREF },
  6359. +{"vssseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E128V, MASK_VSSSEG2E128V, match_vd_neq_vm, INSN_DREF },
  6360. {"vlsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E128V, MASK_VLSSEG3E128V, match_vd_neq_vm, INSN_DREF },
  6361. -{"vssseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E128V, MASK_VSSSEG3E128V, match_opcode, INSN_DREF },
  6362. +{"vssseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E128V, MASK_VSSSEG3E128V, match_vd_neq_vm, INSN_DREF },
  6363. {"vlsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E128V, MASK_VLSSEG4E128V, match_vd_neq_vm, INSN_DREF },
  6364. -{"vssseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E128V, MASK_VSSSEG4E128V, match_opcode, INSN_DREF },
  6365. +{"vssseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E128V, MASK_VSSSEG4E128V, match_vd_neq_vm, INSN_DREF },
  6366. {"vlsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E128V, MASK_VLSSEG5E128V, match_vd_neq_vm, INSN_DREF },
  6367. -{"vssseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E128V, MASK_VSSSEG5E128V, match_opcode, INSN_DREF },
  6368. +{"vssseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E128V, MASK_VSSSEG5E128V, match_vd_neq_vm, INSN_DREF },
  6369. {"vlsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E128V, MASK_VLSSEG6E128V, match_vd_neq_vm, INSN_DREF },
  6370. -{"vssseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E128V, MASK_VSSSEG6E128V, match_opcode, INSN_DREF },
  6371. +{"vssseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E128V, MASK_VSSSEG6E128V, match_vd_neq_vm, INSN_DREF },
  6372. {"vlsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E128V, MASK_VLSSEG7E128V, match_vd_neq_vm, INSN_DREF },
  6373. -{"vssseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E128V, MASK_VSSSEG7E128V, match_opcode, INSN_DREF },
  6374. +{"vssseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E128V, MASK_VSSSEG7E128V, match_vd_neq_vm, INSN_DREF },
  6375. {"vlsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E128V, MASK_VLSSEG8E128V, match_vd_neq_vm, INSN_DREF },
  6376. -{"vssseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E128V, MASK_VSSSEG8E128V, match_opcode, INSN_DREF },
  6377. +{"vssseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E128V, MASK_VSSSEG8E128V, match_vd_neq_vm, INSN_DREF },
  6378. {"vlsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E256V, MASK_VLSSEG2E256V, match_vd_neq_vm, INSN_DREF },
  6379. -{"vssseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E256V, MASK_VSSSEG2E256V, match_opcode, INSN_DREF },
  6380. +{"vssseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E256V, MASK_VSSSEG2E256V, match_vd_neq_vm, INSN_DREF },
  6381. {"vlsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E256V, MASK_VLSSEG3E256V, match_vd_neq_vm, INSN_DREF },
  6382. -{"vssseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E256V, MASK_VSSSEG3E256V, match_opcode, INSN_DREF },
  6383. +{"vssseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E256V, MASK_VSSSEG3E256V, match_vd_neq_vm, INSN_DREF },
  6384. {"vlsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E256V, MASK_VLSSEG4E256V, match_vd_neq_vm, INSN_DREF },
  6385. -{"vssseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E256V, MASK_VSSSEG4E256V, match_opcode, INSN_DREF },
  6386. +{"vssseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E256V, MASK_VSSSEG4E256V, match_vd_neq_vm, INSN_DREF },
  6387. {"vlsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E256V, MASK_VLSSEG5E256V, match_vd_neq_vm, INSN_DREF },
  6388. -{"vssseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E256V, MASK_VSSSEG5E256V, match_opcode, INSN_DREF },
  6389. +{"vssseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E256V, MASK_VSSSEG5E256V, match_vd_neq_vm, INSN_DREF },
  6390. {"vlsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E256V, MASK_VLSSEG6E256V, match_vd_neq_vm, INSN_DREF },
  6391. -{"vssseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E256V, MASK_VSSSEG6E256V, match_opcode, INSN_DREF },
  6392. +{"vssseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E256V, MASK_VSSSEG6E256V, match_vd_neq_vm, INSN_DREF },
  6393. {"vlsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E256V, MASK_VLSSEG7E256V, match_vd_neq_vm, INSN_DREF },
  6394. -{"vssseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E256V, MASK_VSSSEG7E256V, match_opcode, INSN_DREF },
  6395. +{"vssseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E256V, MASK_VSSSEG7E256V, match_vd_neq_vm, INSN_DREF },
  6396. {"vlsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E256V, MASK_VLSSEG8E256V, match_vd_neq_vm, INSN_DREF },
  6397. -{"vssseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E256V, MASK_VSSSEG8E256V, match_opcode, INSN_DREF },
  6398. +{"vssseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E256V, MASK_VSSSEG8E256V, match_vd_neq_vm, INSN_DREF },
  6399. {"vlsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E512V, MASK_VLSSEG2E512V, match_vd_neq_vm, INSN_DREF },
  6400. -{"vssseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E512V, MASK_VSSSEG2E512V, match_opcode, INSN_DREF },
  6401. +{"vssseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E512V, MASK_VSSSEG2E512V, match_vd_neq_vm, INSN_DREF },
  6402. {"vlsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E512V, MASK_VLSSEG3E512V, match_vd_neq_vm, INSN_DREF },
  6403. -{"vssseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E512V, MASK_VSSSEG3E512V, match_opcode, INSN_DREF },
  6404. +{"vssseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E512V, MASK_VSSSEG3E512V, match_vd_neq_vm, INSN_DREF },
  6405. {"vlsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E512V, MASK_VLSSEG4E512V, match_vd_neq_vm, INSN_DREF },
  6406. -{"vssseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E512V, MASK_VSSSEG4E512V, match_opcode, INSN_DREF },
  6407. +{"vssseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E512V, MASK_VSSSEG4E512V, match_vd_neq_vm, INSN_DREF },
  6408. {"vlsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E512V, MASK_VLSSEG5E512V, match_vd_neq_vm, INSN_DREF },
  6409. -{"vssseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E512V, MASK_VSSSEG5E512V, match_opcode, INSN_DREF },
  6410. +{"vssseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E512V, MASK_VSSSEG5E512V, match_vd_neq_vm, INSN_DREF },
  6411. {"vlsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E512V, MASK_VLSSEG6E512V, match_vd_neq_vm, INSN_DREF },
  6412. -{"vssseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E512V, MASK_VSSSEG6E512V, match_opcode, INSN_DREF },
  6413. +{"vssseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E512V, MASK_VSSSEG6E512V, match_vd_neq_vm, INSN_DREF },
  6414. {"vlsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E512V, MASK_VLSSEG7E512V, match_vd_neq_vm, INSN_DREF },
  6415. -{"vssseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E512V, MASK_VSSSEG7E512V, match_opcode, INSN_DREF },
  6416. +{"vssseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E512V, MASK_VSSSEG7E512V, match_vd_neq_vm, INSN_DREF },
  6417. {"vlsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E512V, MASK_VLSSEG8E512V, match_vd_neq_vm, INSN_DREF },
  6418. -{"vssseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E512V, MASK_VSSSEG8E512V, match_opcode, INSN_DREF },
  6419. +{"vssseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E512V, MASK_VSSSEG8E512V, match_vd_neq_vm, INSN_DREF },
  6420. {"vlsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E1024V, MASK_VLSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
  6421. -{"vssseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E1024V, MASK_VSSSEG2E1024V, match_opcode, INSN_DREF },
  6422. +{"vssseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E1024V, MASK_VSSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
  6423. {"vlsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E1024V, MASK_VLSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
  6424. -{"vssseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E1024V, MASK_VSSSEG3E1024V, match_opcode, INSN_DREF },
  6425. +{"vssseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E1024V, MASK_VSSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
  6426. {"vlsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E1024V, MASK_VLSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
  6427. -{"vssseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E1024V, MASK_VSSSEG4E1024V, match_opcode, INSN_DREF },
  6428. +{"vssseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E1024V, MASK_VSSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
  6429. {"vlsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E1024V, MASK_VLSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
  6430. -{"vssseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E1024V, MASK_VSSSEG5E1024V, match_opcode, INSN_DREF },
  6431. +{"vssseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E1024V, MASK_VSSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
  6432. {"vlsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E1024V, MASK_VLSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
  6433. -{"vssseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E1024V, MASK_VSSSEG6E1024V, match_opcode, INSN_DREF },
  6434. +{"vssseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E1024V, MASK_VSSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
  6435. {"vlsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E1024V, MASK_VLSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
  6436. -{"vssseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E1024V, MASK_VSSSEG7E1024V, match_opcode, INSN_DREF },
  6437. +{"vssseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E1024V, MASK_VSSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
  6438. {"vlsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E1024V, MASK_VLSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
  6439. -{"vssseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_opcode, INSN_DREF },
  6440. +{"vssseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
  6441. {"vlxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI8V, MASK_VLXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  6442. {"vsxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI8V, MASK_VSXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
  6443. @@ -1595,53 +1588,53 @@ const struct riscv_opcode riscv_opcodes[] =
  6444. {"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_opcode, INSN_DREF },
  6445. {"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_opcode, INSN_DREF },
  6446. -{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_opcode, INSN_DREF},
  6447. -{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_opcode, INSN_DREF},
  6448. -{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_opcode, INSN_DREF},
  6449. -{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_opcode, INSN_DREF},
  6450. -{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_opcode, INSN_DREF},
  6451. -{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_opcode, INSN_DREF},
  6452. -{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_opcode, INSN_DREF},
  6453. -{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_opcode, INSN_DREF},
  6454. -{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_opcode, INSN_DREF},
  6455. -
  6456. -{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_opcode, INSN_DREF},
  6457. -{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_opcode, INSN_DREF},
  6458. -{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_opcode, INSN_DREF},
  6459. -{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_opcode, INSN_DREF},
  6460. -{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_opcode, INSN_DREF},
  6461. -{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_opcode, INSN_DREF},
  6462. -{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_opcode, INSN_DREF},
  6463. -{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_opcode, INSN_DREF},
  6464. -{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_opcode, INSN_DREF},
  6465. -
  6466. -{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_opcode, INSN_DREF},
  6467. -{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_opcode, INSN_DREF},
  6468. -{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_opcode, INSN_DREF},
  6469. -{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_opcode, INSN_DREF},
  6470. -{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_opcode, INSN_DREF},
  6471. -{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_opcode, INSN_DREF},
  6472. -{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_opcode, INSN_DREF},
  6473. -{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_opcode, INSN_DREF},
  6474. -{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_opcode, INSN_DREF},
  6475. -
  6476. -{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_opcode, INSN_DREF},
  6477. -{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_opcode, INSN_DREF},
  6478. -{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_opcode, INSN_DREF},
  6479. -{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_opcode, INSN_DREF},
  6480. -{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_opcode, INSN_DREF},
  6481. -{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_opcode, INSN_DREF},
  6482. -{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_opcode, INSN_DREF},
  6483. -{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_opcode, INSN_DREF},
  6484. -{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_opcode, INSN_DREF},
  6485. -
  6486. -{"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
  6487. -{"vadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
  6488. -{"vadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
  6489. -{"vsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
  6490. -{"vsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
  6491. -{"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
  6492. -{"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
  6493. +{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
  6494. +{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
  6495. +{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
  6496. +{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
  6497. +{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
  6498. +{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
  6499. +{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
  6500. +{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
  6501. +{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
  6502. +
  6503. +{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
  6504. +{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
  6505. +{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
  6506. +{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
  6507. +{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
  6508. +{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
  6509. +{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
  6510. +{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
  6511. +{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
  6512. +
  6513. +{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
  6514. +{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
  6515. +{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
  6516. +{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
  6517. +{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
  6518. +{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
  6519. +{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
  6520. +{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
  6521. +{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
  6522. +
  6523. +{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
  6524. +{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
  6525. +{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
  6526. +{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
  6527. +{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
  6528. +{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
  6529. +{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
  6530. +{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
  6531. +{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
  6532. +
  6533. +{"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
  6534. +{"vadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_vd_neq_vm, 0 },
  6535. +{"vadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_vd_neq_vm, 0 },
  6536. +{"vsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_vd_neq_vm, 0 },
  6537. +{"vsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_vd_neq_vm, 0 },
  6538. +{"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
  6539. +{"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
  6540. {"vwcvt.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
  6541. {"vwcvtu.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
  6542. @@ -1663,59 +1656,59 @@ const struct riscv_opcode riscv_opcodes[] =
  6543. {"vwsub.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
  6544. {"vwsub.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
  6545. -{"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_opcode, 0 },
  6546. -{"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_opcode, 0 },
  6547. -{"vzext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_opcode, 0 },
  6548. -{"vsext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_opcode, 0 },
  6549. -{"vzext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_opcode, 0 },
  6550. -{"vsext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_opcode, 0 },
  6551. +{"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
  6552. +{"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
  6553. +{"vzext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_vd_neq_vm, 0 },
  6554. +{"vsext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_vd_neq_vm, 0 },
  6555. +{"vzext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_vd_neq_vm, 0 },
  6556. +{"vsext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_vd_neq_vm, 0 },
  6557. -{"vadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_opcode, 0 },
  6558. -{"vadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_opcode, 0 },
  6559. -{"vadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_opcode, 0 },
  6560. +{"vadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_vd_neq_vm, 0 },
  6561. +{"vadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_vd_neq_vm, 0 },
  6562. +{"vadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_vd_neq_vm, 0 },
  6563. {"vmadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
  6564. {"vmadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
  6565. {"vmadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
  6566. {"vmadc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
  6567. {"vmadc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
  6568. {"vmadc.vi", 0, INSN_CLASS_V, "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
  6569. -{"vsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_opcode, 0 },
  6570. -{"vsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_opcode, 0 },
  6571. +{"vsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_vd_neq_vm, 0 },
  6572. +{"vsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_vd_neq_vm, 0 },
  6573. {"vmsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
  6574. {"vmsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
  6575. {"vmsbc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
  6576. {"vmsbc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
  6577. -{"vnot.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
  6578. -
  6579. -{"vand.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
  6580. -{"vand.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
  6581. -{"vand.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
  6582. -{"vor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
  6583. -{"vor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
  6584. -{"vor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
  6585. -{"vxor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
  6586. -{"vxor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
  6587. -{"vxor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
  6588. -
  6589. -{"vsll.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
  6590. -{"vsll.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
  6591. -{"vsll.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
  6592. -{"vsrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
  6593. -{"vsrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
  6594. -{"vsrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
  6595. -{"vsra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
  6596. -{"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
  6597. -{"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
  6598. -
  6599. -{"vncvt.x.x.v",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2, INSN_ALIAS },
  6600. -
  6601. -{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2, 0 },
  6602. -{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2, 0 },
  6603. -{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2, 0 },
  6604. -{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2, 0 },
  6605. -{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2, 0 },
  6606. -{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2, 0 },
  6607. +{"vnot.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_vd_neq_vm, INSN_ALIAS },
  6608. +
  6609. +{"vand.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_vd_neq_vm, 0 },
  6610. +{"vand.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_vd_neq_vm, 0 },
  6611. +{"vand.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_vd_neq_vm, 0 },
  6612. +{"vor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_vd_neq_vm, 0 },
  6613. +{"vor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_vd_neq_vm, 0 },
  6614. +{"vor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_vd_neq_vm, 0 },
  6615. +{"vxor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_vd_neq_vm, 0 },
  6616. +{"vxor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_vd_neq_vm, 0 },
  6617. +{"vxor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_vd_neq_vm, 0 },
  6618. +
  6619. +{"vsll.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_vd_neq_vm, 0 },
  6620. +{"vsll.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_vd_neq_vm, 0 },
  6621. +{"vsll.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_vd_neq_vm, 0 },
  6622. +{"vsrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_vd_neq_vm, 0 },
  6623. +{"vsrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_vd_neq_vm, 0 },
  6624. +{"vsrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_vd_neq_vm, 0 },
  6625. +{"vsra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_vd_neq_vm, 0 },
  6626. +{"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
  6627. +{"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
  6628. +
  6629. +{"vncvt.x.x.v",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
  6630. +
  6631. +{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6632. +{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6633. +{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6634. +{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6635. +{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6636. +{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6637. {"vmseq.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
  6638. {"vmseq.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
  6639. @@ -1755,23 +1748,23 @@ const struct riscv_opcode riscv_opcodes[] =
  6640. {"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
  6641. {"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
  6642. -{"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
  6643. -{"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
  6644. -{"vmin.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
  6645. -{"vmin.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
  6646. -{"vmaxu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
  6647. -{"vmaxu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
  6648. -{"vmax.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
  6649. -{"vmax.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
  6650. -
  6651. -{"vmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
  6652. -{"vmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
  6653. -{"vmulh.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
  6654. -{"vmulh.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
  6655. -{"vmulhu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
  6656. -{"vmulhu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
  6657. -{"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
  6658. -{"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
  6659. +{"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_vd_neq_vm, 0},
  6660. +{"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_vd_neq_vm, 0},
  6661. +{"vmin.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_vd_neq_vm, 0},
  6662. +{"vmin.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_vd_neq_vm, 0},
  6663. +{"vmaxu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_vd_neq_vm, 0},
  6664. +{"vmaxu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_vd_neq_vm, 0},
  6665. +{"vmax.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_vd_neq_vm, 0},
  6666. +{"vmax.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_vd_neq_vm, 0},
  6667. +
  6668. +{"vmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_vd_neq_vm, 0 },
  6669. +{"vmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_vd_neq_vm, 0 },
  6670. +{"vmulh.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_vd_neq_vm, 0 },
  6671. +{"vmulh.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_vd_neq_vm, 0 },
  6672. +{"vmulhu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_vd_neq_vm, 0 },
  6673. +{"vmulhu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_vd_neq_vm, 0 },
  6674. +{"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
  6675. +{"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
  6676. {"vwmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
  6677. {"vwmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
  6678. @@ -1780,14 +1773,14 @@ const struct riscv_opcode riscv_opcodes[] =
  6679. {"vwmulsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
  6680. {"vwmulsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
  6681. -{"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
  6682. -{"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
  6683. -{"vnmsac.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
  6684. -{"vnmsac.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
  6685. -{"vmadd.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
  6686. -{"vmadd.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
  6687. -{"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
  6688. -{"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
  6689. +{"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
  6690. +{"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
  6691. +{"vnmsac.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_vd_neq_vm, 0},
  6692. +{"vnmsac.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_vd_neq_vm, 0},
  6693. +{"vmadd.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_vd_neq_vm, 0},
  6694. +{"vmadd.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_vd_neq_vm, 0},
  6695. +{"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
  6696. +{"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
  6697. {"vwmaccu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  6698. {"vwmaccu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
  6699. @@ -1805,14 +1798,14 @@ const struct riscv_opcode riscv_opcodes[] =
  6700. {"vqmaccsu.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_quad_vd_neq_vs2_neq_vm, 0},
  6701. {"vqmaccus.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_quad_vd_neq_vs2_neq_vm, 0},
  6702. -{"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
  6703. -{"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
  6704. -{"vdiv.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
  6705. -{"vdiv.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
  6706. -{"vremu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
  6707. -{"vremu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
  6708. -{"vrem.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
  6709. -{"vrem.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
  6710. +{"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
  6711. +{"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
  6712. +{"vdiv.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_vd_neq_vm, 0 },
  6713. +{"vdiv.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_vd_neq_vm, 0 },
  6714. +{"vremu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_vd_neq_vm, 0 },
  6715. +{"vremu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_vd_neq_vm, 0 },
  6716. +{"vrem.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_vd_neq_vm, 0 },
  6717. +{"vrem.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_vd_neq_vm, 0 },
  6718. {"vmerge.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
  6719. {"vmerge.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
  6720. @@ -1822,48 +1815,48 @@ const struct riscv_opcode riscv_opcodes[] =
  6721. {"vmv.v.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
  6722. {"vmv.v.i", 0, INSN_CLASS_V, "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
  6723. -{"vsaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
  6724. -{"vsaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
  6725. -{"vsaddu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
  6726. -{"vsadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
  6727. -{"vsadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
  6728. -{"vsadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
  6729. -{"vssubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
  6730. -{"vssubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
  6731. -{"vssub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
  6732. -{"vssub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
  6733. -
  6734. -{"vaaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_opcode, 0 },
  6735. -{"vaaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_opcode, 0 },
  6736. -{"vaadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_opcode, 0 },
  6737. -{"vaadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_opcode, 0 },
  6738. -{"vasubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_opcode, 0 },
  6739. -{"vasubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_opcode, 0 },
  6740. -{"vasub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_opcode, 0 },
  6741. -{"vasub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_opcode, 0 },
  6742. -
  6743. -{"vsmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
  6744. -{"vsmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
  6745. -
  6746. -{"vssrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
  6747. -{"vssrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
  6748. -{"vssrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
  6749. -{"vssra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
  6750. -{"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
  6751. -{"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
  6752. -
  6753. -{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2, 0 },
  6754. -{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2, 0 },
  6755. -{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2, 0 },
  6756. -{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2, 0 },
  6757. -{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2, 0 },
  6758. -{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2, 0 },
  6759. -
  6760. -{"vfadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
  6761. -{"vfadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
  6762. -{"vfsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
  6763. -{"vfsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
  6764. -{"vfrsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
  6765. +{"vsaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_vd_neq_vm, 0 },
  6766. +{"vsaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_vd_neq_vm, 0 },
  6767. +{"vsaddu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_vd_neq_vm, 0 },
  6768. +{"vsadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_vd_neq_vm, 0 },
  6769. +{"vsadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_vd_neq_vm, 0 },
  6770. +{"vsadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_vd_neq_vm, 0 },
  6771. +{"vssubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_vd_neq_vm, 0 },
  6772. +{"vssubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_vd_neq_vm, 0 },
  6773. +{"vssub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_vd_neq_vm, 0 },
  6774. +{"vssub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_vd_neq_vm, 0 },
  6775. +
  6776. +{"vaaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_vd_neq_vm, 0 },
  6777. +{"vaaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_vd_neq_vm, 0 },
  6778. +{"vaadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_vd_neq_vm, 0 },
  6779. +{"vaadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_vd_neq_vm, 0 },
  6780. +{"vasubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_vd_neq_vm, 0 },
  6781. +{"vasubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_vd_neq_vm, 0 },
  6782. +{"vasub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_vd_neq_vm, 0 },
  6783. +{"vasub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_vd_neq_vm, 0 },
  6784. +
  6785. +{"vsmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_vd_neq_vm, 0 },
  6786. +{"vsmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_vd_neq_vm, 0 },
  6787. +
  6788. +{"vssrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_vd_neq_vm, 0 },
  6789. +{"vssrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_vd_neq_vm, 0 },
  6790. +{"vssrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_vd_neq_vm, 0 },
  6791. +{"vssra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_vd_neq_vm, 0 },
  6792. +{"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
  6793. +{"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
  6794. +
  6795. +{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6796. +{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6797. +{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6798. +{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6799. +{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6800. +{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
  6801. +
  6802. +{"vfadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
  6803. +{"vfadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
  6804. +{"vfsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_vd_neq_vm, 0},
  6805. +{"vfsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
  6806. +{"vfrsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
  6807. {"vfwadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  6808. {"vfwadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
  6809. @@ -1874,31 +1867,31 @@ const struct riscv_opcode riscv_opcodes[] =
  6810. {"vfwsub.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
  6811. {"vfwsub.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
  6812. -{"vfmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
  6813. -{"vfmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
  6814. -{"vfdiv.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
  6815. -{"vfdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
  6816. -{"vfrdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
  6817. +{"vfmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
  6818. +{"vfmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
  6819. +{"vfdiv.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_vd_neq_vm, 0},
  6820. +{"vfdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
  6821. +{"vfrdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
  6822. {"vfwmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  6823. {"vfwmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
  6824. -{"vfmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
  6825. -{"vfmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
  6826. -{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
  6827. -{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
  6828. -{"vfmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
  6829. -{"vfmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
  6830. -{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
  6831. -{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
  6832. -{"vfmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
  6833. -{"vfmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
  6834. -{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
  6835. -{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
  6836. -{"vfmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
  6837. -{"vfmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
  6838. -{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
  6839. -{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
  6840. +{"vfmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
  6841. +{"vfmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
  6842. +{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_vd_neq_vm, 0},
  6843. +{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_vd_neq_vm, 0},
  6844. +{"vfmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_vd_neq_vm, 0},
  6845. +{"vfmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_vd_neq_vm, 0},
  6846. +{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_vd_neq_vm, 0},
  6847. +{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_vd_neq_vm, 0},
  6848. +{"vfmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_vd_neq_vm, 0},
  6849. +{"vfmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_vd_neq_vm, 0},
  6850. +{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_vd_neq_vm, 0},
  6851. +{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_vd_neq_vm, 0},
  6852. +{"vfmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_vd_neq_vm, 0},
  6853. +{"vfmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_vd_neq_vm, 0},
  6854. +{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
  6855. +{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
  6856. {"vfwmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  6857. {"vfwmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
  6858. @@ -1909,22 +1902,22 @@ const struct riscv_opcode riscv_opcodes[] =
  6859. {"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
  6860. {"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
  6861. -{"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0},
  6862. -{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRTE7V, MASK_VFRSQRTE7V, match_opcode, 0},
  6863. -{"vfrece7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRECE7V, MASK_VFRECE7V, match_opcode, 0},
  6864. -{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
  6865. +{"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
  6866. +{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRTE7V, MASK_VFRSQRTE7V, match_vd_neq_vm, 0},
  6867. +{"vfrece7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRECE7V, MASK_VFRECE7V, match_vd_neq_vm, 0},
  6868. +{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_vd_neq_vm, 0},
  6869. -{"vfmin.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
  6870. -{"vfmin.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
  6871. -{"vfmax.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
  6872. -{"vfmax.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
  6873. +{"vfmin.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_vd_neq_vm, 0},
  6874. +{"vfmin.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_vd_neq_vm, 0},
  6875. +{"vfmax.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
  6876. +{"vfmax.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0},
  6877. -{"vfsgnj.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
  6878. -{"vfsgnj.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
  6879. -{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
  6880. -{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
  6881. -{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
  6882. -{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
  6883. +{"vfsgnj.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0},
  6884. +{"vfsgnj.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0},
  6885. +{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vd_neq_vm, 0},
  6886. +{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_vd_neq_vm, 0},
  6887. +{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vd_neq_vm, 0},
  6888. +{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_vd_neq_vm, 0},
  6889. {"vmfeq.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
  6890. {"vmfeq.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
  6891. @@ -1944,12 +1937,12 @@ const struct riscv_opcode riscv_opcodes[] =
  6892. {"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
  6893. {"vfmv.v.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
  6894. -{"vfcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_opcode, 0},
  6895. -{"vfcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_opcode, 0},
  6896. -{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_opcode, 0},
  6897. -{"vfcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_opcode, 0},
  6898. -{"vfcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_opcode, 0},
  6899. -{"vfcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_opcode, 0},
  6900. +{"vfcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_vd_neq_vm, 0},
  6901. +{"vfcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_vd_neq_vm, 0},
  6902. +{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_vd_neq_vm, 0},
  6903. +{"vfcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_vd_neq_vm, 0},
  6904. +{"vfcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
  6905. +{"vfcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
  6906. {"vfwcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
  6907. {"vfwcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
  6908. @@ -1959,14 +1952,14 @@ const struct riscv_opcode riscv_opcodes[] =
  6909. {"vfwcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
  6910. {"vfwcvt.f.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
  6911. -{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2, 0},
  6912. -{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2, 0},
  6913. -{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2, 0},
  6914. -{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2, 0},
  6915. -{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2, 0},
  6916. -{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2, 0},
  6917. -{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2, 0},
  6918. -{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2, 0},
  6919. +{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
  6920. +{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
  6921. +{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
  6922. +{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
  6923. +{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
  6924. +{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
  6925. +{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
  6926. +{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
  6927. {"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
  6928. {"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
  6929. @@ -2005,11 +1998,11 @@ const struct riscv_opcode riscv_opcodes[] =
  6930. {"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
  6931. {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
  6932. -{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_opcode, 0},
  6933. -{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_opcode, 0},
  6934. -{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_opcode, 0},
  6935. +{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vm, 0},
  6936. +{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vm, 0},
  6937. +{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vm, 0},
  6938. {"viota.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
  6939. -{"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_opcode, 0},
  6940. +{"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
  6941. {"vmv.x.s", 0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
  6942. {"vmv.s.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
  6943. @@ -2017,15 +2010,15 @@ const struct riscv_opcode riscv_opcodes[] =
  6944. {"vfmv.f.s", 0, INSN_CLASS_V_AND_F, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
  6945. {"vfmv.s.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
  6946. -{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2, 0},
  6947. -{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2, 0},
  6948. -{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
  6949. -{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
  6950. +{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2_neq_vm, 0},
  6951. +{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2_neq_vm, 0},
  6952. +{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_vd_neq_vm, 0},
  6953. +{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_vd_neq_vm, 0},
  6954. -{"vslide1up.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2, 0},
  6955. -{"vslide1down.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
  6956. -{"vfslide1up.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2, 0},
  6957. -{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_opcode, 0},
  6958. +{"vslide1up.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2_neq_vm, 0},
  6959. +{"vslide1down.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_vd_neq_vm, 0},
  6960. +{"vfslide1up.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2_neq_vm, 0},
  6961. +{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_vd_neq_vm, 0},
  6962. {"vrgather.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
  6963. {"vrgather.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
  6964. --
  6965. 2.33.0