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|
- From 74aac3ffbc31ab5640f1cf2ed0bacaeef35b4e68 Mon Sep 17 00:00:00 2001
- From: Nelson Chu <nelson.chu@sifive.com>
- Date: Thu, 13 Aug 2020 15:32:14 +0800
- Subject: [PATCH 24/48] RISC-V: Update the vector mask constraints.
- For now, the destination vector register group for most of masked vector
- instruction can not overlap the source mask register. Unless,
- 1. Comparison instruction.
- 2. Reduction instruction.
- V0 is a special case. It is a carry-in register for v[m]adc and v[m]sbc,
- and is used to choose vs1/rs1/frs1/imm or vs2 for v[f]merge. For vadc and
- vsbc, vd can not overlap the carry-in V0. I use the match_vd_neq_vm to
- check the constraints since V0 and VM have the same encoding.
- I regard vdot[u].vv as a reduction instruction, too. Therefore, I don't
- check the VM constraints for it.
- Besides, I also rewrite the vector failed testcases since their names are
- hard to understand and maintain.
- opcodes/
- * riscv-opc.c (match_narrow_vd_neq_vs2): Add the vm checking.
- Renamed to match_narrow_vd_neq_vs2_neq_vm.
- (match_vd_neq_vs2): Removed. Replace it with match_vd_neq_vs2_vm.
- (riscv_opcodes): Updated.
- gas/
- * config/tc-riscv.c (riscv_ip): Update the comment for V0.
- * testsuite/gas/riscv/vector-insns-fail-zvamo.d: New failed testcase
- for vector AMO operations.
- * testsuite/gas/riscv/vector-insns-fail-zvamo.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-zvamo.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-zvqmac.d: New failed testcase
- for vector quad-widening instructions.
- * testsuite/gas/riscv/vector-insns-fail-zvqmac.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-zvqmac.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-load-store.d: New failed testcase
- for vector load and store instructions.
- * testsuite/gas/riscv/vector-insns-fail-load-store.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-load-store.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-int.d: New failed testcase
- for vector integer arithmetic instructions.
- * testsuite/gas/riscv/vector-insns-fail-arith-int.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-int.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-fixp.d: New failed testcase
- for vector fixed-point arithmetic instructions.
- * testsuite/gas/riscv/vector-insns-fail-arith-fixp.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-fixp.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-floatp.d: New failed testcase
- for vector floating-point arithmetic instructions.
- * testsuite/gas/riscv/vector-insns-fail-arith-floatp.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-floatp.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-widen.d: New failed testcase
- for vector widening instructions.
- * testsuite/gas/riscv/vector-insns-fail-arith-widen.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-widen.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-narrow.d: New failed testcase
- for vector narrowing instructions.
- * testsuite/gas/riscv/vector-insns-fail-arith-narrow.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-arith-narrow.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-mask.d: New failed testcase
- for vector mask instructions.
- * testsuite/gas/riscv/vector-insns-fail-mask.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-mask.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-permutation.d: New failed testcase
- for vector permutation instructions.
- * testsuite/gas/riscv/vector-insns-fail-permutation.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-permutation.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-01.d: Removed.
- * testsuite/gas/riscv/vector-insns-fail-01.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-01.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-02.d: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-02.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-02.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-03.d: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-03.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-03.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-04.d: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-04.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-04.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-05.d: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-05.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-05.s: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-06.d: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-06.l: Likewise.
- * testsuite/gas/riscv/vector-insns-fail-06.s: Likewise.
- ---
- gas/config/tc-riscv.c | 6 +-
- .../gas/riscv/vector-insns-fail-01.d | 3 -
- .../gas/riscv/vector-insns-fail-01.l | 393 -------
- .../gas/riscv/vector-insns-fail-01.s | 1037 -----------------
- .../gas/riscv/vector-insns-fail-02.d | 3 -
- .../gas/riscv/vector-insns-fail-02.l | 121 --
- .../gas/riscv/vector-insns-fail-02.s | 162 ---
- .../gas/riscv/vector-insns-fail-03.d | 3 -
- .../gas/riscv/vector-insns-fail-03.l | 125 --
- .../gas/riscv/vector-insns-fail-03.s | 187 ---
- .../gas/riscv/vector-insns-fail-04.d | 3 -
- .../gas/riscv/vector-insns-fail-04.l | 49 -
- .../gas/riscv/vector-insns-fail-04.s | 85 --
- .../gas/riscv/vector-insns-fail-05.d | 3 -
- .../gas/riscv/vector-insns-fail-05.s | 139 ---
- .../gas/riscv/vector-insns-fail-06.d | 3 -
- .../gas/riscv/vector-insns-fail-06.l | 25 -
- .../gas/riscv/vector-insns-fail-06.s | 73 --
- .../gas/riscv/vector-insns-fail-arith-fixp.d | 3 +
- .../gas/riscv/vector-insns-fail-arith-fixp.l | 27 +
- .../gas/riscv/vector-insns-fail-arith-fixp.s | 81 ++
- .../riscv/vector-insns-fail-arith-floatp.d | 3 +
- .../riscv/vector-insns-fail-arith-floatp.l | 47 +
- .../riscv/vector-insns-fail-arith-floatp.s | 152 +++
- .../gas/riscv/vector-insns-fail-arith-int.d | 3 +
- .../gas/riscv/vector-insns-fail-arith-int.l | 70 ++
- .../gas/riscv/vector-insns-fail-arith-int.s | 210 ++++
- .../riscv/vector-insns-fail-arith-narrow.d | 3 +
- ...-05.l => vector-insns-fail-arith-narrow.l} | 45 +-
- .../riscv/vector-insns-fail-arith-narrow.s | 100 ++
- .../gas/riscv/vector-insns-fail-arith-widen.d | 3 +
- .../gas/riscv/vector-insns-fail-arith-widen.l | 253 ++++
- .../gas/riscv/vector-insns-fail-arith-widen.s | 297 +++++
- .../gas/riscv/vector-insns-fail-load-store.d | 3 +
- .../gas/riscv/vector-insns-fail-load-store.l | 557 +++++++++
- .../gas/riscv/vector-insns-fail-load-store.s | 610 ++++++++++
- .../gas/riscv/vector-insns-fail-mask.d | 3 +
- .../gas/riscv/vector-insns-fail-mask.l | 7 +
- .../gas/riscv/vector-insns-fail-mask.s | 20 +
- .../gas/riscv/vector-insns-fail-permutation.d | 3 +
- .../gas/riscv/vector-insns-fail-permutation.l | 31 +
- .../gas/riscv/vector-insns-fail-permutation.s | 56 +
- .../gas/riscv/vector-insns-fail-zvamo.d | 3 +
- .../gas/riscv/vector-insns-fail-zvamo.l | 109 ++
- .../gas/riscv/vector-insns-fail-zvamo.s | 217 ++++
- .../gas/riscv/vector-insns-fail-zvqmac.d | 3 +
- .../gas/riscv/vector-insns-fail-zvqmac.l | 35 +
- .../gas/riscv/vector-insns-fail-zvqmac.s | 39 +
- opcodes/riscv-opc.c | 817 +++++++------
- 49 files changed, 3391 insertions(+), 2839 deletions(-)
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.d
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.l
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-01.s
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.d
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.l
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-02.s
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.d
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.l
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-03.s
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.d
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.l
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-04.s
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.d
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-05.s
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.d
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.l
- delete mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-06.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
- rename gas/testsuite/gas/riscv/{vector-insns-fail-05.l => vector-insns-fail-arith-narrow.l} (59%)
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s
- diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
- index 2dc55ca5aa..e998890b92 100644
- --- a/gas/config/tc-riscv.c
- +++ b/gas/config/tc-riscv.c
- @@ -2826,7 +2826,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
- INSERT_OPERAND (VS2, *ip, regno);
- continue;
-
- - case '0': /* required vector mask register without .t */
- + /* The `V0` is carry-in register for v[m]adc and v[m]sbc,
- + and is used to choose vs1/rs1/frs1/imm or vs2 for
- + v[f]merge. It use the same encoding as the vector mask
- + register. */
- + case '0':
- if (reg_lookup (&s, RCLASS_VECR, ®no) && regno == 0)
- continue;
- break;
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.d b/gas/testsuite/gas/riscv/vector-insns-fail-01.d
- deleted file mode 100644
- index ade7888937..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-01.d
- +++ /dev/null
- @@ -1,3 +0,0 @@
- -#as: -march=rv32ifv -mcheck-constraints
- -#source: vector-insns-fail-01.s
- -#error_output: vector-insns-fail-01.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.l b/gas/testsuite/gas/riscv/vector-insns-fail-01.l
- deleted file mode 100644
- index 61687938c9..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-01.l
- +++ /dev/null
- @@ -1,393 +0,0 @@
- -.*: Assembler messages:
- -.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
- -.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
- -.*Error: illegal operands `vlxseg2ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg2ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg3ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg3ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg4ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg4ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg5ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg5ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg6ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg6ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg7ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg7ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg8ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg8ei8.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg2ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg2ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg3ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg3ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg4ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg4ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg5ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg5ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg6ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg6ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg7ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg7ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg8ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg8ei16.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg2ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg2ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg3ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg3ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg4ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg4ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg5ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg5ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg6ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg6ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg7ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg7ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg8ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg8ei32.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg2ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg2ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg3ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg3ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg4ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg4ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg5ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg5ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg6ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg6ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg7ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg7ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg8ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg8ei64.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg2ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg2ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg3ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg3ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg4ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg4ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg5ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg5ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg6ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg6ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg7ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg7ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg8ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg8ei128.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg2ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg2ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg3ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg3ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg4ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg4ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg5ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg5ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg6ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg6ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg7ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg7ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg8ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg8ei256.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg2ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg2ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg3ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg3ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg4ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg4ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg5ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg5ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg6ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg6ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg7ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg7ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg8ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg8ei512.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg2ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg2ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg3ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg3ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg4ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg4ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg5ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg5ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg6ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg6ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg7ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg7ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vlxseg8ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v2,v0.t'
- -.*Error: illegal operands `vsxseg8ei1024.v v2,\(a0\),v2'
- -.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v2,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-01.s b/gas/testsuite/gas/riscv/vector-insns-fail-01.s
- deleted file mode 100644
- index 4c1a913f2d..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-01.s
- +++ /dev/null
- @@ -1,1037 +0,0 @@
- -# Vector Unit-Stride Segment Loads and Stores
- -
- - vlseg2e8.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e8.v v4, (a0), v0.t # OK
- - vsseg2e8.v v0, (a0), v0.t # OK
- - vsseg2e8.v v4, (a0), v0.t # OK
- - vlseg2e8ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e8ff.v v4, (a0), v0.t # OK
- - vlseg3e8.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e8.v v4, (a0), v0.t # OK
- - vsseg3e8.v v0, (a0), v0.t # OK
- - vsseg3e8.v v4, (a0), v0.t # OK
- - vlseg3e8ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e8ff.v v4, (a0), v0.t # OK
- - vlseg4e8.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e8.v v4, (a0), v0.t # OK
- - vsseg4e8.v v0, (a0), v0.t # OK
- - vsseg4e8.v v4, (a0), v0.t # OK
- - vlseg4e8ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e8ff.v v4, (a0), v0.t # OK
- - vlseg5e8.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e8.v v4, (a0), v0.t # OK
- - vsseg5e8.v v0, (a0), v0.t # OK
- - vsseg5e8.v v4, (a0), v0.t # OK
- - vlseg5e8ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e8ff.v v4, (a0), v0.t # OK
- - vlseg6e8.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e8.v v4, (a0), v0.t # OK
- - vsseg6e8.v v0, (a0), v0.t # OK
- - vsseg6e8.v v4, (a0), v0.t # OK
- - vlseg6e8ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e8ff.v v4, (a0), v0.t # OK
- - vlseg7e8.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e8.v v4, (a0), v0.t # OK
- - vsseg7e8.v v0, (a0), v0.t # OK
- - vsseg7e8.v v4, (a0), v0.t # OK
- - vlseg7e8ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e8ff.v v4, (a0), v0.t # OK
- - vlseg8e8.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e8.v v4, (a0), v0.t # OK
- - vsseg8e8.v v0, (a0), v0.t # OK
- - vsseg8e8.v v4, (a0), v0.t # OK
- - vlseg8e8ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e8ff.v v4, (a0), v0.t # OK
- -
- - vlseg2e16.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e16.v v4, (a0), v0.t # OK
- - vsseg2e16.v v0, (a0), v0.t # OK
- - vsseg2e16.v v4, (a0), v0.t # OK
- - vlseg2e16ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e16ff.v v4, (a0), v0.t # OK
- - vlseg3e16.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e16.v v4, (a0), v0.t # OK
- - vsseg3e16.v v0, (a0), v0.t # OK
- - vsseg3e16.v v4, (a0), v0.t # OK
- - vlseg3e16ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e16ff.v v4, (a0), v0.t # OK
- - vlseg4e16.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e16.v v4, (a0), v0.t # OK
- - vsseg4e16.v v0, (a0), v0.t # OK
- - vsseg4e16.v v4, (a0), v0.t # OK
- - vlseg4e16ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e16ff.v v4, (a0), v0.t # OK
- - vlseg5e16.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e16.v v4, (a0), v0.t # OK
- - vsseg5e16.v v0, (a0), v0.t # OK
- - vsseg5e16.v v4, (a0), v0.t # OK
- - vlseg5e16ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e16ff.v v4, (a0), v0.t # OK
- - vlseg6e16.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e16.v v4, (a0), v0.t # OK
- - vsseg6e16.v v0, (a0), v0.t # OK
- - vsseg6e16.v v4, (a0), v0.t # OK
- - vlseg6e16ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e16ff.v v4, (a0), v0.t # OK
- - vlseg7e16.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e16.v v4, (a0), v0.t # OK
- - vsseg7e16.v v0, (a0), v0.t # OK
- - vsseg7e16.v v4, (a0), v0.t # OK
- - vlseg7e16ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e16ff.v v4, (a0), v0.t # OK
- - vlseg8e16.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e16.v v4, (a0), v0.t # OK
- - vsseg8e16.v v0, (a0), v0.t # OK
- - vsseg8e16.v v4, (a0), v0.t # OK
- - vlseg8e16ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e16ff.v v4, (a0), v0.t # OK
- -
- - vlseg2e32.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e32.v v4, (a0), v0.t # OK
- - vsseg2e32.v v0, (a0), v0.t # OK
- - vsseg2e32.v v4, (a0), v0.t # OK
- - vlseg2e32ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e32ff.v v4, (a0), v0.t # OK
- - vlseg3e32.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e32.v v4, (a0), v0.t # OK
- - vsseg3e32.v v0, (a0), v0.t # OK
- - vsseg3e32.v v4, (a0), v0.t # OK
- - vlseg3e32ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e32ff.v v4, (a0), v0.t # OK
- - vlseg4e32.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e32.v v4, (a0), v0.t # OK
- - vsseg4e32.v v0, (a0), v0.t # OK
- - vsseg4e32.v v4, (a0), v0.t # OK
- - vlseg4e32ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e32ff.v v4, (a0), v0.t # OK
- - vlseg5e32.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e32.v v4, (a0), v0.t # OK
- - vsseg5e32.v v0, (a0), v0.t # OK
- - vsseg5e32.v v4, (a0), v0.t # OK
- - vlseg5e32ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e32ff.v v4, (a0), v0.t # OK
- - vlseg6e32.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e32.v v4, (a0), v0.t # OK
- - vsseg6e32.v v0, (a0), v0.t # OK
- - vsseg6e32.v v4, (a0), v0.t # OK
- - vlseg6e32ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e32ff.v v4, (a0), v0.t # OK
- - vlseg7e32.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e32.v v4, (a0), v0.t # OK
- - vsseg7e32.v v0, (a0), v0.t # OK
- - vsseg7e32.v v4, (a0), v0.t # OK
- - vlseg7e32ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e32ff.v v4, (a0), v0.t # OK
- - vlseg8e32.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e32.v v4, (a0), v0.t # OK
- - vsseg8e32.v v0, (a0), v0.t # OK
- - vsseg8e32.v v4, (a0), v0.t # OK
- - vlseg8e32ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e32ff.v v4, (a0), v0.t # OK
- -
- - vlseg2e64.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e64.v v4, (a0), v0.t # OK
- - vsseg2e64.v v0, (a0), v0.t # OK
- - vsseg2e64.v v4, (a0), v0.t # OK
- - vlseg2e64ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e64ff.v v4, (a0), v0.t # OK
- - vlseg3e64.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e64.v v4, (a0), v0.t # OK
- - vsseg3e64.v v0, (a0), v0.t # OK
- - vsseg3e64.v v4, (a0), v0.t # OK
- - vlseg3e64ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e64ff.v v4, (a0), v0.t # OK
- - vlseg4e64.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e64.v v4, (a0), v0.t # OK
- - vsseg4e64.v v0, (a0), v0.t # OK
- - vsseg4e64.v v4, (a0), v0.t # OK
- - vlseg4e64ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e64ff.v v4, (a0), v0.t # OK
- - vlseg5e64.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e64.v v4, (a0), v0.t # OK
- - vsseg5e64.v v0, (a0), v0.t # OK
- - vsseg5e64.v v4, (a0), v0.t # OK
- - vlseg5e64ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e64ff.v v4, (a0), v0.t # OK
- - vlseg6e64.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e64.v v4, (a0), v0.t # OK
- - vsseg6e64.v v0, (a0), v0.t # OK
- - vsseg6e64.v v4, (a0), v0.t # OK
- - vlseg6e64ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e64ff.v v4, (a0), v0.t # OK
- - vlseg7e64.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e64.v v4, (a0), v0.t # OK
- - vsseg7e64.v v0, (a0), v0.t # OK
- - vsseg7e64.v v4, (a0), v0.t # OK
- - vlseg7e64ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e64ff.v v4, (a0), v0.t # OK
- - vlseg8e64.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e64.v v4, (a0), v0.t # OK
- - vsseg8e64.v v0, (a0), v0.t # OK
- - vsseg8e64.v v4, (a0), v0.t # OK
- - vlseg8e64ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e64ff.v v4, (a0), v0.t # OK
- -
- - vlseg2e128.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e128.v v4, (a0), v0.t # OK
- - vsseg2e128.v v0, (a0), v0.t # OK
- - vsseg2e128.v v4, (a0), v0.t # OK
- - vlseg2e128ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e128ff.v v4, (a0), v0.t # OK
- - vlseg3e128.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e128.v v4, (a0), v0.t # OK
- - vsseg3e128.v v0, (a0), v0.t # OK
- - vsseg3e128.v v4, (a0), v0.t # OK
- - vlseg3e128ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e128ff.v v4, (a0), v0.t # OK
- - vlseg4e128.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e128.v v4, (a0), v0.t # OK
- - vsseg4e128.v v0, (a0), v0.t # OK
- - vsseg4e128.v v4, (a0), v0.t # OK
- - vlseg4e128ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e128ff.v v4, (a0), v0.t # OK
- - vlseg5e128.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e128.v v4, (a0), v0.t # OK
- - vsseg5e128.v v0, (a0), v0.t # OK
- - vsseg5e128.v v4, (a0), v0.t # OK
- - vlseg5e128ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e128ff.v v4, (a0), v0.t # OK
- - vlseg6e128.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e128.v v4, (a0), v0.t # OK
- - vsseg6e128.v v0, (a0), v0.t # OK
- - vsseg6e128.v v4, (a0), v0.t # OK
- - vlseg6e128ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e128ff.v v4, (a0), v0.t # OK
- - vlseg7e128.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e128.v v4, (a0), v0.t # OK
- - vsseg7e128.v v0, (a0), v0.t # OK
- - vsseg7e128.v v4, (a0), v0.t # OK
- - vlseg7e128ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e128ff.v v4, (a0), v0.t # OK
- - vlseg8e128.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e128.v v4, (a0), v0.t # OK
- - vsseg8e128.v v0, (a0), v0.t # OK
- - vsseg8e128.v v4, (a0), v0.t # OK
- - vlseg8e128ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e128ff.v v4, (a0), v0.t # OK
- -
- - vlseg2e256.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e256.v v4, (a0), v0.t # OK
- - vsseg2e256.v v0, (a0), v0.t # OK
- - vsseg2e256.v v4, (a0), v0.t # OK
- - vlseg2e256ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e256ff.v v4, (a0), v0.t # OK
- - vlseg3e256.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e256.v v4, (a0), v0.t # OK
- - vsseg3e256.v v0, (a0), v0.t # OK
- - vsseg3e256.v v4, (a0), v0.t # OK
- - vlseg3e256ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e256ff.v v4, (a0), v0.t # OK
- - vlseg4e256.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e256.v v4, (a0), v0.t # OK
- - vsseg4e256.v v0, (a0), v0.t # OK
- - vsseg4e256.v v4, (a0), v0.t # OK
- - vlseg4e256ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e256ff.v v4, (a0), v0.t # OK
- - vlseg5e256.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e256.v v4, (a0), v0.t # OK
- - vsseg5e256.v v0, (a0), v0.t # OK
- - vsseg5e256.v v4, (a0), v0.t # OK
- - vlseg5e256ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e256ff.v v4, (a0), v0.t # OK
- - vlseg6e256.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e256.v v4, (a0), v0.t # OK
- - vsseg6e256.v v0, (a0), v0.t # OK
- - vsseg6e256.v v4, (a0), v0.t # OK
- - vlseg6e256ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e256ff.v v4, (a0), v0.t # OK
- - vlseg7e256.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e256.v v4, (a0), v0.t # OK
- - vsseg7e256.v v0, (a0), v0.t # OK
- - vsseg7e256.v v4, (a0), v0.t # OK
- - vlseg7e256ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e256ff.v v4, (a0), v0.t # OK
- - vlseg8e256.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e256.v v4, (a0), v0.t # OK
- - vsseg8e256.v v0, (a0), v0.t # OK
- - vsseg8e256.v v4, (a0), v0.t # OK
- - vlseg8e256ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e256ff.v v4, (a0), v0.t # OK
- -
- - vlseg2e512.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e512.v v4, (a0), v0.t # OK
- - vsseg2e512.v v0, (a0), v0.t # OK
- - vsseg2e512.v v4, (a0), v0.t # OK
- - vlseg2e512ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e512ff.v v4, (a0), v0.t # OK
- - vlseg3e512.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e512.v v4, (a0), v0.t # OK
- - vsseg3e512.v v0, (a0), v0.t # OK
- - vsseg3e512.v v4, (a0), v0.t # OK
- - vlseg3e512ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e512ff.v v4, (a0), v0.t # OK
- - vlseg4e512.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e512.v v4, (a0), v0.t # OK
- - vsseg4e512.v v0, (a0), v0.t # OK
- - vsseg4e512.v v4, (a0), v0.t # OK
- - vlseg4e512ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e512ff.v v4, (a0), v0.t # OK
- - vlseg5e512.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e512.v v4, (a0), v0.t # OK
- - vsseg5e512.v v0, (a0), v0.t # OK
- - vsseg5e512.v v4, (a0), v0.t # OK
- - vlseg5e512ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e512ff.v v4, (a0), v0.t # OK
- - vlseg6e512.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e512.v v4, (a0), v0.t # OK
- - vsseg6e512.v v0, (a0), v0.t # OK
- - vsseg6e512.v v4, (a0), v0.t # OK
- - vlseg6e512ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e512ff.v v4, (a0), v0.t # OK
- - vlseg7e512.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e512.v v4, (a0), v0.t # OK
- - vsseg7e512.v v0, (a0), v0.t # OK
- - vsseg7e512.v v4, (a0), v0.t # OK
- - vlseg7e512ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e512ff.v v4, (a0), v0.t # OK
- - vlseg8e512.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e512.v v4, (a0), v0.t # OK
- - vsseg8e512.v v0, (a0), v0.t # OK
- - vsseg8e512.v v4, (a0), v0.t # OK
- - vlseg8e512ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e512ff.v v4, (a0), v0.t # OK
- -
- - vlseg2e1024.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e1024.v v4, (a0), v0.t # OK
- - vsseg2e1024.v v0, (a0), v0.t # OK
- - vsseg2e1024.v v4, (a0), v0.t # OK
- - vlseg2e1024ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg2e1024ff.v v4, (a0), v0.t # OK
- - vlseg3e1024.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e1024.v v4, (a0), v0.t # OK
- - vsseg3e1024.v v0, (a0), v0.t # OK
- - vsseg3e1024.v v4, (a0), v0.t # OK
- - vlseg3e1024ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg3e1024ff.v v4, (a0), v0.t # OK
- - vlseg4e1024.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e1024.v v4, (a0), v0.t # OK
- - vsseg4e1024.v v0, (a0), v0.t # OK
- - vsseg4e1024.v v4, (a0), v0.t # OK
- - vlseg4e1024ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg4e1024ff.v v4, (a0), v0.t # OK
- - vlseg5e1024.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e1024.v v4, (a0), v0.t # OK
- - vsseg5e1024.v v0, (a0), v0.t # OK
- - vsseg5e1024.v v4, (a0), v0.t # OK
- - vlseg5e1024ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg5e1024ff.v v4, (a0), v0.t # OK
- - vlseg6e1024.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e1024.v v4, (a0), v0.t # OK
- - vsseg6e1024.v v0, (a0), v0.t # OK
- - vsseg6e1024.v v4, (a0), v0.t # OK
- - vlseg6e1024ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg6e1024ff.v v4, (a0), v0.t # OK
- - vlseg7e1024.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e1024.v v4, (a0), v0.t # OK
- - vsseg7e1024.v v0, (a0), v0.t # OK
- - vsseg7e1024.v v4, (a0), v0.t # OK
- - vlseg7e1024ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg7e1024ff.v v4, (a0), v0.t # OK
- - vlseg8e1024.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e1024.v v4, (a0), v0.t # OK
- - vsseg8e1024.v v0, (a0), v0.t # OK
- - vsseg8e1024.v v4, (a0), v0.t # OK
- - vlseg8e1024ff.v v0, (a0), v0.t # vd overlap vm
- - vlseg8e1024ff.v v4, (a0), v0.t # OK
- -
- -# Vector Strided Segment Loads and Stores
- -
- - vlsseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg2e8.v v4, (a0), a1, v0.t # OK
- - vssseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg2e8.v v4, (a0), a1, v0.t # OK
- - vlsseg3e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg3e8.v v4, (a0), a1, v0.t # OK
- - vssseg3e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg3e8.v v4, (a0), a1, v0.t # OK
- - vlsseg4e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg4e8.v v4, (a0), a1, v0.t # OK
- - vssseg4e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg4e8.v v4, (a0), a1, v0.t # OK
- - vlsseg5e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg5e8.v v4, (a0), a1, v0.t # OK
- - vssseg5e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg5e8.v v4, (a0), a1, v0.t # OK
- - vlsseg6e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg6e8.v v4, (a0), a1, v0.t # OK
- - vssseg6e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg6e8.v v4, (a0), a1, v0.t # OK
- - vlsseg7e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg7e8.v v4, (a0), a1, v0.t # OK
- - vssseg7e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg7e8.v v4, (a0), a1, v0.t # OK
- - vlsseg8e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg8e8.v v4, (a0), a1, v0.t # OK
- - vssseg8e8.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg8e8.v v4, (a0), a1, v0.t # OK
- -
- - vlsseg2e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg2e16.v v4, (a0), a1, v0.t # OK
- - vssseg2e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg2e16.v v4, (a0), a1, v0.t # OK
- - vlsseg3e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg3e16.v v4, (a0), a1, v0.t # OK
- - vssseg3e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg3e16.v v4, (a0), a1, v0.t # OK
- - vlsseg4e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg4e16.v v4, (a0), a1, v0.t # OK
- - vssseg4e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg4e16.v v4, (a0), a1, v0.t # OK
- - vlsseg5e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg5e16.v v4, (a0), a1, v0.t # OK
- - vssseg5e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg5e16.v v4, (a0), a1, v0.t # OK
- - vlsseg6e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg6e16.v v4, (a0), a1, v0.t # OK
- - vssseg6e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg6e16.v v4, (a0), a1, v0.t # OK
- - vlsseg7e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg7e16.v v4, (a0), a1, v0.t # OK
- - vssseg7e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg7e16.v v4, (a0), a1, v0.t # OK
- - vlsseg8e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg8e16.v v4, (a0), a1, v0.t # OK
- - vssseg8e16.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg8e16.v v4, (a0), a1, v0.t # OK
- -
- - vlsseg2e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg2e32.v v4, (a0), a1, v0.t # OK
- - vssseg2e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg2e32.v v4, (a0), a1, v0.t # OK
- - vlsseg3e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg3e32.v v4, (a0), a1, v0.t # OK
- - vssseg3e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg3e32.v v4, (a0), a1, v0.t # OK
- - vlsseg4e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg4e32.v v4, (a0), a1, v0.t # OK
- - vssseg4e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg4e32.v v4, (a0), a1, v0.t # OK
- - vlsseg5e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg5e32.v v4, (a0), a1, v0.t # OK
- - vssseg5e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg5e32.v v4, (a0), a1, v0.t # OK
- - vlsseg6e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg6e32.v v4, (a0), a1, v0.t # OK
- - vssseg6e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg6e32.v v4, (a0), a1, v0.t # OK
- - vlsseg7e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg7e32.v v4, (a0), a1, v0.t # OK
- - vssseg7e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg7e32.v v4, (a0), a1, v0.t # OK
- - vlsseg8e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg8e32.v v4, (a0), a1, v0.t # OK
- - vssseg8e32.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg8e32.v v4, (a0), a1, v0.t # OK
- -
- - vlsseg2e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg2e64.v v4, (a0), a1, v0.t # OK
- - vssseg2e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg2e64.v v4, (a0), a1, v0.t # OK
- - vlsseg3e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg3e64.v v4, (a0), a1, v0.t # OK
- - vssseg3e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg3e64.v v4, (a0), a1, v0.t # OK
- - vlsseg4e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg4e64.v v4, (a0), a1, v0.t # OK
- - vssseg4e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg4e64.v v4, (a0), a1, v0.t # OK
- - vlsseg5e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg5e64.v v4, (a0), a1, v0.t # OK
- - vssseg5e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg5e64.v v4, (a0), a1, v0.t # OK
- - vlsseg6e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg6e64.v v4, (a0), a1, v0.t # OK
- - vssseg6e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg6e64.v v4, (a0), a1, v0.t # OK
- - vlsseg7e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg7e64.v v4, (a0), a1, v0.t # OK
- - vssseg7e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg7e64.v v4, (a0), a1, v0.t # OK
- - vlsseg8e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg8e64.v v4, (a0), a1, v0.t # OK
- - vssseg8e64.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg8e64.v v4, (a0), a1, v0.t # OK
- -
- - vlsseg2e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg2e128.v v4, (a0), a1, v0.t # OK
- - vssseg2e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg2e128.v v4, (a0), a1, v0.t # OK
- - vlsseg3e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg3e128.v v4, (a0), a1, v0.t # OK
- - vssseg3e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg3e128.v v4, (a0), a1, v0.t # OK
- - vlsseg4e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg4e128.v v4, (a0), a1, v0.t # OK
- - vssseg4e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg4e128.v v4, (a0), a1, v0.t # OK
- - vlsseg5e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg5e128.v v4, (a0), a1, v0.t # OK
- - vssseg5e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg5e128.v v4, (a0), a1, v0.t # OK
- - vlsseg6e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg6e128.v v4, (a0), a1, v0.t # OK
- - vssseg6e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg6e128.v v4, (a0), a1, v0.t # OK
- - vlsseg7e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg7e128.v v4, (a0), a1, v0.t # OK
- - vssseg7e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg7e128.v v4, (a0), a1, v0.t # OK
- - vlsseg8e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg8e128.v v4, (a0), a1, v0.t # OK
- - vssseg8e128.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg8e128.v v4, (a0), a1, v0.t # OK
- -
- - vlsseg2e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg2e256.v v4, (a0), a1, v0.t # OK
- - vssseg2e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg2e256.v v4, (a0), a1, v0.t # OK
- - vlsseg3e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg3e256.v v4, (a0), a1, v0.t # OK
- - vssseg3e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg3e256.v v4, (a0), a1, v0.t # OK
- - vlsseg4e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg4e256.v v4, (a0), a1, v0.t # OK
- - vssseg4e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg4e256.v v4, (a0), a1, v0.t # OK
- - vlsseg5e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg5e256.v v4, (a0), a1, v0.t # OK
- - vssseg5e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg5e256.v v4, (a0), a1, v0.t # OK
- - vlsseg6e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg6e256.v v4, (a0), a1, v0.t # OK
- - vssseg6e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg6e256.v v4, (a0), a1, v0.t # OK
- - vlsseg7e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg7e256.v v4, (a0), a1, v0.t # OK
- - vssseg7e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg7e256.v v4, (a0), a1, v0.t # OK
- - vlsseg8e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg8e256.v v4, (a0), a1, v0.t # OK
- - vssseg8e256.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg8e256.v v4, (a0), a1, v0.t # OK
- -
- - vlsseg2e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg2e512.v v4, (a0), a1, v0.t # OK
- - vssseg2e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg2e512.v v4, (a0), a1, v0.t # OK
- - vlsseg3e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg3e512.v v4, (a0), a1, v0.t # OK
- - vssseg3e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg3e512.v v4, (a0), a1, v0.t # OK
- - vlsseg4e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg4e512.v v4, (a0), a1, v0.t # OK
- - vssseg4e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg4e512.v v4, (a0), a1, v0.t # OK
- - vlsseg5e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg5e512.v v4, (a0), a1, v0.t # OK
- - vssseg5e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg5e512.v v4, (a0), a1, v0.t # OK
- - vlsseg6e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg6e512.v v4, (a0), a1, v0.t # OK
- - vssseg6e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg6e512.v v4, (a0), a1, v0.t # OK
- - vlsseg7e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg7e512.v v4, (a0), a1, v0.t # OK
- - vssseg7e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg7e512.v v4, (a0), a1, v0.t # OK
- - vlsseg8e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg8e512.v v4, (a0), a1, v0.t # OK
- - vssseg8e512.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg8e512.v v4, (a0), a1, v0.t # OK
- -
- - vlsseg2e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg2e1024.v v4, (a0), a1, v0.t # OK
- - vssseg2e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg2e1024.v v4, (a0), a1, v0.t # OK
- - vlsseg3e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg3e1024.v v4, (a0), a1, v0.t # OK
- - vssseg3e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg3e1024.v v4, (a0), a1, v0.t # OK
- - vlsseg4e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg4e1024.v v4, (a0), a1, v0.t # OK
- - vssseg4e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg4e1024.v v4, (a0), a1, v0.t # OK
- - vlsseg5e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg5e1024.v v4, (a0), a1, v0.t # OK
- - vssseg5e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg5e1024.v v4, (a0), a1, v0.t # OK
- - vlsseg6e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg6e1024.v v4, (a0), a1, v0.t # OK
- - vssseg6e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg6e1024.v v4, (a0), a1, v0.t # OK
- - vlsseg7e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg7e1024.v v4, (a0), a1, v0.t # OK
- - vssseg7e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg7e1024.v v4, (a0), a1, v0.t # OK
- - vlsseg8e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vlsseg8e1024.v v4, (a0), a1, v0.t # OK
- - vssseg8e1024.v v0, (a0), a1, v0.t # vd overlap vm
- - vssseg8e1024.v v4, (a0), a1, v0.t # OK
- -
- -# Vector Indexed Segment Loads and Stores
- -
- - vlxseg2ei8.v v0, (a0), v2 # OK
- - vlxseg2ei8.v v1, (a0), v2 # OK
- - vlxseg2ei8.v v2, (a0), v2 # vd overlap vs2
- - vlxseg2ei8.v v0, (a0), v2, v0.t # vd overlap vm
- - vsxseg2ei8.v v0, (a0), v2
- - vsxseg2ei8.v v1, (a0), v2
- - vsxseg2ei8.v v2, (a0), v2
- - vsxseg2ei8.v v0, (a0), v2, v0.t
- - vlxseg3ei8.v v0, (a0), v2
- - vlxseg3ei8.v v1, (a0), v2
- - vlxseg3ei8.v v2, (a0), v2
- - vlxseg3ei8.v v0, (a0), v2, v0.t
- - vsxseg3ei8.v v0, (a0), v2
- - vsxseg3ei8.v v1, (a0), v2
- - vsxseg3ei8.v v2, (a0), v2
- - vsxseg3ei8.v v0, (a0), v2, v0.t
- - vlxseg4ei8.v v0, (a0), v2
- - vlxseg4ei8.v v1, (a0), v2
- - vlxseg4ei8.v v2, (a0), v2
- - vlxseg4ei8.v v0, (a0), v2, v0.t
- - vsxseg4ei8.v v0, (a0), v2
- - vsxseg4ei8.v v1, (a0), v2
- - vsxseg4ei8.v v2, (a0), v2
- - vsxseg4ei8.v v0, (a0), v2, v0.t
- - vlxseg5ei8.v v0, (a0), v2
- - vlxseg5ei8.v v1, (a0), v2
- - vlxseg5ei8.v v2, (a0), v2
- - vlxseg5ei8.v v0, (a0), v2, v0.t
- - vsxseg5ei8.v v0, (a0), v2
- - vsxseg5ei8.v v1, (a0), v2
- - vsxseg5ei8.v v2, (a0), v2
- - vsxseg5ei8.v v0, (a0), v2, v0.t
- - vlxseg6ei8.v v0, (a0), v2
- - vlxseg6ei8.v v1, (a0), v2
- - vlxseg6ei8.v v2, (a0), v2
- - vlxseg6ei8.v v0, (a0), v2, v0.t
- - vsxseg6ei8.v v0, (a0), v2
- - vsxseg6ei8.v v1, (a0), v2
- - vsxseg6ei8.v v2, (a0), v2
- - vsxseg6ei8.v v0, (a0), v2, v0.t
- - vlxseg7ei8.v v0, (a0), v2
- - vlxseg7ei8.v v1, (a0), v2
- - vlxseg7ei8.v v2, (a0), v2
- - vlxseg7ei8.v v0, (a0), v2, v0.t
- - vsxseg7ei8.v v0, (a0), v2
- - vsxseg7ei8.v v1, (a0), v2
- - vsxseg7ei8.v v2, (a0), v2
- - vsxseg7ei8.v v0, (a0), v2, v0.t
- - vlxseg8ei8.v v0, (a0), v2
- - vlxseg8ei8.v v1, (a0), v2
- - vlxseg8ei8.v v2, (a0), v2
- - vlxseg8ei8.v v0, (a0), v2, v0.t
- - vsxseg8ei8.v v0, (a0), v2
- - vsxseg8ei8.v v1, (a0), v2
- - vsxseg8ei8.v v2, (a0), v2
- - vsxseg8ei8.v v0, (a0), v2, v0.t
- -
- - vlxseg2ei16.v v0, (a0), v2 # OK
- - vlxseg2ei16.v v1, (a0), v2 # OK
- - vlxseg2ei16.v v2, (a0), v2 # vd overlap vs2
- - vlxseg2ei16.v v0, (a0), v2, v0.t # vd overlap vm
- - vsxseg2ei16.v v0, (a0), v2
- - vsxseg2ei16.v v1, (a0), v2
- - vsxseg2ei16.v v2, (a0), v2
- - vsxseg2ei16.v v0, (a0), v2, v0.t
- - vlxseg3ei16.v v0, (a0), v2
- - vlxseg3ei16.v v1, (a0), v2
- - vlxseg3ei16.v v2, (a0), v2
- - vlxseg3ei16.v v0, (a0), v2, v0.t
- - vsxseg3ei16.v v0, (a0), v2
- - vsxseg3ei16.v v1, (a0), v2
- - vsxseg3ei16.v v2, (a0), v2
- - vsxseg3ei16.v v0, (a0), v2, v0.t
- - vlxseg4ei16.v v0, (a0), v2
- - vlxseg4ei16.v v1, (a0), v2
- - vlxseg4ei16.v v2, (a0), v2
- - vlxseg4ei16.v v0, (a0), v2, v0.t
- - vsxseg4ei16.v v0, (a0), v2
- - vsxseg4ei16.v v1, (a0), v2
- - vsxseg4ei16.v v2, (a0), v2
- - vsxseg4ei16.v v0, (a0), v2, v0.t
- - vlxseg5ei16.v v0, (a0), v2
- - vlxseg5ei16.v v1, (a0), v2
- - vlxseg5ei16.v v2, (a0), v2
- - vlxseg5ei16.v v0, (a0), v2, v0.t
- - vsxseg5ei16.v v0, (a0), v2
- - vsxseg5ei16.v v1, (a0), v2
- - vsxseg5ei16.v v2, (a0), v2
- - vsxseg5ei16.v v0, (a0), v2, v0.t
- - vlxseg6ei16.v v0, (a0), v2
- - vlxseg6ei16.v v1, (a0), v2
- - vlxseg6ei16.v v2, (a0), v2
- - vlxseg6ei16.v v0, (a0), v2, v0.t
- - vsxseg6ei16.v v0, (a0), v2
- - vsxseg6ei16.v v1, (a0), v2
- - vsxseg6ei16.v v2, (a0), v2
- - vsxseg6ei16.v v0, (a0), v2, v0.t
- - vlxseg7ei16.v v0, (a0), v2
- - vlxseg7ei16.v v1, (a0), v2
- - vlxseg7ei16.v v2, (a0), v2
- - vlxseg7ei16.v v0, (a0), v2, v0.t
- - vsxseg7ei16.v v0, (a0), v2
- - vsxseg7ei16.v v1, (a0), v2
- - vsxseg7ei16.v v2, (a0), v2
- - vsxseg7ei16.v v0, (a0), v2, v0.t
- - vlxseg8ei16.v v0, (a0), v2
- - vlxseg8ei16.v v1, (a0), v2
- - vlxseg8ei16.v v2, (a0), v2
- - vlxseg8ei16.v v0, (a0), v2, v0.t
- - vsxseg8ei16.v v0, (a0), v2
- - vsxseg8ei16.v v1, (a0), v2
- - vsxseg8ei16.v v2, (a0), v2
- - vsxseg8ei16.v v0, (a0), v2, v0.t
- -
- - vlxseg2ei32.v v0, (a0), v2 # OK
- - vlxseg2ei32.v v1, (a0), v2 # OK
- - vlxseg2ei32.v v2, (a0), v2 # vd overlap vs2
- - vlxseg2ei32.v v0, (a0), v2, v0.t # vd overlap vm
- - vsxseg2ei32.v v0, (a0), v2
- - vsxseg2ei32.v v1, (a0), v2
- - vsxseg2ei32.v v2, (a0), v2
- - vsxseg2ei32.v v0, (a0), v2, v0.t
- - vlxseg3ei32.v v0, (a0), v2
- - vlxseg3ei32.v v1, (a0), v2
- - vlxseg3ei32.v v2, (a0), v2
- - vlxseg3ei32.v v0, (a0), v2, v0.t
- - vsxseg3ei32.v v0, (a0), v2
- - vsxseg3ei32.v v1, (a0), v2
- - vsxseg3ei32.v v2, (a0), v2
- - vsxseg3ei32.v v0, (a0), v2, v0.t
- - vlxseg4ei32.v v0, (a0), v2
- - vlxseg4ei32.v v1, (a0), v2
- - vlxseg4ei32.v v2, (a0), v2
- - vlxseg4ei32.v v0, (a0), v2, v0.t
- - vsxseg4ei32.v v0, (a0), v2
- - vsxseg4ei32.v v1, (a0), v2
- - vsxseg4ei32.v v2, (a0), v2
- - vsxseg4ei32.v v0, (a0), v2, v0.t
- - vlxseg5ei32.v v0, (a0), v2
- - vlxseg5ei32.v v1, (a0), v2
- - vlxseg5ei32.v v2, (a0), v2
- - vlxseg5ei32.v v0, (a0), v2, v0.t
- - vsxseg5ei32.v v0, (a0), v2
- - vsxseg5ei32.v v1, (a0), v2
- - vsxseg5ei32.v v2, (a0), v2
- - vsxseg5ei32.v v0, (a0), v2, v0.t
- - vlxseg6ei32.v v0, (a0), v2
- - vlxseg6ei32.v v1, (a0), v2
- - vlxseg6ei32.v v2, (a0), v2
- - vlxseg6ei32.v v0, (a0), v2, v0.t
- - vsxseg6ei32.v v0, (a0), v2
- - vsxseg6ei32.v v1, (a0), v2
- - vsxseg6ei32.v v2, (a0), v2
- - vsxseg6ei32.v v0, (a0), v2, v0.t
- - vlxseg7ei32.v v0, (a0), v2
- - vlxseg7ei32.v v1, (a0), v2
- - vlxseg7ei32.v v2, (a0), v2
- - vlxseg7ei32.v v0, (a0), v2, v0.t
- - vsxseg7ei32.v v0, (a0), v2
- - vsxseg7ei32.v v1, (a0), v2
- - vsxseg7ei32.v v2, (a0), v2
- - vsxseg7ei32.v v0, (a0), v2, v0.t
- - vlxseg8ei32.v v0, (a0), v2
- - vlxseg8ei32.v v1, (a0), v2
- - vlxseg8ei32.v v2, (a0), v2
- - vlxseg8ei32.v v0, (a0), v2, v0.t
- - vsxseg8ei32.v v0, (a0), v2
- - vsxseg8ei32.v v1, (a0), v2
- - vsxseg8ei32.v v2, (a0), v2
- - vsxseg8ei32.v v0, (a0), v2, v0.t
- -
- - vlxseg2ei64.v v0, (a0), v2 # OK
- - vlxseg2ei64.v v1, (a0), v2 # OK
- - vlxseg2ei64.v v2, (a0), v2 # vd overlap vs2
- - vlxseg2ei64.v v0, (a0), v2, v0.t # vd overlap vm
- - vsxseg2ei64.v v0, (a0), v2
- - vsxseg2ei64.v v1, (a0), v2
- - vsxseg2ei64.v v2, (a0), v2
- - vsxseg2ei64.v v0, (a0), v2, v0.t
- - vlxseg3ei64.v v0, (a0), v2
- - vlxseg3ei64.v v1, (a0), v2
- - vlxseg3ei64.v v2, (a0), v2
- - vlxseg3ei64.v v0, (a0), v2, v0.t
- - vsxseg3ei64.v v0, (a0), v2
- - vsxseg3ei64.v v1, (a0), v2
- - vsxseg3ei64.v v2, (a0), v2
- - vsxseg3ei64.v v0, (a0), v2, v0.t
- - vlxseg4ei64.v v0, (a0), v2
- - vlxseg4ei64.v v1, (a0), v2
- - vlxseg4ei64.v v2, (a0), v2
- - vlxseg4ei64.v v0, (a0), v2, v0.t
- - vsxseg4ei64.v v0, (a0), v2
- - vsxseg4ei64.v v1, (a0), v2
- - vsxseg4ei64.v v2, (a0), v2
- - vsxseg4ei64.v v0, (a0), v2, v0.t
- - vlxseg5ei64.v v0, (a0), v2
- - vlxseg5ei64.v v1, (a0), v2
- - vlxseg5ei64.v v2, (a0), v2
- - vlxseg5ei64.v v0, (a0), v2, v0.t
- - vsxseg5ei64.v v0, (a0), v2
- - vsxseg5ei64.v v1, (a0), v2
- - vsxseg5ei64.v v2, (a0), v2
- - vsxseg5ei64.v v0, (a0), v2, v0.t
- - vlxseg6ei64.v v0, (a0), v2
- - vlxseg6ei64.v v1, (a0), v2
- - vlxseg6ei64.v v2, (a0), v2
- - vlxseg6ei64.v v0, (a0), v2, v0.t
- - vsxseg6ei64.v v0, (a0), v2
- - vsxseg6ei64.v v1, (a0), v2
- - vsxseg6ei64.v v2, (a0), v2
- - vsxseg6ei64.v v0, (a0), v2, v0.t
- - vlxseg7ei64.v v0, (a0), v2
- - vlxseg7ei64.v v1, (a0), v2
- - vlxseg7ei64.v v2, (a0), v2
- - vlxseg7ei64.v v0, (a0), v2, v0.t
- - vsxseg7ei64.v v0, (a0), v2
- - vsxseg7ei64.v v1, (a0), v2
- - vsxseg7ei64.v v2, (a0), v2
- - vsxseg7ei64.v v0, (a0), v2, v0.t
- - vlxseg8ei64.v v0, (a0), v2
- - vlxseg8ei64.v v1, (a0), v2
- - vlxseg8ei64.v v2, (a0), v2
- - vlxseg8ei64.v v0, (a0), v2, v0.t
- - vsxseg8ei64.v v0, (a0), v2
- - vsxseg8ei64.v v1, (a0), v2
- - vsxseg8ei64.v v2, (a0), v2
- - vsxseg8ei64.v v0, (a0), v2, v0.t
- -
- - vlxseg2ei128.v v0, (a0), v2 # OK
- - vlxseg2ei128.v v1, (a0), v2 # OK
- - vlxseg2ei128.v v2, (a0), v2 # vd overlap vs2
- - vlxseg2ei128.v v0, (a0), v2, v0.t # vd overlap vm
- - vsxseg2ei128.v v0, (a0), v2
- - vsxseg2ei128.v v1, (a0), v2
- - vsxseg2ei128.v v2, (a0), v2
- - vsxseg2ei128.v v0, (a0), v2, v0.t
- - vlxseg3ei128.v v0, (a0), v2
- - vlxseg3ei128.v v1, (a0), v2
- - vlxseg3ei128.v v2, (a0), v2
- - vlxseg3ei128.v v0, (a0), v2, v0.t
- - vsxseg3ei128.v v0, (a0), v2
- - vsxseg3ei128.v v1, (a0), v2
- - vsxseg3ei128.v v2, (a0), v2
- - vsxseg3ei128.v v0, (a0), v2, v0.t
- - vlxseg4ei128.v v0, (a0), v2
- - vlxseg4ei128.v v1, (a0), v2
- - vlxseg4ei128.v v2, (a0), v2
- - vlxseg4ei128.v v0, (a0), v2, v0.t
- - vsxseg4ei128.v v0, (a0), v2
- - vsxseg4ei128.v v1, (a0), v2
- - vsxseg4ei128.v v2, (a0), v2
- - vsxseg4ei128.v v0, (a0), v2, v0.t
- - vlxseg5ei128.v v0, (a0), v2
- - vlxseg5ei128.v v1, (a0), v2
- - vlxseg5ei128.v v2, (a0), v2
- - vlxseg5ei128.v v0, (a0), v2, v0.t
- - vsxseg5ei128.v v0, (a0), v2
- - vsxseg5ei128.v v1, (a0), v2
- - vsxseg5ei128.v v2, (a0), v2
- - vsxseg5ei128.v v0, (a0), v2, v0.t
- - vlxseg6ei128.v v0, (a0), v2
- - vlxseg6ei128.v v1, (a0), v2
- - vlxseg6ei128.v v2, (a0), v2
- - vlxseg6ei128.v v0, (a0), v2, v0.t
- - vsxseg6ei128.v v0, (a0), v2
- - vsxseg6ei128.v v1, (a0), v2
- - vsxseg6ei128.v v2, (a0), v2
- - vsxseg6ei128.v v0, (a0), v2, v0.t
- - vlxseg7ei128.v v0, (a0), v2
- - vlxseg7ei128.v v1, (a0), v2
- - vlxseg7ei128.v v2, (a0), v2
- - vlxseg7ei128.v v0, (a0), v2, v0.t
- - vsxseg7ei128.v v0, (a0), v2
- - vsxseg7ei128.v v1, (a0), v2
- - vsxseg7ei128.v v2, (a0), v2
- - vsxseg7ei128.v v0, (a0), v2, v0.t
- - vlxseg8ei128.v v0, (a0), v2
- - vlxseg8ei128.v v1, (a0), v2
- - vlxseg8ei128.v v2, (a0), v2
- - vlxseg8ei128.v v0, (a0), v2, v0.t
- - vsxseg8ei128.v v0, (a0), v2
- - vsxseg8ei128.v v1, (a0), v2
- - vsxseg8ei128.v v2, (a0), v2
- - vsxseg8ei128.v v0, (a0), v2, v0.t
- -
- - vlxseg2ei256.v v0, (a0), v2 # OK
- - vlxseg2ei256.v v1, (a0), v2 # OK
- - vlxseg2ei256.v v2, (a0), v2 # vd overlap vs2
- - vlxseg2ei256.v v0, (a0), v2, v0.t # vd overlap vm
- - vsxseg2ei256.v v0, (a0), v2
- - vsxseg2ei256.v v1, (a0), v2
- - vsxseg2ei256.v v2, (a0), v2
- - vsxseg2ei256.v v0, (a0), v2, v0.t
- - vlxseg3ei256.v v0, (a0), v2
- - vlxseg3ei256.v v1, (a0), v2
- - vlxseg3ei256.v v2, (a0), v2
- - vlxseg3ei256.v v0, (a0), v2, v0.t
- - vsxseg3ei256.v v0, (a0), v2
- - vsxseg3ei256.v v1, (a0), v2
- - vsxseg3ei256.v v2, (a0), v2
- - vsxseg3ei256.v v0, (a0), v2, v0.t
- - vlxseg4ei256.v v0, (a0), v2
- - vlxseg4ei256.v v1, (a0), v2
- - vlxseg4ei256.v v2, (a0), v2
- - vlxseg4ei256.v v0, (a0), v2, v0.t
- - vsxseg4ei256.v v0, (a0), v2
- - vsxseg4ei256.v v1, (a0), v2
- - vsxseg4ei256.v v2, (a0), v2
- - vsxseg4ei256.v v0, (a0), v2, v0.t
- - vlxseg5ei256.v v0, (a0), v2
- - vlxseg5ei256.v v1, (a0), v2
- - vlxseg5ei256.v v2, (a0), v2
- - vlxseg5ei256.v v0, (a0), v2, v0.t
- - vsxseg5ei256.v v0, (a0), v2
- - vsxseg5ei256.v v1, (a0), v2
- - vsxseg5ei256.v v2, (a0), v2
- - vsxseg5ei256.v v0, (a0), v2, v0.t
- - vlxseg6ei256.v v0, (a0), v2
- - vlxseg6ei256.v v1, (a0), v2
- - vlxseg6ei256.v v2, (a0), v2
- - vlxseg6ei256.v v0, (a0), v2, v0.t
- - vsxseg6ei256.v v0, (a0), v2
- - vsxseg6ei256.v v1, (a0), v2
- - vsxseg6ei256.v v2, (a0), v2
- - vsxseg6ei256.v v0, (a0), v2, v0.t
- - vlxseg7ei256.v v0, (a0), v2
- - vlxseg7ei256.v v1, (a0), v2
- - vlxseg7ei256.v v2, (a0), v2
- - vlxseg7ei256.v v0, (a0), v2, v0.t
- - vsxseg7ei256.v v0, (a0), v2
- - vsxseg7ei256.v v1, (a0), v2
- - vsxseg7ei256.v v2, (a0), v2
- - vsxseg7ei256.v v0, (a0), v2, v0.t
- - vlxseg8ei256.v v0, (a0), v2
- - vlxseg8ei256.v v1, (a0), v2
- - vlxseg8ei256.v v2, (a0), v2
- - vlxseg8ei256.v v0, (a0), v2, v0.t
- - vsxseg8ei256.v v0, (a0), v2
- - vsxseg8ei256.v v1, (a0), v2
- - vsxseg8ei256.v v2, (a0), v2
- - vsxseg8ei256.v v0, (a0), v2, v0.t
- -
- - vlxseg2ei512.v v0, (a0), v2 # OK
- - vlxseg2ei512.v v1, (a0), v2 # OK
- - vlxseg2ei512.v v2, (a0), v2 # vd overlap vs2
- - vlxseg2ei512.v v0, (a0), v2, v0.t # vd overlap vm
- - vsxseg2ei512.v v0, (a0), v2
- - vsxseg2ei512.v v1, (a0), v2
- - vsxseg2ei512.v v2, (a0), v2
- - vsxseg2ei512.v v0, (a0), v2, v0.t
- - vlxseg3ei512.v v0, (a0), v2
- - vlxseg3ei512.v v1, (a0), v2
- - vlxseg3ei512.v v2, (a0), v2
- - vlxseg3ei512.v v0, (a0), v2, v0.t
- - vsxseg3ei512.v v0, (a0), v2
- - vsxseg3ei512.v v1, (a0), v2
- - vsxseg3ei512.v v2, (a0), v2
- - vsxseg3ei512.v v0, (a0), v2, v0.t
- - vlxseg4ei512.v v0, (a0), v2
- - vlxseg4ei512.v v1, (a0), v2
- - vlxseg4ei512.v v2, (a0), v2
- - vlxseg4ei512.v v0, (a0), v2, v0.t
- - vsxseg4ei512.v v0, (a0), v2
- - vsxseg4ei512.v v1, (a0), v2
- - vsxseg4ei512.v v2, (a0), v2
- - vsxseg4ei512.v v0, (a0), v2, v0.t
- - vlxseg5ei512.v v0, (a0), v2
- - vlxseg5ei512.v v1, (a0), v2
- - vlxseg5ei512.v v2, (a0), v2
- - vlxseg5ei512.v v0, (a0), v2, v0.t
- - vsxseg5ei512.v v0, (a0), v2
- - vsxseg5ei512.v v1, (a0), v2
- - vsxseg5ei512.v v2, (a0), v2
- - vsxseg5ei512.v v0, (a0), v2, v0.t
- - vlxseg6ei512.v v0, (a0), v2
- - vlxseg6ei512.v v1, (a0), v2
- - vlxseg6ei512.v v2, (a0), v2
- - vlxseg6ei512.v v0, (a0), v2, v0.t
- - vsxseg6ei512.v v0, (a0), v2
- - vsxseg6ei512.v v1, (a0), v2
- - vsxseg6ei512.v v2, (a0), v2
- - vsxseg6ei512.v v0, (a0), v2, v0.t
- - vlxseg7ei512.v v0, (a0), v2
- - vlxseg7ei512.v v1, (a0), v2
- - vlxseg7ei512.v v2, (a0), v2
- - vlxseg7ei512.v v0, (a0), v2, v0.t
- - vsxseg7ei512.v v0, (a0), v2
- - vsxseg7ei512.v v1, (a0), v2
- - vsxseg7ei512.v v2, (a0), v2
- - vsxseg7ei512.v v0, (a0), v2, v0.t
- - vlxseg8ei512.v v0, (a0), v2
- - vlxseg8ei512.v v1, (a0), v2
- - vlxseg8ei512.v v2, (a0), v2
- - vlxseg8ei512.v v0, (a0), v2, v0.t
- - vsxseg8ei512.v v0, (a0), v2
- - vsxseg8ei512.v v1, (a0), v2
- - vsxseg8ei512.v v2, (a0), v2
- - vsxseg8ei512.v v0, (a0), v2, v0.t
- -
- - vlxseg2ei1024.v v0, (a0), v2 # OK
- - vlxseg2ei1024.v v1, (a0), v2 # OK
- - vlxseg2ei1024.v v2, (a0), v2 # vd overlap vs2
- - vlxseg2ei1024.v v0, (a0), v2, v0.t # vd overlap vm
- - vsxseg2ei1024.v v0, (a0), v2
- - vsxseg2ei1024.v v1, (a0), v2
- - vsxseg2ei1024.v v2, (a0), v2
- - vsxseg2ei1024.v v0, (a0), v2, v0.t
- - vlxseg3ei1024.v v0, (a0), v2
- - vlxseg3ei1024.v v1, (a0), v2
- - vlxseg3ei1024.v v2, (a0), v2
- - vlxseg3ei1024.v v0, (a0), v2, v0.t
- - vsxseg3ei1024.v v0, (a0), v2
- - vsxseg3ei1024.v v1, (a0), v2
- - vsxseg3ei1024.v v2, (a0), v2
- - vsxseg3ei1024.v v0, (a0), v2, v0.t
- - vlxseg4ei1024.v v0, (a0), v2
- - vlxseg4ei1024.v v1, (a0), v2
- - vlxseg4ei1024.v v2, (a0), v2
- - vlxseg4ei1024.v v0, (a0), v2, v0.t
- - vsxseg4ei1024.v v0, (a0), v2
- - vsxseg4ei1024.v v1, (a0), v2
- - vsxseg4ei1024.v v2, (a0), v2
- - vsxseg4ei1024.v v0, (a0), v2, v0.t
- - vlxseg5ei1024.v v0, (a0), v2
- - vlxseg5ei1024.v v1, (a0), v2
- - vlxseg5ei1024.v v2, (a0), v2
- - vlxseg5ei1024.v v0, (a0), v2, v0.t
- - vsxseg5ei1024.v v0, (a0), v2
- - vsxseg5ei1024.v v1, (a0), v2
- - vsxseg5ei1024.v v2, (a0), v2
- - vsxseg5ei1024.v v0, (a0), v2, v0.t
- - vlxseg6ei1024.v v0, (a0), v2
- - vlxseg6ei1024.v v1, (a0), v2
- - vlxseg6ei1024.v v2, (a0), v2
- - vlxseg6ei1024.v v0, (a0), v2, v0.t
- - vsxseg6ei1024.v v0, (a0), v2
- - vsxseg6ei1024.v v1, (a0), v2
- - vsxseg6ei1024.v v2, (a0), v2
- - vsxseg6ei1024.v v0, (a0), v2, v0.t
- - vlxseg7ei1024.v v0, (a0), v2
- - vlxseg7ei1024.v v1, (a0), v2
- - vlxseg7ei1024.v v2, (a0), v2
- - vlxseg7ei1024.v v0, (a0), v2, v0.t
- - vsxseg7ei1024.v v0, (a0), v2
- - vsxseg7ei1024.v v1, (a0), v2
- - vsxseg7ei1024.v v2, (a0), v2
- - vsxseg7ei1024.v v0, (a0), v2, v0.t
- - vlxseg8ei1024.v v0, (a0), v2
- - vlxseg8ei1024.v v1, (a0), v2
- - vlxseg8ei1024.v v2, (a0), v2
- - vlxseg8ei1024.v v0, (a0), v2, v0.t
- - vsxseg8ei1024.v v0, (a0), v2
- - vsxseg8ei1024.v v1, (a0), v2
- - vsxseg8ei1024.v v2, (a0), v2
- - vsxseg8ei1024.v v0, (a0), v2, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.d b/gas/testsuite/gas/riscv/vector-insns-fail-02.d
- deleted file mode 100644
- index 6780b8553d..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-02.d
- +++ /dev/null
- @@ -1,3 +0,0 @@
- -#as: -march=rv32ifv_zvqmac -mcheck-constraints
- -#source: vector-insns-fail-02.s
- -#error_output: vector-insns-fail-02.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.l b/gas/testsuite/gas/riscv/vector-insns-fail-02.l
- deleted file mode 100644
- index c015fd75fc..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-02.l
- +++ /dev/null
- @@ -1,121 +0,0 @@
- -.*: Assembler messages:
- -.*Error: illegal operands `vwaddu.vv v1,v2,v4'
- -.*Error: illegal operands `vwaddu.vv v2,v2,v4'
- -.*Error: illegal operands `vwaddu.vv v2,v3,v4'
- -.*Error: illegal operands `vwaddu.vv v4,v2,v4'
- -.*Error: illegal operands `vwaddu.vv v4,v2,v5'
- -.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwsubu.vv v1,v2,v4'
- -.*Error: illegal operands `vwsubu.vv v2,v2,v4'
- -.*Error: illegal operands `vwsubu.vv v2,v3,v4'
- -.*Error: illegal operands `vwsubu.vv v4,v2,v4'
- -.*Error: illegal operands `vwsubu.vv v4,v2,v5'
- -.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwadd.vv v1,v2,v4'
- -.*Error: illegal operands `vwadd.vv v2,v2,v4'
- -.*Error: illegal operands `vwadd.vv v2,v3,v4'
- -.*Error: illegal operands `vwadd.vv v4,v2,v4'
- -.*Error: illegal operands `vwadd.vv v4,v2,v5'
- -.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwsub.vv v1,v2,v4'
- -.*Error: illegal operands `vwsub.vv v2,v2,v4'
- -.*Error: illegal operands `vwsub.vv v2,v3,v4'
- -.*Error: illegal operands `vwsub.vv v4,v2,v4'
- -.*Error: illegal operands `vwsub.vv v4,v2,v5'
- -.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwmul.vv v1,v2,v4'
- -.*Error: illegal operands `vwmul.vv v2,v2,v4'
- -.*Error: illegal operands `vwmul.vv v2,v3,v4'
- -.*Error: illegal operands `vwmul.vv v4,v2,v4'
- -.*Error: illegal operands `vwmul.vv v4,v2,v5'
- -.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwmulu.vv v1,v2,v4'
- -.*Error: illegal operands `vwmulu.vv v2,v2,v4'
- -.*Error: illegal operands `vwmulu.vv v2,v3,v4'
- -.*Error: illegal operands `vwmulu.vv v4,v2,v4'
- -.*Error: illegal operands `vwmulu.vv v4,v2,v5'
- -.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
- -.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
- -.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
- -.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
- -.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
- -.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
- -.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
- -.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
- -.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
- -.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
- -.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwmacc.vv v1,v2,v4'
- -.*Error: illegal operands `vwmacc.vv v2,v2,v4'
- -.*Error: illegal operands `vwmacc.vv v2,v3,v4'
- -.*Error: illegal operands `vwmacc.vv v4,v2,v4'
- -.*Error: illegal operands `vwmacc.vv v4,v2,v5'
- -.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
- -.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
- -.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
- -.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
- -.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
- -.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
- -.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
- -.*Error: illegal operands `vqmaccu.vv v4,v6,v8'
- -.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
- -.*Error: illegal operands `vqmaccu.vv v8,v4,v10'
- -.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
- -.*Error: illegal operands `vqmacc.vv v2,v4,v8'
- -.*Error: illegal operands `vqmacc.vv v4,v4,v8'
- -.*Error: illegal operands `vqmacc.vv v4,v6,v8'
- -.*Error: illegal operands `vqmacc.vv v8,v4,v8'
- -.*Error: illegal operands `vqmacc.vv v8,v4,v10'
- -.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
- -.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
- -.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
- -.*Error: illegal operands `vqmaccsu.vv v4,v6,v8'
- -.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
- -.*Error: illegal operands `vqmaccsu.vv v8,v4,v10'
- -.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
- -.*Error: illegal operands `vfwadd.vv v1,v2,v4'
- -.*Error: illegal operands `vfwadd.vv v2,v2,v4'
- -.*Error: illegal operands `vfwadd.vv v2,v3,v4'
- -.*Error: illegal operands `vfwadd.vv v4,v2,v4'
- -.*Error: illegal operands `vfwadd.vv v4,v2,v5'
- -.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vfwsub.vv v1,v2,v4'
- -.*Error: illegal operands `vfwsub.vv v2,v2,v4'
- -.*Error: illegal operands `vfwsub.vv v2,v3,v4'
- -.*Error: illegal operands `vfwsub.vv v4,v2,v4'
- -.*Error: illegal operands `vfwsub.vv v4,v2,v5'
- -.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vfwmul.vv v1,v2,v4'
- -.*Error: illegal operands `vfwmul.vv v2,v2,v4'
- -.*Error: illegal operands `vfwmul.vv v2,v3,v4'
- -.*Error: illegal operands `vfwmul.vv v4,v2,v4'
- -.*Error: illegal operands `vfwmul.vv v4,v2,v5'
- -.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
- -.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
- -.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
- -.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
- -.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
- -.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
- -.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
- -.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
- -.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
- -.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
- -.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
- -.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
- -.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
- -.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
- -.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
- -.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
- -.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
- -.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
- -.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
- -.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
- -.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-02.s b/gas/testsuite/gas/riscv/vector-insns-fail-02.s
- deleted file mode 100644
- index bf493c8ddb..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-02.s
- +++ /dev/null
- @@ -1,162 +0,0 @@
- -# Widening Vector Arithmetic Instructions (VV)
- -# Quad-Widening Vector Arithmetic Instructions (VV)
- -
- - vwaddu.vv v0, v2, v4 # OK
- - vwaddu.vv v1, v2, v4 # vd should be multiple of 2
- - vwaddu.vv v2, v2, v4 # vd overlap vs2
- - vwaddu.vv v2, v3, v4 # vd overlap vs2
- - vwaddu.vv v4, v2, v4 # vd overlap vs1
- - vwaddu.vv v4, v2, v5 # vd overlap vs1
- - vwaddu.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwsubu.vv v0, v2, v4 # OK
- - vwsubu.vv v1, v2, v4 # vd should be multiple of 2
- - vwsubu.vv v2, v2, v4 # vd overlap vs2
- - vwsubu.vv v2, v3, v4 # vd overlap vs2
- - vwsubu.vv v4, v2, v4 # vd overlap vs1
- - vwsubu.vv v4, v2, v5 # vd overlap vs1
- - vwsubu.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwadd.vv v0, v2, v4 # OK
- - vwadd.vv v1, v2, v4 # vd should be multiple of 2
- - vwadd.vv v2, v2, v4 # vd overlap vs2
- - vwadd.vv v2, v3, v4 # vd overlap vs2
- - vwadd.vv v4, v2, v4 # vd overlap vs1
- - vwadd.vv v4, v2, v5 # vd overlap vs1
- - vwadd.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwsub.vv v0, v2, v4 # OK
- - vwsub.vv v1, v2, v4 # vd should be multiple of 2
- - vwsub.vv v2, v2, v4 # vd overlap vs2
- - vwsub.vv v2, v3, v4 # vd overlap vs2
- - vwsub.vv v4, v2, v4 # vd overlap vs1
- - vwsub.vv v4, v2, v5 # vd overlap vs1
- - vwsub.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwmul.vv v0, v2, v4 # OK
- - vwmul.vv v1, v2, v4 # vd should be multiple of 2
- - vwmul.vv v2, v2, v4 # vd overlap vs2
- - vwmul.vv v2, v3, v4 # vd overlap vs2
- - vwmul.vv v4, v2, v4 # vd overlap vs1
- - vwmul.vv v4, v2, v5 # vd overlap vs1
- - vwmul.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwmulu.vv v0, v2, v4 # OK
- - vwmulu.vv v1, v2, v4 # vd should be multiple of 2
- - vwmulu.vv v2, v2, v4 # vd overlap vs2
- - vwmulu.vv v2, v3, v4 # vd overlap vs2
- - vwmulu.vv v4, v2, v4 # vd overlap vs1
- - vwmulu.vv v4, v2, v5 # vd overlap vs1
- - vwmulu.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwmulsu.vv v0, v2, v4 # OK
- - vwmulsu.vv v1, v2, v4 # vd should be multiple of 2
- - vwmulsu.vv v2, v2, v4 # vd overlap vs2
- - vwmulsu.vv v2, v3, v4 # vd overlap vs2
- - vwmulsu.vv v4, v2, v4 # vd overlap vs1
- - vwmulsu.vv v4, v2, v5 # vd overlap vs1
- - vwmulsu.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwmaccu.vv v0, v2, v4 # OK
- - vwmaccu.vv v1, v2, v4 # vd should be multiple of 2
- - vwmaccu.vv v2, v2, v4 # vd overlap vs1
- - vwmaccu.vv v2, v3, v4 # vd overlap vs1
- - vwmaccu.vv v4, v2, v4 # vd overlap vs2
- - vwmaccu.vv v4, v2, v5 # vd overlap vs2
- - vwmaccu.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwmacc.vv v0, v2, v4 # OK
- - vwmacc.vv v1, v2, v4 # vd should be multiple of 2
- - vwmacc.vv v2, v2, v4 # vd overlap vs1
- - vwmacc.vv v2, v3, v4 # vd overlap vs1
- - vwmacc.vv v4, v2, v4 # vd overlap vs2
- - vwmacc.vv v4, v2, v5 # vd overlap vs2
- - vwmacc.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwmaccsu.vv v0, v2, v4 # OK
- - vwmaccsu.vv v1, v2, v4 # vd should be multiple of 2
- - vwmaccsu.vv v2, v2, v4 # vd overlap vs1
- - vwmaccsu.vv v2, v3, v4 # vd overlap vs1
- - vwmaccsu.vv v4, v2, v4 # vd overlap vs2
- - vwmaccsu.vv v4, v2, v5 # vd overlap vs2
- - vwmaccsu.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vqmaccu.vv v0, v4, v8 # OK
- - vqmaccu.vv v2, v4, v8 # vd should be multiple of 4
- - vqmaccu.vv v4, v4, v8 # vd overlap vs1
- - vqmaccu.vv v4, v6, v8 # vd overlap vs1
- - vqmaccu.vv v8, v4, v8 # vd overlap vs2
- - vqmaccu.vv v8, v4, v10 # vd overlap vs2
- - vqmaccu.vv v0, v4, v8, v0.t # vd overlap vm
- -
- - vqmacc.vv v0, v4, v8 # OK
- - vqmacc.vv v2, v4, v8 # vd should be multiple of 4
- - vqmacc.vv v4, v4, v8 # vd overlap vs1
- - vqmacc.vv v4, v6, v8 # vd overlap vs1
- - vqmacc.vv v8, v4, v8 # vd overlap vs2
- - vqmacc.vv v8, v4, v10 # vd overlap vs2
- - vqmacc.vv v0, v4, v8, v0.t # vd overlap vm
- -
- - vqmaccsu.vv v0, v4, v8 # OK
- - vqmaccsu.vv v2, v4, v8 # vd should be multiple of 4
- - vqmaccsu.vv v4, v4, v8 # vd overlap vs1
- - vqmaccsu.vv v4, v6, v8 # vd overlap vs1
- - vqmaccsu.vv v8, v4, v8 # vd overlap vs2
- - vqmaccsu.vv v8, v4, v10 # vd overlap vs2
- - vqmaccsu.vv v0, v4, v8, v0.t # vd overlap vm
- -
- - vfwadd.vv v0, v2, v4 # OK
- - vfwadd.vv v1, v2, v4 # vd should be multiple of 2
- - vfwadd.vv v2, v2, v4 # vd overlap vs2
- - vfwadd.vv v2, v3, v4 # vd overlap vs2
- - vfwadd.vv v4, v2, v4 # vd overlap vs1
- - vfwadd.vv v4, v2, v5 # vd overlap vs1
- - vfwadd.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vfwsub.vv v0, v2, v4 # OK
- - vfwsub.vv v1, v2, v4 # vd should be multiple of 2
- - vfwsub.vv v2, v2, v4 # vd overlap vs2
- - vfwsub.vv v2, v3, v4 # vd overlap vs2
- - vfwsub.vv v4, v2, v4 # vd overlap vs1
- - vfwsub.vv v4, v2, v5 # vd overlap vs1
- - vfwsub.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vfwmul.vv v0, v2, v4 # OK
- - vfwmul.vv v1, v2, v4 # vd should be multiple of 2
- - vfwmul.vv v2, v2, v4 # vd overlap vs2
- - vfwmul.vv v2, v3, v4 # vd overlap vs2
- - vfwmul.vv v4, v2, v4 # vd overlap vs1
- - vfwmul.vv v4, v2, v5 # vd overlap vs1
- - vfwmul.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vfwmacc.vv v0, v2, v4 # OK
- - vfwmacc.vv v1, v2, v4 # vd should be multiple of 2
- - vfwmacc.vv v2, v2, v4 # vd overlap vs1
- - vfwmacc.vv v2, v3, v4 # vd overlap vs1
- - vfwmacc.vv v4, v2, v4 # vd overlap vs2
- - vfwmacc.vv v4, v2, v5 # vd overlap vs2
- - vfwmacc.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vfwnmacc.vv v0, v2, v4 # OK
- - vfwnmacc.vv v1, v2, v4 # vd should be multiple of 2
- - vfwnmacc.vv v2, v2, v4 # vd overlap vs1
- - vfwnmacc.vv v2, v3, v4 # vd overlap vs1
- - vfwnmacc.vv v4, v2, v4 # vd overlap vs2
- - vfwnmacc.vv v4, v2, v5 # vd overlap vs2
- - vfwnmacc.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vfwmsac.vv v0, v2, v4 # OK
- - vfwmsac.vv v1, v2, v4 # vd should be multiple of 2
- - vfwmsac.vv v2, v2, v4 # vd overlap vs1
- - vfwmsac.vv v2, v3, v4 # vd overlap vs1
- - vfwmsac.vv v4, v2, v4 # vd overlap vs2
- - vfwmsac.vv v4, v2, v5 # vd overlap vs2
- - vfwmsac.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vfwnmsac.vv v0, v2, v4 # OK
- - vfwnmsac.vv v1, v2, v4 # vd should be multiple of 2
- - vfwnmsac.vv v2, v2, v4 # vd overlap vs1
- - vfwnmsac.vv v2, v3, v4 # vd overlap vs1
- - vfwnmsac.vv v4, v2, v4 # vd overlap vs2
- - vfwnmsac.vv v4, v2, v5 # vd overlap vs2
- - vfwnmsac.vv v0, v2, v4, v0.t # vd overlap vm
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.d b/gas/testsuite/gas/riscv/vector-insns-fail-03.d
- deleted file mode 100644
- index 1bfe441872..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-03.d
- +++ /dev/null
- @@ -1,3 +0,0 @@
- -#as: -march=rv32ifv_zvqmac -mcheck-constraints
- -#source: vector-insns-fail-03.s
- -#error_output: vector-insns-fail-03.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.l b/gas/testsuite/gas/riscv/vector-insns-fail-03.l
- deleted file mode 100644
- index 128e22726d..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-03.l
- +++ /dev/null
- @@ -1,125 +0,0 @@
- -.*: Assembler messages:
- -.*Error: illegal operands `vwcvt.x.x.v v1,v2'
- -.*Error: illegal operands `vwcvt.x.x.v v2,v2'
- -.*Error: illegal operands `vwcvt.x.x.v v2,v3'
- -.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
- -.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
- -.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
- -.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
- -.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
- -.*Error: illegal operands `vwaddu.vx v1,v2,a1'
- -.*Error: illegal operands `vwaddu.vx v2,v2,a1'
- -.*Error: illegal operands `vwaddu.vx v2,v3,a1'
- -.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwsubu.vx v1,v2,a1'
- -.*Error: illegal operands `vwsubu.vx v2,v2,a1'
- -.*Error: illegal operands `vwsubu.vx v2,v3,a1'
- -.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwadd.vx v1,v2,a1'
- -.*Error: illegal operands `vwadd.vx v2,v2,a1'
- -.*Error: illegal operands `vwadd.vx v2,v3,a1'
- -.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwsub.vx v1,v2,a1'
- -.*Error: illegal operands `vwsub.vx v2,v2,a1'
- -.*Error: illegal operands `vwsub.vx v2,v3,a1'
- -.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwmul.vx v1,v2,a1'
- -.*Error: illegal operands `vwmul.vx v2,v2,a1'
- -.*Error: illegal operands `vwmul.vx v2,v3,a1'
- -.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwmulu.vx v1,v2,a1'
- -.*Error: illegal operands `vwmulu.vx v2,v2,a1'
- -.*Error: illegal operands `vwmulu.vx v2,v3,a1'
- -.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
- -.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
- -.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
- -.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwmaccu.vx v1,a1,v4'
- -.*Error: illegal operands `vwmaccu.vx v4,a1,v4'
- -.*Error: illegal operands `vwmaccu.vx v4,a1,v5'
- -.*Error: illegal operands `vwmaccu.vx v0,a1,v4,v0.t'
- -.*Error: illegal operands `vwmacc.vx v1,a1,v4'
- -.*Error: illegal operands `vwmacc.vx v4,a1,v4'
- -.*Error: illegal operands `vwmacc.vx v4,a1,v5'
- -.*Error: illegal operands `vwmacc.vx v0,a1,v4,v0.t'
- -.*Error: illegal operands `vwmaccsu.vx v1,a1,v4'
- -.*Error: illegal operands `vwmaccsu.vx v4,a1,v4'
- -.*Error: illegal operands `vwmaccsu.vx v4,a1,v5'
- -.*Error: illegal operands `vwmaccsu.vx v0,a1,v4,v0.t'
- -.*Error: illegal operands `vwmaccus.vx v1,a1,v4'
- -.*Error: illegal operands `vwmaccus.vx v4,a1,v4'
- -.*Error: illegal operands `vwmaccus.vx v4,a1,v5'
- -.*Error: illegal operands `vwmaccus.vx v0,a1,v4,v0.t'
- -.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
- -.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
- -.*Error: illegal operands `vqmaccu.vx v4,a1,v6'
- -.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
- -.*Error: illegal operands `vqmacc.vx v2,a1,v4'
- -.*Error: illegal operands `vqmacc.vx v4,a1,v4'
- -.*Error: illegal operands `vqmacc.vx v4,a1,v6'
- -.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
- -.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
- -.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
- -.*Error: illegal operands `vqmaccsu.vx v4,a1,v6'
- -.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
- -.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
- -.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
- -.*Error: illegal operands `vqmaccus.vx v4,a1,v6'
- -.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
- -.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
- -.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
- -.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
- -.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
- -.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
- -.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
- -.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
- -.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
- -.*Error: illegal operands `vfwmul.vf v1,v2,fa1'
- -.*Error: illegal operands `vfwmul.vf v2,v2,fa1'
- -.*Error: illegal operands `vfwmul.vf v2,v3,fa1'
- -.*Error: illegal operands `vfwmul.vf v0,v2,fa1,v0.t'
- -.*Error: illegal operands `vfwmacc.vf v1,fa1,v4'
- -.*Error: illegal operands `vfwmacc.vf v4,fa1,v4'
- -.*Error: illegal operands `vfwmacc.vf v4,fa1,v5'
- -.*Error: illegal operands `vfwmacc.vf v0,fa1,v4,v0.t'
- -.*Error: illegal operands `vfwnmacc.vf v1,fa1,v4'
- -.*Error: illegal operands `vfwnmacc.vf v4,fa1,v4'
- -.*Error: illegal operands `vfwnmacc.vf v4,fa1,v5'
- -.*Error: illegal operands `vfwnmacc.vf v0,fa1,v4,v0.t'
- -.*Error: illegal operands `vfwmsac.vf v1,fa1,v4'
- -.*Error: illegal operands `vfwmsac.vf v4,fa1,v4'
- -.*Error: illegal operands `vfwmsac.vf v4,fa1,v5'
- -.*Error: illegal operands `vfwmsac.vf v0,fa1,v4,v0.t'
- -.*Error: illegal operands `vfwnmsac.vf v1,fa1,v4'
- -.*Error: illegal operands `vfwnmsac.vf v4,fa1,v4'
- -.*Error: illegal operands `vfwnmsac.vf v4,fa1,v5'
- -.*Error: illegal operands `vfwnmsac.vf v0,fa1,v4,v0.t'
- -.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
- -.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
- -.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
- -.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
- -.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
- -.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
- -.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
- -.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
- -.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
- -.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
- -.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
- -.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
- -.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
- -.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
- -.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
- -.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
- -.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
- -.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
- -.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
- -.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
- -.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
- -.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
- -.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
- -.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
- -.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
- -.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
- -.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
- -.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-03.s b/gas/testsuite/gas/riscv/vector-insns-fail-03.s
- deleted file mode 100644
- index 9450b9ceb0..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-03.s
- +++ /dev/null
- @@ -1,187 +0,0 @@
- -# Widening Vector Arithmetic Instructions (V[X|F])
- -
- - vwcvt.x.x.v v0, v2 # OK
- - vwcvt.x.x.v v1, v2 # vd should be multiple of 2
- - vwcvt.x.x.v v2, v2 # vd overlap vs2
- - vwcvt.x.x.v v2, v3 # vd overlap vs2
- - vwcvt.x.x.v v0, v2, v0.t # vd overlap vm
- -
- - vwcvtu.x.x.v v0, v2 # OK
- - vwcvtu.x.x.v v1, v2 # vd should be multiple of 2
- - vwcvtu.x.x.v v2, v2 # vd overlap vs2
- - vwcvtu.x.x.v v2, v3 # vd overlap vs2
- - vwcvtu.x.x.v v0, v2, v0.t # vd overlap vm
- -
- - vwaddu.vx v0, v2, a1 # OK
- - vwaddu.vx v1, v2, a1 # vd should be multiple of 2
- - vwaddu.vx v2, v2, a1 # vd overlap vs2
- - vwaddu.vx v2, v3, a1 # vd overlap vs2
- - vwaddu.vx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwsubu.vx v0, v2, a1 # OK
- - vwsubu.vx v1, v2, a1 # vd should be multiple of 2
- - vwsubu.vx v2, v2, a1 # vd overlap vs2
- - vwsubu.vx v2, v3, a1 # vd overlap vs2
- - vwsubu.vx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwadd.vx v0, v2, a1 # OK
- - vwadd.vx v1, v2, a1 # vd should be multiple of 2
- - vwadd.vx v2, v2, a1 # vd overlap vs2
- - vwadd.vx v2, v3, a1 # vd overlap vs2
- - vwadd.vx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwsub.vx v0, v2, a1 # OK
- - vwsub.vx v1, v2, a1 # vd should be multiple of 2
- - vwsub.vx v2, v2, a1 # vd overlap vs2
- - vwsub.vx v2, v3, a1 # vd overlap vs2
- - vwsub.vx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwmul.vx v0, v2, a1 # OK
- - vwmul.vx v1, v2, a1 # vd should be multiple of 2
- - vwmul.vx v2, v2, a1 # vd overlap vs2
- - vwmul.vx v2, v3, a1 # vd overlap vs2
- - vwmul.vx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwmulu.vx v0, v2, a1 # OK
- - vwmulu.vx v1, v2, a1 # vd should be multiple of 2
- - vwmulu.vx v2, v2, a1 # vd overlap vs2
- - vwmulu.vx v2, v3, a1 # vd overlap vs2
- - vwmulu.vx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwmulsu.vx v0, v2, a1 # OK
- - vwmulsu.vx v1, v2, a1 # vd should be multiple of 2
- - vwmulsu.vx v2, v2, a1 # vd overlap vs2
- - vwmulsu.vx v2, v3, a1 # vd overlap vs2
- - vwmulsu.vx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwmaccu.vx v0, a1, v4 # OK
- - vwmaccu.vx v1, a1, v4 # vd should be multiple of 2
- - vwmaccu.vx v4, a1, v4 # vd overlap vs2
- - vwmaccu.vx v4, a1, v5 # vd overlap vs2
- - vwmaccu.vx v0, a1, v4, v0.t # vd overlap vm
- -
- - vwmacc.vx v0, a1, v4 # OK
- - vwmacc.vx v1, a1, v4 # vd should be multiple of 2
- - vwmacc.vx v4, a1, v4 # vd overlap vs2
- - vwmacc.vx v4, a1, v5 # vd overlap vs2
- - vwmacc.vx v0, a1, v4, v0.t # vd overlap vm
- -
- - vwmaccsu.vx v0, a1, v4 # OK
- - vwmaccsu.vx v1, a1, v4 # vd should be multiple of 2
- - vwmaccsu.vx v4, a1, v4 # vd overlap vs2
- - vwmaccsu.vx v4, a1, v5 # vd overlap vs2
- - vwmaccsu.vx v0, a1, v4, v0.t # vd overlap vm
- -
- - vwmaccus.vx v0, a1, v4 # OK
- - vwmaccus.vx v1, a1, v4 # vd should be multiple of 2
- - vwmaccus.vx v4, a1, v4 # vd overlap vs2
- - vwmaccus.vx v4, a1, v5 # vd overlap vs2
- - vwmaccus.vx v0, a1, v4, v0.t # vd overlap vm
- -
- - vqmaccu.vx v0, a1, v4 # OK
- - vqmaccu.vx v2, a1, v4 # vd should be multiple of 4
- - vqmaccu.vx v4, a1, v4 # vd overlap vs2
- - vqmaccu.vx v4, a1, v6 # vd overlap vs2
- - vqmaccu.vx v0, a1, v4, v0.t # vd overlap vm
- -
- - vqmacc.vx v0, a1, v4 # OK
- - vqmacc.vx v2, a1, v4 # vd should be multiple of 4
- - vqmacc.vx v4, a1, v4 # vd overlap vs2
- - vqmacc.vx v4, a1, v6 # vd overlap vs2
- - vqmacc.vx v0, a1, v4, v0.t # vd overlap vm
- -
- - vqmaccsu.vx v0, a1, v4 # OK
- - vqmaccsu.vx v2, a1, v4 # vd should be multiple of 4
- - vqmaccsu.vx v4, a1, v4 # vd overlap vs2
- - vqmaccsu.vx v4, a1, v6 # vd overlap vs2
- - vqmaccsu.vx v0, a1, v4, v0.t # vd overlap vm
- -
- - vqmaccus.vx v0, a1, v4 # OK
- - vqmaccus.vx v2, a1, v4 # vd should be multiple of 4
- - vqmaccus.vx v4, a1, v4 # vd overlap vs2
- - vqmaccus.vx v4, a1, v6 # vd overlap vs2
- - vqmaccus.vx v0, a1, v4, v0.t # vd overlap vm
- -
- - vfwadd.vf v0, v2, fa1 # OK
- - vfwadd.vf v1, v2, fa1 # vd should be multiple of 2
- - vfwadd.vf v2, v2, fa1 # vd overlap vs2
- - vfwadd.vf v2, v3, fa1 # vd overlap vs2
- - vfwadd.vf v0, v2, fa1, v0.t # vd overlap vm
- -
- - vfwsub.vf v0, v2, fa1 # OK
- - vfwsub.vf v1, v2, fa1 # vd should be multiple of 2
- - vfwsub.vf v2, v2, fa1 # vd overlap vs2
- - vfwsub.vf v2, v3, fa1 # vd overlap vs2
- - vfwsub.vf v0, v2, fa1, v0.t # vd overlap vm
- -
- - vfwmul.vf v0, v2, fa1 # OK
- - vfwmul.vf v1, v2, fa1 # vd should be multiple of 2
- - vfwmul.vf v2, v2, fa1 # vd overlap vs2
- - vfwmul.vf v2, v3, fa1 # vd overlap vs2
- - vfwmul.vf v0, v2, fa1, v0.t # vd overlap vm
- -
- - vfwmacc.vf v0, fa1, v4 # OK
- - vfwmacc.vf v1, fa1, v4 # vd should be multiple of 2
- - vfwmacc.vf v4, fa1, v4 # vd overlap vs2
- - vfwmacc.vf v4, fa1, v5 # vd overlap vs2
- - vfwmacc.vf v0, fa1, v4, v0.t # vd overlap vm
- -
- - vfwnmacc.vf v0, fa1, v4 # OK
- - vfwnmacc.vf v1, fa1, v4 # vd should be multiple of 2
- - vfwnmacc.vf v4, fa1, v4 # vd overlap vs2
- - vfwnmacc.vf v4, fa1, v5 # vd overlap vs2
- - vfwnmacc.vf v0, fa1, v4, v0.t # vd overlap vm
- -
- - vfwmsac.vf v0, fa1, v4 # OK
- - vfwmsac.vf v1, fa1, v4 # vd should be multiple of 2
- - vfwmsac.vf v4, fa1, v4 # vd overlap vs2
- - vfwmsac.vf v4, fa1, v5 # vd overlap vs2
- - vfwmsac.vf v0, fa1, v4, v0.t # vd overlap vm
- -
- - vfwnmsac.vf v0, fa1, v4 # OK
- - vfwnmsac.vf v1, fa1, v4 # vd should be multiple of 2
- - vfwnmsac.vf v4, fa1, v4 # vd overlap vs2
- - vfwnmsac.vf v4, fa1, v5 # vd overlap vs2
- - vfwnmsac.vf v0, fa1, v4, v0.t # vd overlap vm
- -
- - vfwcvt.xu.f.v v0, v2 # OK
- - vfwcvt.xu.f.v v1, v2 # vd should be multiple of 2
- - vfwcvt.xu.f.v v2, v2 # vd overlap vs2
- - vfwcvt.xu.f.v v2, v3 # vd overlap vs2
- - vfwcvt.xu.f.v v0, v2, v0.t # vd overlap vm
- -
- - vfwcvt.x.f.v v0, v2 # OK
- - vfwcvt.x.f.v v1, v2 # vd should be multiple of 2
- - vfwcvt.x.f.v v2, v2 # vd overlap vs2
- - vfwcvt.x.f.v v2, v3 # vd overlap vs2
- - vfwcvt.x.f.v v0, v2, v0.t # vd overlap vm
- -
- - vfwcvt.rtz.xu.f.v v0, v2 # OK
- - vfwcvt.rtz.xu.f.v v1, v2 # vd should be multiple of 2
- - vfwcvt.rtz.xu.f.v v2, v2 # vd overlap vs2
- - vfwcvt.rtz.xu.f.v v2, v3 # vd overlap vs2
- - vfwcvt.rtz.xu.f.v v0, v2, v0.t # vd overlap vm
- -
- - vfwcvt.rtz.x.f.v v0, v2 # OK
- - vfwcvt.rtz.x.f.v v1, v2 # vd should be multiple of 2
- - vfwcvt.rtz.x.f.v v2, v2 # vd overlap vs2
- - vfwcvt.rtz.x.f.v v2, v3 # vd overlap vs2
- - vfwcvt.rtz.x.f.v v0, v2, v0.t # vd overlap vm
- -
- - vfwcvt.f.xu.v v0, v2 # OK
- - vfwcvt.f.xu.v v1, v2 # vd should be multiple of 2
- - vfwcvt.f.xu.v v2, v2 # vd overlap vs2
- - vfwcvt.f.xu.v v2, v3 # vd overlap vs2
- - vfwcvt.f.xu.v v0, v2, v0.t # vd overlap vm
- -
- - vfwcvt.f.x.v v0, v2 # OK
- - vfwcvt.f.x.v v1, v2 # vd should be multiple of 2
- - vfwcvt.f.x.v v2, v2 # vd overlap vs2
- - vfwcvt.f.x.v v2, v3 # vd overlap vs2
- - vfwcvt.f.x.v v0, v2, v0.t # vd overlap vm
- -
- - vfwcvt.f.f.v v0, v2 # OK
- - vfwcvt.f.f.v v1, v2 # vd should be multiple of 2
- - vfwcvt.f.f.v v2, v2 # vd overlap vs2
- - vfwcvt.f.f.v v2, v3 # vd overlap vs2
- - vfwcvt.f.f.v v0, v2, v0.t # vd overlap vm
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.d b/gas/testsuite/gas/riscv/vector-insns-fail-04.d
- deleted file mode 100644
- index d483884544..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-04.d
- +++ /dev/null
- @@ -1,3 +0,0 @@
- -#as: -march=rv32ifv -mcheck-constraints
- -#source: vector-insns-fail-04.s
- -#error_output: vector-insns-fail-04.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.l b/gas/testsuite/gas/riscv/vector-insns-fail-04.l
- deleted file mode 100644
- index 9a9c76c19d..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-04.l
- +++ /dev/null
- @@ -1,49 +0,0 @@
- -.*: Assembler messages:
- -.*Error: illegal operands `vwaddu.wv v1,v2,v4'
- -.*Error: illegal operands `vwaddu.wv v2,v3,v4'
- -.*Error: illegal operands `vwaddu.wv v4,v2,v4'
- -.*Error: illegal operands `vwaddu.wv v4,v2,v5'
- -.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwsubu.wv v1,v2,v4'
- -.*Error: illegal operands `vwsubu.wv v2,v3,v4'
- -.*Error: illegal operands `vwsubu.wv v4,v2,v4'
- -.*Error: illegal operands `vwsubu.wv v4,v2,v5'
- -.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwadd.wv v1,v2,v4'
- -.*Error: illegal operands `vwadd.wv v2,v3,v4'
- -.*Error: illegal operands `vwadd.wv v4,v2,v4'
- -.*Error: illegal operands `vwadd.wv v4,v2,v5'
- -.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwsub.wv v1,v2,v4'
- -.*Error: illegal operands `vwsub.wv v2,v3,v4'
- -.*Error: illegal operands `vwsub.wv v4,v2,v4'
- -.*Error: illegal operands `vwsub.wv v4,v2,v5'
- -.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vfwadd.wv v1,v2,v4'
- -.*Error: illegal operands `vfwadd.wv v2,v3,v4'
- -.*Error: illegal operands `vfwadd.wv v4,v2,v4'
- -.*Error: illegal operands `vfwadd.wv v4,v2,v5'
- -.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vfwsub.wv v1,v2,v4'
- -.*Error: illegal operands `vfwsub.wv v2,v3,v4'
- -.*Error: illegal operands `vfwsub.wv v4,v2,v4'
- -.*Error: illegal operands `vfwsub.wv v4,v2,v5'
- -.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vwaddu.wx v1,v2,a1'
- -.*Error: illegal operands `vwaddu.wx v2,v3,a1'
- -.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwsubu.wx v1,v2,a1'
- -.*Error: illegal operands `vwsubu.wx v2,v3,a1'
- -.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwadd.wx v1,v2,a1'
- -.*Error: illegal operands `vwadd.wx v2,v3,a1'
- -.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vwsub.wx v1,v2,a1'
- -.*Error: illegal operands `vwsub.wx v2,v3,a1'
- -.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
- -.*Error: illegal operands `vfwadd.wf v1,v2,fa1'
- -.*Error: illegal operands `vfwadd.wf v2,v3,fa1'
- -.*Error: illegal operands `vfwadd.wf v0,v2,fa1,v0.t'
- -.*Error: illegal operands `vfwsub.wf v1,v2,fa1'
- -.*Error: illegal operands `vfwsub.wf v2,v3,fa1'
- -.*Error: illegal operands `vfwsub.wf v0,v2,fa1,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-04.s b/gas/testsuite/gas/riscv/vector-insns-fail-04.s
- deleted file mode 100644
- index e1db16d53b..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-04.s
- +++ /dev/null
- @@ -1,85 +0,0 @@
- -# Widening Vector Arithmetic Instructions (W[V|X])
- -
- - vwaddu.wv v0, v2, v4 # OK
- - vwaddu.wv v1, v2, v4 # vd should be multiple of 2
- - vwaddu.wv v2, v2, v4 # OK
- - vwaddu.wv v2, v3, v4 # vs2 should be multiple of 2
- - vwaddu.wv v4, v2, v4 # vd overlap vs1
- - vwaddu.wv v4, v2, v5 # vd overlap vs1
- - vwaddu.wv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwsubu.wv v0, v2, v4 # OK
- - vwsubu.wv v1, v2, v4 # vd should be multiple of 2
- - vwsubu.wv v2, v2, v4 # OK
- - vwsubu.wv v2, v3, v4 # vs2 should be multiple of 2
- - vwsubu.wv v4, v2, v4 # vd overlap vs1
- - vwsubu.wv v4, v2, v5 # vd overlap vs1
- - vwsubu.wv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwadd.wv v0, v2, v4 # OK
- - vwadd.wv v1, v2, v4 # vd should be multiple of 2
- - vwadd.wv v2, v2, v4 # OK
- - vwadd.wv v2, v3, v4 # vs2 should be multiple of 2
- - vwadd.wv v4, v2, v4 # vd overlap vs1
- - vwadd.wv v4, v2, v5 # vd overlap vs1
- - vwadd.wv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwsub.wv v0, v2, v4 # OK
- - vwsub.wv v1, v2, v4 # vd should be multiple of 2
- - vwsub.wv v2, v2, v4 # OK
- - vwsub.wv v2, v3, v4 # vs2 should be multiple of 2
- - vwsub.wv v4, v2, v4 # vd overlap vs1
- - vwsub.wv v4, v2, v5 # vd overlap vs1
- - vwsub.wv v0, v2, v4, v0.t # vd overlap vm
- -
- - vfwadd.wv v0, v2, v4 # OK
- - vfwadd.wv v1, v2, v4 # vd should be multiple of 2
- - vfwadd.wv v2, v2, v4 # OK
- - vfwadd.wv v2, v3, v4 # vs2 should be multiple of 2
- - vfwadd.wv v4, v2, v4 # vd overlap vs1
- - vfwadd.wv v4, v2, v5 # vd overlap vs1
- - vfwadd.wv v0, v2, v4, v0.t # vd overlap vm
- -
- - vfwsub.wv v0, v2, v4 # OK
- - vfwsub.wv v1, v2, v4 # vd should be multiple of 2
- - vfwsub.wv v2, v2, v4 # OK
- - vfwsub.wv v2, v3, v4 # vs2 should be multiple of 2
- - vfwsub.wv v4, v2, v4 # vd overlap vs1
- - vfwsub.wv v4, v2, v5 # vd overlap vs1
- - vfwsub.wv v0, v2, v4, v0.t # vd overlap vm
- -
- - vwaddu.wx v0, v2, a1 # OK
- - vwaddu.wx v1, v2, a1 # vd should be multiple of 2
- - vwaddu.wx v2, v2, a1 # OK
- - vwaddu.wx v2, v3, a1 # vs2 should be multiple of 2
- - vwaddu.wx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwsubu.wx v0, v2, a1 # OK
- - vwsubu.wx v1, v2, a1 # vd should be multiple of 2
- - vwsubu.wx v2, v2, a1 # OK
- - vwsubu.wx v2, v3, a1 # vs2 should be multiple of 2
- - vwsubu.wx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwadd.wx v0, v2, a1 # OK
- - vwadd.wx v1, v2, a1 # vd should be multiple of 2
- - vwadd.wx v2, v2, a1 # OK
- - vwadd.wx v2, v3, a1 # vs2 should be multiple of 2
- - vwadd.wx v0, v2, a1, v0.t # vd overlap vm
- -
- - vwsub.wx v0, v2, a1 # OK
- - vwsub.wx v1, v2, a1 # vd should be multiple of 2
- - vwsub.wx v2, v2, a1 # OK
- - vwsub.wx v2, v3, a1 # vs2 should be multiple of 2
- - vwsub.wx v0, v2, a1, v0.t # vd overlap vm
- -
- - vfwadd.wf v0, v2, fa1 # OK
- - vfwadd.wf v1, v2, fa1 # vd should be multiple of 2
- - vfwadd.wf v2, v2, fa1 # OK
- - vfwadd.wf v2, v3, fa1 # vs2 should be multiple of 2
- - vfwadd.wf v0, v2, fa1, v0.t # vd overlap vm
- -
- - vfwsub.wf v0, v2, fa1 # OK
- - vfwsub.wf v1, v2, fa1 # vd should be multiple of 2
- - vfwsub.wf v2, v2, fa1 # OK
- - vfwsub.wf v2, v3, fa1 # vs2 should be multiple of 2
- - vfwsub.wf v0, v2, fa1, v0.t # vd overlap vm
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.d b/gas/testsuite/gas/riscv/vector-insns-fail-05.d
- deleted file mode 100644
- index b13053ab06..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-05.d
- +++ /dev/null
- @@ -1,3 +0,0 @@
- -#as: -march=rv32ifv -mcheck-constraints
- -#source: vector-insns-fail-05.s
- -#error_output: vector-insns-fail-05.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.s b/gas/testsuite/gas/riscv/vector-insns-fail-05.s
- deleted file mode 100644
- index 6b68680fd9..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-05.s
- +++ /dev/null
- @@ -1,139 +0,0 @@
- -# Narrowing Vector Arithmetic Instructions
- -
- - vncvt.x.x.v v0, v2 # OK
- - vncvt.x.x.v v2, v2 # vd overlap vs2
- - vncvt.x.x.v v2, v3 # vs2 should be multiple of 2
- - vncvt.x.x.v v3, v2 # vd overlap vs2
- - vncvt.x.x.v v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnsrl.wv v0, v2, v4 # OK
- - vnsrl.wv v2, v2, v4 # vd overlap vs2
- - vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
- - vnsrl.wv v3, v2, v4 # vd overlap vs2
- - vnsrl.wv v4, v2, v4 # OK
- - vnsrl.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnsrl.wx v0, v2, a1 # OK
- - vnsrl.wx v2, v2, a1 # vd overlap vs2
- - vnsrl.wx v2, v3, a1 # vs2 should be multiple of 2
- - vnsrl.wx v3, v2, a1 # vd overlap vs2
- - vnsrl.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnsrl.wi v0, v2, 1 # OK
- - vnsrl.wi v2, v2, 1 # vd overlap vs2
- - vnsrl.wi v2, v3, 1 # vs2 should be multiple of 2
- - vnsrl.wi v3, v2, 1 # vd overlap vs2
- - vnsrl.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnsra.wv v0, v2, v4 # OK
- - vnsra.wv v2, v2, v4 # vd overlap vs2
- - vnsra.wv v2, v3, v4 # vs2 should be multiple of 2
- - vnsra.wv v3, v2, v4 # vd overlap vs2
- - vnsra.wv v4, v2, v4 # OK
- - vnsra.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnsra.wx v0, v2, a1 # OK
- - vnsra.wx v2, v2, a1 # vd overlap vs2
- - vnsra.wx v2, v3, a1 # vs2 should be multiple of 2
- - vnsra.wx v3, v2, a1 # vd overlap vs2
- - vnsra.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnsra.wi v0, v2, 1 # OK
- - vnsra.wi v2, v2, 1 # vd overlap vs2
- - vnsra.wi v2, v3, 1 # vs2 should be multiple of 2
- - vnsra.wi v3, v2, 1 # vd overlap vs2
- - vnsra.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnclipu.wv v0, v2, v4 # OK
- - vnclipu.wv v2, v2, v4 # vd overlap vs2
- - vnclipu.wv v2, v3, v4 # vs2 should be multiple of 2
- - vnclipu.wv v3, v2, v4 # vd overlap vs2
- - vnclipu.wv v4, v2, v4 # OK
- - vnclipu.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnclipu.wx v0, v2, a1 # OK
- - vnclipu.wx v2, v2, a1 # vd overlap vs2
- - vnclipu.wx v2, v3, a1 # vs2 should be multiple of 2
- - vnclipu.wx v3, v2, a1 # vd overlap vs2
- - vnclipu.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnclipu.wi v0, v2, 1 # OK
- - vnclipu.wi v2, v2, 1 # vd overlap vs2
- - vnclipu.wi v2, v3, 1 # vs2 should be multiple of 2
- - vnclipu.wi v3, v2, 1 # vd overlap vs2
- - vnclipu.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnclip.wv v0, v2, v4 # OK
- - vnclip.wv v2, v2, v4 # vd overlap vs2
- - vnclip.wv v2, v3, v4 # vs2 should be multiple of 2
- - vnclip.wv v3, v2, v4 # vd overlap vs2
- - vnclip.wv v4, v2, v4 # OK
- - vnclip.wv v0, v2, v4, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnclip.wx v0, v2, a1 # OK
- - vnclip.wx v2, v2, a1 # vd overlap vs2
- - vnclip.wx v2, v3, a1 # vs2 should be multiple of 2
- - vnclip.wx v3, v2, a1 # vd overlap vs2
- - vnclip.wx v0, v2, a1, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vnclip.wi v0, v2, 1 # OK
- - vnclip.wi v2, v2, 1 # vd overlap vs2
- - vnclip.wi v2, v3, 1 # vs2 should be multiple of 2
- - vnclip.wi v3, v2, 1 # vd overlap vs2
- - vnclip.wi v0, v2, 1, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vfncvt.xu.f.w v0, v2 # OK
- - vfncvt.xu.f.w v2, v2 # vd overlap vs2
- - vfncvt.xu.f.w v2, v3 # vs2 should be multiple of 2
- - vfncvt.xu.f.w v3, v2 # vd overlap vs2
- - vfncvt.xu.f.w v4, v2 # OK
- - vfncvt.xu.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vfncvt.x.f.w v0, v2 # OK
- - vfncvt.x.f.w v2, v2 # vd overlap vs2
- - vfncvt.x.f.w v2, v3 # vs2 should be multiple of 2
- - vfncvt.x.f.w v3, v2 # vd overlap vs2
- - vfncvt.x.f.w v4, v2 # OK
- - vfncvt.x.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vfncvt.rtz.xu.f.w v0, v2 # OK
- - vfncvt.rtz.xu.f.w v2, v2 # vd overlap vs2
- - vfncvt.rtz.xu.f.w v2, v3 # vs2 should be multiple of 2
- - vfncvt.rtz.xu.f.w v3, v2 # vd overlap vs2
- - vfncvt.rtz.xu.f.w v4, v2 # OK
- - vfncvt.rtz.xu.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vfncvt.rtz.x.f.w v0, v2 # OK
- - vfncvt.rtz.x.f.w v2, v2 # vd overlap vs2
- - vfncvt.rtz.x.f.w v2, v3 # vs2 should be multiple of 2
- - vfncvt.rtz.x.f.w v3, v2 # vd overlap vs2
- - vfncvt.rtz.x.f.w v4, v2 # OK
- - vfncvt.rtz.x.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vfncvt.f.xu.w v0, v2 # OK
- - vfncvt.f.xu.w v2, v2 # vd overlap vs2
- - vfncvt.f.xu.w v2, v3 # vs2 should be multiple of 2
- - vfncvt.f.xu.w v3, v2 # vd overlap vs2
- - vfncvt.f.xu.w v4, v2 # OK
- - vfncvt.f.xu.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vfncvt.f.x.w v0, v2 # OK
- - vfncvt.f.x.w v2, v2 # vd overlap vs2
- - vfncvt.f.x.w v2, v3 # vs2 should be multiple of 2
- - vfncvt.f.x.w v3, v2 # vd overlap vs2
- - vfncvt.f.x.w v4, v2 # OK
- - vfncvt.f.x.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vfncvt.f.f.w v0, v2 # OK
- - vfncvt.f.f.w v2, v2 # vd overlap vs2
- - vfncvt.f.f.w v2, v3 # vs2 should be multiple of 2
- - vfncvt.f.f.w v3, v2 # vd overlap vs2
- - vfncvt.f.f.w v4, v2 # OK
- - vfncvt.f.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- -
- - vfncvt.rod.f.f.w v0, v2 # OK
- - vfncvt.rod.f.f.w v2, v2 # vd overlap vs2
- - vfncvt.rod.f.f.w v2, v3 # vs2 should be multiple of 2
- - vfncvt.rod.f.f.w v3, v2 # vd overlap vs2
- - vfncvt.rod.f.f.w v4, v2 # OK
- - vfncvt.rod.f.f.w v0, v2, v0.t # We can't know the LMUL, so skip the vm checking
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.d b/gas/testsuite/gas/riscv/vector-insns-fail-06.d
- deleted file mode 100644
- index a2a2220d68..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-06.d
- +++ /dev/null
- @@ -1,3 +0,0 @@
- -#as: -march=rv32ifv -mcheck-constraints
- -#source: vector-insns-fail-06.s
- -#error_output: vector-insns-fail-06.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.l b/gas/testsuite/gas/riscv/vector-insns-fail-06.l
- deleted file mode 100644
- index 4c540eb272..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-06.l
- +++ /dev/null
- @@ -1,25 +0,0 @@
- -.*: Assembler messages:
- -.*Error: illegal operands `viota.m v2,v2'
- -.*Error: illegal operands `viota.m v0,v2,v0.t'
- -.*Error: illegal operands `vslideup.vx v2,v2,a4'
- -.*Error: illegal operands `vslideup.vi v2,v2,1'
- -.*Error: illegal operands `vslide1up.vx v2,v2,a4'
- -.*Error: illegal operands `vfslide1up.vf v2,v2,fa4'
- -.*Error: illegal operands `vrgather.vv v2,v2,v4'
- -.*Error: illegal operands `vrgather.vv v4,v2,v4'
- -.*Error: illegal operands `vrgather.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vrgather.vx v2,v2,a4'
- -.*Error: illegal operands `vrgather.vx v0,v2,a4,v0.t'
- -.*Error: illegal operands `vrgather.vi v2,v2,1'
- -.*Error: illegal operands `vrgather.vi v0,v2,1,v0.t'
- -.*Error: illegal operands `vrgatherei16.vv v2,v2,v4'
- -.*Error: illegal operands `vrgatherei16.vv v4,v2,v4'
- -.*Error: illegal operands `vrgatherei16.vv v0,v2,v4,v0.t'
- -.*Error: illegal operands `vcompress.vm v2,v2,v4'
- -.*Error: illegal operands `vcompress.vm v4,v2,v4'
- -.*Error: illegal operands `vmv2r.v v1,v2'
- -.*Error: illegal operands `vmv2r.v v2,v3'
- -.*Error: illegal operands `vmv4r.v v2,v4'
- -.*Error: illegal operands `vmv4r.v v4,v7'
- -.*Error: illegal operands `vmv8r.v v6,v8'
- -.*Error: illegal operands `vmv8r.v v8,v12'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-06.s b/gas/testsuite/gas/riscv/vector-insns-fail-06.s
- deleted file mode 100644
- index 3a35aadb49..0000000000
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-06.s
- +++ /dev/null
- @@ -1,73 +0,0 @@
- -# Vector Iota Instruction
- -# Vector Slideup Instructions
- -# Vector Slide1up
- -# Vector Register Gather Instruction
- -# Vector Compress Instruction
- -# Vector Load/Store Whole Register Instructions
- -# Whole Vector Register Move
- -
- - viota.m v0, v2 # OK
- - viota.m v2, v2 # vd overlap vs2
- - viota.m v0, v2, v0.t # vd overlap vm
- -
- - vslideup.vx v0, v2, a4 # OK
- - vslideup.vx v1, v2, a4 # OK
- - vslideup.vx v2, v2, a4 # vd overlap vs2
- - vslideup.vx v0, v2, a4, v0.t # vd overlap vm
- -
- - vslideup.vi v0, v2, 1 # OK
- - vslideup.vi v1, v2, 1 # OK
- - vslideup.vi v2, v2, 1 # vd overlap vs2
- - vslideup.vi v0, v2, 1, v0.t # vd overlap vm
- -
- - vslide1up.vx v0, v2, a4 # OK
- - vslide1up.vx v1, v2, a4 # OK
- - vslide1up.vx v2, v2, a4 # vd overlap vs2
- - vslide1up.vx v0, v2, a4, v0.t # vd overlap vm
- -
- - vfslide1up.vf v0, v2, fa4 # OK
- - vfslide1up.vf v1, v2, fa4 # OK
- - vfslide1up.vf v2, v2, fa4 # vd overlap vs2
- - vfslide1up.vf v0, v2, fa4, v0.t # vd overlap vm
- -
- - vrgather.vv v0, v2, v4 # OK
- - vrgather.vv v1, v2, v4 # OK
- - vrgather.vv v2, v2, v4 # vd overlap vs2
- - vrgather.vv v4, v2, v4 # vd overlap vs1
- - vrgather.vv v0, v2, v4, v0.t # vd overlap vm
- -
- - vrgather.vx v0, v2, a4 # OK
- - vrgather.vx v1, v2, a4 # OK
- - vrgather.vx v2, v2, a4 # vd overlap vs2
- - vrgather.vx v0, v2, a4, v0.t # vd overlap vm
- -
- - vrgather.vi v0, v2, 1 # OK
- - vrgather.vi v1, v2, 1 # OK
- - vrgather.vi v2, v2, 1 # vd overlap vs2
- - vrgather.vi v0, v2, 1, v0.t # vd overlap vm
- -
- - vrgatherei16.vv v0, v2, v4 # OK
- - vrgatherei16.vv v1, v2, v4 # OK
- - vrgatherei16.vv v2, v2, v4 # vd overlap vs2
- - vrgatherei16.vv v4, v2, v4 # vd overlap vs1
- - vrgatherei16.vv v0, v2, v4, v0.t# vd overlap vm
- -
- - vcompress.vm v0, v2, v4 # OK
- - vcompress.vm v1, v2, v4 # OK
- - vcompress.vm v2, v2, v4 # vd overlap vs2
- - vcompress.vm v4, v2, v4 # vd overlap vs1
- -
- - vmv1r.v v0, v1 # OK
- - vmv1r.v v2, v3 # OK
- -
- - vmv2r.v v0, v2 # OK
- - vmv2r.v v1, v2 # vd must be aligned to 2
- - vmv2r.v v2, v3 # vs2 must be aligned to 2
- -
- - vmv4r.v v0, v4 # OK
- - vmv4r.v v2, v4 # vd must be aligned to 4
- - vmv4r.v v4, v7 # vs2 must be aligned to 4
- -
- - vmv8r.v v0, v8 # OK
- - vmv8r.v v6, v8 # vd must be aligned to 8
- - vmv8r.v v8, v12 # vs2 must be aligned to 8
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
- new file mode 100644
- index 0000000000..df48418486
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32iv -mcheck-constraints
- +#source: vector-insns-fail-arith-fixp.s
- +#error_output: vector-insns-fail-arith-fixp.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
- new file mode 100644
- index 0000000000..a3c126d8ec
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
- @@ -0,0 +1,27 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vsaddu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vsaddu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vsaddu.vi v0,v4,15,v0.t'
- +.*Error: illegal operands `vsadd.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vsadd.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vsadd.vi v0,v4,15,v0.t'
- +.*Error: illegal operands `vssubu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vssubu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vssub.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vssub.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vaaddu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vaaddu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vaadd.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vaadd.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vasubu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vasubu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vasub.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vasub.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vsmul.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vsmul.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vssrl.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vssrl.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vssrl.vi v0,v4,31,v0.t'
- +.*Error: illegal operands `vssra.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vssra.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vssra.vi v0,v4,31,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
- new file mode 100644
- index 0000000000..1fbcb601ea
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
- @@ -0,0 +1,81 @@
- +# Vector Single-Width Saturating Add and Subtract
- +
- + vsaddu.vv v4, v4, v8 # OK
- + vsaddu.vv v8, v4, v8 # OK
- + vsaddu.vv v0, v4, v8, v0.t # vd overlap vm
- + vsaddu.vx v4, v4, a1 # OK
- + vsaddu.vx v0, v4, a1, v0.t # vd overlap vm
- + vsaddu.vi v4, v4, 15 # OK
- + vsaddu.vi v0, v4, 15, v0.t # vd overlap vm
- +
- + vsadd.vv v4, v4, v8
- + vsadd.vv v8, v4, v8
- + vsadd.vv v0, v4, v8, v0.t
- + vsadd.vx v4, v4, a1
- + vsadd.vx v0, v4, a1, v0.t
- + vsadd.vi v4, v4, 15
- + vsadd.vi v0, v4, 15, v0.t
- +
- + vssubu.vv v4, v4, v8 # OK
- + vssubu.vv v8, v4, v8 # OK
- + vssubu.vv v0, v4, v8, v0.t # vd overlap vm
- + vssubu.vx v4, v4, a1 # OK
- + vssubu.vx v0, v4, a1, v0.t # vd overlap vm
- +
- + vssub.vv v4, v4, v8
- + vssub.vv v8, v4, v8
- + vssub.vv v0, v4, v8, v0.t
- + vssub.vx v4, v4, a1
- + vssub.vx v0, v4, a1, v0.t
- +
- +# Vector Single-Width Averaging Add and Subtract
- +
- + vaaddu.vv v4, v4, v8 # OK
- + vaaddu.vv v8, v4, v8 # OK
- + vaaddu.vv v0, v4, v8, v0.t # vd overlap vm
- + vaaddu.vx v4, v4, a1 # OK
- + vaaddu.vx v0, v4, a1, v0.t # vd overlap vm
- +
- + vaadd.vv v4, v4, v8
- + vaadd.vv v8, v4, v8
- + vaadd.vv v0, v4, v8, v0.t
- + vaadd.vx v4, v4, a1
- + vaadd.vx v0, v4, a1, v0.t
- +
- + vasubu.vv v4, v4, v8
- + vasubu.vv v8, v4, v8
- + vasubu.vv v0, v4, v8, v0.t
- + vasubu.vx v4, v4, a1
- + vasubu.vx v0, v4, a1, v0.t
- +
- + vasub.vv v4, v4, v8
- + vasub.vv v8, v4, v8
- + vasub.vv v0, v4, v8, v0.t
- + vasub.vx v4, v4, a1
- + vasub.vx v0, v4, a1, v0.t
- +
- +# Vector Single-Width Fractional Multiply with Rounding and Saturation
- +
- + vsmul.vv v4, v4, v8 # OK
- + vsmul.vv v8, v4, v8 # OK
- + vsmul.vv v0, v4, v8, v0.t # vd overlap vm
- + vsmul.vx v4, v4, a1 # OK
- + vsmul.vx v0, v4, a1, v0.t # vd overlap vm
- +
- +# Vector Single-Width Scaling Shift Instructions
- +
- + vssrl.vv v4, v4, v8 # OK
- + vssrl.vv v8, v4, v8 # OK
- + vssrl.vv v0, v4, v8, v0.t # vd overlap vm
- + vssrl.vx v4, v4, a1 # OK
- + vssrl.vx v0, v4, a1, v0.t # vd overlap vm
- + vssrl.vi v4, v4, 31 # OK
- + vssrl.vi v0, v4, 31, v0.t # vd overlap vm
- +
- + vssra.vv v4, v4, v8
- + vssra.vv v8, v4, v8
- + vssra.vv v0, v4, v8, v0.t
- + vssra.vx v4, v4, a1
- + vssra.vx v0, v4, a1, v0.t
- + vssra.vi v4, v4, 31
- + vssra.vi v0, v4, 31, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
- new file mode 100644
- index 0000000000..796f7e2ded
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv -mcheck-constraints
- +#source: vector-insns-fail-arith-floatp.s
- +#error_output: vector-insns-fail-arith-floatp.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
- new file mode 100644
- index 0000000000..0fc28a82d7
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
- @@ -0,0 +1,47 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vfadd.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfadd.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfsub.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfsub.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfrsub.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfmul.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfmul.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfdiv.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfdiv.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfrdiv.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfmacc.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfmacc.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfnmacc.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfnmacc.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfmsac.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfmsac.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfnmsac.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfnmsac.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfmadd.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfmadd.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfnmadd.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfnmadd.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfmsub.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfmsub.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfnmsub.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfnmsub.vf v0,fa1,v4,v0.t'
- +.*Error: illegal operands `vfsqrt.v v0,v4,v0.t'
- +.*Error: illegal operands `vfrece7.v v0,v4,v0.t'
- +.*Error: illegal operands `vfrsqrte7.v v0,v4,v0.t'
- +.*Error: illegal operands `vfclass.v v0,v4,v0.t'
- +.*Error: illegal operands `vfmin.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfmin.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfmax.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfmax.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfsgnj.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfsgnj.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfsgnjn.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfsgnjn.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfsgnjx.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vfsgnjx.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vfcvt.xu.f.v v0,v4,v0.t'
- +.*Error: illegal operands `vfcvt.x.f.v v0,v4,v0.t'
- +.*Error: illegal operands `vfcvt.rtz.xu.f.v v0,v4,v0.t'
- +.*Error: illegal operands `vfcvt.rtz.x.f.v v0,v4,v0.t'
- +.*Error: illegal operands `vfcvt.f.xu.v v0,v4,v0.t'
- +.*Error: illegal operands `vfcvt.f.x.v v0,v4,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
- new file mode 100644
- index 0000000000..3231c35ada
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
- @@ -0,0 +1,152 @@
- +# Vector Single-Width Floating-Point Add/Subtract Instructions
- +
- + vfadd.vv v4, v4, v8 # OK
- + vfadd.vv v8, v4, v8 # OK
- + vfadd.vv v0, v4, v8, v0.t # vd overlap vm
- + vfadd.vf v4, v4, fa1 # OK
- + vfadd.vf v0, v4, fa1, v0.t # vd overlap vm
- +
- + vfsub.vv v4, v4, v8
- + vfsub.vv v8, v4, v8
- + vfsub.vv v0, v4, v8, v0.t
- + vfsub.vf v4, v4, fa1
- + vfsub.vf v0, v4, fa1, v0.t
- +
- + vfrsub.vf v4, v4, fa1 # OK
- + vfrsub.vf v0, v4, fa1, v0.t # vd overlap vm
- +
- +# Vector Single-Width Floating-Point Multiply/Divide Instructions
- +
- + vfmul.vv v4, v4, v8 # OK
- + vfmul.vv v8, v4, v8 # OK
- + vfmul.vv v0, v4, v8, v0.t # vd overlap vm
- + vfmul.vf v4, v4, fa1 # OK
- + vfmul.vf v0, v4, fa1, v0.t # vd overlap vm
- +
- + vfdiv.vv v4, v4, v8
- + vfdiv.vv v8, v4, v8
- + vfdiv.vv v0, v4, v8, v0.t
- + vfdiv.vf v4, v4, fa1
- + vfdiv.vf v0, v4, fa1, v0.t
- +
- + vfrdiv.vf v4, v4, fa1 # OK
- + vfrdiv.vf v0, v4, fa1, v0.t # vd overlap vm
- +
- +# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
- +
- + vfmacc.vv v4, v4, v8 # OK
- + vfmacc.vv v8, v4, v8 # OK
- + vfmacc.vv v0, v4, v8, v0.t # vd overlap vm
- + vfmacc.vf v4, fa1, v4 # OK
- + vfmacc.vf v0, fa1, v4, v0.t # vd overlap vm
- +
- + vfnmacc.vv v4, v4, v8
- + vfnmacc.vv v8, v4, v8
- + vfnmacc.vv v0, v4, v8, v0.t
- + vfnmacc.vf v4, fa1, v4
- + vfnmacc.vf v0, fa1, v4, v0.t
- +
- + vfmsac.vv v4, v4, v8
- + vfmsac.vv v8, v4, v8
- + vfmsac.vv v0, v4, v8, v0.t
- + vfmsac.vf v4, fa1, v4
- + vfmsac.vf v0, fa1, v4, v0.t
- +
- + vfnmsac.vv v4, v4, v8
- + vfnmsac.vv v8, v4, v8
- + vfnmsac.vv v0, v4, v8, v0.t
- + vfnmsac.vf v4, fa1, v4
- + vfnmsac.vf v0, fa1, v4, v0.t
- +
- + vfmadd.vv v4, v4, v8
- + vfmadd.vv v8, v4, v8
- + vfmadd.vv v0, v4, v8, v0.t
- + vfmadd.vf v4, fa1, v4
- + vfmadd.vf v0, fa1, v4, v0.t
- +
- + vfnmadd.vv v4, v4, v8
- + vfnmadd.vv v8, v4, v8
- + vfnmadd.vv v0, v4, v8, v0.t
- + vfnmadd.vf v4, fa1, v4
- + vfnmadd.vf v0, fa1, v4, v0.t
- +
- + vfmsub.vv v4, v4, v8
- + vfmsub.vv v8, v4, v8
- + vfmsub.vv v0, v4, v8, v0.t
- + vfmsub.vf v4, fa1, v4
- + vfmsub.vf v0, fa1, v4, v0.t
- +
- + vfnmsub.vv v4, v4, v8
- + vfnmsub.vv v8, v4, v8
- + vfnmsub.vv v0, v4, v8, v0.t
- + vfnmsub.vf v4, fa1, v4
- + vfnmsub.vf v0, fa1, v4, v0.t
- +
- +# Vector Floating-Point Square-Root Instruction
- +
- + vfsqrt.v v4, v4 # OK
- + vfsqrt.v v0, v4, v0.t # vd overlap vm
- +
- +# Vector Floating-Point Reciprocal Estimate Instruction
- +
- + vfrece7.v v4, v4 # OK
- + vfrece7.v v0, v4, v0.t # vd overlap vm
- +
- +# Vector Floating-Point Reciprocal Square-Root Estimate Instruction
- +
- + vfrsqrte7.v v4, v4 # OK
- + vfrsqrte7.v v0, v4, v0.t # vd overlap vm
- +
- +# Vector Floating-Point Classify Instruction
- +
- + vfclass.v v4, v4 # OK
- + vfclass.v v0, v4, v0.t # vd overlap vm
- +
- +# Vector Floating-Point MIN/MAX Instructions
- +
- + vfmin.vv v4, v4, v8 # OK
- + vfmin.vv v8, v4, v8 # OK
- + vfmin.vv v0, v4, v8, v0.t # vd overlap vm
- + vfmin.vf v4, v4, fa1 # OK
- + vfmin.vf v0, v4, fa1, v0.t # vd overlap vm
- +
- + vfmax.vv v4, v4, v8
- + vfmax.vv v8, v4, v8
- + vfmax.vv v0, v4, v8, v0.t
- + vfmax.vf v4, v4, fa1
- + vfmax.vf v0, v4, fa1, v0.t
- +
- +# Vector Floating-Point Sign-Injection Instructions
- +
- + vfsgnj.vv v4, v4, v8 # OK
- + vfsgnj.vv v8, v4, v8 # OK
- + vfsgnj.vv v0, v4, v8, v0.t # vd overlap vm
- + vfsgnj.vf v4, v4, fa1 # OK
- + vfsgnj.vf v0, v4, fa1, v0.t # vd overlap vm
- +
- + vfsgnjn.vv v4, v4, v8
- + vfsgnjn.vv v8, v4, v8
- + vfsgnjn.vv v0, v4, v8, v0.t
- + vfsgnjn.vf v4, v4, fa1
- + vfsgnjn.vf v0, v4, fa1, v0.t
- +
- + vfsgnjx.vv v4, v4, v8
- + vfsgnjx.vv v8, v4, v8
- + vfsgnjx.vv v0, v4, v8, v0.t
- + vfsgnjx.vf v4, v4, fa1
- + vfsgnjx.vf v0, v4, fa1, v0.t
- +
- +# Single-Width Floating-Point/Integer Type-Convert Instructions
- +
- + vfcvt.xu.f.v v4, v4 # OK
- + vfcvt.xu.f.v v0, v4, v0.t # vd overlap vm
- + vfcvt.x.f.v v4, v4
- + vfcvt.x.f.v v0, v4, v0.t
- + vfcvt.rtz.xu.f.v v4, v4
- + vfcvt.rtz.xu.f.v v0, v4, v0.t
- + vfcvt.rtz.x.f.v v4, v4
- + vfcvt.rtz.x.f.v v0, v4, v0.t
- + vfcvt.f.xu.v v4, v4
- + vfcvt.f.xu.v v0, v4, v0.t
- + vfcvt.f.x.v v4, v4
- + vfcvt.f.x.v v0, v4, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
- new file mode 100644
- index 0000000000..55b350bc85
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32iv -mcheck-constraints
- +#source: vector-insns-fail-arith-int.s
- +#error_output: vector-insns-fail-arith-int.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
- new file mode 100644
- index 0000000000..480406af93
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
- @@ -0,0 +1,70 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vadd.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vadd.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vadd.vi v0,v4,15,v0.t'
- +.*Error: illegal operands `vsub.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vsub.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vrsub.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vrsub.vi v0,v4,15,v0.t'
- +.*Error: illegal operands `vzext.vf2 v0,v4,v0.t'
- +.*Error: illegal operands `vsext.vf2 v0,v4,v0.t'
- +.*Error: illegal operands `vzext.vf4 v0,v4,v0.t'
- +.*Error: illegal operands `vsext.vf4 v0,v4,v0.t'
- +.*Error: illegal operands `vzext.vf8 v0,v4,v0.t'
- +.*Error: illegal operands `vsext.vf8 v0,v4,v0.t'
- +.*Error: illegal operands `vadc.vvm v0,v4,v8,v0'
- +.*Error: illegal operands `vadc.vxm v0,v4,a1,v0'
- +.*Error: illegal operands `vadc.vim v0,v4,15,v0'
- +.*Error: illegal operands `vsbc.vvm v0,v4,v8,v0'
- +.*Error: illegal operands `vsbc.vxm v0,v4,a1,v0'
- +.*Error: illegal operands `vnot.v v0,v4,v0.t'
- +.*Error: illegal operands `vand.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vand.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vand.vi v0,v4,15,v0.t'
- +.*Error: illegal operands `vor.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vor.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vor.vi v0,v4,15,v0.t'
- +.*Error: illegal operands `vxor.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vxor.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vxor.vi v0,v4,15,v0.t'
- +.*Error: illegal operands `vsll.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vsll.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vsll.vi v0,v4,31,v0.t'
- +.*Error: illegal operands `vsrl.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vsrl.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vsrl.vi v0,v4,31,v0.t'
- +.*Error: illegal operands `vsra.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vsra.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vsra.vi v0,v4,31,v0.t'
- +.*Error: illegal operands `vminu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vminu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vmin.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vmin.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vmaxu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vmaxu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vmax.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vmax.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vmul.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vmul.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vmulh.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vmulh.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vmulhu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vmulhu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vmulhsu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vmulhsu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vdivu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vdivu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vdiv.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vdiv.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vremu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vremu.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vrem.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vrem.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vmacc.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vmacc.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vnmsac.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vnmsac.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vmadd.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vmadd.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vnmsub.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vnmsub.vx v0,a1,v4,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
- new file mode 100644
- index 0000000000..e014125c29
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
- @@ -0,0 +1,210 @@
- +# Vector Single-Width Integer Add and Subtract
- +
- + vadd.vv v4, v4, v8 # OK
- + vadd.vv v8, v4, v8 # OK
- + vadd.vv v0, v4, v8, v0.t # vd overlap vm
- + vadd.vx v4, v4, a1 # OK
- + vadd.vx v0, v4, a1, v0.t # vd overlap vm
- + vadd.vi v4, v4, 15 # OK
- + vadd.vi v0, v4, 15, v0.t # vd overlap vm
- +
- + vsub.vv v4, v4, v8 # OK
- + vsub.vv v8, v4, v8 # OK
- + vsub.vv v0, v4, v8, v0.t # vd overlap vm
- + vsub.vx v4, v4, a1 # OK
- + vsub.vx v0, v4, a1, v0.t # vd overlap vm
- +
- + vrsub.vx v4, v4, a1 # OK
- + vrsub.vx v0, v4, a1, v0.t # vd overlap vm
- + vrsub.vi v4, v4, 15 # OK
- + vrsub.vi v0, v4, 15, v0.t # vd overlap vm
- +
- +# Vector Integer Extension
- +
- + vzext.vf2 v4, v4 # OK
- + vzext.vf2 v0, v4, v0.t # vd overlap vm
- + vsext.vf2 v4, v4
- + vsext.vf2 v0, v4, v0.t
- + vzext.vf4 v4, v4
- + vzext.vf4 v0, v4, v0.t
- + vsext.vf4 v4, v4
- + vsext.vf4 v0, v4, v0.t
- + vzext.vf8 v4, v4
- + vzext.vf8 v0, v4, v0.t
- + vsext.vf8 v4, v4
- + vsext.vf8 v0, v4, v0.t
- +
- +# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
- +
- + vadc.vvm v4, v4, v8, v0 # OK
- + vadc.vvm v8, v4, v8, v0 # OK
- + vadc.vvm v0, v4, v8, v0 # vd overlap vm
- + vadc.vxm v4, v4, a1, v0 # OK
- + vadc.vxm v0, v4, a1, v0 # vd overlap vm
- + vadc.vim v4, v4, 15, v0 # OK
- + vadc.vim v0, v4, 15, v0 # vd overlap vm
- +
- + vsbc.vvm v4, v4, v8, v0 # OK
- + vsbc.vvm v8, v4, v8, v0 # OK
- + vsbc.vvm v0, v4, v8, v0 # vd overlap vm
- + vsbc.vxm v4, v4, a1, v0 # OK
- + vsbc.vxm v0, v4, a1, v0 # vd overlap vm
- +
- +# Vector Bitwise Logical Instructions
- +
- + vnot.v v4, v4 # OK
- + vnot.v v0, v4, v0.t # vd overlap vm
- +
- + vand.vv v4, v4, v8 # OK
- + vand.vv v8, v4, v8 # OK
- + vand.vv v0, v4, v8, v0.t # vd overlap vm
- + vand.vx v4, v4, a1 # OK
- + vand.vx v0, v4, a1, v0.t # vd overlap vm
- + vand.vi v4, v4, 15 # OK
- + vand.vi v0, v4, 15, v0.t # vd overlap vm
- +
- + vor.vv v4, v4, v8
- + vor.vv v8, v4, v8
- + vor.vv v0, v4, v8, v0.t
- + vor.vx v4, v4, a1
- + vor.vx v0, v4, a1, v0.t
- + vor.vi v4, v4, 15
- + vor.vi v0, v4, 15, v0.t
- +
- + vxor.vv v4, v4, v8
- + vxor.vv v8, v4, v8
- + vxor.vv v0, v4, v8, v0.t
- + vxor.vx v4, v4, a1
- + vxor.vx v0, v4, a1, v0.t
- + vxor.vi v4, v4, 15
- + vxor.vi v0, v4, 15, v0.t
- +
- +# Vector Single-Width Bit Shift Instructions
- +
- + vsll.vv v4, v4, v8 # OK
- + vsll.vv v8, v4, v8 # OK
- + vsll.vv v0, v4, v8, v0.t # vd overlap vm
- + vsll.vx v4, v4, a1 # OK
- + vsll.vx v0, v4, a1, v0.t # vd overlap vm
- + vsll.vi v4, v4, 31 # OK
- + vsll.vi v0, v4, 31, v0.t # vd overlap vm
- +
- + vsrl.vv v4, v4, v8
- + vsrl.vv v8, v4, v8
- + vsrl.vv v0, v4, v8, v0.t
- + vsrl.vx v4, v4, a1
- + vsrl.vx v0, v4, a1, v0.t
- + vsrl.vi v4, v4, 31
- + vsrl.vi v0, v4, 31, v0.t
- +
- + vsra.vv v4, v4, v8
- + vsra.vv v8, v4, v8
- + vsra.vv v0, v4, v8, v0.t
- + vsra.vx v4, v4, a1
- + vsra.vx v0, v4, a1, v0.t
- + vsra.vi v4, v4, 31
- + vsra.vi v0, v4, 31, v0.t
- +
- +# Vector Integer Min/Max Instructions
- +
- + vminu.vv v4, v4, v8 # OK
- + vminu.vv v8, v4, v8 # OK
- + vminu.vv v0, v4, v8, v0.t # vd overlap vm
- + vminu.vx v4, v4, a1 # OK
- + vminu.vx v0, v4, a1, v0.t # vd overlap vm
- +
- + vmin.vv v4, v4, v8
- + vmin.vv v8, v4, v8
- + vmin.vv v0, v4, v8, v0.t
- + vmin.vx v4, v4, a1
- + vmin.vx v0, v4, a1, v0.t
- +
- + vmaxu.vv v4, v4, v8
- + vmaxu.vv v8, v4, v8
- + vmaxu.vv v0, v4, v8, v0.t
- + vmaxu.vx v4, v4, a1
- + vmaxu.vx v0, v4, a1, v0.t
- +
- + vmax.vv v4, v4, v8
- + vmax.vv v8, v4, v8
- + vmax.vv v0, v4, v8, v0.t
- + vmax.vx v4, v4, a1
- + vmax.vx v0, v4, a1, v0.t
- +
- +# Vector Single-Width Integer Multiply Instructions
- +
- + vmul.vv v4, v4, v8 # OK
- + vmul.vv v8, v4, v8 # OK
- + vmul.vv v0, v4, v8, v0.t # vd overlap vm
- + vmul.vx v4, v4, a1 # OK
- + vmul.vx v0, v4, a1, v0.t # vd overlap vm
- +
- + vmulh.vv v4, v4, v8
- + vmulh.vv v8, v4, v8
- + vmulh.vv v0, v4, v8, v0.t
- + vmulh.vx v4, v4, a1
- + vmulh.vx v0, v4, a1, v0.t
- +
- + vmulhu.vv v4, v4, v8
- + vmulhu.vv v8, v4, v8
- + vmulhu.vv v0, v4, v8, v0.t
- + vmulhu.vx v4, v4, a1
- + vmulhu.vx v0, v4, a1, v0.t
- +
- + vmulhsu.vv v4, v4, v8
- + vmulhsu.vv v8, v4, v8
- + vmulhsu.vv v0, v4, v8, v0.t
- + vmulhsu.vx v4, v4, a1
- + vmulhsu.vx v0, v4, a1, v0.t
- +
- +# Vector Integer Divide Instructions
- +
- + vdivu.vv v4, v4, v8 # OK
- + vdivu.vv v8, v4, v8 # OK
- + vdivu.vv v0, v4, v8, v0.t # vd overlap vm
- + vdivu.vx v4, v4, a1 # OK
- + vdivu.vx v0, v4, a1, v0.t # vd overlap vm
- +
- + vdiv.vv v4, v4, v8
- + vdiv.vv v8, v4, v8
- + vdiv.vv v0, v4, v8, v0.t
- + vdiv.vx v4, v4, a1
- + vdiv.vx v0, v4, a1, v0.t
- +
- + vremu.vv v4, v4, v8
- + vremu.vv v8, v4, v8
- + vremu.vv v0, v4, v8, v0.t
- + vremu.vx v4, v4, a1
- + vremu.vx v0, v4, a1, v0.t
- +
- + vrem.vv v4, v4, v8
- + vrem.vv v8, v4, v8
- + vrem.vv v0, v4, v8, v0.t
- + vrem.vx v4, v4, a1
- + vrem.vx v0, v4, a1, v0.t
- +
- +# Vector Single-Width Integer Multiply-Add Instructions
- +
- + vmacc.vv v4, v4, v8 # OK
- + vmacc.vv v8, v4, v8 # OK
- + vmacc.vv v0, v4, v8, v0.t # vd overlap vm
- + vmacc.vx v4, a1, v4 # OK
- + vmacc.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vnmsac.vv v4, v4, v8
- + vnmsac.vv v8, v4, v8
- + vnmsac.vv v0, v4, v8, v0.t
- + vnmsac.vx v4, a1, v4
- + vnmsac.vx v0, a1, v4, v0.t
- +
- + vmadd.vv v4, v4, v8
- + vmadd.vv v8, v4, v8
- + vmadd.vv v0, v4, v8, v0.t
- + vmadd.vx v4, a1, v4
- + vmadd.vx v0, a1, v4, v0.t
- +
- + vnmsub.vv v4, v4, v8
- + vnmsub.vv v8, v4, v8
- + vnmsub.vv v0, v4, v8, v0.t
- + vnmsub.vx v4, a1, v4
- + vnmsub.vx v0, a1, v4, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
- new file mode 100644
- index 0000000000..e7a4d4e00c
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv -mcheck-constraints
- +#source: vector-insns-fail-arith-narrow.s
- +#error_output: vector-insns-fail-arith-narrow.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-05.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
- similarity index 59%
- rename from gas/testsuite/gas/riscv/vector-insns-fail-05.l
- rename to gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
- index f2bee3d1e0..dcbe3b3f79 100644
- --- a/gas/testsuite/gas/riscv/vector-insns-fail-05.l
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
- @@ -2,63 +2,84 @@
- .*Error: illegal operands `vncvt.x.x.v v2,v2'
- .*Error: illegal operands `vncvt.x.x.v v2,v3'
- .*Error: illegal operands `vncvt.x.x.v v3,v2'
- +.*Error: illegal operands `vncvt.x.x.v v0,v2,v0.t'
- .*Error: illegal operands `vnsrl.wv v2,v2,v4'
- .*Error: illegal operands `vnsrl.wv v2,v3,v4'
- .*Error: illegal operands `vnsrl.wv v3,v2,v4'
- +.*Error: illegal operands `vnsrl.wv v0,v2,v4,v0.t'
- .*Error: illegal operands `vnsrl.wx v2,v2,a1'
- .*Error: illegal operands `vnsrl.wx v2,v3,a1'
- .*Error: illegal operands `vnsrl.wx v3,v2,a1'
- -.*Error: illegal operands `vnsrl.wi v2,v2,1'
- -.*Error: illegal operands `vnsrl.wi v2,v3,1'
- -.*Error: illegal operands `vnsrl.wi v3,v2,1'
- +.*Error: illegal operands `vnsrl.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vnsrl.wi v2,v2,31'
- +.*Error: illegal operands `vnsrl.wi v2,v3,31'
- +.*Error: illegal operands `vnsrl.wi v3,v2,31'
- +.*Error: illegal operands `vnsrl.wi v0,v2,31,v0.t'
- .*Error: illegal operands `vnsra.wv v2,v2,v4'
- .*Error: illegal operands `vnsra.wv v2,v3,v4'
- .*Error: illegal operands `vnsra.wv v3,v2,v4'
- +.*Error: illegal operands `vnsra.wv v0,v2,v4,v0.t'
- .*Error: illegal operands `vnsra.wx v2,v2,a1'
- .*Error: illegal operands `vnsra.wx v2,v3,a1'
- .*Error: illegal operands `vnsra.wx v3,v2,a1'
- -.*Error: illegal operands `vnsra.wi v2,v2,1'
- -.*Error: illegal operands `vnsra.wi v2,v3,1'
- -.*Error: illegal operands `vnsra.wi v3,v2,1'
- +.*Error: illegal operands `vnsra.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vnsra.wi v2,v2,31'
- +.*Error: illegal operands `vnsra.wi v2,v3,31'
- +.*Error: illegal operands `vnsra.wi v3,v2,31'
- +.*Error: illegal operands `vnsra.wi v0,v2,31,v0.t'
- .*Error: illegal operands `vnclipu.wv v2,v2,v4'
- .*Error: illegal operands `vnclipu.wv v2,v3,v4'
- .*Error: illegal operands `vnclipu.wv v3,v2,v4'
- +.*Error: illegal operands `vnclipu.wv v0,v2,v4,v0.t'
- .*Error: illegal operands `vnclipu.wx v2,v2,a1'
- .*Error: illegal operands `vnclipu.wx v2,v3,a1'
- .*Error: illegal operands `vnclipu.wx v3,v2,a1'
- -.*Error: illegal operands `vnclipu.wi v2,v2,1'
- -.*Error: illegal operands `vnclipu.wi v2,v3,1'
- -.*Error: illegal operands `vnclipu.wi v3,v2,1'
- +.*Error: illegal operands `vnclipu.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vnclipu.wi v2,v2,31'
- +.*Error: illegal operands `vnclipu.wi v2,v3,31'
- +.*Error: illegal operands `vnclipu.wi v3,v2,31'
- +.*Error: illegal operands `vnclipu.wi v0,v2,31,v0.t'
- .*Error: illegal operands `vnclip.wv v2,v2,v4'
- .*Error: illegal operands `vnclip.wv v2,v3,v4'
- .*Error: illegal operands `vnclip.wv v3,v2,v4'
- +.*Error: illegal operands `vnclip.wv v0,v2,v4,v0.t'
- .*Error: illegal operands `vnclip.wx v2,v2,a1'
- .*Error: illegal operands `vnclip.wx v2,v3,a1'
- .*Error: illegal operands `vnclip.wx v3,v2,a1'
- -.*Error: illegal operands `vnclip.wi v2,v2,1'
- -.*Error: illegal operands `vnclip.wi v2,v3,1'
- -.*Error: illegal operands `vnclip.wi v3,v2,1'
- +.*Error: illegal operands `vnclip.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vnclip.wi v2,v2,31'
- +.*Error: illegal operands `vnclip.wi v2,v3,31'
- +.*Error: illegal operands `vnclip.wi v3,v2,31'
- +.*Error: illegal operands `vnclip.wi v0,v2,31,v0.t'
- .*Error: illegal operands `vfncvt.xu.f.w v2,v2'
- .*Error: illegal operands `vfncvt.xu.f.w v2,v3'
- .*Error: illegal operands `vfncvt.xu.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.xu.f.w v0,v2,v0.t'
- .*Error: illegal operands `vfncvt.x.f.w v2,v2'
- .*Error: illegal operands `vfncvt.x.f.w v2,v3'
- .*Error: illegal operands `vfncvt.x.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.x.f.w v0,v2,v0.t'
- .*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v2'
- .*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v3'
- .*Error: illegal operands `vfncvt.rtz.xu.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.rtz.xu.f.w v0,v2,v0.t'
- .*Error: illegal operands `vfncvt.rtz.x.f.w v2,v2'
- .*Error: illegal operands `vfncvt.rtz.x.f.w v2,v3'
- .*Error: illegal operands `vfncvt.rtz.x.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.rtz.x.f.w v0,v2,v0.t'
- .*Error: illegal operands `vfncvt.f.xu.w v2,v2'
- .*Error: illegal operands `vfncvt.f.xu.w v2,v3'
- .*Error: illegal operands `vfncvt.f.xu.w v3,v2'
- +.*Error: illegal operands `vfncvt.f.xu.w v0,v2,v0.t'
- .*Error: illegal operands `vfncvt.f.x.w v2,v2'
- .*Error: illegal operands `vfncvt.f.x.w v2,v3'
- .*Error: illegal operands `vfncvt.f.x.w v3,v2'
- +.*Error: illegal operands `vfncvt.f.x.w v0,v2,v0.t'
- .*Error: illegal operands `vfncvt.f.f.w v2,v2'
- .*Error: illegal operands `vfncvt.f.f.w v2,v3'
- .*Error: illegal operands `vfncvt.f.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.f.f.w v0,v2,v0.t'
- .*Error: illegal operands `vfncvt.rod.f.f.w v2,v2'
- .*Error: illegal operands `vfncvt.rod.f.f.w v2,v3'
- .*Error: illegal operands `vfncvt.rod.f.f.w v3,v2'
- +.*Error: illegal operands `vfncvt.rod.f.f.w v0,v2,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
- new file mode 100644
- index 0000000000..a843d076ff
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
- @@ -0,0 +1,100 @@
- +# Vector Narrowing Integer Right Shift Instructions
- +
- + # vncvt.x.x.v vd,vs,vm = vnsrl.wx vd,vs,x0,vm
- + vncvt.x.x.v v2, v2 # vd overlap vs2
- + vncvt.x.x.v v2, v3 # vs2 should be multiple of 2
- + vncvt.x.x.v v3, v2 # vd overlap vs2
- + vncvt.x.x.v v0, v2, v0.t # vd overlap vm
- +
- + vnsrl.wv v2, v2, v4 # vd overlap vs2
- + vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
- + vnsrl.wv v3, v2, v4 # vd overlap vs2
- + vnsrl.wv v4, v2, v4 # OK
- + vnsrl.wv v0, v2, v4, v0.t # vd overlap vm
- + vnsrl.wx v2, v2, a1 # vd overlap vs2
- + vnsrl.wx v2, v3, a1 # vs2 should be multiple of 2
- + vnsrl.wx v3, v2, a1 # vd overlap vs2
- + vnsrl.wx v0, v2, a1, v0.t # vd overlap vm
- + vnsrl.wi v2, v2, 31 # vd overlap vs2
- + vnsrl.wi v2, v3, 31 # vs2 should be multiple of 2
- + vnsrl.wi v3, v2, 31 # vd overlap vs2
- + vnsrl.wi v0, v2, 31, v0.t # vd overlap vm
- +
- + vnsra.wv v2, v2, v4
- + vnsra.wv v2, v3, v4
- + vnsra.wv v3, v2, v4
- + vnsra.wv v4, v2, v4
- + vnsra.wv v0, v2, v4, v0.t
- + vnsra.wx v2, v2, a1
- + vnsra.wx v2, v3, a1
- + vnsra.wx v3, v2, a1
- + vnsra.wx v0, v2, a1, v0.t
- + vnsra.wi v2, v2, 31
- + vnsra.wi v2, v3, 31
- + vnsra.wi v3, v2, 31
- + vnsra.wi v0, v2, 31, v0.t
- +
- +# Vector Narrowing Fixed-Point Clip Instructions
- +
- + vnclipu.wv v2, v2, v4 # vd overlap vs2
- + vnclipu.wv v2, v3, v4 # vs2 should be multiple of 2
- + vnclipu.wv v3, v2, v4 # vd overlap vs2
- + vnclipu.wv v4, v2, v4 # OK
- + vnclipu.wv v0, v2, v4, v0.t # vd overlap vm
- + vnclipu.wx v2, v2, a1 # vd overlap vs2
- + vnclipu.wx v2, v3, a1 # vs2 should be multiple of 2
- + vnclipu.wx v3, v2, a1 # vd overlap vs2
- + vnclipu.wx v0, v2, a1, v0.t # vd overlap vm
- + vnclipu.wi v2, v2, 31 # vd overlap vs2
- + vnclipu.wi v2, v3, 31 # vs2 should be multiple of 2
- + vnclipu.wi v3, v2, 31 # vd overlap vs2
- + vnclipu.wi v0, v2, 31, v0.t # vd overlap vm
- +
- + vnclip.wv v2, v2, v4
- + vnclip.wv v2, v3, v4
- + vnclip.wv v3, v2, v4
- + vnclip.wv v4, v2, v4
- + vnclip.wv v0, v2, v4, v0.t
- + vnclip.wx v2, v2, a1
- + vnclip.wx v2, v3, a1
- + vnclip.wx v3, v2, a1
- + vnclip.wx v0, v2, a1, v0.t
- + vnclip.wi v2, v2, 31
- + vnclip.wi v2, v3, 31
- + vnclip.wi v3, v2, 31
- + vnclip.wi v0, v2, 31, v0.t
- +
- +# Narrowing Floating-Point/Integer Type-Convert Instructions
- +
- + vfncvt.xu.f.w v2, v2 # vd overlap vs2
- + vfncvt.xu.f.w v2, v3 # vs2 should be multiple of 2
- + vfncvt.xu.f.w v3, v2 # vd overlap vs2
- + vfncvt.xu.f.w v0, v2, v0.t # vd overlap vm
- + vfncvt.x.f.w v2, v2
- + vfncvt.x.f.w v2, v3
- + vfncvt.x.f.w v3, v2
- + vfncvt.x.f.w v0, v2, v0.t
- + vfncvt.rtz.xu.f.w v2, v2
- + vfncvt.rtz.xu.f.w v2, v3
- + vfncvt.rtz.xu.f.w v3, v2
- + vfncvt.rtz.xu.f.w v0, v2, v0.t
- + vfncvt.rtz.x.f.w v2, v2
- + vfncvt.rtz.x.f.w v2, v3
- + vfncvt.rtz.x.f.w v3, v2
- + vfncvt.rtz.x.f.w v0, v2, v0.t
- + vfncvt.f.xu.w v2, v2
- + vfncvt.f.xu.w v2, v3
- + vfncvt.f.xu.w v3, v2
- + vfncvt.f.xu.w v0, v2, v0.t
- + vfncvt.f.x.w v2, v2
- + vfncvt.f.x.w v2, v3
- + vfncvt.f.x.w v3, v2
- + vfncvt.f.x.w v0, v2, v0.t
- + vfncvt.f.f.w v2, v2
- + vfncvt.f.f.w v2, v3
- + vfncvt.f.f.w v3, v2
- + vfncvt.f.f.w v0, v2, v0.t
- + vfncvt.rod.f.f.w v2, v2
- + vfncvt.rod.f.f.w v2, v3
- + vfncvt.rod.f.f.w v3, v2
- + vfncvt.rod.f.f.w v0, v2, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
- new file mode 100644
- index 0000000000..e5f034882c
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv -mcheck-constraints
- +#source: vector-insns-fail-arith-widen.s
- +#error_output: vector-insns-fail-arith-widen.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
- new file mode 100644
- index 0000000000..5684601697
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
- @@ -0,0 +1,253 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
- +.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
- +.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
- +.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
- +.*Error: illegal operands `vwcvt.x.x.v v1,v2'
- +.*Error: illegal operands `vwcvt.x.x.v v2,v2'
- +.*Error: illegal operands `vwcvt.x.x.v v2,v3'
- +.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
- +.*Error: illegal operands `vwaddu.vv v1,v2,v4'
- +.*Error: illegal operands `vwaddu.vv v2,v2,v4'
- +.*Error: illegal operands `vwaddu.vv v2,v3,v4'
- +.*Error: illegal operands `vwaddu.vv v4,v2,v4'
- +.*Error: illegal operands `vwaddu.vv v4,v2,v5'
- +.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwaddu.vx v1,v2,a1'
- +.*Error: illegal operands `vwaddu.vx v2,v2,a1'
- +.*Error: illegal operands `vwaddu.vx v2,v3,a1'
- +.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwaddu.wv v1,v2,v4'
- +.*Error: illegal operands `vwaddu.wv v2,v3,v4'
- +.*Error: illegal operands `vwaddu.wv v4,v2,v4'
- +.*Error: illegal operands `vwaddu.wv v4,v2,v5'
- +.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwaddu.wx v1,v2,a1'
- +.*Error: illegal operands `vwaddu.wx v2,v3,a1'
- +.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwsubu.vv v1,v2,v4'
- +.*Error: illegal operands `vwsubu.vv v2,v2,v4'
- +.*Error: illegal operands `vwsubu.vv v2,v3,v4'
- +.*Error: illegal operands `vwsubu.vv v4,v2,v4'
- +.*Error: illegal operands `vwsubu.vv v4,v2,v5'
- +.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwsubu.vx v1,v2,a1'
- +.*Error: illegal operands `vwsubu.vx v2,v2,a1'
- +.*Error: illegal operands `vwsubu.vx v2,v3,a1'
- +.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwsubu.wv v1,v2,v4'
- +.*Error: illegal operands `vwsubu.wv v2,v3,v4'
- +.*Error: illegal operands `vwsubu.wv v4,v2,v4'
- +.*Error: illegal operands `vwsubu.wv v4,v2,v5'
- +.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwsubu.wx v1,v2,a1'
- +.*Error: illegal operands `vwsubu.wx v2,v3,a1'
- +.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwadd.vv v1,v2,v4'
- +.*Error: illegal operands `vwadd.vv v2,v2,v4'
- +.*Error: illegal operands `vwadd.vv v2,v3,v4'
- +.*Error: illegal operands `vwadd.vv v4,v2,v4'
- +.*Error: illegal operands `vwadd.vv v4,v2,v5'
- +.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwadd.vx v1,v2,a1'
- +.*Error: illegal operands `vwadd.vx v2,v2,a1'
- +.*Error: illegal operands `vwadd.vx v2,v3,a1'
- +.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwadd.wv v1,v2,v4'
- +.*Error: illegal operands `vwadd.wv v2,v3,v4'
- +.*Error: illegal operands `vwadd.wv v4,v2,v4'
- +.*Error: illegal operands `vwadd.wv v4,v2,v5'
- +.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwadd.wx v1,v2,a1'
- +.*Error: illegal operands `vwadd.wx v2,v3,a1'
- +.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwsub.vv v1,v2,v4'
- +.*Error: illegal operands `vwsub.vv v2,v2,v4'
- +.*Error: illegal operands `vwsub.vv v2,v3,v4'
- +.*Error: illegal operands `vwsub.vv v4,v2,v4'
- +.*Error: illegal operands `vwsub.vv v4,v2,v5'
- +.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwsub.vx v1,v2,a1'
- +.*Error: illegal operands `vwsub.vx v2,v2,a1'
- +.*Error: illegal operands `vwsub.vx v2,v3,a1'
- +.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwsub.wv v1,v2,v4'
- +.*Error: illegal operands `vwsub.wv v2,v3,v4'
- +.*Error: illegal operands `vwsub.wv v4,v2,v4'
- +.*Error: illegal operands `vwsub.wv v4,v2,v5'
- +.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwsub.wx v1,v2,a1'
- +.*Error: illegal operands `vwsub.wx v2,v3,a1'
- +.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwmul.vv v1,v2,v4'
- +.*Error: illegal operands `vwmul.vv v2,v2,v4'
- +.*Error: illegal operands `vwmul.vv v2,v3,v4'
- +.*Error: illegal operands `vwmul.vv v4,v2,v4'
- +.*Error: illegal operands `vwmul.vv v4,v2,v5'
- +.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmul.vx v1,v2,a1'
- +.*Error: illegal operands `vwmul.vx v2,v2,a1'
- +.*Error: illegal operands `vwmul.vx v2,v3,a1'
- +.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwmulu.vv v1,v2,v4'
- +.*Error: illegal operands `vwmulu.vv v2,v2,v4'
- +.*Error: illegal operands `vwmulu.vv v2,v3,v4'
- +.*Error: illegal operands `vwmulu.vv v4,v2,v4'
- +.*Error: illegal operands `vwmulu.vv v4,v2,v5'
- +.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmulu.vx v1,v2,a1'
- +.*Error: illegal operands `vwmulu.vx v2,v2,a1'
- +.*Error: illegal operands `vwmulu.vx v2,v3,a1'
- +.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
- +.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
- +.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
- +.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
- +.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
- +.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
- +.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
- +.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
- +.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
- +.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
- +.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
- +.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
- +.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
- +.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
- +.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmaccu.vx v1,a1,v2'
- +.*Error: illegal operands `vwmaccu.vx v2,a1,v2'
- +.*Error: illegal operands `vwmaccu.vx v2,a1,v3'
- +.*Error: illegal operands `vwmaccu.vx v0,a1,v2,v0.t'
- +.*Error: illegal operands `vwmacc.vv v1,v2,v4'
- +.*Error: illegal operands `vwmacc.vv v2,v2,v4'
- +.*Error: illegal operands `vwmacc.vv v2,v3,v4'
- +.*Error: illegal operands `vwmacc.vv v4,v2,v4'
- +.*Error: illegal operands `vwmacc.vv v4,v2,v5'
- +.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmacc.vx v1,a1,v2'
- +.*Error: illegal operands `vwmacc.vx v2,a1,v2'
- +.*Error: illegal operands `vwmacc.vx v2,a1,v3'
- +.*Error: illegal operands `vwmacc.vx v0,a1,v2,v0.t'
- +.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
- +.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
- +.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
- +.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
- +.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
- +.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vwmaccsu.vx v1,a1,v2'
- +.*Error: illegal operands `vwmaccsu.vx v2,a1,v2'
- +.*Error: illegal operands `vwmaccsu.vx v2,a1,v3'
- +.*Error: illegal operands `vwmaccsu.vx v0,a1,v2,v0.t'
- +.*Error: illegal operands `vwmaccus.vx v1,a1,v2'
- +.*Error: illegal operands `vwmaccus.vx v2,a1,v2'
- +.*Error: illegal operands `vwmaccus.vx v2,a1,v3'
- +.*Error: illegal operands `vwmaccus.vx v0,a1,v2,v0.t'
- +.*Error: illegal operands `vfwadd.vv v1,v2,v4'
- +.*Error: illegal operands `vfwadd.vv v2,v2,v4'
- +.*Error: illegal operands `vfwadd.vv v2,v3,v4'
- +.*Error: illegal operands `vfwadd.vv v4,v2,v4'
- +.*Error: illegal operands `vfwadd.vv v4,v2,v5'
- +.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
- +.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
- +.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
- +.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
- +.*Error: illegal operands `vfwadd.wv v1,v2,v4'
- +.*Error: illegal operands `vfwadd.wv v2,v3,v4'
- +.*Error: illegal operands `vfwadd.wv v4,v2,v4'
- +.*Error: illegal operands `vfwadd.wv v4,v2,v5'
- +.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwsub.vv v1,v2,v4'
- +.*Error: illegal operands `vfwsub.vv v2,v2,v4'
- +.*Error: illegal operands `vfwsub.vv v2,v3,v4'
- +.*Error: illegal operands `vfwsub.vv v4,v2,v4'
- +.*Error: illegal operands `vfwsub.vv v4,v2,v5'
- +.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
- +.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
- +.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
- +.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
- +.*Error: illegal operands `vfwsub.wv v1,v2,v4'
- +.*Error: illegal operands `vfwsub.wv v2,v3,v4'
- +.*Error: illegal operands `vfwsub.wv v4,v2,v4'
- +.*Error: illegal operands `vfwsub.wv v4,v2,v5'
- +.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwmul.vv v1,v2,v4'
- +.*Error: illegal operands `vfwmul.vv v2,v2,v4'
- +.*Error: illegal operands `vfwmul.vv v2,v3,v4'
- +.*Error: illegal operands `vfwmul.vv v4,v2,v4'
- +.*Error: illegal operands `vfwmul.vv v4,v2,v5'
- +.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
- +.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
- +.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
- +.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
- +.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
- +.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
- +.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
- +.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
- +.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
- +.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwmacc.vf v1,fa1,v2'
- +.*Error: illegal operands `vfwmacc.vf v2,fa1,v2'
- +.*Error: illegal operands `vfwmacc.vf v2,fa1,v3'
- +.*Error: illegal operands `vfwmacc.vf v0,fa1,v2,v0.t'
- +.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
- +.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
- +.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
- +.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
- +.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
- +.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwnmacc.vf v1,fa1,v2'
- +.*Error: illegal operands `vfwnmacc.vf v2,fa1,v2'
- +.*Error: illegal operands `vfwnmacc.vf v2,fa1,v3'
- +.*Error: illegal operands `vfwnmacc.vf v0,fa1,v2,v0.t'
- +.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
- +.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
- +.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
- +.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
- +.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
- +.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwmsac.vf v1,fa1,v2'
- +.*Error: illegal operands `vfwmsac.vf v2,fa1,v2'
- +.*Error: illegal operands `vfwmsac.vf v2,fa1,v3'
- +.*Error: illegal operands `vfwmsac.vf v0,fa1,v2,v0.t'
- +.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
- +.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
- +.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
- +.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
- +.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
- +.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
- +.*Error: illegal operands `vfwnmsac.vf v1,fa1,v2'
- +.*Error: illegal operands `vfwnmsac.vf v2,fa1,v2'
- +.*Error: illegal operands `vfwnmsac.vf v2,fa1,v3'
- +.*Error: illegal operands `vfwnmsac.vf v0,fa1,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
- +.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
- +.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
- +.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
- +.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
- +.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
- +.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
- +.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
- +.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
- +.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
- +.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
- new file mode 100644
- index 0000000000..addedd4dc2
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
- @@ -0,0 +1,297 @@
- +# Vector Widening Integer Add/Subtract
- +
- + # vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm
- + vwcvtu.x.x.v v1, v2 # vd should be multiple of 2
- + vwcvtu.x.x.v v2, v2 # vd overlap vs2
- + vwcvtu.x.x.v v2, v3 # vd overlap vs2
- + vwcvtu.x.x.v v0, v2, v0.t # vd overlap vm
- +
- + # vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm
- + vwcvt.x.x.v v1, v2
- + vwcvt.x.x.v v2, v2
- + vwcvt.x.x.v v2, v3
- + vwcvt.x.x.v v0, v2, v0.t
- +
- + vwaddu.vv v1, v2, v4 # vd should be multiple of 2
- + vwaddu.vv v2, v2, v4 # vd overlap vs2
- + vwaddu.vv v2, v3, v4 # vd overlap vs2
- + vwaddu.vv v4, v2, v4 # vd overlap vs1
- + vwaddu.vv v4, v2, v5 # vd overlap vs1
- + vwaddu.vv v0, v2, v4, v0.t # vd overlap vm
- + vwaddu.vx v1, v2, a1 # vd should be multiple of 2
- + vwaddu.vx v2, v2, a1 # vd overlap vs2
- + vwaddu.vx v2, v3, a1 # vd overlap vs2
- + vwaddu.vx v0, v2, a1, v0.t # vd overlap vm
- + vwaddu.wv v1, v2, v4 # vd should be multiple of 2
- + vwaddu.wv v2, v2, v4 # OK
- + vwaddu.wv v2, v3, v4 # vs2 should be multiple of 2
- + vwaddu.wv v4, v2, v4 # vd overlap vs1
- + vwaddu.wv v4, v2, v5 # vd overlap vs1
- + vwaddu.wv v0, v2, v4, v0.t # vd overlap vm
- + vwaddu.wx v1, v2, a1 # vd should be multiple of 2
- + vwaddu.wx v2, v2, a1 # OK
- + vwaddu.wx v2, v3, a1 # vs2 should be multiple of 2
- + vwaddu.wx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwsubu.vv v1, v2, v4
- + vwsubu.vv v2, v2, v4
- + vwsubu.vv v2, v3, v4
- + vwsubu.vv v4, v2, v4
- + vwsubu.vv v4, v2, v5
- + vwsubu.vv v0, v2, v4, v0.t
- + vwsubu.vx v1, v2, a1
- + vwsubu.vx v2, v2, a1
- + vwsubu.vx v2, v3, a1
- + vwsubu.vx v0, v2, a1, v0.t
- + vwsubu.wv v1, v2, v4
- + vwsubu.wv v2, v2, v4
- + vwsubu.wv v2, v3, v4
- + vwsubu.wv v4, v2, v4
- + vwsubu.wv v4, v2, v5
- + vwsubu.wv v0, v2, v4, v0.t
- + vwsubu.wx v1, v2, a1
- + vwsubu.wx v2, v2, a1
- + vwsubu.wx v2, v3, a1
- + vwsubu.wx v0, v2, a1, v0.t
- +
- + vwadd.vv v1, v2, v4
- + vwadd.vv v2, v2, v4
- + vwadd.vv v2, v3, v4
- + vwadd.vv v4, v2, v4
- + vwadd.vv v4, v2, v5
- + vwadd.vv v0, v2, v4, v0.t
- + vwadd.vx v1, v2, a1
- + vwadd.vx v2, v2, a1
- + vwadd.vx v2, v3, a1
- + vwadd.vx v0, v2, a1, v0.t
- + vwadd.wv v1, v2, v4
- + vwadd.wv v2, v2, v4
- + vwadd.wv v2, v3, v4
- + vwadd.wv v4, v2, v4
- + vwadd.wv v4, v2, v5
- + vwadd.wv v0, v2, v4, v0.t
- + vwadd.wx v1, v2, a1
- + vwadd.wx v2, v2, a1
- + vwadd.wx v2, v3, a1
- + vwadd.wx v0, v2, a1, v0.t
- +
- + vwsub.vv v1, v2, v4
- + vwsub.vv v2, v2, v4
- + vwsub.vv v2, v3, v4
- + vwsub.vv v4, v2, v4
- + vwsub.vv v4, v2, v5
- + vwsub.vv v0, v2, v4, v0.t
- + vwsub.vx v1, v2, a1
- + vwsub.vx v2, v2, a1
- + vwsub.vx v2, v3, a1
- + vwsub.vx v0, v2, a1, v0.t
- + vwsub.wv v1, v2, v4
- + vwsub.wv v2, v2, v4
- + vwsub.wv v2, v3, v4
- + vwsub.wv v4, v2, v4
- + vwsub.wv v4, v2, v5
- + vwsub.wv v0, v2, v4, v0.t
- + vwsub.wx v1, v2, a1
- + vwsub.wx v2, v2, a1
- + vwsub.wx v2, v3, a1
- + vwsub.wx v0, v2, a1, v0.t
- +
- +# Vector Widening Integer Multiply Instructions
- +
- + vwmul.vv v1, v2, v4 # vd should be multiple of 2
- + vwmul.vv v2, v2, v4 # vd overlap vs2
- + vwmul.vv v2, v3, v4 # vd overlap vs2
- + vwmul.vv v4, v2, v4 # vd overlap vs1
- + vwmul.vv v4, v2, v5 # vd overlap vs1
- + vwmul.vv v0, v2, v4, v0.t # vd overlap vm
- + vwmul.vx v1, v2, a1 # vd should be multiple of 2
- + vwmul.vx v2, v2, a1 # vd overlap vs2
- + vwmul.vx v2, v3, a1 # vd overlap vs2
- + vwmul.vx v0, v2, a1, v0.t # vd overlap vm
- +
- + vwmulu.vv v1, v2, v4
- + vwmulu.vv v2, v2, v4
- + vwmulu.vv v2, v3, v4
- + vwmulu.vv v4, v2, v4
- + vwmulu.vv v4, v2, v5
- + vwmulu.vv v0, v2, v4, v0.t
- + vwmulu.vx v1, v2, a1
- + vwmulu.vx v2, v2, a1
- + vwmulu.vx v2, v3, a1
- + vwmulu.vx v0, v2, a1, v0.t
- +
- + vwmulsu.vv v1, v2, v4
- + vwmulsu.vv v2, v2, v4
- + vwmulsu.vv v2, v3, v4
- + vwmulsu.vv v4, v2, v4
- + vwmulsu.vv v4, v2, v5
- + vwmulsu.vv v0, v2, v4, v0.t
- + vwmulsu.vx v1, v2, a1
- + vwmulsu.vx v2, v2, a1
- + vwmulsu.vx v2, v3, a1
- + vwmulsu.vx v0, v2, a1, v0.t
- +
- +# Vector Widening Integer Multiply-Add Instructions
- +
- + vwmaccu.vv v1, v2, v4 # vd should be multiple of 2
- + vwmaccu.vv v2, v2, v4 # vd overlap vs1
- + vwmaccu.vv v2, v3, v4 # vd overlap vs1
- + vwmaccu.vv v4, v2, v4 # vd overlap vs2
- + vwmaccu.vv v4, v2, v5 # vd overlap vs2
- + vwmaccu.vv v0, v2, v4, v0.t # vd overlap vm
- + vwmaccu.vx v1, a1, v2 # vd should be multiple of 2
- + vwmaccu.vx v2, a1, v2 # vd overlap vs2
- + vwmaccu.vx v2, a1, v3 # vd overlap vs2
- + vwmaccu.vx v0, a1, v2, v0.t # vd overlap vm
- +
- + vwmacc.vv v1, v2, v4
- + vwmacc.vv v2, v2, v4
- + vwmacc.vv v2, v3, v4
- + vwmacc.vv v4, v2, v4
- + vwmacc.vv v4, v2, v5
- + vwmacc.vv v0, v2, v4, v0.t
- + vwmacc.vx v1, a1, v2
- + vwmacc.vx v2, a1, v2
- + vwmacc.vx v2, a1, v3
- + vwmacc.vx v0, a1, v2, v0.t
- +
- + vwmaccsu.vv v1, v2, v4
- + vwmaccsu.vv v2, v2, v4
- + vwmaccsu.vv v2, v3, v4
- + vwmaccsu.vv v4, v2, v4
- + vwmaccsu.vv v4, v2, v5
- + vwmaccsu.vv v0, v2, v4, v0.t
- + vwmaccsu.vx v1, a1, v2
- + vwmaccsu.vx v2, a1, v2
- + vwmaccsu.vx v2, a1, v3
- + vwmaccsu.vx v0, a1, v2, v0.t
- +
- + vwmaccus.vx v1, a1, v2 # vd should be multiple of 2
- + vwmaccus.vx v2, a1, v2 # vd overlap vs2
- + vwmaccus.vx v2, a1, v3 # vd overlap vs2
- + vwmaccus.vx v0, a1, v2, v0.t # vd overlap vm
- +
- +# Vector Widening Floating-Point Add/Subtract Instructions
- +
- + vfwadd.vv v1, v2, v4 # vd should be multiple of 2
- + vfwadd.vv v2, v2, v4 # vd overlap vs2
- + vfwadd.vv v2, v3, v4 # vd overlap vs2
- + vfwadd.vv v4, v2, v4 # vd overlap vs1
- + vfwadd.vv v4, v2, v5 # vd overlap vs1
- + vfwadd.vv v0, v2, v4, v0.t # vd overlap vm
- + vfwadd.vf v1, v2, fa1 # vd should be multiple of 2
- + vfwadd.vf v2, v2, fa1 # vd overlap vs2
- + vfwadd.vf v2, v3, fa1 # vd overlap vs2
- + vfwadd.vf v0, v2, fa1, v0.t # vd overlap vm
- + vfwadd.wv v1, v2, v4 # vd should be multiple of 2
- + vfwadd.wv v2, v2, v4 # OK
- + vfwadd.wv v2, v3, v4 # vs2 should be multiple of 2
- + vfwadd.wv v4, v2, v4 # vd overlap vs1
- + vfwadd.wv v4, v2, v5 # vd overlap vs1
- + vfwadd.wv v0, v2, v4, v0.t # vd overlap vm
- +
- + vfwsub.vv v1, v2, v4
- + vfwsub.vv v2, v2, v4
- + vfwsub.vv v2, v3, v4
- + vfwsub.vv v4, v2, v4
- + vfwsub.vv v4, v2, v5
- + vfwsub.vv v0, v2, v4, v0.t
- + vfwsub.vf v1, v2, fa1
- + vfwsub.vf v2, v2, fa1
- + vfwsub.vf v2, v3, fa1
- + vfwsub.vf v0, v2, fa1, v0.t
- + vfwsub.wv v1, v2, v4
- + vfwsub.wv v2, v2, v4
- + vfwsub.wv v2, v3, v4
- + vfwsub.wv v4, v2, v4
- + vfwsub.wv v4, v2, v5
- + vfwsub.wv v0, v2, v4, v0.t
- +
- +# Vector Widening Floating-Point Multiply
- +
- + vfwmul.vv v1, v2, v4 # vd should be multiple of 2
- + vfwmul.vv v2, v2, v4 # vd overlap vs2
- + vfwmul.vv v2, v3, v4 # vd overlap vs2
- + vfwmul.vv v4, v2, v4 # vd overlap vs1
- + vfwmul.vv v4, v2, v5 # vd overlap vs1
- + vfwmul.vv v0, v2, v4, v0.t # vd overlap vm
- + vfwsub.vf v1, v2, fa1 # vd should be multiple of 2
- + vfwsub.vf v2, v2, fa1 # vd overlap vs2
- + vfwsub.vf v2, v3, fa1 # vd overlap vs2
- + vfwsub.vf v0, v2, fa1, v0.t # vd overlap vm
- +
- +# Vector Widening Floating-Point Fused Multiply-Add Instructions
- + vfwmacc.vv v1, v2, v4 # vd should be multiple of 2
- + vfwmacc.vv v2, v2, v4 # vd overlap vs1
- + vfwmacc.vv v2, v3, v4 # vd overlap vs1
- + vfwmacc.vv v4, v2, v4 # vd overlap vs2
- + vfwmacc.vv v4, v2, v5 # vd overlap vs2
- + vfwmacc.vv v0, v2, v4, v0.t # vd overlap vm
- + vfwmacc.vf v1, fa1, v2 # vd should be multiple of 2
- + vfwmacc.vf v2, fa1, v2 # vd overlap vs2
- + vfwmacc.vf v2, fa1, v3 # vd overlap vs2
- + vfwmacc.vf v0, fa1, v2, v0.t # vd overlap vm
- +
- + vfwnmacc.vv v1, v2, v4
- + vfwnmacc.vv v2, v2, v4
- + vfwnmacc.vv v2, v3, v4
- + vfwnmacc.vv v4, v2, v4
- + vfwnmacc.vv v4, v2, v5
- + vfwnmacc.vv v0, v2, v4, v0.t
- + vfwnmacc.vf v1, fa1, v2
- + vfwnmacc.vf v2, fa1, v2
- + vfwnmacc.vf v2, fa1, v3
- + vfwnmacc.vf v0, fa1, v2, v0.t
- +
- + vfwmsac.vv v1, v2, v4
- + vfwmsac.vv v2, v2, v4
- + vfwmsac.vv v2, v3, v4
- + vfwmsac.vv v4, v2, v4
- + vfwmsac.vv v4, v2, v5
- + vfwmsac.vv v0, v2, v4, v0.t
- + vfwmsac.vf v1, fa1, v2
- + vfwmsac.vf v2, fa1, v2
- + vfwmsac.vf v2, fa1, v3
- + vfwmsac.vf v0, fa1, v2, v0.t
- +
- + vfwnmsac.vv v1, v2, v4
- + vfwnmsac.vv v2, v2, v4
- + vfwnmsac.vv v2, v3, v4
- + vfwnmsac.vv v4, v2, v4
- + vfwnmsac.vv v4, v2, v5
- + vfwnmsac.vv v0, v2, v4, v0.t
- + vfwnmsac.vf v1, fa1, v2
- + vfwnmsac.vf v2, fa1, v2
- + vfwnmsac.vf v2, fa1, v3
- + vfwnmsac.vf v0, fa1, v2, v0.t
- +
- +# Widening Floating-Point/Integer Type-Convert Instructions
- +
- + vfwcvt.xu.f.v v1, v2 # vd should be multiple of 2
- + vfwcvt.xu.f.v v2, v2 # vd overlap vs2
- + vfwcvt.xu.f.v v2, v3 # vd overlap vs2
- + vfwcvt.xu.f.v v0, v2, v0.t # vd overlap vm
- + vfwcvt.x.f.v v1, v2
- + vfwcvt.x.f.v v2, v2
- + vfwcvt.x.f.v v2, v3
- + vfwcvt.x.f.v v0, v2, v0.t
- + vfwcvt.rtz.xu.f.v v1, v2
- + vfwcvt.rtz.xu.f.v v2, v2
- + vfwcvt.rtz.xu.f.v v2, v3
- + vfwcvt.rtz.xu.f.v v0, v2, v0.t
- + vfwcvt.rtz.x.f.v v1, v2
- + vfwcvt.rtz.x.f.v v2, v2
- + vfwcvt.rtz.x.f.v v2, v3
- + vfwcvt.rtz.x.f.v v0, v2, v0.t
- + vfwcvt.f.xu.v v1, v2
- + vfwcvt.f.xu.v v2, v2
- + vfwcvt.f.xu.v v2, v3
- + vfwcvt.f.xu.v v0, v2, v0.t
- + vfwcvt.f.x.v v1, v2
- + vfwcvt.f.x.v v2, v2
- + vfwcvt.f.x.v v2, v3
- + vfwcvt.f.x.v v0, v2, v0.t
- + vfwcvt.f.f.v v1, v2
- + vfwcvt.f.f.v v2, v2
- + vfwcvt.f.f.v v2, v3
- + vfwcvt.f.f.v v0, v2, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
- new file mode 100644
- index 0000000000..763191f31e
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32iv -mcheck-constraints
- +#source: vector-insns-fail-load-store.s
- +#error_output: vector-insns-fail-load-store.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
- new file mode 100644
- index 0000000000..bd04cbb263
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
- @@ -0,0 +1,557 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vle8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vle1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vse8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vse16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vse32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vse64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vse128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vse256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vse512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vse1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlse8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlse16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlse32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlse64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlse128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlse256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlse512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlse1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vsse8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vsse16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vsse32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vsse64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vsse128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vsse256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vsse512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vsse1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlxei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsuxei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsuxei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsuxei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsuxei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg2e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg3e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg4e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg5e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg6e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg7e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg8e8.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg2e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg3e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg4e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg5e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg6e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg7e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg8e16.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg2e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg3e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg4e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg5e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg6e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg7e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg8e32.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg2e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg3e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg4e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg5e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg6e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg7e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg8e64.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg2e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg3e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg4e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg5e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg6e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg7e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg8e128.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e128ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg2e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg3e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg4e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg5e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg6e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg7e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg8e256.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e256ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg2e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg3e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg4e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg5e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg6e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg7e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg8e512.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e512ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg2e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg2e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg3e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg3e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg4e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg4e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg5e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg5e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg6e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg6e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg7e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg7e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vsseg8e1024.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlseg8e1024ff.v v0,\(a0\),v0.t'
- +.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg2e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg3e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg4e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg5e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg6e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg7e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg8e8.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg2e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg3e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg4e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg5e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg6e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg7e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg8e16.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg2e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg3e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg4e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg5e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg6e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg7e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg8e32.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg2e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg3e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg4e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg5e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg6e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg7e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg8e64.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg2e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg3e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg4e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg5e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg6e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg7e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg8e128.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg2e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg3e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg4e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg5e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg6e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg7e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg8e256.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg2e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg3e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg4e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg5e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg6e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg7e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg8e512.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg2e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg2e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg3e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg3e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg4e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg4e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg5e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg5e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg6e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg6e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg7e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg7e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlsseg8e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vssseg8e1024.v v0,\(a0\),a1,v0.t'
- +.*Error: illegal operands `vlxseg2ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg2ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg2ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg2ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg3ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg3ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg3ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg3ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg4ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg4ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg4ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg4ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg5ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg5ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg5ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg5ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg6ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg6ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg6ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg6ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg7ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg7ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg7ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg7ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg8ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg8ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg8ei8.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg8ei8.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg2ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg2ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg2ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg2ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg3ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg3ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg3ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg3ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg4ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg4ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg4ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg4ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg5ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg5ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg5ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg5ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg6ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg6ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg6ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg6ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg7ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg7ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg7ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg7ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg8ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg8ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg8ei16.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg8ei16.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg2ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg2ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg2ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg2ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg3ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg3ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg3ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg3ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg4ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg4ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg4ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg4ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg5ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg5ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg5ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg5ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg6ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg6ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg6ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg6ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg7ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg7ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg7ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg7ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg8ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg8ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg8ei32.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg8ei32.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg2ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg2ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg2ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg2ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg3ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg3ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg3ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg3ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg4ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg4ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg4ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg4ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg5ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg5ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg5ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg5ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg6ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg6ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg6ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg6ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg7ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg7ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg7ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg7ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg8ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg8ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg8ei64.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg8ei64.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg2ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg2ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg2ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg2ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg3ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg3ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg3ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg3ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg4ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg4ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg4ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg4ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg5ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg5ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg5ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg5ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg6ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg6ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg6ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg6ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg7ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg7ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg7ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg7ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg8ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg8ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg8ei128.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg8ei128.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg2ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg2ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg2ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg2ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg3ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg3ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg3ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg3ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg4ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg4ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg4ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg4ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg5ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg5ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg5ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg5ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg6ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg6ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg6ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg6ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg7ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg7ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg7ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg7ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg8ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg8ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg8ei256.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg8ei256.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg2ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg2ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg2ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg2ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg3ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg3ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg3ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg3ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg4ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg4ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg4ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg4ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg5ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg5ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg5ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg5ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg6ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg6ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg6ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg6ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg7ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg7ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg7ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg7ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg8ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg8ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg8ei512.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg8ei512.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg2ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg2ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg2ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg2ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg3ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg3ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg3ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg3ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg4ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg4ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg4ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg4ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg5ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg5ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg5ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg5ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg6ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg6ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg6ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg6ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg7ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg7ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg7ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg7ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vlxseg8ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vlxseg8ei1024.v v0,\(a0\),v4,v0.t'
- +.*Error: illegal operands `vsxseg8ei1024.v v4,\(a0\),v4'
- +.*Error: illegal operands `vsxseg8ei1024.v v0,\(a0\),v4,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
- new file mode 100644
- index 0000000000..05f9358aed
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
- @@ -0,0 +1,610 @@
- +# Vector Unit-Stride Loads and Stores
- +
- + vle8.v v0, (a0), v0.t # vd overlap vm
- + vle8ff.v v0, (a0), v0.t # vd overlap vm
- + vle16.v v0, (a0), v0.t
- + vle16ff.v v0, (a0), v0.t
- + vle32.v v0, (a0), v0.t
- + vle32ff.v v0, (a0), v0.t
- + vle64.v v0, (a0), v0.t
- + vle64ff.v v0, (a0), v0.t
- + vle128.v v0, (a0), v0.t
- + vle128ff.v v0, (a0), v0.t
- + vle256.v v0, (a0), v0.t
- + vle256ff.v v0, (a0), v0.t
- + vle512.v v0, (a0), v0.t
- + vle512ff.v v0, (a0), v0.t
- + vle1024.v v0, (a0), v0.t
- + vle1024ff.v v0, (a0), v0.t
- +
- + vse8.v v0, (a0), v0.t # vd overlap vm
- + vse16.v v0, (a0), v0.t
- + vse32.v v0, (a0), v0.t
- + vse64.v v0, (a0), v0.t
- + vse128.v v0, (a0), v0.t
- + vse256.v v0, (a0), v0.t
- + vse512.v v0, (a0), v0.t
- + vse1024.v v0, (a0), v0.t
- +
- +# Vector Strided Loads and Stores
- +
- + vlse8.v v0, (a0), a1, v0.t # vd overlap vm
- + vlse16.v v0, (a0), a1, v0.t
- + vlse32.v v0, (a0), a1, v0.t
- + vlse64.v v0, (a0), a1, v0.t
- + vlse128.v v0, (a0), a1, v0.t
- + vlse256.v v0, (a0), a1, v0.t
- + vlse512.v v0, (a0), a1, v0.t
- + vlse1024.v v0, (a0), a1, v0.t
- +
- + vsse8.v v0, (a0), a1, v0.t
- + vsse16.v v0, (a0), a1, v0.t
- + vsse32.v v0, (a0), a1, v0.t
- + vsse64.v v0, (a0), a1, v0.t
- + vsse128.v v0, (a0), a1, v0.t
- + vsse256.v v0, (a0), a1, v0.t
- + vsse512.v v0, (a0), a1, v0.t
- + vsse1024.v v0, (a0), a1, v0.t
- +
- +# Vector Indexed Loads and Stores
- +
- + vlxei8.v v4, (a0), v4 # OK
- + vlxei8.v v0, (a0), v4, v0.t # vd overlap vm
- + vlxei16.v v4, (a0), v4
- + vlxei16.v v0, (a0), v4, v0.t
- + vlxei32.v v4, (a0), v4
- + vlxei32.v v0, (a0), v4, v0.t
- + vlxei64.v v4, (a0), v4
- + vlxei64.v v0, (a0), v4, v0.t
- +
- + vsxei8.v v4, (a0), v4
- + vsxei8.v v0, (a0), v4, v0.t
- + vsxei16.v v4, (a0), v4
- + vsxei16.v v0, (a0), v4, v0.t
- + vsxei32.v v4, (a0), v4
- + vsxei32.v v0, (a0), v4, v0.t
- + vsxei64.v v4, (a0), v4
- + vsxei64.v v0, (a0), v4, v0.t
- +
- + vsuxei8.v v4, (a0), v4
- + vsuxei8.v v0, (a0), v4, v0.t
- + vsuxei16.v v4, (a0), v4
- + vsuxei16.v v0, (a0), v4, v0.t
- + vsuxei32.v v4, (a0), v4
- + vsuxei32.v v0, (a0), v4, v0.t
- + vsuxei64.v v4, (a0), v4
- + vsuxei64.v v0, (a0), v4, v0.t
- +
- +# Vector Unit-Stride Segment Loads and Stores
- +
- + vlseg2e8.v v0, (a0), v0.t # vd overlap vm
- + vsseg2e8.v v0, (a0), v0.t # vd overlap vm
- + vlseg2e8ff.v v0, (a0), v0.t # vd overlap vm
- + vlseg3e8.v v0, (a0), v0.t
- + vsseg3e8.v v0, (a0), v0.t
- + vlseg3e8ff.v v0, (a0), v0.t
- + vlseg4e8.v v0, (a0), v0.t
- + vsseg4e8.v v0, (a0), v0.t
- + vlseg4e8ff.v v0, (a0), v0.t
- + vlseg5e8.v v0, (a0), v0.t
- + vsseg5e8.v v0, (a0), v0.t
- + vlseg5e8ff.v v0, (a0), v0.t
- + vlseg6e8.v v0, (a0), v0.t
- + vsseg6e8.v v0, (a0), v0.t
- + vlseg6e8ff.v v0, (a0), v0.t
- + vlseg7e8.v v0, (a0), v0.t
- + vsseg7e8.v v0, (a0), v0.t
- + vlseg7e8ff.v v0, (a0), v0.t
- + vlseg8e8.v v0, (a0), v0.t
- + vsseg8e8.v v0, (a0), v0.t
- + vlseg8e8ff.v v0, (a0), v0.t
- +
- + vlseg2e16.v v0, (a0), v0.t
- + vsseg2e16.v v0, (a0), v0.t
- + vlseg2e16ff.v v0, (a0), v0.t
- + vlseg3e16.v v0, (a0), v0.t
- + vsseg3e16.v v0, (a0), v0.t
- + vlseg3e16ff.v v0, (a0), v0.t
- + vlseg4e16.v v0, (a0), v0.t
- + vsseg4e16.v v0, (a0), v0.t
- + vlseg4e16ff.v v0, (a0), v0.t
- + vlseg5e16.v v0, (a0), v0.t
- + vsseg5e16.v v0, (a0), v0.t
- + vlseg5e16ff.v v0, (a0), v0.t
- + vlseg6e16.v v0, (a0), v0.t
- + vsseg6e16.v v0, (a0), v0.t
- + vlseg6e16ff.v v0, (a0), v0.t
- + vlseg7e16.v v0, (a0), v0.t
- + vsseg7e16.v v0, (a0), v0.t
- + vlseg7e16ff.v v0, (a0), v0.t
- + vlseg8e16.v v0, (a0), v0.t
- + vsseg8e16.v v0, (a0), v0.t
- + vlseg8e16ff.v v0, (a0), v0.t
- +
- + vlseg2e32.v v0, (a0), v0.t
- + vsseg2e32.v v0, (a0), v0.t
- + vlseg2e32ff.v v0, (a0), v0.t
- + vlseg3e32.v v0, (a0), v0.t
- + vsseg3e32.v v0, (a0), v0.t
- + vlseg3e32ff.v v0, (a0), v0.t
- + vlseg4e32.v v0, (a0), v0.t
- + vsseg4e32.v v0, (a0), v0.t
- + vlseg4e32ff.v v0, (a0), v0.t
- + vlseg5e32.v v0, (a0), v0.t
- + vsseg5e32.v v0, (a0), v0.t
- + vlseg5e32ff.v v0, (a0), v0.t
- + vlseg6e32.v v0, (a0), v0.t
- + vsseg6e32.v v0, (a0), v0.t
- + vlseg6e32ff.v v0, (a0), v0.t
- + vlseg7e32.v v0, (a0), v0.t
- + vsseg7e32.v v0, (a0), v0.t
- + vlseg7e32ff.v v0, (a0), v0.t
- + vlseg8e32.v v0, (a0), v0.t
- + vsseg8e32.v v0, (a0), v0.t
- + vlseg8e32ff.v v0, (a0), v0.t
- +
- + vlseg2e64.v v0, (a0), v0.t
- + vsseg2e64.v v0, (a0), v0.t
- + vlseg2e64ff.v v0, (a0), v0.t
- + vlseg3e64.v v0, (a0), v0.t
- + vsseg3e64.v v0, (a0), v0.t
- + vlseg3e64ff.v v0, (a0), v0.t
- + vlseg4e64.v v0, (a0), v0.t
- + vsseg4e64.v v0, (a0), v0.t
- + vlseg4e64ff.v v0, (a0), v0.t
- + vlseg5e64.v v0, (a0), v0.t
- + vsseg5e64.v v0, (a0), v0.t
- + vlseg5e64ff.v v0, (a0), v0.t
- + vlseg6e64.v v0, (a0), v0.t
- + vsseg6e64.v v0, (a0), v0.t
- + vlseg6e64ff.v v0, (a0), v0.t
- + vlseg7e64.v v0, (a0), v0.t
- + vsseg7e64.v v0, (a0), v0.t
- + vlseg7e64ff.v v0, (a0), v0.t
- + vlseg8e64.v v0, (a0), v0.t
- + vsseg8e64.v v0, (a0), v0.t
- + vlseg8e64ff.v v0, (a0), v0.t
- +
- + vlseg2e128.v v0, (a0), v0.t
- + vsseg2e128.v v0, (a0), v0.t
- + vlseg2e128ff.v v0, (a0), v0.t
- + vlseg3e128.v v0, (a0), v0.t
- + vsseg3e128.v v0, (a0), v0.t
- + vlseg3e128ff.v v0, (a0), v0.t
- + vlseg4e128.v v0, (a0), v0.t
- + vsseg4e128.v v0, (a0), v0.t
- + vlseg4e128ff.v v0, (a0), v0.t
- + vlseg5e128.v v0, (a0), v0.t
- + vsseg5e128.v v0, (a0), v0.t
- + vlseg5e128ff.v v0, (a0), v0.t
- + vlseg6e128.v v0, (a0), v0.t
- + vsseg6e128.v v0, (a0), v0.t
- + vlseg6e128ff.v v0, (a0), v0.t
- + vlseg7e128.v v0, (a0), v0.t
- + vsseg7e128.v v0, (a0), v0.t
- + vlseg7e128ff.v v0, (a0), v0.t
- + vlseg8e128.v v0, (a0), v0.t
- + vsseg8e128.v v0, (a0), v0.t
- + vlseg8e128ff.v v0, (a0), v0.t
- +
- + vlseg2e256.v v0, (a0), v0.t
- + vsseg2e256.v v0, (a0), v0.t
- + vlseg2e256ff.v v0, (a0), v0.t
- + vlseg3e256.v v0, (a0), v0.t
- + vsseg3e256.v v0, (a0), v0.t
- + vlseg3e256ff.v v0, (a0), v0.t
- + vlseg4e256.v v0, (a0), v0.t
- + vsseg4e256.v v0, (a0), v0.t
- + vlseg4e256ff.v v0, (a0), v0.t
- + vlseg5e256.v v0, (a0), v0.t
- + vsseg5e256.v v0, (a0), v0.t
- + vlseg5e256ff.v v0, (a0), v0.t
- + vlseg6e256.v v0, (a0), v0.t
- + vsseg6e256.v v0, (a0), v0.t
- + vlseg6e256ff.v v0, (a0), v0.t
- + vlseg7e256.v v0, (a0), v0.t
- + vsseg7e256.v v0, (a0), v0.t
- + vlseg7e256ff.v v0, (a0), v0.t
- + vlseg8e256.v v0, (a0), v0.t
- + vsseg8e256.v v0, (a0), v0.t
- + vlseg8e256ff.v v0, (a0), v0.t
- +
- + vlseg2e512.v v0, (a0), v0.t
- + vsseg2e512.v v0, (a0), v0.t
- + vlseg2e512ff.v v0, (a0), v0.t
- + vlseg3e512.v v0, (a0), v0.t
- + vsseg3e512.v v0, (a0), v0.t
- + vlseg3e512ff.v v0, (a0), v0.t
- + vlseg4e512.v v0, (a0), v0.t
- + vsseg4e512.v v0, (a0), v0.t
- + vlseg4e512ff.v v0, (a0), v0.t
- + vlseg5e512.v v0, (a0), v0.t
- + vsseg5e512.v v0, (a0), v0.t
- + vlseg5e512ff.v v0, (a0), v0.t
- + vlseg6e512.v v0, (a0), v0.t
- + vsseg6e512.v v0, (a0), v0.t
- + vlseg6e512ff.v v0, (a0), v0.t
- + vlseg7e512.v v0, (a0), v0.t
- + vsseg7e512.v v0, (a0), v0.t
- + vlseg7e512ff.v v0, (a0), v0.t
- + vlseg8e512.v v0, (a0), v0.t
- + vsseg8e512.v v0, (a0), v0.t
- + vlseg8e512ff.v v0, (a0), v0.t
- +
- + vlseg2e1024.v v0, (a0), v0.t
- + vsseg2e1024.v v0, (a0), v0.t
- + vlseg2e1024ff.v v0, (a0), v0.t
- + vlseg3e1024.v v0, (a0), v0.t
- + vsseg3e1024.v v0, (a0), v0.t
- + vlseg3e1024ff.v v0, (a0), v0.t
- + vlseg4e1024.v v0, (a0), v0.t
- + vsseg4e1024.v v0, (a0), v0.t
- + vlseg4e1024ff.v v0, (a0), v0.t
- + vlseg5e1024.v v0, (a0), v0.t
- + vsseg5e1024.v v0, (a0), v0.t
- + vlseg5e1024ff.v v0, (a0), v0.t
- + vlseg6e1024.v v0, (a0), v0.t
- + vsseg6e1024.v v0, (a0), v0.t
- + vlseg6e1024ff.v v0, (a0), v0.t
- + vlseg7e1024.v v0, (a0), v0.t
- + vsseg7e1024.v v0, (a0), v0.t
- + vlseg7e1024ff.v v0, (a0), v0.t
- + vlseg8e1024.v v0, (a0), v0.t
- + vsseg8e1024.v v0, (a0), v0.t
- + vlseg8e1024ff.v v0, (a0), v0.t
- +
- +# Vector Strided Segment Loads and Stores
- +
- + vlsseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vssseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
- + vlsseg3e8.v v0, (a0), a1, v0.t
- + vssseg3e8.v v0, (a0), a1, v0.t
- + vlsseg4e8.v v0, (a0), a1, v0.t
- + vssseg4e8.v v0, (a0), a1, v0.t
- + vlsseg5e8.v v0, (a0), a1, v0.t
- + vssseg5e8.v v0, (a0), a1, v0.t
- + vlsseg6e8.v v0, (a0), a1, v0.t
- + vssseg6e8.v v0, (a0), a1, v0.t
- + vlsseg7e8.v v0, (a0), a1, v0.t
- + vssseg7e8.v v0, (a0), a1, v0.t
- + vlsseg8e8.v v0, (a0), a1, v0.t
- + vssseg8e8.v v0, (a0), a1, v0.t
- +
- + vlsseg2e16.v v0, (a0), a1, v0.t
- + vssseg2e16.v v0, (a0), a1, v0.t
- + vlsseg3e16.v v0, (a0), a1, v0.t
- + vssseg3e16.v v0, (a0), a1, v0.t
- + vlsseg4e16.v v0, (a0), a1, v0.t
- + vssseg4e16.v v0, (a0), a1, v0.t
- + vlsseg5e16.v v0, (a0), a1, v0.t
- + vssseg5e16.v v0, (a0), a1, v0.t
- + vlsseg6e16.v v0, (a0), a1, v0.t
- + vssseg6e16.v v0, (a0), a1, v0.t
- + vlsseg7e16.v v0, (a0), a1, v0.t
- + vssseg7e16.v v0, (a0), a1, v0.t
- + vlsseg8e16.v v0, (a0), a1, v0.t
- + vssseg8e16.v v0, (a0), a1, v0.t
- +
- + vlsseg2e32.v v0, (a0), a1, v0.t
- + vssseg2e32.v v0, (a0), a1, v0.t
- + vlsseg3e32.v v0, (a0), a1, v0.t
- + vssseg3e32.v v0, (a0), a1, v0.t
- + vlsseg4e32.v v0, (a0), a1, v0.t
- + vssseg4e32.v v0, (a0), a1, v0.t
- + vlsseg5e32.v v0, (a0), a1, v0.t
- + vssseg5e32.v v0, (a0), a1, v0.t
- + vlsseg6e32.v v0, (a0), a1, v0.t
- + vssseg6e32.v v0, (a0), a1, v0.t
- + vlsseg7e32.v v0, (a0), a1, v0.t
- + vssseg7e32.v v0, (a0), a1, v0.t
- + vlsseg8e32.v v0, (a0), a1, v0.t
- + vssseg8e32.v v0, (a0), a1, v0.t
- +
- + vlsseg2e64.v v0, (a0), a1, v0.t
- + vssseg2e64.v v0, (a0), a1, v0.t
- + vlsseg3e64.v v0, (a0), a1, v0.t
- + vssseg3e64.v v0, (a0), a1, v0.t
- + vlsseg4e64.v v0, (a0), a1, v0.t
- + vssseg4e64.v v0, (a0), a1, v0.t
- + vlsseg5e64.v v0, (a0), a1, v0.t
- + vssseg5e64.v v0, (a0), a1, v0.t
- + vlsseg6e64.v v0, (a0), a1, v0.t
- + vssseg6e64.v v0, (a0), a1, v0.t
- + vlsseg7e64.v v0, (a0), a1, v0.t
- + vssseg7e64.v v0, (a0), a1, v0.t
- + vlsseg8e64.v v0, (a0), a1, v0.t
- + vssseg8e64.v v0, (a0), a1, v0.t
- +
- + vlsseg2e128.v v0, (a0), a1, v0.t
- + vssseg2e128.v v0, (a0), a1, v0.t
- + vlsseg3e128.v v0, (a0), a1, v0.t
- + vssseg3e128.v v0, (a0), a1, v0.t
- + vlsseg4e128.v v0, (a0), a1, v0.t
- + vssseg4e128.v v0, (a0), a1, v0.t
- + vlsseg5e128.v v0, (a0), a1, v0.t
- + vssseg5e128.v v0, (a0), a1, v0.t
- + vlsseg6e128.v v0, (a0), a1, v0.t
- + vssseg6e128.v v0, (a0), a1, v0.t
- + vlsseg7e128.v v0, (a0), a1, v0.t
- + vssseg7e128.v v0, (a0), a1, v0.t
- + vlsseg8e128.v v0, (a0), a1, v0.t
- + vssseg8e128.v v0, (a0), a1, v0.t
- +
- + vlsseg2e256.v v0, (a0), a1, v0.t
- + vssseg2e256.v v0, (a0), a1, v0.t
- + vlsseg3e256.v v0, (a0), a1, v0.t
- + vssseg3e256.v v0, (a0), a1, v0.t
- + vlsseg4e256.v v0, (a0), a1, v0.t
- + vssseg4e256.v v0, (a0), a1, v0.t
- + vlsseg5e256.v v0, (a0), a1, v0.t
- + vssseg5e256.v v0, (a0), a1, v0.t
- + vlsseg6e256.v v0, (a0), a1, v0.t
- + vssseg6e256.v v0, (a0), a1, v0.t
- + vlsseg7e256.v v0, (a0), a1, v0.t
- + vssseg7e256.v v0, (a0), a1, v0.t
- + vlsseg8e256.v v0, (a0), a1, v0.t
- + vssseg8e256.v v0, (a0), a1, v0.t
- +
- + vlsseg2e512.v v0, (a0), a1, v0.t
- + vssseg2e512.v v0, (a0), a1, v0.t
- + vlsseg3e512.v v0, (a0), a1, v0.t
- + vssseg3e512.v v0, (a0), a1, v0.t
- + vlsseg4e512.v v0, (a0), a1, v0.t
- + vssseg4e512.v v0, (a0), a1, v0.t
- + vlsseg5e512.v v0, (a0), a1, v0.t
- + vssseg5e512.v v0, (a0), a1, v0.t
- + vlsseg6e512.v v0, (a0), a1, v0.t
- + vssseg6e512.v v0, (a0), a1, v0.t
- + vlsseg7e512.v v0, (a0), a1, v0.t
- + vssseg7e512.v v0, (a0), a1, v0.t
- + vlsseg8e512.v v0, (a0), a1, v0.t
- + vssseg8e512.v v0, (a0), a1, v0.t
- +
- + vlsseg2e1024.v v0, (a0), a1, v0.t
- + vssseg2e1024.v v0, (a0), a1, v0.t
- + vlsseg3e1024.v v0, (a0), a1, v0.t
- + vssseg3e1024.v v0, (a0), a1, v0.t
- + vlsseg4e1024.v v0, (a0), a1, v0.t
- + vssseg4e1024.v v0, (a0), a1, v0.t
- + vlsseg5e1024.v v0, (a0), a1, v0.t
- + vssseg5e1024.v v0, (a0), a1, v0.t
- + vlsseg6e1024.v v0, (a0), a1, v0.t
- + vssseg6e1024.v v0, (a0), a1, v0.t
- + vlsseg7e1024.v v0, (a0), a1, v0.t
- + vssseg7e1024.v v0, (a0), a1, v0.t
- + vlsseg8e1024.v v0, (a0), a1, v0.t
- + vssseg8e1024.v v0, (a0), a1, v0.t
- +
- +# Vector Indexed Segment Loads and Stores
- +
- + vlxseg2ei8.v v4, (a0), v4 # vd overlap vs2
- + vlxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
- + vsxseg2ei8.v v4, (a0), v4 # vd overlap vs2
- + vsxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
- + vlxseg3ei8.v v4, (a0), v4
- + vlxseg3ei8.v v0, (a0), v4, v0.t
- + vsxseg3ei8.v v4, (a0), v4
- + vsxseg3ei8.v v0, (a0), v4, v0.t
- + vlxseg4ei8.v v4, (a0), v4
- + vlxseg4ei8.v v0, (a0), v4, v0.t
- + vsxseg4ei8.v v4, (a0), v4
- + vsxseg4ei8.v v0, (a0), v4, v0.t
- + vlxseg5ei8.v v4, (a0), v4
- + vlxseg5ei8.v v0, (a0), v4, v0.t
- + vsxseg5ei8.v v4, (a0), v4
- + vsxseg5ei8.v v0, (a0), v4, v0.t
- + vlxseg6ei8.v v4, (a0), v4
- + vlxseg6ei8.v v0, (a0), v4, v0.t
- + vsxseg6ei8.v v4, (a0), v4
- + vsxseg6ei8.v v0, (a0), v4, v0.t
- + vlxseg7ei8.v v4, (a0), v4
- + vlxseg7ei8.v v0, (a0), v4, v0.t
- + vsxseg7ei8.v v4, (a0), v4
- + vsxseg7ei8.v v0, (a0), v4, v0.t
- + vlxseg8ei8.v v4, (a0), v4
- + vlxseg8ei8.v v0, (a0), v4, v0.t
- + vsxseg8ei8.v v4, (a0), v4
- + vsxseg8ei8.v v0, (a0), v4, v0.t
- +
- + vlxseg2ei16.v v4, (a0), v4
- + vlxseg2ei16.v v0, (a0), v4, v0.t
- + vsxseg2ei16.v v4, (a0), v4
- + vsxseg2ei16.v v0, (a0), v4, v0.t
- + vlxseg3ei16.v v4, (a0), v4
- + vlxseg3ei16.v v0, (a0), v4, v0.t
- + vsxseg3ei16.v v4, (a0), v4
- + vsxseg3ei16.v v0, (a0), v4, v0.t
- + vlxseg4ei16.v v4, (a0), v4
- + vlxseg4ei16.v v0, (a0), v4, v0.t
- + vsxseg4ei16.v v4, (a0), v4
- + vsxseg4ei16.v v0, (a0), v4, v0.t
- + vlxseg5ei16.v v4, (a0), v4
- + vlxseg5ei16.v v0, (a0), v4, v0.t
- + vsxseg5ei16.v v4, (a0), v4
- + vsxseg5ei16.v v0, (a0), v4, v0.t
- + vlxseg6ei16.v v4, (a0), v4
- + vlxseg6ei16.v v0, (a0), v4, v0.t
- + vsxseg6ei16.v v4, (a0), v4
- + vsxseg6ei16.v v0, (a0), v4, v0.t
- + vlxseg7ei16.v v4, (a0), v4
- + vlxseg7ei16.v v0, (a0), v4, v0.t
- + vsxseg7ei16.v v4, (a0), v4
- + vsxseg7ei16.v v0, (a0), v4, v0.t
- + vlxseg8ei16.v v4, (a0), v4
- + vlxseg8ei16.v v0, (a0), v4, v0.t
- + vsxseg8ei16.v v4, (a0), v4
- + vsxseg8ei16.v v0, (a0), v4, v0.t
- +
- + vlxseg2ei32.v v4, (a0), v4
- + vlxseg2ei32.v v0, (a0), v4, v0.t
- + vsxseg2ei32.v v4, (a0), v4
- + vsxseg2ei32.v v0, (a0), v4, v0.t
- + vlxseg3ei32.v v4, (a0), v4
- + vlxseg3ei32.v v0, (a0), v4, v0.t
- + vsxseg3ei32.v v4, (a0), v4
- + vsxseg3ei32.v v0, (a0), v4, v0.t
- + vlxseg4ei32.v v4, (a0), v4
- + vlxseg4ei32.v v0, (a0), v4, v0.t
- + vsxseg4ei32.v v4, (a0), v4
- + vsxseg4ei32.v v0, (a0), v4, v0.t
- + vlxseg5ei32.v v4, (a0), v4
- + vlxseg5ei32.v v0, (a0), v4, v0.t
- + vsxseg5ei32.v v4, (a0), v4
- + vsxseg5ei32.v v0, (a0), v4, v0.t
- + vlxseg6ei32.v v4, (a0), v4
- + vlxseg6ei32.v v0, (a0), v4, v0.t
- + vsxseg6ei32.v v4, (a0), v4
- + vsxseg6ei32.v v0, (a0), v4, v0.t
- + vlxseg7ei32.v v4, (a0), v4
- + vlxseg7ei32.v v0, (a0), v4, v0.t
- + vsxseg7ei32.v v4, (a0), v4
- + vsxseg7ei32.v v0, (a0), v4, v0.t
- + vlxseg8ei32.v v4, (a0), v4
- + vlxseg8ei32.v v0, (a0), v4, v0.t
- + vsxseg8ei32.v v4, (a0), v4
- + vsxseg8ei32.v v0, (a0), v4, v0.t
- +
- + vlxseg2ei64.v v4, (a0), v4
- + vlxseg2ei64.v v0, (a0), v4, v0.t
- + vsxseg2ei64.v v4, (a0), v4
- + vsxseg2ei64.v v0, (a0), v4, v0.t
- + vlxseg3ei64.v v4, (a0), v4
- + vlxseg3ei64.v v0, (a0), v4, v0.t
- + vsxseg3ei64.v v4, (a0), v4
- + vsxseg3ei64.v v0, (a0), v4, v0.t
- + vlxseg4ei64.v v4, (a0), v4
- + vlxseg4ei64.v v0, (a0), v4, v0.t
- + vsxseg4ei64.v v4, (a0), v4
- + vsxseg4ei64.v v0, (a0), v4, v0.t
- + vlxseg5ei64.v v4, (a0), v4
- + vlxseg5ei64.v v0, (a0), v4, v0.t
- + vsxseg5ei64.v v4, (a0), v4
- + vsxseg5ei64.v v0, (a0), v4, v0.t
- + vlxseg6ei64.v v4, (a0), v4
- + vlxseg6ei64.v v0, (a0), v4, v0.t
- + vsxseg6ei64.v v4, (a0), v4
- + vsxseg6ei64.v v0, (a0), v4, v0.t
- + vlxseg7ei64.v v4, (a0), v4
- + vlxseg7ei64.v v0, (a0), v4, v0.t
- + vsxseg7ei64.v v4, (a0), v4
- + vsxseg7ei64.v v0, (a0), v4, v0.t
- + vlxseg8ei64.v v4, (a0), v4
- + vlxseg8ei64.v v0, (a0), v4, v0.t
- + vsxseg8ei64.v v4, (a0), v4
- + vsxseg8ei64.v v0, (a0), v4, v0.t
- +
- + vlxseg2ei128.v v4, (a0), v4
- + vlxseg2ei128.v v0, (a0), v4, v0.t
- + vsxseg2ei128.v v4, (a0), v4
- + vsxseg2ei128.v v0, (a0), v4, v0.t
- + vlxseg3ei128.v v4, (a0), v4
- + vlxseg3ei128.v v0, (a0), v4, v0.t
- + vsxseg3ei128.v v4, (a0), v4
- + vsxseg3ei128.v v0, (a0), v4, v0.t
- + vlxseg4ei128.v v4, (a0), v4
- + vlxseg4ei128.v v0, (a0), v4, v0.t
- + vsxseg4ei128.v v4, (a0), v4
- + vsxseg4ei128.v v0, (a0), v4, v0.t
- + vlxseg5ei128.v v4, (a0), v4
- + vlxseg5ei128.v v0, (a0), v4, v0.t
- + vsxseg5ei128.v v4, (a0), v4
- + vsxseg5ei128.v v0, (a0), v4, v0.t
- + vlxseg6ei128.v v4, (a0), v4
- + vlxseg6ei128.v v0, (a0), v4, v0.t
- + vsxseg6ei128.v v4, (a0), v4
- + vsxseg6ei128.v v0, (a0), v4, v0.t
- + vlxseg7ei128.v v4, (a0), v4
- + vlxseg7ei128.v v0, (a0), v4, v0.t
- + vsxseg7ei128.v v4, (a0), v4
- + vsxseg7ei128.v v0, (a0), v4, v0.t
- + vlxseg8ei128.v v4, (a0), v4
- + vlxseg8ei128.v v0, (a0), v4, v0.t
- + vsxseg8ei128.v v4, (a0), v4
- + vsxseg8ei128.v v0, (a0), v4, v0.t
- +
- + vlxseg2ei256.v v4, (a0), v4
- + vlxseg2ei256.v v0, (a0), v4, v0.t
- + vsxseg2ei256.v v4, (a0), v4
- + vsxseg2ei256.v v0, (a0), v4, v0.t
- + vlxseg3ei256.v v4, (a0), v4
- + vlxseg3ei256.v v0, (a0), v4, v0.t
- + vsxseg3ei256.v v4, (a0), v4
- + vsxseg3ei256.v v0, (a0), v4, v0.t
- + vlxseg4ei256.v v4, (a0), v4
- + vlxseg4ei256.v v0, (a0), v4, v0.t
- + vsxseg4ei256.v v4, (a0), v4
- + vsxseg4ei256.v v0, (a0), v4, v0.t
- + vlxseg5ei256.v v4, (a0), v4
- + vlxseg5ei256.v v0, (a0), v4, v0.t
- + vsxseg5ei256.v v4, (a0), v4
- + vsxseg5ei256.v v0, (a0), v4, v0.t
- + vlxseg6ei256.v v4, (a0), v4
- + vlxseg6ei256.v v0, (a0), v4, v0.t
- + vsxseg6ei256.v v4, (a0), v4
- + vsxseg6ei256.v v0, (a0), v4, v0.t
- + vlxseg7ei256.v v4, (a0), v4
- + vlxseg7ei256.v v0, (a0), v4, v0.t
- + vsxseg7ei256.v v4, (a0), v4
- + vsxseg7ei256.v v0, (a0), v4, v0.t
- + vlxseg8ei256.v v4, (a0), v4
- + vlxseg8ei256.v v0, (a0), v4, v0.t
- + vsxseg8ei256.v v4, (a0), v4
- + vsxseg8ei256.v v0, (a0), v4, v0.t
- +
- + vlxseg2ei512.v v4, (a0), v4
- + vlxseg2ei512.v v0, (a0), v4, v0.t
- + vsxseg2ei512.v v4, (a0), v4
- + vsxseg2ei512.v v0, (a0), v4, v0.t
- + vlxseg3ei512.v v4, (a0), v4
- + vlxseg3ei512.v v0, (a0), v4, v0.t
- + vsxseg3ei512.v v4, (a0), v4
- + vsxseg3ei512.v v0, (a0), v4, v0.t
- + vlxseg4ei512.v v4, (a0), v4
- + vlxseg4ei512.v v0, (a0), v4, v0.t
- + vsxseg4ei512.v v4, (a0), v4
- + vsxseg4ei512.v v0, (a0), v4, v0.t
- + vlxseg5ei512.v v4, (a0), v4
- + vlxseg5ei512.v v0, (a0), v4, v0.t
- + vsxseg5ei512.v v4, (a0), v4
- + vsxseg5ei512.v v0, (a0), v4, v0.t
- + vlxseg6ei512.v v4, (a0), v4
- + vlxseg6ei512.v v0, (a0), v4, v0.t
- + vsxseg6ei512.v v4, (a0), v4
- + vsxseg6ei512.v v0, (a0), v4, v0.t
- + vlxseg7ei512.v v4, (a0), v4
- + vlxseg7ei512.v v0, (a0), v4, v0.t
- + vsxseg7ei512.v v4, (a0), v4
- + vsxseg7ei512.v v0, (a0), v4, v0.t
- + vlxseg8ei512.v v4, (a0), v4
- + vlxseg8ei512.v v0, (a0), v4, v0.t
- + vsxseg8ei512.v v4, (a0), v4
- + vsxseg8ei512.v v0, (a0), v4, v0.t
- +
- + vlxseg2ei1024.v v4, (a0), v4
- + vlxseg2ei1024.v v0, (a0), v4, v0.t
- + vsxseg2ei1024.v v4, (a0), v4
- + vsxseg2ei1024.v v0, (a0), v4, v0.t
- + vlxseg3ei1024.v v4, (a0), v4
- + vlxseg3ei1024.v v0, (a0), v4, v0.t
- + vsxseg3ei1024.v v4, (a0), v4
- + vsxseg3ei1024.v v0, (a0), v4, v0.t
- + vlxseg4ei1024.v v4, (a0), v4
- + vlxseg4ei1024.v v0, (a0), v4, v0.t
- + vsxseg4ei1024.v v4, (a0), v4
- + vsxseg4ei1024.v v0, (a0), v4, v0.t
- + vlxseg5ei1024.v v4, (a0), v4
- + vlxseg5ei1024.v v0, (a0), v4, v0.t
- + vsxseg5ei1024.v v4, (a0), v4
- + vsxseg5ei1024.v v0, (a0), v4, v0.t
- + vlxseg6ei1024.v v4, (a0), v4
- + vlxseg6ei1024.v v0, (a0), v4, v0.t
- + vsxseg6ei1024.v v4, (a0), v4
- + vsxseg6ei1024.v v0, (a0), v4, v0.t
- + vlxseg7ei1024.v v4, (a0), v4
- + vlxseg7ei1024.v v0, (a0), v4, v0.t
- + vsxseg7ei1024.v v4, (a0), v4
- + vsxseg7ei1024.v v0, (a0), v4, v0.t
- + vlxseg8ei1024.v v4, (a0), v4
- + vlxseg8ei1024.v v0, (a0), v4, v0.t
- + vsxseg8ei1024.v v4, (a0), v4
- + vsxseg8ei1024.v v0, (a0), v4, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.d b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
- new file mode 100644
- index 0000000000..35f9e2c32c
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32iv -mcheck-constraints
- +#source: vector-insns-fail-mask.s
- +#error_output: vector-insns-fail-mask.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
- new file mode 100644
- index 0000000000..5c4e881489
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
- @@ -0,0 +1,7 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vmsbf.m v0,v4,v0.t'
- +.*Error: illegal operands `vmsif.m v0,v4,v0.t'
- +.*Error: illegal operands `vmsof.m v0,v4,v0.t'
- +.*Error: illegal operands `viota.m v4,v4'
- +.*Error: illegal operands `viota.m v0,v4,v0.t'
- +.*Error: illegal operands `vid.v v0,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
- new file mode 100644
- index 0000000000..580b101c77
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
- @@ -0,0 +1,20 @@
- +# Vector Set-before-first Mask Bit
- +
- + vmsbf.m v0, v4, v0.t # vd overlap vm
- +
- +# Vector Set-including-first Mask Bit
- +
- + vmsif.m v0, v4, v0.t # vd overlap vm
- +
- +# Vector Set-only-first Mask Bit
- +
- + vmsof.m v0, v4, v0.t # vd overlap vm
- +
- +# Vector Iota Instruction
- +
- + viota.m v4, v4 # vd overlap vs2
- + viota.m v0, v4, v0.t # vd overlap vm
- +
- +# Vector Element Index Instruction
- +
- + vid.v v0, v0.t # vd overlap vm
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
- new file mode 100644
- index 0000000000..9822e2919a
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32ifv -mcheck-constraints
- +#source: vector-insns-fail-permutation.s
- +#error_output: vector-insns-fail-permutation.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
- new file mode 100644
- index 0000000000..c208f5710f
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
- @@ -0,0 +1,31 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vslideup.vx v4,v4,a1'
- +.*Error: illegal operands `vslideup.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vslideup.vi v4,v4,31'
- +.*Error: illegal operands `vslideup.vi v0,v4,31,v0.t'
- +.*Error: illegal operands `vslidedown.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vslidedown.vi v0,v4,31,v0.t'
- +.*Error: illegal operands `vslide1up.vx v4,v4,a1'
- +.*Error: illegal operands `vslide1up.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vfslide1up.vf v4,v4,fa1'
- +.*Error: illegal operands `vfslide1up.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vslide1down.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vfslide1down.vf v0,v4,fa1,v0.t'
- +.*Error: illegal operands `vrgather.vv v4,v4,v8'
- +.*Error: illegal operands `vrgather.vv v8,v4,v8'
- +.*Error: illegal operands `vrgather.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vrgather.vx v4,v4,a1'
- +.*Error: illegal operands `vrgather.vx v0,v4,a1,v0.t'
- +.*Error: illegal operands `vrgather.vi v4,v4,31'
- +.*Error: illegal operands `vrgather.vi v0,v4,31,v0.t'
- +.*Error: illegal operands `vrgatherei16.vv v4,v4,v8'
- +.*Error: illegal operands `vrgatherei16.vv v8,v4,v8'
- +.*Error: illegal operands `vrgatherei16.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vcompress.vm v4,v4,v8'
- +.*Error: illegal operands `vcompress.vm v8,v4,v8'
- +.*Error: illegal operands `vmv2r.v v30,v31'
- +.*Error: illegal operands `vmv2r.v v31,v30'
- +.*Error: illegal operands `vmv4r.v v28,v30'
- +.*Error: illegal operands `vmv4r.v v30,v28'
- +.*Error: illegal operands `vmv8r.v v24,v26'
- +.*Error: illegal operands `vmv8r.v v26,v24'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
- new file mode 100644
- index 0000000000..85116457ff
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
- @@ -0,0 +1,56 @@
- +# Vector Slideup Instructions
- +
- + vslideup.vx v4, v4, a1 # vd overlap vs2
- + vslideup.vx v0, v4, a1, v0.t # vd overlap vm
- + vslideup.vi v4, v4, 31 # vd overlap vs2
- + vslideup.vi v0, v4, 31, v0.t # vd overlap vm
- +
- + vslidedown.vx v4, v4, a1 # OK
- + vslidedown.vx v0, v4, a1, v0.t # vd overlap vm
- + vslidedown.vi v4, v4, 31 # OK
- + vslidedown.vi v0, v4, 31, v0.t # vd overlap vm
- +
- + vslide1up.vx v4, v4, a1 # vd overlap vs2
- + vslide1up.vx v0, v4, a1, v0.t # vd overlap vm
- + vfslide1up.vf v4, v4, fa1 # vd overlap vs2
- + vfslide1up.vf v0, v4, fa1, v0.t # vd overlap vm
- +
- + vslide1down.vx v4, v4, a1 # OK
- + vslide1down.vx v0, v4, a1, v0.t # vd overlap vm
- + vfslide1down.vf v4, v4, fa1 # OK
- + vfslide1down.vf v0, v4, fa1, v0.t # vd overlap vm
- +
- +# Vector Register Gather Instructions
- +
- + vrgather.vv v4, v4, v8 # vd overlap vs2
- + vrgather.vv v8, v4, v8 # vd overlap vs1
- + vrgather.vv v0, v4, v8, v0.t # vd overlap vm
- + vrgather.vx v4, v4, a1 # vd overlap vs2
- + vrgather.vx v0, v4, a1, v0.t # vd overlap vm
- + vrgather.vi v4, v4, 31 # vd overlap vs2
- + vrgather.vi v0, v4, 31, v0.t # vd overlap vm
- +
- + vrgatherei16.vv v4, v4, v8 # vd overlap vs2
- + vrgatherei16.vv v8, v4, v8 # vd overlap vs1
- + vrgatherei16.vv v0, v4, v8, v0.t # vd overlap vm
- +
- +# Vector Compress Instruction
- +
- + vcompress.vm v4, v4, v8 # vd overlap vs2
- + vcompress.vm v8, v4, v8 # vd overlap vs1
- +
- +# Whole Vector Register Move
- +
- + vmv1r.v v31, v31 # OK, HINT
- +
- + vmv2r.v v30, v30 # OK, HINT
- + vmv2r.v v30, v31 # vs2 must be aligned to 2
- + vmv2r.v v31, v30 # vd must be aligned to 2
- +
- + vmv4r.v v28, v28 # OK, HINT
- + vmv4r.v v28, v30 # vs2 must be aligned to 4
- + vmv4r.v v30, v28 # vd must be aligned to 4
- +
- + vmv8r.v v24, v24 # OK, HINT
- + vmv8r.v v24, v26 # vs2 must be aligned to 8
- + vmv8r.v v26, v24 # vd must be aligned to 8
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
- new file mode 100644
- index 0000000000..5749449bd0
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32iav -mcheck-constraints
- +#source: vector-insns-fail-zvamo.s
- +#error_output: vector-insns-fail-zvamo.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
- new file mode 100644
- index 0000000000..6207fb2fee
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
- @@ -0,0 +1,109 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vamoaddei8.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoaddei8.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoaddei8.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoswapei8.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoswapei8.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoswapei8.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoxorei8.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoxorei8.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoxorei8.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoandei8.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoandei8.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoandei8.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoorei8.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoorei8.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoorei8.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominei8.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamominei8.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominei8.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxei8.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamomaxei8.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxei8.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominuei8.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamominuei8.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominuei8.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxuei8.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamomaxuei8.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxuei8.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoaddei16.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoaddei16.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoaddei16.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoswapei16.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoswapei16.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoswapei16.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoxorei16.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoxorei16.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoxorei16.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoandei16.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoandei16.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoandei16.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoorei16.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoorei16.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoorei16.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominei16.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominei16.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamominei16.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxei16.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxei16.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamomaxei16.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominuei16.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominuei16.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamominuei16.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxuei16.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxuei16.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamomaxuei16.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoaddei32.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoaddei32.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoaddei32.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoswapei32.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoswapei32.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoswapei32.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoxorei32.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoxorei32.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoxorei32.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoandei32.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoandei32.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoandei32.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoorei32.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoorei32.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoorei32.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominei32.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamominei32.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominei32.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxei32.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamomaxei32.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxei32.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominuei32.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamominuei32.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominuei32.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxuei32.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamomaxuei32.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxuei32.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoaddei64.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoaddei64.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoaddei64.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoswapei64.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoswapei64.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoswapei64.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoxorei64.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoxorei64.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoxorei64.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoandei64.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoandei64.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoandei64.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoorei64.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamoorei64.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamoorei64.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominei64.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamominei64.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominei64.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxei64.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamomaxei64.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxei64.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominuei64.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamominuei64.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamominuei64.v x0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxuei64.v v4,\(a1\),v4,v0'
- +.*Error: illegal operands `vamomaxuei64.v v0,\(a1\),v4,v0,v0.t'
- +.*Error: illegal operands `vamomaxuei64.v x0,\(a1\),v4,v0,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
- new file mode 100644
- index 0000000000..0fd3c26a58
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
- @@ -0,0 +1,217 @@
- +# Vector AMO Operations
- +
- + vamoaddei8.v v0, (a1), v4, v0 # OK
- + vamoaddei8.v v4, (a1), v4, v0 # vd must match vs3
- + vamoaddei8.v v0, (a1), v4, v0, v0.t # vd overlap vm
- + vamoaddei8.v x0, (a1), v4, v0 # OK
- + vamoaddei8.v x0, (a1), v4, v0, v0.t # vs3 overlap vm
- +
- + vamoswapei8.v v0, (a1), v4, v0
- + vamoswapei8.v v4, (a1), v4, v0
- + vamoswapei8.v v0, (a1), v4, v0, v0.t
- + vamoswapei8.v x0, (a1), v4, v0
- + vamoswapei8.v x0, (a1), v4, v0, v0.t
- +
- + vamoxorei8.v v0, (a1), v4, v0
- + vamoxorei8.v v4, (a1), v4, v0
- + vamoxorei8.v v0, (a1), v4, v0, v0.t
- + vamoxorei8.v x0, (a1), v4, v0
- + vamoxorei8.v x0, (a1), v4, v0, v0.t
- +
- + vamoandei8.v v0, (a1), v4, v0
- + vamoandei8.v v4, (a1), v4, v0
- + vamoandei8.v v0, (a1), v4, v0, v0.t
- + vamoandei8.v x0, (a1), v4, v0
- + vamoandei8.v x0, (a1), v4, v0, v0.t
- +
- + vamoorei8.v v0, (a1), v4, v0
- + vamoorei8.v v4, (a1), v4, v0
- + vamoorei8.v v0, (a1), v4, v0, v0.t
- + vamoorei8.v x0, (a1), v4, v0
- + vamoorei8.v x0, (a1), v4, v0, v0.t
- +
- + vamominei8.v v0, (a1), v4, v0
- + vamominei8.v v4, (a1), v4, v0
- + vamominei8.v v0, (a1), v4, v0, v0.t
- + vamominei8.v x0, (a1), v4, v0
- + vamominei8.v x0, (a1), v4, v0, v0.t
- +
- + vamomaxei8.v v0, (a1), v4, v0
- + vamomaxei8.v v4, (a1), v4, v0
- + vamomaxei8.v v0, (a1), v4, v0, v0.t
- + vamomaxei8.v x0, (a1), v4, v0
- + vamomaxei8.v x0, (a1), v4, v0, v0.t
- +
- + vamominuei8.v v0, (a1), v4, v0
- + vamominuei8.v v4, (a1), v4, v0
- + vamominuei8.v v0, (a1), v4, v0, v0.t
- + vamominuei8.v x0, (a1), v4, v0
- + vamominuei8.v x0, (a1), v4, v0, v0.t
- +
- + vamomaxuei8.v v0, (a1), v4, v0
- + vamomaxuei8.v v4, (a1), v4, v0
- + vamomaxuei8.v v0, (a1), v4, v0, v0.t
- + vamomaxuei8.v x0, (a1), v4, v0
- + vamomaxuei8.v x0, (a1), v4, v0, v0.t
- +
- + vamoaddei16.v v0, (a1), v4, v0
- + vamoaddei16.v v4, (a1), v4, v0
- + vamoaddei16.v v0, (a1), v4, v0, v0.t
- + vamoaddei16.v x0, (a1), v4, v0
- + vamoaddei16.v x0, (a1), v4, v0, v0.t
- +
- + vamoswapei16.v v0, (a1), v4, v0
- + vamoswapei16.v v0, (a1), v4, v0, v0.t
- + vamoswapei16.v v4, (a1), v4, v0
- + vamoswapei16.v x0, (a1), v4, v0
- + vamoswapei16.v x0, (a1), v4, v0, v0.t
- +
- + vamoxorei16.v v0, (a1), v4, v0
- + vamoxorei16.v v0, (a1), v4, v0, v0.t
- + vamoxorei16.v v4, (a1), v4, v0
- + vamoxorei16.v x0, (a1), v4, v0
- + vamoxorei16.v x0, (a1), v4, v0, v0.t
- +
- + vamoandei16.v v0, (a1), v4, v0
- + vamoandei16.v v0, (a1), v4, v0, v0.t
- + vamoandei16.v v4, (a1), v4, v0
- + vamoandei16.v x0, (a1), v4, v0
- + vamoandei16.v x0, (a1), v4, v0, v0.t
- +
- + vamoorei16.v v0, (a1), v4, v0
- + vamoorei16.v v0, (a1), v4, v0, v0.t
- + vamoorei16.v v4, (a1), v4, v0
- + vamoorei16.v x0, (a1), v4, v0
- + vamoorei16.v x0, (a1), v4, v0, v0.t
- +
- + vamominei16.v v0, (a1), v4, v0
- + vamominei16.v v0, (a1), v4, v0, v0.t
- + vamominei16.v v4, (a1), v4, v0
- + vamominei16.v x0, (a1), v4, v0
- + vamominei16.v x0, (a1), v4, v0, v0.t
- +
- + vamomaxei16.v v0, (a1), v4, v0
- + vamomaxei16.v v0, (a1), v4, v0, v0.t
- + vamomaxei16.v v4, (a1), v4, v0
- + vamomaxei16.v x0, (a1), v4, v0
- + vamomaxei16.v x0, (a1), v4, v0, v0.t
- +
- + vamominuei16.v v0, (a1), v4, v0
- + vamominuei16.v v0, (a1), v4, v0, v0.t
- + vamominuei16.v v4, (a1), v4, v0
- + vamominuei16.v x0, (a1), v4, v0
- + vamominuei16.v x0, (a1), v4, v0, v0.t
- +
- + vamomaxuei16.v v0, (a1), v4, v0
- + vamomaxuei16.v v0, (a1), v4, v0, v0.t
- + vamomaxuei16.v v4, (a1), v4, v0
- + vamomaxuei16.v x0, (a1), v4, v0
- + vamomaxuei16.v x0, (a1), v4, v0, v0.t
- +
- + vamoaddei32.v v0, (a1), v4, v0
- + vamoaddei32.v v0, (a1), v4, v0, v0.t
- + vamoaddei32.v v4, (a1), v4, v0
- + vamoaddei32.v x0, (a1), v4, v0
- + vamoaddei32.v x0, (a1), v4, v0, v0.t
- +
- + vamoswapei32.v v0, (a1), v4, v0
- + vamoswapei32.v v4, (a1), v4, v0
- + vamoswapei32.v v0, (a1), v4, v0, v0.t
- + vamoswapei32.v x0, (a1), v4, v0
- + vamoswapei32.v x0, (a1), v4, v0, v0.t
- +
- + vamoxorei32.v v0, (a1), v4, v0
- + vamoxorei32.v v4, (a1), v4, v0
- + vamoxorei32.v v0, (a1), v4, v0, v0.t
- + vamoxorei32.v x0, (a1), v4, v0
- + vamoxorei32.v x0, (a1), v4, v0, v0.t
- +
- + vamoandei32.v v0, (a1), v4, v0
- + vamoandei32.v v4, (a1), v4, v0
- + vamoandei32.v v0, (a1), v4, v0, v0.t
- + vamoandei32.v x0, (a1), v4, v0
- + vamoandei32.v x0, (a1), v4, v0, v0.t
- +
- + vamoorei32.v v0, (a1), v4, v0
- + vamoorei32.v v4, (a1), v4, v0
- + vamoorei32.v v0, (a1), v4, v0, v0.t
- + vamoorei32.v x0, (a1), v4, v0
- + vamoorei32.v x0, (a1), v4, v0, v0.t
- +
- + vamominei32.v v0, (a1), v4, v0
- + vamominei32.v v4, (a1), v4, v0
- + vamominei32.v v0, (a1), v4, v0, v0.t
- + vamominei32.v x0, (a1), v4, v0
- + vamominei32.v x0, (a1), v4, v0, v0.t
- +
- + vamomaxei32.v v0, (a1), v4, v0
- + vamomaxei32.v v4, (a1), v4, v0
- + vamomaxei32.v v0, (a1), v4, v0, v0.t
- + vamomaxei32.v x0, (a1), v4, v0
- + vamomaxei32.v x0, (a1), v4, v0, v0.t
- +
- + vamominuei32.v v0, (a1), v4, v0
- + vamominuei32.v v4, (a1), v4, v0
- + vamominuei32.v v0, (a1), v4, v0, v0.t
- + vamominuei32.v x0, (a1), v4, v0
- + vamominuei32.v x0, (a1), v4, v0, v0.t
- +
- + vamomaxuei32.v v0, (a1), v4, v0
- + vamomaxuei32.v v4, (a1), v4, v0
- + vamomaxuei32.v v0, (a1), v4, v0, v0.t
- + vamomaxuei32.v x0, (a1), v4, v0
- + vamomaxuei32.v x0, (a1), v4, v0, v0.t
- +
- + vamoaddei64.v v0, (a1), v4, v0
- + vamoaddei64.v v4, (a1), v4, v0
- + vamoaddei64.v v0, (a1), v4, v0, v0.t
- + vamoaddei64.v x0, (a1), v4, v0
- + vamoaddei64.v x0, (a1), v4, v0, v0.t
- +
- + vamoswapei64.v v0, (a1), v4, v0
- + vamoswapei64.v v4, (a1), v4, v0
- + vamoswapei64.v v0, (a1), v4, v0, v0.t
- + vamoswapei64.v x0, (a1), v4, v0
- + vamoswapei64.v x0, (a1), v4, v0, v0.t
- +
- + vamoxorei64.v v0, (a1), v4, v0
- + vamoxorei64.v v4, (a1), v4, v0
- + vamoxorei64.v v0, (a1), v4, v0, v0.t
- + vamoxorei64.v x0, (a1), v4, v0
- + vamoxorei64.v x0, (a1), v4, v0, v0.t
- +
- + vamoandei64.v v0, (a1), v4, v0
- + vamoandei64.v v4, (a1), v4, v0
- + vamoandei64.v v0, (a1), v4, v0, v0.t
- + vamoandei64.v x0, (a1), v4, v0
- + vamoandei64.v x0, (a1), v4, v0, v0.t
- +
- + vamoorei64.v v0, (a1), v4, v0
- + vamoorei64.v v4, (a1), v4, v0
- + vamoorei64.v v0, (a1), v4, v0, v0.t
- + vamoorei64.v x0, (a1), v4, v0
- + vamoorei64.v x0, (a1), v4, v0, v0.t
- +
- + vamominei64.v v0, (a1), v4, v0
- + vamominei64.v v4, (a1), v4, v0
- + vamominei64.v v0, (a1), v4, v0, v0.t
- + vamominei64.v x0, (a1), v4, v0
- + vamominei64.v x0, (a1), v4, v0, v0.t
- +
- + vamomaxei64.v v0, (a1), v4, v0
- + vamomaxei64.v v4, (a1), v4, v0
- + vamomaxei64.v v0, (a1), v4, v0, v0.t
- + vamomaxei64.v x0, (a1), v4, v0
- + vamomaxei64.v x0, (a1), v4, v0, v0.t
- +
- + vamominuei64.v v0, (a1), v4, v0
- + vamominuei64.v v4, (a1), v4, v0
- + vamominuei64.v v0, (a1), v4, v0, v0.t
- + vamominuei64.v x0, (a1), v4, v0
- + vamominuei64.v x0, (a1), v4, v0, v0.t
- +
- + vamomaxuei64.v v0, (a1), v4, v0
- + vamomaxuei64.v v4, (a1), v4, v0
- + vamomaxuei64.v v0, (a1), v4, v0, v0.t
- + vamomaxuei64.v x0, (a1), v4, v0
- + vamomaxuei64.v x0, (a1), v4, v0, v0.t
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d
- new file mode 100644
- index 0000000000..912408ed06
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.d
- @@ -0,0 +1,3 @@
- +#as: -march=rv32iv_zvqmac -mcheck-constraints
- +#source: vector-insns-fail-zvqmac.s
- +#error_output: vector-insns-fail-zvqmac.l
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
- new file mode 100644
- index 0000000000..e5c157fd89
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.l
- @@ -0,0 +1,35 @@
- +.*: Assembler messages:
- +.*Error: illegal operands `vqmaccu.vv v2,v4,v8'
- +.*Error: illegal operands `vqmaccu.vv v4,v4,v8'
- +.*Error: illegal operands `vqmaccu.vv v4,v7,v8'
- +.*Error: illegal operands `vqmaccu.vv v8,v4,v8'
- +.*Error: illegal operands `vqmaccu.vv v8,v4,v11'
- +.*Error: illegal operands `vqmaccu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vqmaccu.vx v2,a1,v4'
- +.*Error: illegal operands `vqmaccu.vx v4,a1,v4'
- +.*Error: illegal operands `vqmaccu.vx v4,a1,v7'
- +.*Error: illegal operands `vqmaccu.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vqmacc.vv v2,v4,v8'
- +.*Error: illegal operands `vqmacc.vv v4,v4,v8'
- +.*Error: illegal operands `vqmacc.vv v4,v7,v8'
- +.*Error: illegal operands `vqmacc.vv v8,v4,v8'
- +.*Error: illegal operands `vqmacc.vv v8,v4,v11'
- +.*Error: illegal operands `vqmacc.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vqmacc.vx v2,a1,v4'
- +.*Error: illegal operands `vqmacc.vx v4,a1,v4'
- +.*Error: illegal operands `vqmacc.vx v4,a1,v7'
- +.*Error: illegal operands `vqmacc.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vqmaccsu.vv v2,v4,v8'
- +.*Error: illegal operands `vqmaccsu.vv v4,v4,v8'
- +.*Error: illegal operands `vqmaccsu.vv v4,v7,v8'
- +.*Error: illegal operands `vqmaccsu.vv v8,v4,v8'
- +.*Error: illegal operands `vqmaccsu.vv v8,v4,v11'
- +.*Error: illegal operands `vqmaccsu.vv v0,v4,v8,v0.t'
- +.*Error: illegal operands `vqmaccsu.vx v2,a1,v4'
- +.*Error: illegal operands `vqmaccsu.vx v4,a1,v4'
- +.*Error: illegal operands `vqmaccsu.vx v4,a1,v7'
- +.*Error: illegal operands `vqmaccsu.vx v0,a1,v4,v0.t'
- +.*Error: illegal operands `vqmaccus.vx v2,a1,v4'
- +.*Error: illegal operands `vqmaccus.vx v4,a1,v4'
- +.*Error: illegal operands `vqmaccus.vx v4,a1,v7'
- +.*Error: illegal operands `vqmaccus.vx v0,a1,v4,v0.t'
- diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s
- new file mode 100644
- index 0000000000..930e211dae
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvqmac.s
- @@ -0,0 +1,39 @@
- +# Quad-Widening Vector Arithmetic Instructions
- +
- + vqmaccu.vv v2, v4, v8 # vd should be multiple of 4
- + vqmaccu.vv v4, v4, v8 # vd overlap vs1
- + vqmaccu.vv v4, v7, v8 # vd overlap vs1
- + vqmaccu.vv v8, v4, v8 # vd overlap vs2
- + vqmaccu.vv v8, v4, v11 # vd overlap vs2
- + vqmaccu.vv v0, v4, v8, v0.t # vd overlap vm
- + vqmaccu.vx v2, a1, v4 # vd should be multiple of 4
- + vqmaccu.vx v4, a1, v4 # vd overlap vs2
- + vqmaccu.vx v4, a1, v7 # vd overlap vs2
- + vqmaccu.vx v0, a1, v4, v0.t # vd overlap vm
- +
- + vqmacc.vv v2, v4, v8
- + vqmacc.vv v4, v4, v8
- + vqmacc.vv v4, v7, v8
- + vqmacc.vv v8, v4, v8
- + vqmacc.vv v8, v4, v11
- + vqmacc.vv v0, v4, v8, v0.t
- + vqmacc.vx v2, a1, v4
- + vqmacc.vx v4, a1, v4
- + vqmacc.vx v4, a1, v7
- + vqmacc.vx v0, a1, v4, v0.t
- +
- + vqmaccsu.vv v2, v4, v8
- + vqmaccsu.vv v4, v4, v8
- + vqmaccsu.vv v4, v7, v8
- + vqmaccsu.vv v8, v4, v8
- + vqmaccsu.vv v8, v4, v11
- + vqmaccsu.vv v0, v4, v8, v0.t
- + vqmaccsu.vx v2, a1, v4
- + vqmaccsu.vx v4, a1, v4
- + vqmaccsu.vx v4, a1, v7
- + vqmaccsu.vx v0, a1, v4, v0.t
- +
- + vqmaccus.vx v2, a1, v4 # vd should be multiple of 4
- + vqmaccus.vx v4, a1, v4 # vd overlap vs2
- + vqmaccus.vx v4, a1, v7 # vd overlap vs2
- + vqmaccus.vx v0, a1, v4, v0.t # vd overlap vm
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index c7ecb7c965..58190fd7c9 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -381,16 +381,18 @@ match_quad_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
- }
-
- static int
- -match_narrow_vd_neq_vs2 (const struct riscv_opcode *op,
- - insn_t insn,
- - int constraints)
- +match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
- + insn_t insn,
- + int constraints)
- {
- int vd = (insn & MASK_VD) >> OP_SH_VD;
- int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- + int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
-
- if (constraints
- && ((vs2 % 2) != 0
- - || (vd >= vs2 && vd <= (vs2 + 1))))
- + || (vd >= vs2 && vd <= (vs2 + 1))
- + || (!vm && vd >= vm && vd <= (vm + 1))))
- return 0;
-
- return match_opcode (op, insn, 0);
- @@ -432,19 +434,10 @@ match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
- return match_opcode (op, insn, 0);
- }
-
- -static int
- -match_vd_neq_vs2 (const struct riscv_opcode *op,
- - insn_t insn,
- - int constraints)
- -{
- - int vd = (insn & MASK_VD) >> OP_SH_VD;
- - int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
- -
- - if (constraints && vs2 == vd)
- - return 0;
- -
- - return match_opcode (op, insn, 0);
- -}
- +/* v[m]adc and v[m]sbc use the vm encoding to encode the
- + carry-in v0 register. The carry-in v0 register can not
- + overlap with the vd, too. Therefore, we use the same
- + match_vd_neq_vm to check the overlap constraints. */
-
- static int
- match_vd_neq_vm (const struct riscv_opcode *op,
- @@ -1066,305 +1059,305 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vsetvl", 0, INSN_CLASS_V, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
- {"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
-
- -{"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
- -{"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
- -{"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
- -{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
- -{"vle128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128V, MASK_VLE128V, match_opcode, INSN_DREF },
- -{"vle256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256V, MASK_VLE256V, match_opcode, INSN_DREF },
- -{"vle512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512V, MASK_VLE512V, match_opcode, INSN_DREF },
- -{"vle1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024V, MASK_VLE1024V, match_opcode, INSN_DREF },
- -
- -{"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
- -{"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
- -{"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
- -{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
- -{"vse128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE128V, MASK_VSE128V, match_opcode, INSN_DREF },
- -{"vse256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE256V, MASK_VSE256V, match_opcode, INSN_DREF },
- -{"vse512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE512V, MASK_VSE512V, match_opcode, INSN_DREF },
- -{"vse1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE1024V, MASK_VSE1024V, match_opcode, INSN_DREF },
- -
- -{"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
- -{"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
- -{"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
- -{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
- -{"vlse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE128V, MASK_VLSE128V, match_opcode, INSN_DREF },
- -{"vlse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE256V, MASK_VLSE256V, match_opcode, INSN_DREF },
- -{"vlse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE512V, MASK_VLSE512V, match_opcode, INSN_DREF },
- -{"vlse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE1024V, MASK_VLSE1024V, match_opcode, INSN_DREF },
- -
- -{"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
- -{"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
- -{"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
- -{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
- -{"vsse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE128V, MASK_VSSE128V, match_opcode, INSN_DREF },
- -{"vsse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE256V, MASK_VSSE256V, match_opcode, INSN_DREF },
- -{"vsse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_opcode, INSN_DREF },
- -{"vsse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_opcode, INSN_DREF },
- -
- -{"vlxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_opcode, INSN_DREF },
- -{"vlxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_opcode, INSN_DREF },
- -{"vlxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_opcode, INSN_DREF },
- -{"vlxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_opcode, INSN_DREF },
- -
- -{"vsxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_opcode, INSN_DREF },
- -{"vsxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_opcode, INSN_DREF },
- -{"vsxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_opcode, INSN_DREF },
- -{"vsxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_opcode, INSN_DREF },
- -
- -{"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF },
- -{"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF },
- -{"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF },
- -{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF },
- -
- -{"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
- -{"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
- -{"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
- -{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
- -{"vle128ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128FFV, MASK_VLE128FFV, match_opcode, INSN_DREF },
- -{"vle256ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256FFV, MASK_VLE256FFV, match_opcode, INSN_DREF },
- -{"vle512ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512FFV, MASK_VLE512FFV, match_opcode, INSN_DREF },
- -{"vle1024ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024FFV, MASK_VLE1024FFV, match_opcode, INSN_DREF },
- +{"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
- +{"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
- +{"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_vd_neq_vm, INSN_DREF },
- +{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_vd_neq_vm, INSN_DREF },
- +{"vle128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128V, MASK_VLE128V, match_vd_neq_vm, INSN_DREF },
- +{"vle256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256V, MASK_VLE256V, match_vd_neq_vm, INSN_DREF },
- +{"vle512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512V, MASK_VLE512V, match_vd_neq_vm, INSN_DREF },
- +{"vle1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024V, MASK_VLE1024V, match_vd_neq_vm, INSN_DREF },
- +
- +{"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_vd_neq_vm, INSN_DREF },
- +{"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_vd_neq_vm, INSN_DREF },
- +{"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_vd_neq_vm, INSN_DREF },
- +{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_vd_neq_vm, INSN_DREF },
- +{"vse128.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE128V, MASK_VSE128V, match_vd_neq_vm, INSN_DREF },
- +{"vse256.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE256V, MASK_VSE256V, match_vd_neq_vm, INSN_DREF },
- +{"vse512.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE512V, MASK_VSE512V, match_vd_neq_vm, INSN_DREF },
- +{"vse1024.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE1024V, MASK_VSE1024V, match_vd_neq_vm, INSN_DREF },
- +
- +{"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_vd_neq_vm, INSN_DREF },
- +{"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_vd_neq_vm, INSN_DREF },
- +{"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_vd_neq_vm, INSN_DREF },
- +{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_vd_neq_vm, INSN_DREF },
- +{"vlse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE128V, MASK_VLSE128V, match_vd_neq_vm, INSN_DREF },
- +{"vlse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE256V, MASK_VLSE256V, match_vd_neq_vm, INSN_DREF },
- +{"vlse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE512V, MASK_VLSE512V, match_vd_neq_vm, INSN_DREF },
- +{"vlse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE1024V, MASK_VLSE1024V, match_vd_neq_vm, INSN_DREF },
- +
- +{"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_vd_neq_vm, INSN_DREF },
- +{"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_vd_neq_vm, INSN_DREF },
- +{"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_vd_neq_vm, INSN_DREF },
- +{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_vd_neq_vm, INSN_DREF },
- +{"vsse128.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE128V, MASK_VSSE128V, match_vd_neq_vm, INSN_DREF },
- +{"vsse256.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE256V, MASK_VSSE256V, match_vd_neq_vm, INSN_DREF },
- +{"vsse512.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE512V, MASK_VSSE512V, match_vd_neq_vm, INSN_DREF },
- +{"vsse1024.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE1024V, MASK_VSSE1024V, match_vd_neq_vm, INSN_DREF },
- +
- +{"vlxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI8V, MASK_VLXEI8V, match_vd_neq_vm, INSN_DREF },
- +{"vlxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI16V, MASK_VLXEI16V, match_vd_neq_vm, INSN_DREF },
- +{"vlxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI32V, MASK_VLXEI32V, match_vd_neq_vm, INSN_DREF },
- +{"vlxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLXEI64V, MASK_VLXEI64V, match_vd_neq_vm, INSN_DREF },
- +
- +{"vsxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI8V, MASK_VSXEI8V, match_vd_neq_vm, INSN_DREF },
- +{"vsxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI16V, MASK_VSXEI16V, match_vd_neq_vm, INSN_DREF },
- +{"vsxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI32V, MASK_VSXEI32V, match_vd_neq_vm, INSN_DREF },
- +{"vsxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSXEI64V, MASK_VSXEI64V, match_vd_neq_vm, INSN_DREF },
- +
- +{"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
- +{"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
- +{"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
- +{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
- +
- +{"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
- +{"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
- +{"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
- +{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
- +{"vle128ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE128FFV, MASK_VLE128FFV, match_vd_neq_vm, INSN_DREF },
- +{"vle256ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE256FFV, MASK_VLE256FFV, match_vd_neq_vm, INSN_DREF },
- +{"vle512ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE512FFV, MASK_VLE512FFV, match_vd_neq_vm, INSN_DREF },
- +{"vle1024ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE1024FFV, MASK_VLE1024FFV, match_vd_neq_vm, INSN_DREF },
-
- {"vlseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF },
- +{"vsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
- {"vlseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF },
- +{"vsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_vd_neq_vm, INSN_DREF },
- {"vlseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF },
- +{"vsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_vd_neq_vm, INSN_DREF },
- {"vlseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF },
- +{"vsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_vd_neq_vm, INSN_DREF },
- {"vlseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF },
- +{"vsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_vd_neq_vm, INSN_DREF },
- {"vlseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF },
- +{"vsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_vd_neq_vm, INSN_DREF },
- {"vlseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF },
- +{"vsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_vd_neq_vm, INSN_DREF },
-
- {"vlseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF },
- +{"vsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_vd_neq_vm, INSN_DREF },
- {"vlseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF },
- +{"vsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_vd_neq_vm, INSN_DREF },
- {"vlseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF },
- +{"vsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_vd_neq_vm, INSN_DREF },
- {"vlseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF },
- +{"vsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_vd_neq_vm, INSN_DREF },
- {"vlseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF },
- +{"vsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_vd_neq_vm, INSN_DREF },
- {"vlseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF },
- +{"vsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_vd_neq_vm, INSN_DREF },
- {"vlseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF },
- +{"vsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_vd_neq_vm, INSN_DREF },
-
- {"vlseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF },
- +{"vsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_vd_neq_vm, INSN_DREF },
- {"vlseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF },
- +{"vsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_vd_neq_vm, INSN_DREF },
- {"vlseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF },
- +{"vsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_vd_neq_vm, INSN_DREF },
- {"vlseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF },
- +{"vsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_vd_neq_vm, INSN_DREF },
- {"vlseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF },
- +{"vsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_vd_neq_vm, INSN_DREF },
- {"vlseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF },
- +{"vsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_vd_neq_vm, INSN_DREF },
- {"vlseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF },
- +{"vsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
-
- {"vlseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF },
- +{"vsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
- {"vlseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF },
- +{"vsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
- {"vlseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF },
- +{"vsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
- {"vlseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF },
- +{"vsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
- {"vlseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF },
- +{"vsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
- {"vlseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF },
- +{"vsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
- {"vlseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF },
- +{"vsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
-
- {"vlseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E128V, MASK_VLSEG2E128V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E128V, MASK_VSSEG2E128V, match_opcode, INSN_DREF },
- +{"vsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E128V, MASK_VSSEG2E128V, match_vd_neq_vm, INSN_DREF },
- {"vlseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E128V, MASK_VLSEG3E128V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E128V, MASK_VSSEG3E128V, match_opcode, INSN_DREF },
- +{"vsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E128V, MASK_VSSEG3E128V, match_vd_neq_vm, INSN_DREF },
- {"vlseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E128V, MASK_VLSEG4E128V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E128V, MASK_VSSEG4E128V, match_opcode, INSN_DREF },
- +{"vsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E128V, MASK_VSSEG4E128V, match_vd_neq_vm, INSN_DREF },
- {"vlseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E128V, MASK_VLSEG5E128V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E128V, MASK_VSSEG5E128V, match_opcode, INSN_DREF },
- +{"vsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E128V, MASK_VSSEG5E128V, match_vd_neq_vm, INSN_DREF },
- {"vlseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E128V, MASK_VLSEG6E128V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E128V, MASK_VSSEG6E128V, match_opcode, INSN_DREF },
- +{"vsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E128V, MASK_VSSEG6E128V, match_vd_neq_vm, INSN_DREF },
- {"vlseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E128V, MASK_VLSEG7E128V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E128V, MASK_VSSEG7E128V, match_opcode, INSN_DREF },
- +{"vsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E128V, MASK_VSSEG7E128V, match_vd_neq_vm, INSN_DREF },
- {"vlseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E128V, MASK_VLSEG8E128V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E128V, MASK_VSSEG8E128V, match_opcode, INSN_DREF },
- +{"vsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E128V, MASK_VSSEG8E128V, match_vd_neq_vm, INSN_DREF },
-
- {"vlseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E256V, MASK_VLSEG2E256V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E256V, MASK_VSSEG2E256V, match_opcode, INSN_DREF },
- +{"vsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E256V, MASK_VSSEG2E256V, match_vd_neq_vm, INSN_DREF },
- {"vlseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E256V, MASK_VLSEG3E256V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E256V, MASK_VSSEG3E256V, match_opcode, INSN_DREF },
- +{"vsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E256V, MASK_VSSEG3E256V, match_vd_neq_vm, INSN_DREF },
- {"vlseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E256V, MASK_VLSEG4E256V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E256V, MASK_VSSEG4E256V, match_opcode, INSN_DREF },
- +{"vsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E256V, MASK_VSSEG4E256V, match_vd_neq_vm, INSN_DREF },
- {"vlseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E256V, MASK_VLSEG5E256V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E256V, MASK_VSSEG5E256V, match_opcode, INSN_DREF },
- +{"vsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E256V, MASK_VSSEG5E256V, match_vd_neq_vm, INSN_DREF },
- {"vlseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E256V, MASK_VLSEG6E256V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E256V, MASK_VSSEG6E256V, match_opcode, INSN_DREF },
- +{"vsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E256V, MASK_VSSEG6E256V, match_vd_neq_vm, INSN_DREF },
- {"vlseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E256V, MASK_VLSEG7E256V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E256V, MASK_VSSEG7E256V, match_opcode, INSN_DREF },
- +{"vsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E256V, MASK_VSSEG7E256V, match_vd_neq_vm, INSN_DREF },
- {"vlseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E256V, MASK_VLSEG8E256V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E256V, MASK_VSSEG8E256V, match_opcode, INSN_DREF },
- +{"vsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E256V, MASK_VSSEG8E256V, match_vd_neq_vm, INSN_DREF },
-
- {"vlseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E512V, MASK_VLSEG2E512V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E512V, MASK_VSSEG2E512V, match_opcode, INSN_DREF },
- +{"vsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E512V, MASK_VSSEG2E512V, match_vd_neq_vm, INSN_DREF },
- {"vlseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E512V, MASK_VLSEG3E512V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E512V, MASK_VSSEG3E512V, match_opcode, INSN_DREF },
- +{"vsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E512V, MASK_VSSEG3E512V, match_vd_neq_vm, INSN_DREF },
- {"vlseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E512V, MASK_VLSEG4E512V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E512V, MASK_VSSEG4E512V, match_opcode, INSN_DREF },
- +{"vsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E512V, MASK_VSSEG4E512V, match_vd_neq_vm, INSN_DREF },
- {"vlseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E512V, MASK_VLSEG5E512V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E512V, MASK_VSSEG5E512V, match_opcode, INSN_DREF },
- +{"vsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E512V, MASK_VSSEG5E512V, match_vd_neq_vm, INSN_DREF },
- {"vlseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E512V, MASK_VLSEG6E512V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E512V, MASK_VSSEG6E512V, match_opcode, INSN_DREF },
- +{"vsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E512V, MASK_VSSEG6E512V, match_vd_neq_vm, INSN_DREF },
- {"vlseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E512V, MASK_VLSEG7E512V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E512V, MASK_VSSEG7E512V, match_opcode, INSN_DREF },
- +{"vsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E512V, MASK_VSSEG7E512V, match_vd_neq_vm, INSN_DREF },
- {"vlseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E512V, MASK_VLSEG8E512V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E512V, MASK_VSSEG8E512V, match_opcode, INSN_DREF },
- +{"vsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E512V, MASK_VSSEG8E512V, match_vd_neq_vm, INSN_DREF },
-
- {"vlseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E1024V, MASK_VLSEG2E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E1024V, MASK_VSSEG2E1024V, match_opcode, INSN_DREF },
- +{"vsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E1024V, MASK_VSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E1024V, MASK_VLSEG3E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E1024V, MASK_VSSEG3E1024V, match_opcode, INSN_DREF },
- +{"vsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E1024V, MASK_VSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E1024V, MASK_VLSEG4E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E1024V, MASK_VSSEG4E1024V, match_opcode, INSN_DREF },
- +{"vsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E1024V, MASK_VSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E1024V, MASK_VLSEG5E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E1024V, MASK_VSSEG5E1024V, match_opcode, INSN_DREF },
- +{"vsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E1024V, MASK_VSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E1024V, MASK_VLSEG6E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E1024V, MASK_VSSEG6E1024V, match_opcode, INSN_DREF },
- +{"vsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E1024V, MASK_VSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E1024V, MASK_VLSEG7E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E1024V, MASK_VSSEG7E1024V, match_opcode, INSN_DREF },
- +{"vsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E1024V, MASK_VSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E1024V, MASK_VLSEG8E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E1024V, MASK_VSSEG8E1024V, match_opcode, INSN_DREF },
- +{"vsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E1024V, MASK_VSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
-
- {"vlsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF },
- +{"vssseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF },
- +{"vssseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF },
- +{"vssseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF },
- +{"vssseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF },
- +{"vssseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF },
- +{"vssseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF },
- +{"vssseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_vd_neq_vm, INSN_DREF },
-
- {"vlsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF },
- +{"vssseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF },
- +{"vssseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF },
- +{"vssseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF },
- +{"vssseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF },
- +{"vssseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF },
- +{"vssseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF },
- +{"vssseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_vd_neq_vm, INSN_DREF },
-
- {"vlsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF },
- +{"vssseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF },
- +{"vssseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF },
- +{"vssseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF },
- +{"vssseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF },
- +{"vssseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF },
- +{"vssseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF },
- +{"vssseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
-
- {"vlsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF },
- +{"vssseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF },
- +{"vssseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF },
- +{"vssseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF },
- +{"vssseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF },
- +{"vssseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF },
- +{"vssseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF },
- +{"vssseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
-
- {"vlsseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E128V, MASK_VLSSEG2E128V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E128V, MASK_VSSSEG2E128V, match_opcode, INSN_DREF },
- +{"vssseg2e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E128V, MASK_VSSSEG2E128V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E128V, MASK_VLSSEG3E128V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E128V, MASK_VSSSEG3E128V, match_opcode, INSN_DREF },
- +{"vssseg3e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E128V, MASK_VSSSEG3E128V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E128V, MASK_VLSSEG4E128V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E128V, MASK_VSSSEG4E128V, match_opcode, INSN_DREF },
- +{"vssseg4e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E128V, MASK_VSSSEG4E128V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E128V, MASK_VLSSEG5E128V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E128V, MASK_VSSSEG5E128V, match_opcode, INSN_DREF },
- +{"vssseg5e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E128V, MASK_VSSSEG5E128V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E128V, MASK_VLSSEG6E128V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E128V, MASK_VSSSEG6E128V, match_opcode, INSN_DREF },
- +{"vssseg6e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E128V, MASK_VSSSEG6E128V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E128V, MASK_VLSSEG7E128V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E128V, MASK_VSSSEG7E128V, match_opcode, INSN_DREF },
- +{"vssseg7e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E128V, MASK_VSSSEG7E128V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E128V, MASK_VLSSEG8E128V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E128V, MASK_VSSSEG8E128V, match_opcode, INSN_DREF },
- +{"vssseg8e128.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E128V, MASK_VSSSEG8E128V, match_vd_neq_vm, INSN_DREF },
-
- {"vlsseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E256V, MASK_VLSSEG2E256V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E256V, MASK_VSSSEG2E256V, match_opcode, INSN_DREF },
- +{"vssseg2e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E256V, MASK_VSSSEG2E256V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E256V, MASK_VLSSEG3E256V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E256V, MASK_VSSSEG3E256V, match_opcode, INSN_DREF },
- +{"vssseg3e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E256V, MASK_VSSSEG3E256V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E256V, MASK_VLSSEG4E256V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E256V, MASK_VSSSEG4E256V, match_opcode, INSN_DREF },
- +{"vssseg4e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E256V, MASK_VSSSEG4E256V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E256V, MASK_VLSSEG5E256V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E256V, MASK_VSSSEG5E256V, match_opcode, INSN_DREF },
- +{"vssseg5e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E256V, MASK_VSSSEG5E256V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E256V, MASK_VLSSEG6E256V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E256V, MASK_VSSSEG6E256V, match_opcode, INSN_DREF },
- +{"vssseg6e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E256V, MASK_VSSSEG6E256V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E256V, MASK_VLSSEG7E256V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E256V, MASK_VSSSEG7E256V, match_opcode, INSN_DREF },
- +{"vssseg7e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E256V, MASK_VSSSEG7E256V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E256V, MASK_VLSSEG8E256V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E256V, MASK_VSSSEG8E256V, match_opcode, INSN_DREF },
- +{"vssseg8e256.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E256V, MASK_VSSSEG8E256V, match_vd_neq_vm, INSN_DREF },
-
- {"vlsseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E512V, MASK_VLSSEG2E512V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E512V, MASK_VSSSEG2E512V, match_opcode, INSN_DREF },
- +{"vssseg2e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E512V, MASK_VSSSEG2E512V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E512V, MASK_VLSSEG3E512V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E512V, MASK_VSSSEG3E512V, match_opcode, INSN_DREF },
- +{"vssseg3e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E512V, MASK_VSSSEG3E512V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E512V, MASK_VLSSEG4E512V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E512V, MASK_VSSSEG4E512V, match_opcode, INSN_DREF },
- +{"vssseg4e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E512V, MASK_VSSSEG4E512V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E512V, MASK_VLSSEG5E512V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E512V, MASK_VSSSEG5E512V, match_opcode, INSN_DREF },
- +{"vssseg5e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E512V, MASK_VSSSEG5E512V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E512V, MASK_VLSSEG6E512V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E512V, MASK_VSSSEG6E512V, match_opcode, INSN_DREF },
- +{"vssseg6e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E512V, MASK_VSSSEG6E512V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E512V, MASK_VLSSEG7E512V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E512V, MASK_VSSSEG7E512V, match_opcode, INSN_DREF },
- +{"vssseg7e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E512V, MASK_VSSSEG7E512V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E512V, MASK_VLSSEG8E512V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E512V, MASK_VSSSEG8E512V, match_opcode, INSN_DREF },
- +{"vssseg8e512.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E512V, MASK_VSSSEG8E512V, match_vd_neq_vm, INSN_DREF },
-
- {"vlsseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E1024V, MASK_VLSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E1024V, MASK_VSSSEG2E1024V, match_opcode, INSN_DREF },
- +{"vssseg2e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E1024V, MASK_VSSSEG2E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E1024V, MASK_VLSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E1024V, MASK_VSSSEG3E1024V, match_opcode, INSN_DREF },
- +{"vssseg3e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E1024V, MASK_VSSSEG3E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E1024V, MASK_VLSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E1024V, MASK_VSSSEG4E1024V, match_opcode, INSN_DREF },
- +{"vssseg4e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E1024V, MASK_VSSSEG4E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E1024V, MASK_VLSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E1024V, MASK_VSSSEG5E1024V, match_opcode, INSN_DREF },
- +{"vssseg5e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E1024V, MASK_VSSSEG5E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E1024V, MASK_VLSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E1024V, MASK_VSSSEG6E1024V, match_opcode, INSN_DREF },
- +{"vssseg6e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E1024V, MASK_VSSSEG6E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E1024V, MASK_VLSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E1024V, MASK_VSSSEG7E1024V, match_opcode, INSN_DREF },
- +{"vssseg7e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E1024V, MASK_VSSSEG7E1024V, match_vd_neq_vm, INSN_DREF },
- {"vlsseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E1024V, MASK_VLSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
- -{"vssseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_opcode, INSN_DREF },
- +{"vssseg8e1024.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E1024V, MASK_VSSSEG8E1024V, match_vd_neq_vm, INSN_DREF },
-
- {"vlxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLXSEG2EI8V, MASK_VLXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- {"vsxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSXSEG2EI8V, MASK_VSXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
- @@ -1595,53 +1588,53 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_opcode, INSN_DREF },
- {"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_opcode, INSN_DREF },
-
- -{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_opcode, INSN_DREF},
- -{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_opcode, INSN_DREF},
- -{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_opcode, INSN_DREF},
- -{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_opcode, INSN_DREF},
- -{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_opcode, INSN_DREF},
- -{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_opcode, INSN_DREF},
- -{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_opcode, INSN_DREF},
- -{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_opcode, INSN_DREF},
- -{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_opcode, INSN_DREF},
- -
- -{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_opcode, INSN_DREF},
- -{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_opcode, INSN_DREF},
- -{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_opcode, INSN_DREF},
- -{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_opcode, INSN_DREF},
- -{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_opcode, INSN_DREF},
- -{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_opcode, INSN_DREF},
- -{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_opcode, INSN_DREF},
- -{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_opcode, INSN_DREF},
- -{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_opcode, INSN_DREF},
- -
- -{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_opcode, INSN_DREF},
- -{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_opcode, INSN_DREF},
- -{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_opcode, INSN_DREF},
- -{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_opcode, INSN_DREF},
- -{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_opcode, INSN_DREF},
- -{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_opcode, INSN_DREF},
- -{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_opcode, INSN_DREF},
- -{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_opcode, INSN_DREF},
- -{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_opcode, INSN_DREF},
- -
- -{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_opcode, INSN_DREF},
- -{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_opcode, INSN_DREF},
- -{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_opcode, INSN_DREF},
- -{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_opcode, INSN_DREF},
- -{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_opcode, INSN_DREF},
- -{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_opcode, INSN_DREF},
- -{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_opcode, INSN_DREF},
- -{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_opcode, INSN_DREF},
- -{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_opcode, INSN_DREF},
- -
- -{"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
- -{"vadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
- -{"vadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
- -{"vsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
- -{"vsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
- -{"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
- -{"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
- +{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
- +{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
- +{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
- +{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
- +{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
- +{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
- +{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
- +{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
- +{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
- +
- +{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
- +{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
- +{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
- +{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
- +{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
- +{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
- +{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
- +{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
- +{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
- +
- +{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
- +{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
- +{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
- +{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
- +{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
- +{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
- +{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
- +{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
- +{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
- +
- +{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
- +{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
- +{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
- +{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
- +{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
- +{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
- +{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
- +{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
- +{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
- +
- +{"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
- +{"vadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_vd_neq_vm, 0 },
- +{"vadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_vd_neq_vm, 0 },
- +{"vsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_vd_neq_vm, 0 },
- +{"vsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_vd_neq_vm, 0 },
- +{"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
- +{"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
-
- {"vwcvt.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
- {"vwcvtu.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
- @@ -1663,59 +1656,59 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vwsub.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
- {"vwsub.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
-
- -{"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_opcode, 0 },
- -{"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_opcode, 0 },
- -{"vzext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_opcode, 0 },
- -{"vsext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_opcode, 0 },
- -{"vzext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_opcode, 0 },
- -{"vsext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_opcode, 0 },
- +{"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
- +{"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
- +{"vzext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_vd_neq_vm, 0 },
- +{"vsext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_vd_neq_vm, 0 },
- +{"vzext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_vd_neq_vm, 0 },
- +{"vsext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_vd_neq_vm, 0 },
-
- -{"vadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_opcode, 0 },
- -{"vadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_opcode, 0 },
- -{"vadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_opcode, 0 },
- +{"vadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_vd_neq_vm, 0 },
- +{"vadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_vd_neq_vm, 0 },
- +{"vadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_vd_neq_vm, 0 },
- {"vmadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
- {"vmadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
- {"vmadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
- {"vmadc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
- {"vmadc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
- {"vmadc.vi", 0, INSN_CLASS_V, "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
- -{"vsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_opcode, 0 },
- -{"vsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_opcode, 0 },
- +{"vsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_vd_neq_vm, 0 },
- +{"vsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_vd_neq_vm, 0 },
- {"vmsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
- {"vmsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
- {"vmsbc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
- {"vmsbc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
-
- -{"vnot.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
- -
- -{"vand.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
- -{"vand.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
- -{"vand.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
- -{"vor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
- -{"vor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
- -{"vor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
- -{"vxor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
- -{"vxor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
- -{"vxor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
- -
- -{"vsll.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
- -{"vsll.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
- -{"vsll.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
- -{"vsrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
- -{"vsrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
- -{"vsrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
- -{"vsra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
- -{"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
- -{"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
- -
- -{"vncvt.x.x.v",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2, INSN_ALIAS },
- -
- -{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2, 0 },
- -{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2, 0 },
- -{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2, 0 },
- -{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2, 0 },
- -{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2, 0 },
- -{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2, 0 },
- +{"vnot.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_vd_neq_vm, INSN_ALIAS },
- +
- +{"vand.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_vd_neq_vm, 0 },
- +{"vand.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_vd_neq_vm, 0 },
- +{"vand.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_vd_neq_vm, 0 },
- +{"vor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_vd_neq_vm, 0 },
- +{"vor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_vd_neq_vm, 0 },
- +{"vor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_vd_neq_vm, 0 },
- +{"vxor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_vd_neq_vm, 0 },
- +{"vxor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_vd_neq_vm, 0 },
- +{"vxor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_vd_neq_vm, 0 },
- +
- +{"vsll.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_vd_neq_vm, 0 },
- +{"vsll.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_vd_neq_vm, 0 },
- +{"vsll.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_vd_neq_vm, 0 },
- +{"vsrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_vd_neq_vm, 0 },
- +{"vsrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_vd_neq_vm, 0 },
- +{"vsrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_vd_neq_vm, 0 },
- +{"vsra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_vd_neq_vm, 0 },
- +{"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
- +{"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
- +
- +{"vncvt.x.x.v",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXV, MASK_VNCVTXXV, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
- +
- +{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
-
- {"vmseq.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
- {"vmseq.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
- @@ -1755,23 +1748,23 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
- {"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
-
- -{"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
- -{"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
- -{"vmin.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
- -{"vmin.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
- -{"vmaxu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
- -{"vmaxu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
- -{"vmax.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
- -{"vmax.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
- -
- -{"vmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
- -{"vmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
- -{"vmulh.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
- -{"vmulh.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
- -{"vmulhu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
- -{"vmulhu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
- -{"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
- -{"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
- +{"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_vd_neq_vm, 0},
- +{"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_vd_neq_vm, 0},
- +{"vmin.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_vd_neq_vm, 0},
- +{"vmin.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_vd_neq_vm, 0},
- +{"vmaxu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_vd_neq_vm, 0},
- +{"vmaxu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_vd_neq_vm, 0},
- +{"vmax.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_vd_neq_vm, 0},
- +{"vmax.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_vd_neq_vm, 0},
- +
- +{"vmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_vd_neq_vm, 0 },
- +{"vmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_vd_neq_vm, 0 },
- +{"vmulh.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_vd_neq_vm, 0 },
- +{"vmulh.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_vd_neq_vm, 0 },
- +{"vmulhu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_vd_neq_vm, 0 },
- +{"vmulhu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_vd_neq_vm, 0 },
- +{"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
- +{"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
-
- {"vwmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
- {"vwmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
- @@ -1780,14 +1773,14 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vwmulsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
- {"vwmulsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
-
- -{"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
- -{"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
- -{"vnmsac.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
- -{"vnmsac.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
- -{"vmadd.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
- -{"vmadd.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
- -{"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
- -{"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
- +{"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
- +{"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
- +{"vnmsac.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_vd_neq_vm, 0},
- +{"vnmsac.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_vd_neq_vm, 0},
- +{"vmadd.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_vd_neq_vm, 0},
- +{"vmadd.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_vd_neq_vm, 0},
- +{"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
- +{"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
-
- {"vwmaccu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- {"vwmaccu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
- @@ -1805,14 +1798,14 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vqmaccsu.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_quad_vd_neq_vs2_neq_vm, 0},
- {"vqmaccus.vx", 0, INSN_CLASS_V_AND_ZVQMAC, "Vd,s,VtVm", MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_quad_vd_neq_vs2_neq_vm, 0},
-
- -{"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
- -{"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
- -{"vdiv.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
- -{"vdiv.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
- -{"vremu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
- -{"vremu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
- -{"vrem.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
- -{"vrem.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
- +{"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
- +{"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
- +{"vdiv.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_vd_neq_vm, 0 },
- +{"vdiv.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_vd_neq_vm, 0 },
- +{"vremu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_vd_neq_vm, 0 },
- +{"vremu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_vd_neq_vm, 0 },
- +{"vrem.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_vd_neq_vm, 0 },
- +{"vrem.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_vd_neq_vm, 0 },
-
- {"vmerge.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
- {"vmerge.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
- @@ -1822,48 +1815,48 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vmv.v.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
- {"vmv.v.i", 0, INSN_CLASS_V, "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
-
- -{"vsaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
- -{"vsaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
- -{"vsaddu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
- -{"vsadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
- -{"vsadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
- -{"vsadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
- -{"vssubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
- -{"vssubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
- -{"vssub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
- -{"vssub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
- -
- -{"vaaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_opcode, 0 },
- -{"vaaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_opcode, 0 },
- -{"vaadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_opcode, 0 },
- -{"vaadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_opcode, 0 },
- -{"vasubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_opcode, 0 },
- -{"vasubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_opcode, 0 },
- -{"vasub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_opcode, 0 },
- -{"vasub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_opcode, 0 },
- -
- -{"vsmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
- -{"vsmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
- -
- -{"vssrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
- -{"vssrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
- -{"vssrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
- -{"vssra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
- -{"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
- -{"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
- -
- -{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2, 0 },
- -{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2, 0 },
- -{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2, 0 },
- -{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2, 0 },
- -{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2, 0 },
- -{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2, 0 },
- -
- -{"vfadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
- -{"vfadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
- -{"vfsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
- -{"vfsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
- -{"vfrsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
- +{"vsaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_vd_neq_vm, 0 },
- +{"vsaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_vd_neq_vm, 0 },
- +{"vsaddu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_vd_neq_vm, 0 },
- +{"vsadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_vd_neq_vm, 0 },
- +{"vsadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_vd_neq_vm, 0 },
- +{"vsadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_vd_neq_vm, 0 },
- +{"vssubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_vd_neq_vm, 0 },
- +{"vssubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_vd_neq_vm, 0 },
- +{"vssub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_vd_neq_vm, 0 },
- +{"vssub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_vd_neq_vm, 0 },
- +
- +{"vaaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_vd_neq_vm, 0 },
- +{"vaaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_vd_neq_vm, 0 },
- +{"vaadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_vd_neq_vm, 0 },
- +{"vaadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_vd_neq_vm, 0 },
- +{"vasubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_vd_neq_vm, 0 },
- +{"vasubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_vd_neq_vm, 0 },
- +{"vasub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_vd_neq_vm, 0 },
- +{"vasub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_vd_neq_vm, 0 },
- +
- +{"vsmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_vd_neq_vm, 0 },
- +{"vsmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_vd_neq_vm, 0 },
- +
- +{"vssrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_vd_neq_vm, 0 },
- +{"vssrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_vd_neq_vm, 0 },
- +{"vssrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_vd_neq_vm, 0 },
- +{"vssra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_vd_neq_vm, 0 },
- +{"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
- +{"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
- +
- +{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
- +
- +{"vfadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
- +{"vfadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
- +{"vfsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_vd_neq_vm, 0},
- +{"vfsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
- +{"vfrsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
-
- {"vfwadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- {"vfwadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
- @@ -1874,31 +1867,31 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vfwsub.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
- {"vfwsub.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
-
- -{"vfmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
- -{"vfmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
- -{"vfdiv.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
- -{"vfdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
- -{"vfrdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
- +{"vfmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
- +{"vfmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
- +{"vfdiv.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_vd_neq_vm, 0},
- +{"vfdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
- +{"vfrdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
-
- {"vfwmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- {"vfwmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
-
- -{"vfmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
- -{"vfmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
- -{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
- -{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
- -{"vfmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
- -{"vfmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
- -{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
- -{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
- -{"vfmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
- -{"vfmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
- -{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
- -{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
- -{"vfmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
- -{"vfmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
- -{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
- -{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
- +{"vfmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
- +{"vfmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
- +{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_vd_neq_vm, 0},
- +{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_vd_neq_vm, 0},
- +{"vfmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_vd_neq_vm, 0},
- +{"vfmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_vd_neq_vm, 0},
- +{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_vd_neq_vm, 0},
- +{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_vd_neq_vm, 0},
- +{"vfmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_vd_neq_vm, 0},
- +{"vfmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_vd_neq_vm, 0},
- +{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_vd_neq_vm, 0},
- +{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_vd_neq_vm, 0},
- +{"vfmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_vd_neq_vm, 0},
- +{"vfmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_vd_neq_vm, 0},
- +{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
- +{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
-
- {"vfwmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- {"vfwmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
- @@ -1909,22 +1902,22 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
- {"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
-
- -{"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0},
- -{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRTE7V, MASK_VFRSQRTE7V, match_opcode, 0},
- -{"vfrece7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRECE7V, MASK_VFRECE7V, match_opcode, 0},
- -{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
- +{"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
- +{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRTE7V, MASK_VFRSQRTE7V, match_vd_neq_vm, 0},
- +{"vfrece7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRECE7V, MASK_VFRECE7V, match_vd_neq_vm, 0},
- +{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_vd_neq_vm, 0},
-
- -{"vfmin.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
- -{"vfmin.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
- -{"vfmax.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
- -{"vfmax.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
- +{"vfmin.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_vd_neq_vm, 0},
- +{"vfmin.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_vd_neq_vm, 0},
- +{"vfmax.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
- +{"vfmax.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0},
-
- -{"vfsgnj.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
- -{"vfsgnj.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
- -{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
- -{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
- -{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
- -{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
- +{"vfsgnj.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0},
- +{"vfsgnj.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0},
- +{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vd_neq_vm, 0},
- +{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_vd_neq_vm, 0},
- +{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vd_neq_vm, 0},
- +{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_vd_neq_vm, 0},
-
- {"vmfeq.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
- {"vmfeq.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
- @@ -1944,12 +1937,12 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
- {"vfmv.v.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
-
- -{"vfcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_opcode, 0},
- -{"vfcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_opcode, 0},
- -{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_opcode, 0},
- -{"vfcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_opcode, 0},
- -{"vfcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_opcode, 0},
- -{"vfcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_opcode, 0},
- +{"vfcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_vd_neq_vm, 0},
- +{"vfcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_vd_neq_vm, 0},
- +{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_vd_neq_vm, 0},
- +{"vfcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_vd_neq_vm, 0},
- +{"vfcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
- +{"vfcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
-
- {"vfwcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
- {"vfwcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
- @@ -1959,14 +1952,14 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vfwcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
- {"vfwcvt.f.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
-
- -{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2, 0},
- -{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2, 0},
- -{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2, 0},
- -{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2, 0},
- -{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2, 0},
- -{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2, 0},
- -{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2, 0},
- -{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2, 0},
- +{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
- +{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
- +{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
- +{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
- +{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
- +{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
- +{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
- +{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
-
- {"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
- {"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
- @@ -2005,11 +1998,11 @@ const struct riscv_opcode riscv_opcodes[] =
-
- {"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
- {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
- -{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_opcode, 0},
- -{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_opcode, 0},
- -{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_opcode, 0},
- +{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vm, 0},
- +{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vm, 0},
- +{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vm, 0},
- {"viota.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
- -{"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_opcode, 0},
- +{"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
-
- {"vmv.x.s", 0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
- {"vmv.s.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
- @@ -2017,15 +2010,15 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vfmv.f.s", 0, INSN_CLASS_V_AND_F, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
- {"vfmv.s.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
-
- -{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2, 0},
- -{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2, 0},
- -{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
- -{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
- +{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2_neq_vm, 0},
- +{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2_neq_vm, 0},
- +{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_vd_neq_vm, 0},
- +{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_vd_neq_vm, 0},
-
- -{"vslide1up.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2, 0},
- -{"vslide1down.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
- -{"vfslide1up.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2, 0},
- -{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_opcode, 0},
- +{"vslide1up.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2_neq_vm, 0},
- +{"vslide1down.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_vd_neq_vm, 0},
- +{"vfslide1up.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2_neq_vm, 0},
- +{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_vd_neq_vm, 0},
-
- {"vrgather.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
- {"vrgather.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
- --
- 2.33.0
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