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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
  ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
- Add GICv3 support for ls1028a, ls2088a, ls1088a.
- Add lpuart support on ls1028aqds.
- Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based
  platforms.
Tom Rini 4 лет назад
Родитель
Сommit
b9da77f195
100 измененных файлов с 2234 добавлено и 97 удалено
  1. 4 0
      arch/arm/cpu/armv8/fsl-layerscape/Kconfig
  2. 6 4
      arch/arm/cpu/armv8/fsl-layerscape/cpu.c
  3. 4 0
      arch/arm/cpu/armv8/fsl-layerscape/fdt.c
  4. 44 0
      arch/arm/cpu/armv8/fsl-layerscape/soc.c
  5. 2 1
      arch/arm/dts/Makefile
  6. 15 0
      arch/arm/dts/fsl-ls1028a-qds-duart.dts
  7. 15 0
      arch/arm/dts/fsl-ls1028a-qds-lpuart.dts
  8. 4 0
      arch/arm/dts/fsl-ls1028a-qds.dtsi
  9. 60 0
      arch/arm/dts/fsl-ls1028a.dtsi
  10. 48 0
      arch/arm/dts/fsl-ls1043-post.dtsi
  11. 81 0
      arch/arm/dts/fsl-ls1043a-rdb.dts
  12. 1 1
      arch/arm/dts/fsl-ls1043a.dtsi
  13. 49 0
      arch/arm/dts/fsl-ls1046-post.dtsi
  14. 67 0
      arch/arm/dts/fsl-ls1046a-rdb.dts
  15. 1 1
      arch/arm/dts/fsl-ls1046a.dtsi
  16. 102 0
      arch/arm/dts/fsl-ls1088a-rdb.dts
  17. 96 6
      arch/arm/dts/fsl-ls1088a.dtsi
  18. 84 6
      arch/arm/dts/fsl-ls2080a.dtsi
  19. 88 0
      arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
  20. 52 0
      arch/arm/dts/fsl-lx2160a-rdb.dts
  21. 65 0
      arch/arm/dts/fsl-lx2160a.dtsi
  22. 44 0
      arch/arm/dts/qoriq-fman3-0-10g-0.dtsi
  23. 44 0
      arch/arm/dts/qoriq-fman3-0-10g-1.dtsi
  24. 43 0
      arch/arm/dts/qoriq-fman3-0-1g-0.dtsi
  25. 43 0
      arch/arm/dts/qoriq-fman3-0-1g-1.dtsi
  26. 43 0
      arch/arm/dts/qoriq-fman3-0-1g-2.dtsi
  27. 43 0
      arch/arm/dts/qoriq-fman3-0-1g-3.dtsi
  28. 43 0
      arch/arm/dts/qoriq-fman3-0-1g-4.dtsi
  29. 43 0
      arch/arm/dts/qoriq-fman3-0-1g-5.dtsi
  30. 82 0
      arch/arm/dts/qoriq-fman3-0.dtsi
  31. 4 0
      arch/arm/include/asm/arch-fsl-layerscape/soc.h
  32. 1 0
      board/freescale/ls1028a/MAINTAINERS
  33. 32 0
      board/freescale/ls1028a/ls1028a.c
  34. 2 0
      board/freescale/ls1043ardb/ls1043ardb.c
  35. 2 0
      board/freescale/ls1046afrwy/ls1046afrwy.c
  36. 2 0
      board/freescale/ls1046aqds/ls1046aqds.c
  37. 1 1
      board/freescale/ls1046ardb/ddr.h
  38. 2 0
      board/freescale/ls1046ardb/ls1046ardb.c
  39. 2 0
      board/freescale/ls1088a/eth_ls1088ardb.c
  40. 5 0
      board/freescale/ls1088a/ls1088a.c
  41. 7 0
      board/freescale/ls2080ardb/eth_ls2080rdb.c
  42. 4 0
      board/freescale/ls2080ardb/ls2080ardb.c
  43. 0 25
      board/freescale/lx2160a/lx2160a.c
  44. 2 1
      configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
  45. 2 1
      configs/ls1028aqds_tfa_defconfig
  46. 88 0
      configs/ls1028aqds_tfa_lpuart_defconfig
  47. 1 0
      configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
  48. 1 0
      configs/ls1028ardb_tfa_defconfig
  49. 3 0
      configs/ls1043ardb_SECURE_BOOT_defconfig
  50. 3 0
      configs/ls1043ardb_defconfig
  51. 3 0
      configs/ls1043ardb_nand_SECURE_BOOT_defconfig
  52. 3 0
      configs/ls1043ardb_nand_defconfig
  53. 3 0
      configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
  54. 3 0
      configs/ls1043ardb_sdcard_defconfig
  55. 3 0
      configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
  56. 3 0
      configs/ls1043ardb_tfa_defconfig
  57. 3 0
      configs/ls1046ardb_emmc_defconfig
  58. 3 0
      configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
  59. 3 0
      configs/ls1046ardb_qspi_defconfig
  60. 3 0
      configs/ls1046ardb_qspi_spl_defconfig
  61. 3 0
      configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
  62. 3 0
      configs/ls1046ardb_sdcard_defconfig
  63. 3 0
      configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
  64. 3 0
      configs/ls1046ardb_tfa_defconfig
  65. 1 0
      configs/ls1088aqds_defconfig
  66. 1 0
      configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
  67. 1 0
      configs/ls1088aqds_qspi_defconfig
  68. 1 0
      configs/ls1088aqds_sdcard_ifc_defconfig
  69. 1 0
      configs/ls1088aqds_sdcard_qspi_defconfig
  70. 1 0
      configs/ls1088aqds_tfa_defconfig
  71. 5 0
      configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
  72. 5 0
      configs/ls1088ardb_qspi_defconfig
  73. 5 0
      configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
  74. 5 0
      configs/ls1088ardb_sdcard_qspi_defconfig
  75. 5 0
      configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
  76. 5 0
      configs/ls1088ardb_tfa_defconfig
  77. 1 0
      configs/ls2080aqds_SECURE_BOOT_defconfig
  78. 1 0
      configs/ls2080aqds_defconfig
  79. 1 0
      configs/ls2080aqds_nand_defconfig
  80. 1 0
      configs/ls2080aqds_qspi_defconfig
  81. 1 0
      configs/ls2080aqds_sdcard_defconfig
  82. 1 0
      configs/ls2080ardb_SECURE_BOOT_defconfig
  83. 1 0
      configs/ls2080ardb_defconfig
  84. 1 0
      configs/ls2080ardb_nand_defconfig
  85. 1 0
      configs/ls2081ardb_defconfig
  86. 1 0
      configs/ls2088aqds_tfa_defconfig
  87. 5 0
      configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
  88. 5 0
      configs/ls2088ardb_qspi_defconfig
  89. 6 1
      configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
  90. 5 0
      configs/ls2088ardb_tfa_defconfig
  91. 4 0
      configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
  92. 4 0
      configs/lx2160ardb_tfa_defconfig
  93. 7 0
      drivers/net/Kconfig
  94. 1 0
      drivers/net/Makefile
  95. 386 47
      drivers/net/fm/eth.c
  96. 80 0
      drivers/net/fm/fm.c
  97. 23 0
      drivers/net/fm/fm.h
  98. 2 0
      drivers/net/fm/init.c
  99. 1 0
      drivers/net/fm/memac.c
  100. 137 2
      drivers/net/fm/memac_phy.c

+ 4 - 0
arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -46,6 +46,7 @@ config ARCH_LS1028A
 	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 	select SYS_FSL_ERRATUM_A050382
+	select RESV_RAM if GIC_V3_ITS
 	imply PANIC_HANG
 
 config ARCH_LS1043A
@@ -152,6 +153,7 @@ config ARCH_LS1088A
 	select SYS_I2C_MXC_I2C2 if !TFABOOT
 	select SYS_I2C_MXC_I2C3 if !TFABOOT
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
+	select RESV_RAM if GIC_V3_ITS
 	imply SCSI
 	imply PANIC_HANG
 
@@ -202,6 +204,7 @@ config ARCH_LS2080A
 	select SYS_I2C_MXC_I2C2 if !TFABOOT
 	select SYS_I2C_MXC_I2C3 if !TFABOOT
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
+	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG
 
@@ -229,6 +232,7 @@ config ARCH_LX2160A
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
+	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG
 	imply SCSI

+ 6 - 4
arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -1156,8 +1156,10 @@ int arch_early_init_r(void)
 	fsl_rgmii_init();
 #endif
 #ifdef CONFIG_FMAN_ENET
+#ifndef CONFIG_DM_ETH
 	fman_enet_init();
 #endif
+#endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	setup_qbman_portals();
 #endif
@@ -1379,7 +1381,7 @@ static int tfa_dram_init_banksize(void)
 	if (i > 0)
 		ret = 0;
 
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 	if (gd->bd->bi_dram[2].size >=
@@ -1402,7 +1404,7 @@ static int tfa_dram_init_banksize(void)
 				board_reserve_ram_top(gd->bd->bi_dram[0].size);
 		}
 	}
-#endif	/* CONFIG_FSL_MC_ENET */
+#endif	/* CONFIG_RESV_RAM */
 
 	return ret;
 }
@@ -1465,7 +1467,7 @@ int dram_init_banksize(void)
 	}
 #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
 
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 	if (gd->bd->bi_dram[2].size >=
@@ -1488,7 +1490,7 @@ int dram_init_banksize(void)
 				board_reserve_ram_top(gd->bd->bi_dram[0].size);
 		}
 	}
-#endif	/* CONFIG_FSL_MC_ENET */
+#endif	/* CONFIG_RESV_RAM */
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE

+ 4 - 0
arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -471,6 +471,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
 			     CONFIG_SYS_CLK_FREQ, 1);
 
+#ifdef CONFIG_GIC_V3_ITS
+	ls_gic_rd_tables_init(blob);
+#endif
+
 #if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
 	ft_pci_setup(blob, bd);
 #endif

+ 44 - 0
arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -6,10 +6,12 @@
 
 #include <common.h>
 #include <clock_legacy.h>
+#include <cpu_func.h>
 #include <env.h>
 #include <fsl_immap.h>
 #include <fsl_ifc.h>
 #include <init.h>
+#include <linux/sizes.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <asm/io.h>
@@ -17,6 +19,7 @@
 #include <asm/arch-fsl-layerscape/config.h>
 #include <asm/arch-fsl-layerscape/ns_access.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/gic-v3.h>
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 #include <fsl_csu.h>
 #endif
@@ -30,9 +33,50 @@
 #include <fsl_immap.h>
 #ifdef CONFIG_TFABOOT
 #include <env_internal.h>
+#endif
+#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+#ifdef CONFIG_GIC_V3_ITS
+#define PENDTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
+#define PROPTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
+#define GIC_LPI_SIZE		ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
+				PROPTABLE_MAX_SZ, SZ_1M)
+static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
+{
+	u32 phandle;
+	int err;
+	struct fdt_memory gic_rd_tables;
+
+	gic_rd_tables.start = base;
+	gic_rd_tables.end = base + size - 1;
+	err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
+					 &phandle);
+	if (err < 0)
+		debug("%s: failed to add reserved memory: %d\n", __func__, err);
+
+	return err;
+}
+
+int ls_gic_rd_tables_init(void *blob)
+{
+	u64 gic_lpi_base;
+	int ret;
+
+	gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
+	ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
+	if (ret)
+		return ret;
+
+	ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+	if (ret)
+		debug("%s: failed to init gic-lpi-tables\n", __func__);
+
+	return ret;
+}
+#endif
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);

+ 2 - 1
arch/arm/dts/Makefile

@@ -377,7 +377,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls1088a-rdb.dtb \
 	fsl-ls1088a-qds.dtb \
 	fsl-ls1028a-rdb.dtb \
-	fsl-ls1028a-qds.dtb \
+	fsl-ls1028a-qds-duart.dtb \
+	fsl-ls1028a-qds-lpuart.dtb \
 	fsl-lx2160a-rdb.dtb \
 	fsl-lx2160a-qds.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \

+ 15 - 0
arch/arm/dts/fsl-ls1028a-qds-duart.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Freescale Layerscape-1028AQDS family SoC.
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-qds.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &serial0;
+	};
+};

+ 15 - 0
arch/arm/dts/fsl-ls1028a-qds-lpuart.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Freescale Layerscape-1028AQDS family SoC.
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-qds.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &lpuart0;
+	};
+};

+ 4 - 0
arch/arm/dts/fsl-ls1028a-qds.dts → arch/arm/dts/fsl-ls1028a-qds.dtsi

@@ -151,6 +151,10 @@
 	status = "okay";
 };
 
+&lpuart0 {
+	status = "okay";
+};
+
 &sata {
 	status = "okay";
 };

+ 60 - 0
arch/arm/dts/fsl-ls1028a.dtsi

@@ -240,6 +240,66 @@
 		status = "disabled";
 	};
 
+	lpuart0: serial@2260000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x2260000 0x0 0x1000>;
+		interrupts = <0 232 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart1: serial@2270000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x2270000 0x0 0x1000>;
+		interrupts = <0 233 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart2: serial@2280000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x2280000 0x0 0x1000>;
+		interrupts = <0 234 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart3: serial@2290000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x2290000 0x0 0x1000>;
+		interrupts = <0 235 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart4: serial@22a0000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x22a0000 0x0 0x1000>;
+		interrupts = <0 236 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
+	lpuart5: serial@22b0000 {
+		compatible = "fsl,ls1021a-lpuart";
+		reg = <0x0 0x22b0000 0x0 0x1000>;
+		interrupts = <0 237 0x4>;
+		clocks = <&sysclk>;
+		clock-names = "ipg";
+		little-endian;
+		status = "disabled";
+	};
+
 	usb1: usb3@3100000 {
 		compatible = "fsl,layerscape-dwc3";
 		reg = <0x0 0x3100000 0x0 0x10000>;

+ 48 - 0
arch/arm/dts/fsl-ls1043-post.dtsi

@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 device tree nodes for ls1043
+ *
+ * Copyright 2015-2016 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+&soc {
+
+/* include used FMan blocks */
+#include "qoriq-fman3-0.dtsi"
+#include "qoriq-fman3-0-1g-0.dtsi"
+#include "qoriq-fman3-0-1g-1.dtsi"
+#include "qoriq-fman3-0-1g-2.dtsi"
+#include "qoriq-fman3-0-1g-3.dtsi"
+#include "qoriq-fman3-0-1g-4.dtsi"
+#include "qoriq-fman3-0-1g-5.dtsi"
+#include "qoriq-fman3-0-10g-0.dtsi"
+
+};
+
+&fman0 {
+	fsl,erratum-a050385;
+
+	/* these aliases provide the FMan ports mapping */
+	enet0: ethernet@e0000 {
+	};
+
+	enet1: ethernet@e2000 {
+	};
+
+	enet2: ethernet@e4000 {
+	};
+
+	enet3: ethernet@e6000 {
+	};
+
+	enet4: ethernet@e8000 {
+	};
+
+	enet5: ethernet@ea000 {
+	};
+
+	enet6: ethernet@f0000 {
+	};
+};

+ 81 - 0
arch/arm/dts/fsl-ls1043a-rdb.dts

@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright (C) 2015, Freescale Semiconductor
+ * Copyright 2020 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
@@ -98,3 +99,83 @@
 &duart1 {
 	status = "okay";
 };
+
+#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+	ethernet@e0000 {
+		phy-handle = <&qsgmii_phy1>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@e2000 {
+		phy-handle = <&qsgmii_phy2>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@e4000 {
+		phy-handle = <&rgmii_phy1>;
+		phy-connection-type = "rgmii-txid";
+		status = "okay";
+	};
+
+	ethernet@e6000 {
+		phy-handle = <&rgmii_phy2>;
+		phy-connection-type = "rgmii-txid";
+		status = "okay";
+	};
+
+	ethernet@e8000 {
+		phy-handle = <&qsgmii_phy3>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@ea000 {
+		phy-handle = <&qsgmii_phy4>;
+		phy-connection-type = "qsgmii";
+		status = "okay";
+	};
+
+	ethernet@f0000 { /* 10GEC1 */
+		phy-handle = <&aqr105_phy>;
+		phy-connection-type = "xgmii";
+		status = "okay";
+	};
+
+	mdio@fc000 {
+		rgmii_phy1: ethernet-phy@1 {
+			reg = <0x1>;
+		};
+
+		rgmii_phy2: ethernet-phy@2 {
+			reg = <0x2>;
+		};
+
+		qsgmii_phy1: ethernet-phy@4 {
+			reg = <0x4>;
+		};
+
+		qsgmii_phy2: ethernet-phy@5 {
+			reg = <0x5>;
+		};
+
+		qsgmii_phy3: ethernet-phy@6 {
+			reg = <0x6>;
+		};
+
+		qsgmii_phy4: ethernet-phy@7 {
+			reg = <0x7>;
+		};
+	};
+
+	mdio@fd000 {
+		aqr105_phy: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			interrupts = <0 132 4>;
+			reg = <0x1>;
+		};
+	};
+};

+ 1 - 1
arch/arm/dts/fsl-ls1043a.dtsi

@@ -31,7 +31,7 @@
 		interrupts = <1 9 0xf08>;
 	};
 
-	soc {
+	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;

+ 49 - 0
arch/arm/dts/fsl-ls1046-post.dtsi

@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 device tree nodes for ls1046
+ *
+ * Copyright 2015-2016 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+&soc {
+
+/* include used FMan blocks */
+#include "qoriq-fman3-0.dtsi"
+#include "qoriq-fman3-0-1g-0.dtsi"
+#include "qoriq-fman3-0-1g-1.dtsi"
+#include "qoriq-fman3-0-1g-2.dtsi"
+#include "qoriq-fman3-0-1g-3.dtsi"
+#include "qoriq-fman3-0-1g-4.dtsi"
+#include "qoriq-fman3-0-1g-5.dtsi"
+#include "qoriq-fman3-0-10g-0.dtsi"
+#include "qoriq-fman3-0-10g-1.dtsi"
+};
+
+&fman0 {
+	/* these aliases provide the FMan ports mapping */
+	enet0: ethernet@e0000 {
+	};
+
+	enet1: ethernet@e2000 {
+	};
+
+	enet2: ethernet@e4000 {
+	};
+
+	enet3: ethernet@e6000 {
+	};
+
+	enet4: ethernet@e8000 {
+	};
+
+	enet5: ethernet@ea000 {
+	};
+
+	enet6: ethernet@f0000 {
+	};
+
+	enet7: ethernet@f2000 {
+	};
+};

+ 67 - 0
arch/arm/dts/fsl-ls1046a-rdb.dts

@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  *
  * Copyright 2016, Freescale Semiconductor
+ * Copyright 2020 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
@@ -51,3 +52,69 @@
 &i2c3 {
 	status = "okay";
 };
+
+#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+	ethernet@e4000 {
+		phy-handle = <&rgmii_phy1>;
+		phy-connection-type = "rgmii-id";
+		status = "okay";
+	};
+
+	ethernet@e6000 {
+		phy-handle = <&rgmii_phy2>;
+		phy-connection-type = "rgmii-id";
+		status = "okay";
+	};
+
+	ethernet@e8000 {
+		phy-handle = <&sgmii_phy1>;
+		phy-connection-type = "sgmii";
+		status = "okay";
+	};
+
+	ethernet@ea000 {
+		phy-handle = <&sgmii_phy2>;
+		phy-connection-type = "sgmii";
+		status = "okay";
+	};
+
+	ethernet@f0000 { /* 10GEC1 */
+		phy-handle = <&aqr106_phy>;
+		phy-connection-type = "xgmii";
+		status = "okay";
+	};
+
+	ethernet@f2000 { /* 10GEC2 */
+		fixed-link = <0 1 1000 0 0>;
+		phy-connection-type = "xgmii";
+		status = "okay";
+	};
+
+	mdio@fc000 {
+		rgmii_phy1: ethernet-phy@1 {
+			reg = <0x1>;
+		};
+
+		rgmii_phy2: ethernet-phy@2 {
+			reg = <0x2>;
+		};
+
+		sgmii_phy1: ethernet-phy@3 {
+			reg = <0x3>;
+		};
+
+		sgmii_phy2: ethernet-phy@4 {
+			reg = <0x4>;
+		};
+	};
+
+	mdio@fd000 {
+		aqr106_phy: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			interrupts = <0 131 4>;
+			reg = <0x0>;
+		};
+	};
+};

+ 1 - 1
arch/arm/dts/fsl-ls1046a.dtsi

@@ -31,7 +31,7 @@
 		interrupts = <1 9 0xf08>;
 	};
 
-	soc {
+	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;

+ 102 - 0
arch/arm/dts/fsl-ls1088a-rdb.dts

@@ -17,6 +17,108 @@
 	};
 };
 
+&dpmac1 {
+	status = "okay";
+	phy-connection-type = "xgmii";
+};
+
+&dpmac2 {
+	status = "okay";
+	phy-handle = <&mdio2_phy1>;
+	phy-connection-type = "xgmii";
+};
+
+&dpmac3 {
+	status = "okay";
+	phy-handle = <&mdio1_phy5>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac4 {
+	status = "okay";
+	phy-handle = <&mdio1_phy6>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac5 {
+	status = "okay";
+	phy-handle = <&mdio1_phy7>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac6 {
+	status = "okay";
+	phy-handle = <&mdio1_phy8>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac7 {
+	status = "okay";
+	phy-handle = <&mdio1_phy1>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac8 {
+	status = "okay";
+	phy-handle = <&mdio1_phy2>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac9 {
+	status = "okay";
+	phy-handle = <&mdio1_phy3>;
+	phy-connection-type = "qsgmii";
+};
+
+&dpmac10 {
+	status = "okay";
+	phy-handle = <&mdio1_phy4>;
+	phy-connection-type = "qsgmii";
+};
+
+&emdio1 {
+	status = "okay";
+
+	/* Freescale F104 PHY1 */
+	mdio1_phy1: emdio1_phy@1 {
+		reg = <0x1c>;
+		};
+	mdio1_phy2: emdio1_phy@2 {
+		reg = <0x1d>;
+		};
+	mdio1_phy3: emdio1_phy@3 {
+		reg = <0x1e>;
+		};
+	mdio1_phy4: emdio1_phy@4 {
+		reg = <0x1f>;
+	};
+
+	/* F104 PHY2 */
+	mdio1_phy5: emdio1_phy@5 {
+		reg = <0x0c>;
+	};
+	mdio1_phy6: emdio1_phy@6 {
+		reg = <0x0d>;
+	};
+	mdio1_phy7: emdio1_phy@7 {
+		reg = <0x0e>;
+	};
+	mdio1_phy8: emdio1_phy@8 {
+		reg = <0x0f>;
+	};
+};
+
+&emdio2 {
+	status = "okay";
+
+	/* Aquantia AQR105 10G PHY */
+	mdio2_phy1: emdio2_phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <0 2 0x4>;
+		reg = <0x0>;
+	};
+};
+
 &i2c0 {
 	status = "okay";
 	u-boot,dm-pre-reloc;

+ 96 - 6
arch/arm/dts/fsl-ls1088a.dtsi

@@ -82,12 +82,6 @@
 		interrupts = <0 32 0x1>; /* edge triggered */
 	};
 
-	fsl_mc: fsl-mc@80c000000 {
-		compatible = "fsl,qoriq-mc";
-		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
-		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
-	};
-
 	dspi: dspi@2100000 {
 		compatible = "fsl,vf610-dspi";
 		#address-cells = <1>;
@@ -197,4 +191,100 @@
 		method = "smc";
 	};
 
+	fsl_mc: fsl-mc@80c000000 {
+		compatible = "fsl,qoriq-mc", "simple-mfd";
+		reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
+		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+		#address-cells = <3>;
+		#size-cells = <1>;
+
+		/*
+		 * Region type 0x0 - MC portals
+		 * Region type 0x1 - QBMAN portals
+		 */
+		ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+			  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+		dpmacs {
+			compatible = "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dpmac1: dpmac@1 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x1>;
+				status = "disabled";
+			};
+
+			dpmac2: dpmac@2 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x2>;
+				status = "disabled";
+			};
+
+			dpmac3: dpmac@3 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x3>;
+				status = "disabled";
+			};
+
+			dpmac4: dpmac@4 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x4>;
+				status = "disabled";
+			};
+
+			dpmac5: dpmac@5 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x5>;
+				status = "disabled";
+			};
+
+			dpmac6: dpmac@6 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x6>;
+				status = "disabled";
+			};
+
+			dpmac7: dpmac@7 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x7>;
+				status = "disabled";
+			};
+
+			dpmac8: dpmac@8 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x8>;
+				status = "disabled";
+			};
+
+			dpmac9: dpmac@9 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x9>;
+				status = "disabled";
+			};
+
+			dpmac10: dpmac@a {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0xa>;
+				status = "disabled";
+			};
+		};
+	};
+
+	emdio1: mdio@8B96000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8B96000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	emdio2: mdio@8B97000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8B97000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };

+ 84 - 6
arch/arm/dts/fsl-ls2080a.dtsi

@@ -50,12 +50,6 @@
 		interrupts = <0 32 0x1>; /* edge triggered */
 	};
 
-	fsl_mc: fsl-mc@80c000000 {
-		compatible = "fsl,qoriq-mc";
-		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
-		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
-	};
-
 	i2c0: i2c@2000000 {
 		status = "disabled";
 		compatible = "fsl,vf610-i2c";
@@ -200,4 +194,88 @@
 			status = "disabled";
 	};
 
+	fsl_mc: fsl-mc@80c000000 {
+		compatible = "fsl,qoriq-mc", "simple-mfd";
+		reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
+		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+		#address-cells = <3>;
+		#size-cells = <1>;
+
+		/*
+		 * Region type 0x0 - MC portals
+		 * Region type 0x1 - QBMAN portals
+		 */
+		ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+			0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+		dpmacs {
+			compatible = "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dpmac1: dpmac@1 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x1>;
+				status = "disabled";
+			};
+
+			dpmac2: dpmac@2 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x2>;
+				status = "disabled";
+			};
+
+			dpmac3: dpmac@3 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x3>;
+				status = "disabled";
+			};
+
+			dpmac4: dpmac@4 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x4>;
+				status = "disabled";
+			};
+
+			dpmac5: dpmac@5 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x5>;
+				status = "disabled";
+			};
+
+			dpmac6: dpmac@6 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x6>;
+				status = "disabled";
+			};
+
+			dpmac7: dpmac@7 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x7>;
+				status = "disabled";
+			};
+
+			dpmac8: dpmac@8 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x8>;
+				status = "disabled";
+			};
+		};
+	};
+
+	emdio1: mdio@8B96000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8B96000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	emdio2: mdio@8B97000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8B97000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };

+ 88 - 0
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts

@@ -21,6 +21,94 @@
 	};
 };
 
+&dpmac1 {
+	status = "okay";
+	phy-handle = <&mdio1_phy1>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+	status = "okay";
+	phy-handle = <&mdio1_phy2>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac3 {
+	status = "okay";
+	phy-handle = <&mdio1_phy3>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac4 {
+	status = "okay";
+	phy-handle = <&mdio1_phy4>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac5 {
+	status = "okay";
+	phy-handle = <&mdio2_phy1>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac6 {
+	status = "okay";
+	phy-handle = <&mdio2_phy2>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac7 {
+	status = "okay";
+	phy-handle = <&mdio2_phy3>;
+	phy-connection-type = "xfi";
+};
+
+&dpmac8 {
+	status = "okay";
+	phy-handle = <&mdio2_phy4>;
+	phy-connection-type = "xfi";
+};
+
+&emdio1 {
+	status = "okay";
+
+	/* CS4340 PHYs */
+	mdio1_phy1: emdio1_phy@1 {
+		reg = <0x10>;
+	};
+	mdio1_phy2: emdio1_phy@2 {
+		reg = <0x11>;
+	};
+	mdio1_phy3: emdio1_phy@3 {
+		reg = <0x12>;
+	};
+	mdio1_phy4: emdio1_phy@4 {
+		reg = <0x13>;
+	};
+};
+
+&emdio2 {
+	status = "okay";
+
+	/* AQR405 PHYs */
+	mdio2_phy1: emdio2_phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x0>;
+	};
+	mdio2_phy2: emdio2_phy@2 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x1>;
+	};
+	mdio2_phy3: emdio2_phy@3 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x2>;
+	};
+	mdio2_phy4: emdio2_phy@4 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x3>;
+	};
+};
+
 &dspi {
 	bus-num = <0>;
 	status = "okay";

+ 52 - 0
arch/arm/dts/fsl-lx2160a-rdb.dts

@@ -21,6 +21,58 @@
 	};
 };
 
+&dpmac3 {
+	status = "okay";
+	phy-handle = <&aquantia_phy1>;
+	phy-connection-type = "usxgmii";
+};
+
+&dpmac4 {
+	status = "okay";
+	phy-handle = <&aquantia_phy2>;
+	phy-connection-type = "usxgmii";
+};
+
+&dpmac17 {
+	status = "okay";
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+};
+
+&dpmac18 {
+	status = "okay";
+	phy-handle = <&rgmii_phy2>;
+	phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+	status = "okay";
+	rgmii_phy1: ethernet-phy@1 {
+		/* AR8035 PHY - "compatible" property not strictly needed */
+		compatible = "ethernet-phy-id004d.d072";
+		reg = <0x1>;
+		/* Poll mode - no "interrupts" property defined */
+	};
+	rgmii_phy2: ethernet-phy@2 {
+		/* AR8035 PHY - "compatible" property not strictly needed */
+		compatible = "ethernet-phy-id004d.d072";
+		reg = <0x2>;
+		/* Poll mode - no "interrupts" property defined */
+	};
+	aquantia_phy1: ethernet-phy@4 {
+		/* AQR107 PHY - "compatible" property not strictly needed */
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x4>;
+	};
+	aquantia_phy2: ethernet-phy@5 {
+		/* AQR107 PHY - "compatible" property not strictly needed */
+		compatible = "ethernet-phy-ieee802.3-c45";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x5>;
+	};
+};
+
 &esdhc0 {
 	status = "okay";
 };

+ 65 - 0
arch/arm/dts/fsl-lx2160a.dtsi

@@ -363,4 +363,69 @@
 		bus-range = <0x0 0xff>;
 		ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
 	};
+
+	fsl_mc: fsl-mc@80c000000 {
+		compatible = "fsl,qoriq-mc", "simple-mfd";
+		reg = <0x00000008 0x0c000000 0 0x40>,
+		      <0x00000000 0x08340000 0 0x40000>;
+		#address-cells = <3>;
+		#size-cells = <1>;
+
+		/*
+		 * Region type 0x0 - MC portals
+		 * Region type 0x1 - QBMAN portals
+		 */
+		ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+			  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+		dpmacs {
+			compatible = "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dpmac3: dpmac@3 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x3>;
+				status = "disabled";
+			};
+
+			dpmac4: dpmac@4 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x4>;
+				status = "disabled";
+			};
+
+			dpmac17: dpmac@11 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x11>;
+				status = "disabled";
+			};
+
+			dpmac18: dpmac@12 {
+				compatible = "fsl,qoriq-mc-dpmac";
+				reg = <0x12>;
+				status = "disabled";
+			};
+		};
+	};
+
+	/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
+	emdio1: mdio@8b96000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8b96000 0x0 0x1000>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	/* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
+	emdio2: mdio@8b97000 {
+		compatible = "fsl,ls-mdio";
+		reg = <0x0 0x8b97000 0x0 0x1000>;
+		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };

+ 44 - 0
arch/arm/dts/qoriq-fman3-0-10g-0.dtsi

@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 10g port #0 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x10: port@90000 {
+		cell-index = <0x10>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x90000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	fman0_tx_0x30: port@b0000 {
+		cell-index = <0x30>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xb0000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	ethernet@f0000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-memac";
+		reg = <0xf0000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
+		pcsphy-handle = <&pcsphy6>;
+		status = "disabled";
+	};
+
+	mdio@f1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xf1000 0x1000>;
+
+		pcsphy6: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};

+ 44 - 0
arch/arm/dts/qoriq-fman3-0-10g-1.dtsi

@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 10g port #1 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x11: port@91000 {
+		cell-index = <0x11>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x91000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	fman0_tx_0x31: port@b1000 {
+		cell-index = <0x31>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xb1000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	ethernet@f2000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-memac";
+		reg = <0xf2000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
+		pcsphy-handle = <&pcsphy7>;
+		status = "disabled";
+	};
+
+	mdio@f3000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xf3000 0x1000>;
+
+		pcsphy7: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};

+ 43 - 0
arch/arm/dts/qoriq-fman3-0-1g-0.dtsi

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #0 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x08: port@88000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x88000 0x1000>;
+	};
+
+	fman0_tx_0x28: port@a8000 {
+		cell-index = <0x28>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa8000 0x1000>;
+	};
+
+	ethernet@e0000 {
+		cell-index = <0>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe0000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy0>;
+		status = "disabled";
+	};
+
+	mdio@e1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe1000 0x1000>;
+
+		pcsphy0: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};

+ 43 - 0
arch/arm/dts/qoriq-fman3-0-1g-1.dtsi

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #1 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x09: port@89000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x89000 0x1000>;
+	};
+
+	fman0_tx_0x29: port@a9000 {
+		cell-index = <0x29>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa9000 0x1000>;
+	};
+
+	ethernet@e2000 {
+		cell-index = <1>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe2000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy1>;
+		status = "disabled";
+	};
+
+	mdio@e3000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe3000 0x1000>;
+
+		pcsphy1: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};

+ 43 - 0
arch/arm/dts/qoriq-fman3-0-1g-2.dtsi

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #2 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x0a: port@8a000 {
+		cell-index = <0xa>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8a000 0x1000>;
+	};
+
+	fman0_tx_0x2a: port@aa000 {
+		cell-index = <0x2a>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xaa000 0x1000>;
+	};
+
+	ethernet@e4000 {
+		cell-index = <2>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe4000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy2>;
+		status = "disabled";
+	};
+
+	mdio@e5000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe5000 0x1000>;
+
+		pcsphy2: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};

+ 43 - 0
arch/arm/dts/qoriq-fman3-0-1g-3.dtsi

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #3 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x0b: port@8b000 {
+		cell-index = <0xb>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8b000 0x1000>;
+	};
+
+	fman0_tx_0x2b: port@ab000 {
+		cell-index = <0x2b>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xab000 0x1000>;
+	};
+
+	ethernet@e6000 {
+		cell-index = <3>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe6000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy3>;
+		status = "disabled";
+	};
+
+	mdio@e7000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe7000 0x1000>;
+
+		pcsphy3: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};

+ 43 - 0
arch/arm/dts/qoriq-fman3-0-1g-4.dtsi

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #4 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x0c: port@8c000 {
+		cell-index = <0xc>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8c000 0x1000>;
+	};
+
+	fman0_tx_0x2c: port@ac000 {
+		cell-index = <0x2c>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xac000 0x1000>;
+	};
+
+	ethernet@e8000 {
+		cell-index = <4>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe8000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy4>;
+		status = "disabled";
+	};
+
+	mdio@e9000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe9000 0x1000>;
+
+		pcsphy4: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};

+ 43 - 0
arch/arm/dts/qoriq-fman3-0-1g-5.dtsi

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #5 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@1a00000 {
+	fman0_rx_0x0d: port@8d000 {
+		cell-index = <0xd>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8d000 0x1000>;
+	};
+
+	fman0_tx_0x2d: port@ad000 {
+		cell-index = <0x2d>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xad000 0x1000>;
+	};
+
+	ethernet@ea000 {
+		cell-index = <5>;
+		compatible = "fsl,fman-memac";
+		reg = <0xea000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy5>;
+		status = "disabled";
+	};
+
+	mdio@eb000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xeb000 0x1000>;
+
+		pcsphy5: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};

+ 82 - 0
arch/arm/dts/qoriq-fman3-0.dtsi

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman0: fman@1a00000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <0>;
+	compatible = "fsl,fman";
+	ranges = <0x0 0x0 0x1a00000 0xfe000>;
+	reg = <0x0 0x1a00000 0x0 0xfe000>;
+	clocks = <&clockgen 3 0>;
+	clock-names = "fmanclk";
+	fsl,qman-channel-range = <0x800 0x10>;
+	ptimer-handle = <&ptp_timer0>;
+
+	muram@0 {
+		compatible = "fsl,fman-muram";
+		reg = <0x0 0x60000>;
+	};
+
+	fman0_oh_0x2: port@82000 {
+		cell-index = <0x2>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x82000 0x1000>;
+	};
+
+	fman0_oh_0x3: port@83000 {
+		cell-index = <0x3>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x83000 0x1000>;
+	};
+
+	fman0_oh_0x4: port@84000 {
+		cell-index = <0x4>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x84000 0x1000>;
+	};
+
+	fman0_oh_0x5: port@85000 {
+		cell-index = <0x5>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x85000 0x1000>;
+	};
+
+	fman0_oh_0x6: port@86000 {
+		cell-index = <0x6>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x86000 0x1000>;
+	};
+
+	fman0_oh_0x7: port@87000 {
+		cell-index = <0x7>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x87000 0x1000>;
+	};
+
+	mdio0: mdio@fc000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfc000 0x1000>;
+	};
+
+	xmdio0: mdio@fd000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfd000 0x1000>;
+	};
+};
+
+ptp_timer0: ptp-timer@1afe000 {
+	compatible = "fsl,fman-ptp-timer";
+	reg = <0x0 0x1afe000 0x0 0x1000>;
+	clocks = <&clockgen 3 0>;
+};

+ 4 - 0
arch/arm/include/asm/arch-fsl-layerscape/soc.h

@@ -158,6 +158,10 @@ void erratum_a010315(void);
 
 bool soc_has_dp_ddr(void);
 bool soc_has_aiop(void);
+
+#ifdef CONFIG_GIC_V3_ITS
+int ls_gic_rd_tables_init(void *blob);
+#endif
 #endif
 
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */

+ 1 - 0
board/freescale/ls1028a/MAINTAINERS

@@ -8,6 +8,7 @@ F:	board/freescale/ls1028a/
 F:	include/configs/ls1028a_common.h
 F:	include/configs/ls1028aqds.h
 F:	configs/ls1028aqds_tfa_defconfig
+F:	configs/ls1028aqds_tfa_lpuart_defconfig
 
 LS1028ARDB BOARD
 M:	Sudhanshu Gupta <sudhanshu.gupta@nxp.com>

+ 32 - 0
board/freescale/ls1028a/ls1028a.c

@@ -31,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int config_board_mux(void)
 {
+#ifndef CONFIG_LPUART
 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
 	u8 reg;
 
@@ -55,9 +56,18 @@ int config_board_mux(void)
 	reg &= ~(0xc0);
 	QIXIS_WRITE(brdcfg[15], reg);
 #endif
+#endif
+
 	return 0;
 }
 
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+	return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
+}
+#endif
+
 int board_init(void)
 {
 #ifdef CONFIG_ENV_IS_NOWHERE
@@ -120,11 +130,33 @@ int misc_init_r(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_LPUART
+	u8 uart;
+#endif
+
 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 	i2c_early_init_f();
 #endif
 
 	fsl_lsch3_early_init_f();
+
+#ifdef CONFIG_LPUART
+	/*
+	 * Field| Function
+	 * --------------------------------------------------------------
+	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
+	 * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
+	 * --------------------------------------------------------------
+	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
+	 * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
+	 */
+	/* use lpuart0 as system console */
+	uart = QIXIS_READ(brdcfg[13]);
+	uart &= ~CFG_LPUART_MUX_MASK;
+	uart |= CFG_LPUART_EN;
+	QIXIS_WRITE(brdcfg[13], uart);
+#endif
+
 	return 0;
 }
 

+ 2 - 0
board/freescale/ls1043ardb/ls1043ardb.c

@@ -285,7 +285,9 @@ int ft_board_setup(void *blob, bd_t *bd)
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
+#endif
 #endif
 
 	fdt_fixup_icid(blob);

+ 2 - 0
board/freescale/ls1046afrwy/ls1046afrwy.c

@@ -232,7 +232,9 @@ int ft_board_setup(void *blob, bd_t *bd)
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
+#endif
 #endif
 
 	fdt_fixup_icid(blob);

+ 2 - 0
board/freescale/ls1046aqds/ls1046aqds.c

@@ -462,7 +462,9 @@ int ft_board_setup(void *blob, bd_t *bd)
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
+#endif
 	fdt_fixup_board_enet(blob);
 #endif
 

+ 1 - 1
board/freescale/ls1046ardb/ddr.h

@@ -32,7 +32,7 @@ static const struct board_specific_parameters udimm0[] = {
 	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
 	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
 	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2300, 0, 8,     9, 0x0A0B0C10, 0x1213140E,},
+	{2,  2300, 0, 8,     7, 0x08090A0E, 0x1011120C,},
 	{}
 };
 

+ 2 - 0
board/freescale/ls1046ardb/ls1046ardb.c

@@ -172,7 +172,9 @@ int ft_board_setup(void *blob, bd_t *bd)
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
+#endif
 #endif
 
 	fdt_fixup_icid(blob);

+ 2 - 0
board/freescale/ls1088a/eth_ls1088ardb.c

@@ -18,6 +18,7 @@
 #include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FSL_MC_ENET)
@@ -95,6 +96,7 @@ int board_eth_init(bd_t *bis)
 
 	return pci_eth_init(bis);
 }
+#endif
 
 #if defined(CONFIG_RESET_PHY_R)
 void reset_phy(void)

+ 5 - 0
board/freescale/ls1088a/ls1088a.c

@@ -801,6 +801,11 @@ int board_init(void)
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
+
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+	pci_init();
+#endif
+
 	return 0;
 }
 

+ 7 - 0
board/freescale/ls2080ardb/eth_ls2080rdb.c

@@ -23,6 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_eth_init(bd_t *bis)
 {
+#ifndef CONFIG_DM_ETH
 #if defined(CONFIG_FSL_MC_ENET)
 	int i, interface;
 	struct memac_mdio_info mdio_info;
@@ -99,6 +100,7 @@ int board_eth_init(bd_t *bis)
 
 	cpu_eth_init(bis);
 #endif /* CONFIG_FSL_MC_ENET */
+#endif /* !CONFIG_DM_ETH */
 
 #ifdef CONFIG_PHY_AQUANTIA
 	/*
@@ -112,7 +114,12 @@ int board_eth_init(bd_t *bis)
 	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 #endif
+
+#ifdef CONFIG_DM_ETH
+	return 0;
+#else
 	return pci_eth_init(bis);
+#endif
 }
 
 #if defined(CONFIG_RESET_PHY_R)

+ 4 - 0
board/freescale/ls2080ardb/ls2080ardb.c

@@ -244,6 +244,10 @@ int board_init(void)
 	sec_init();
 #endif
 
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+	pci_init();
+#endif
+
 	return 0;
 }
 

+ 0 - 25
board/freescale/lx2160a/lx2160a.c

@@ -29,14 +29,11 @@
 #include "../common/vid.h"
 #include <fsl_immap.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
-#include <asm/gic-v3.h>
-#include <cpu_func.h>
 
 #ifdef CONFIG_EMC2305
 #include "../common/emc2305.h"
 #endif
 
-#define GIC_LPI_SIZE                             0x200000
 #ifdef CONFIG_TARGET_LX2160AQDS
 #define CFG_MUX_I2C_SDHC(reg, value)		((reg & 0x3f) | value)
 #define SET_CFG_MUX1_SDHC1_SDHC(reg)		(reg & 0x3f)
@@ -644,21 +641,6 @@ void board_quiesce_devices(void)
 }
 #endif
 
-#ifdef CONFIG_GIC_V3_ITS
-void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
-{
-	u32 phandle;
-	int err;
-	struct fdt_memory gic_lpi;
-
-	gic_lpi.start = gic_lpi_base;
-	gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
-	err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
-	if (err < 0)
-		debug("failed to add reserved memory: %d\n", err);
-}
-#endif
-
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
@@ -670,7 +652,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 	u64 mc_memory_base = 0;
 	u64 mc_memory_size = 0;
 	u16 total_memory_banks;
-	u64 __maybe_unused gic_lpi_base;
 
 	ft_cpu_setup(blob, bd);
 
@@ -690,12 +671,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 		size[i] = gd->bd->bi_dram[i].size;
 	}
 
-#ifdef CONFIG_GIC_V3_ITS
-	gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
-	gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
-	fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
-#endif
-
 #ifdef CONFIG_RESV_RAM
 	/* reduce size if reserved memory is within this bank */
 	if (gd->arch.resv_ram >= base[0] &&

+ 2 - 1
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig

@@ -28,7 +28,7 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
@@ -79,3 +79,4 @@ CONFIG_WDT_SP805=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 2 - 1
configs/ls1028aqds_tfa_defconfig

@@ -30,7 +30,7 @@ CONFIG_CMD_WDT=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0x20500000
@@ -84,3 +84,4 @@ CONFIG_WDT=y
 CONFIG_WDT_SP805=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 88 - 0
configs/ls1028aqds_tfa_lpuart_defconfig

@@ -0,0 +1,88 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028AQDS=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x500000
+CONFIG_DM_GPIO=y
+CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x20500000
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_E1000=y
+CONFIG_FSL_ENETC=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

+ 1 - 0
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig

@@ -76,3 +76,4 @@ CONFIG_WDT_SP805=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls1028ardb_tfa_defconfig

@@ -85,3 +85,4 @@ CONFIG_WDT=y
 CONFIG_WDT_SP805=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 3 - 0
configs/ls1043ardb_SECURE_BOOT_defconfig

@@ -14,6 +14,7 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -40,6 +41,8 @@ CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y

+ 3 - 0
configs/ls1043ardb_defconfig

@@ -14,6 +14,7 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -44,6 +45,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1043ardb_nand_SECURE_BOOT_defconfig

@@ -32,6 +32,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -61,6 +62,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1043ardb_nand_defconfig

@@ -32,6 +32,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -62,6 +63,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig

@@ -31,6 +31,7 @@ CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -59,6 +60,8 @@ CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y

+ 3 - 0
configs/ls1043ardb_sdcard_defconfig

@@ -30,6 +30,7 @@ CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -61,6 +62,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig

@@ -16,6 +16,7 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -42,6 +43,8 @@ CONFIG_SF_DEFAULT_BUS=1
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y

+ 3 - 0
configs/ls1043ardb_tfa_defconfig

@@ -17,6 +17,7 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -49,6 +50,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1046ardb_emmc_defconfig

@@ -32,6 +32,7 @@ CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -59,6 +60,8 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig

@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -40,6 +41,8 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1046ardb_qspi_defconfig

@@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -43,6 +44,8 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1046ardb_qspi_spl_defconfig

@@ -34,6 +34,7 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_OS_BASE=0x40980000
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_SPL=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -61,6 +62,8 @@ CONFIG_MTD_RAW_NAND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y

+ 3 - 0
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig

@@ -31,6 +31,7 @@ CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -55,6 +56,8 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1046ardb_sdcard_defconfig

@@ -31,6 +31,7 @@ CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -58,6 +59,8 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig

@@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -40,6 +41,8 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 3 - 0
configs/ls1046ardb_tfa_defconfig

@@ -18,6 +18,7 @@ CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_MISC_INIT_R=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -45,6 +46,8 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_PCI=y

+ 1 - 0
configs/ls1088aqds_defconfig

@@ -64,3 +64,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig

@@ -66,3 +66,4 @@ CONFIG_USB_GADGET=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls1088aqds_qspi_defconfig

@@ -67,3 +67,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls1088aqds_sdcard_ifc_defconfig

@@ -72,3 +72,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls1088aqds_sdcard_qspi_defconfig

@@ -76,3 +76,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls1088aqds_tfa_defconfig

@@ -84,3 +84,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 5 - 0
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_SYS_TEXT_BASE=0x20100000
 CONFIG_ENV_SIZE=0x2000
@@ -21,6 +22,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -43,8 +45,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

+ 5 - 0
configs/ls1088ardb_qspi_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_SYS_TEXT_BASE=0x20100000
 CONFIG_ENV_SIZE=0x2000
@@ -22,6 +23,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -46,8 +48,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

+ 5 - 0
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_SYS_TEXT_BASE=0x80400000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -33,6 +34,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -55,8 +57,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

+ 5 - 0
configs/ls1088ardb_sdcard_qspi_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_SYS_TEXT_BASE=0x80400000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -32,6 +33,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -56,8 +58,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

+ 5 - 0
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
@@ -24,6 +25,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -50,8 +52,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

+ 5 - 0
configs/ls1088ardb_tfa_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_GIC_V3_ITS=y
 CONFIG_TARGET_LS1088ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
@@ -25,6 +26,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -55,8 +57,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

+ 1 - 0
configs/ls2080aqds_SECURE_BOOT_defconfig

@@ -66,3 +66,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls2080aqds_defconfig

@@ -67,3 +67,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls2080aqds_nand_defconfig

@@ -74,3 +74,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls2080aqds_qspi_defconfig

@@ -66,3 +66,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls2080aqds_sdcard_defconfig

@@ -73,3 +73,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls2080ardb_SECURE_BOOT_defconfig

@@ -64,3 +64,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls2080ardb_defconfig

@@ -65,3 +65,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls2080ardb_nand_defconfig

@@ -70,3 +70,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls2081ardb_defconfig

@@ -62,3 +62,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 1 - 0
configs/ls2088aqds_tfa_defconfig

@@ -78,3 +78,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 5 - 0
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig

@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=10
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -39,8 +40,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -59,3 +63,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 5 - 0
configs/ls2088ardb_qspi_defconfig

@@ -19,6 +19,7 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -45,8 +46,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -63,3 +67,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 6 - 1
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig

@@ -22,6 +22,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -31,7 +32,7 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
@@ -54,8 +55,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -76,3 +80,4 @@ CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 5 - 0
configs/ls2088ardb_tfa_defconfig

@@ -23,6 +23,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -62,8 +63,11 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
@@ -81,3 +85,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y

+ 4 - 0
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig

@@ -22,6 +22,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -49,7 +50,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

+ 4 - 0
configs/lx2160ardb_tfa_defconfig

@@ -24,6 +24,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2
 CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -55,7 +56,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

+ 7 - 0
drivers/net/Kconfig

@@ -640,4 +640,11 @@ config MVMDIO
 
 	  This driver is used by the MVPP2 and MVNETA drivers.
 
+config FSL_LS_MDIO
+	bool "NXP Layerscape MDIO interface support"
+	depends on DM_MDIO
+	help
+	  This driver supports the MDIO bus found on the Fman 10G Ethernet MACs and
+	  on the mEMAC (which supports both Clauses 22 and 45).
+
 endif # NETDEVICES

+ 1 - 0
drivers/net/Makefile

@@ -83,3 +83,4 @@ obj-y += mscc_eswitch/
 obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
 obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
 obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
+obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o

+ 386 - 47
drivers/net/fm/eth.c

@@ -1,10 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  *	Dave Liu <daveliu@freescale.com>
  */
 #include <common.h>
 #include <asm/io.h>
+#ifdef CONFIG_DM_ETH
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <linux/compat.h>
+#include <phy_interface.h>
+#endif
 #include <malloc.h>
 #include <net.h>
 #include <hwconfig.h>
@@ -18,8 +25,10 @@
 
 #include "fm.h"
 
+#ifndef CONFIG_DM_ETH
 static struct eth_device *devlist[NUM_FM_PORTS];
 static int num_controllers;
+#endif
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
 
@@ -37,10 +46,18 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
 #ifdef CONFIG_SYS_FMAN_V3
 	u32 value;
 	struct mii_dev bus;
-	bus.priv = priv->mac->phyregs;
 	bool sgmii_2500 = (priv->enet_if ==
 			PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
-	int i = 0;
+	int i = 0, j;
+
+#ifndef CONFIG_DM_ETH
+	bus.priv = priv->mac->phyregs;
+#else
+	bus.priv = priv->pcs_mdio;
+#endif
+	bus.read = memac_mdio_read;
+	bus.write = memac_mdio_write;
+	bus.reset = memac_mdio_reset;
 
 qsgmii_loop:
 	/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
@@ -51,6 +68,10 @@ qsgmii_loop:
 	else
 		value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
 
+	for (j = 0; j <= 3; j++)
+		debug("dump PCS reg %#x: %#x\n", j,
+		      memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
+
 	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
 
 	/* Dev ability according to SGMII specification */
@@ -98,9 +119,8 @@ qsgmii_loop:
 #endif
 }
 
-static void dtsec_init_phy(struct eth_device *dev)
+static void dtsec_init_phy(struct fm_eth *fm_eth)
 {
-	struct fm_eth *fm_eth = dev->priv;
 #ifndef CONFIG_SYS_FMAN_V3
 	struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
 
@@ -114,10 +134,10 @@ static void dtsec_init_phy(struct eth_device *dev)
 		dtsec_configure_serdes(fm_eth);
 }
 
+#ifndef CONFIG_DM_ETH
 #ifdef CONFIG_PHYLIB
-static int tgec_is_fibre(struct eth_device *dev)
+static int tgec_is_fibre(struct fm_eth *fm)
 {
-	struct fm_eth *fm = dev->priv;
 	char phyopt[20];
 
 	sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
@@ -125,6 +145,7 @@ static int tgec_is_fibre(struct eth_device *dev)
 	return hwconfig_arg_cmp(phyopt, "xfi");
 }
 #endif
+#endif /* CONFIG_DM_ETH */
 #endif
 
 static u16 muram_readw(u16 *addr)
@@ -168,6 +189,8 @@ static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
 	/* wait until the rx port is not busy */
 	while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
 		;
+	if (!timeout)
+		printf("%s - timeout\n", __func__);
 }
 
 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
@@ -196,6 +219,8 @@ static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
 	/* wait until the tx port is not busy */
 	while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
 		;
+	if (!timeout)
+		printf("%s - timeout\n", __func__);
 }
 
 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
@@ -435,23 +460,39 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
 	sync();
 }
 
+#ifndef CONFIG_DM_ETH
 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
+#else
+static int fm_eth_open(struct udevice *dev)
+#endif
 {
-	struct fm_eth *fm_eth;
+#ifndef CONFIG_DM_ETH
+	struct fm_eth *fm_eth = dev->priv;
+#else
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct fm_eth *fm_eth = dev_get_priv(dev);
+#endif
+	unsigned char *enetaddr;
 	struct fsl_enet_mac *mac;
 #ifdef CONFIG_PHYLIB
 	int ret;
 #endif
 
-	fm_eth = (struct fm_eth *)dev->priv;
 	mac = fm_eth->mac;
 
+#ifndef CONFIG_DM_ETH
+	enetaddr = &dev->enetaddr[0];
+#else
+	enetaddr = pdata->enetaddr;
+#endif
+
 	/* setup the MAC address */
-	if (dev->enetaddr[0] & 0x01) {
-		printf("%s: MacAddress is multcast address\n",	__func__);
-		return 1;
+	if (enetaddr[0] & 0x01) {
+		printf("%s: MacAddress is multicast address\n",	__func__);
+		enetaddr[0] = 0;
+		enetaddr[5] = fm_eth->num;
 	}
-	mac->set_mac_addr(mac, dev->enetaddr);
+	mac->set_mac_addr(mac, enetaddr);
 
 	/* enable bmi Rx port */
 	setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
@@ -466,8 +507,12 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
 	if (fm_eth->phydev) {
 		ret = phy_startup(fm_eth->phydev);
 		if (ret) {
+#ifndef CONFIG_DM_ETH
 			printf("%s: Could not initialize\n",
 			       fm_eth->phydev->dev->name);
+#else
+			printf("%s: Could not initialize\n", dev->name);
+#endif
 			return ret;
 		}
 	} else {
@@ -481,6 +526,8 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
 
 	/* set the MAC-PHY mode */
 	mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
+	debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
+	      fm_eth->phydev->speed, fm_eth->phydev->link);
 
 	if (!fm_eth->phydev->link)
 		printf("%s: No link.\n", fm_eth->phydev->dev->name);
@@ -488,7 +535,11 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
 	return fm_eth->phydev->link ? 0 : -1;
 }
 
+#ifndef CONFIG_DM_ETH
 static void fm_eth_halt(struct eth_device *dev)
+#else
+static void fm_eth_halt(struct udevice *dev)
+#endif
 {
 	struct fm_eth *fm_eth;
 	struct fsl_enet_mac *mac;
@@ -511,7 +562,11 @@ static void fm_eth_halt(struct eth_device *dev)
 #endif
 }
 
+#ifndef CONFIG_DM_ETH
 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
+#else
+static int fm_eth_send(struct udevice *dev, void *buf, int len)
+#endif
 {
 	struct fm_eth *fm_eth;
 	struct fm_port_global_pram *pram;
@@ -569,20 +624,50 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
 	return 1;
 }
 
-static int fm_eth_recv(struct eth_device *dev)
+static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
+					  struct fm_port_bd *rxbd)
 {
-	struct fm_eth *fm_eth;
 	struct fm_port_global_pram *pram;
-	struct fm_port_bd *rxbd, *rxbd_base;
-	u16 status, len;
-	u32 buf_lo, buf_hi;
-	u8 *data;
+	struct fm_port_bd *rxbd_base;
 	u16 offset_out;
-	int ret = 1;
 
-	fm_eth = (struct fm_eth *)dev->priv;
 	pram = fm_eth->rx_pram;
-	rxbd = fm_eth->cur_rxbd;
+
+	/* clear the RxBDs */
+	muram_writew(&rxbd->status, RxBD_EMPTY);
+	muram_writew(&rxbd->len, 0);
+	sync();
+
+	/* advance RxBD */
+	rxbd++;
+	rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
+	if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
+		rxbd = rxbd_base;
+
+	/* update RxQD */
+	offset_out = muram_readw(&pram->rxqd.offset_out);
+	offset_out += sizeof(struct fm_port_bd);
+	if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
+		offset_out = 0;
+	muram_writew(&pram->rxqd.offset_out, offset_out);
+	sync();
+
+	return rxbd;
+}
+
+#ifndef CONFIG_DM_ETH
+static int fm_eth_recv(struct eth_device *dev)
+#else
+static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+#endif
+{
+	struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
+	struct fm_port_bd *rxbd = fm_eth->cur_rxbd;
+	u32 buf_lo, buf_hi;
+	u16 status, len;
+	int ret = -1;
+	u8 *data;
+
 	status = muram_readw(&rxbd->status);
 
 	while (!(status & RxBD_EMPTY)) {
@@ -591,38 +676,40 @@ static int fm_eth_recv(struct eth_device *dev)
 			buf_lo = in_be32(&rxbd->buf_ptr_lo);
 			data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
 			len = muram_readw(&rxbd->len);
+#ifndef CONFIG_DM_ETH
 			net_process_received_packet(data, len);
+#else
+			*packetp = data;
+			return len;
+#endif
 		} else {
 			printf("%s: Rx error\n", dev->name);
 			ret = 0;
 		}
 
-		/* clear the RxBDs */
-		muram_writew(&rxbd->status, RxBD_EMPTY);
-		muram_writew(&rxbd->len, 0);
-		sync();
+		/* free current bd, advance to next one */
+		rxbd = fm_eth_free_one(fm_eth, rxbd);
 
-		/* advance RxBD */
-		rxbd++;
-		rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
-		if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
-			rxbd = rxbd_base;
 		/* read next status */
 		status = muram_readw(&rxbd->status);
-
-		/* update RxQD */
-		offset_out = muram_readw(&pram->rxqd.offset_out);
-		offset_out += sizeof(struct fm_port_bd);
-		if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
-			offset_out = 0;
-		muram_writew(&pram->rxqd.offset_out, offset_out);
-		sync();
 	}
 	fm_eth->cur_rxbd = (void *)rxbd;
 
 	return ret;
 }
 
+#ifdef CONFIG_DM_ETH
+static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+	struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
+
+	fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
+
+	return 0;
+}
+#endif /* CONFIG_DM_ETH */
+
+#ifndef CONFIG_DM_ETH
 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
 {
 	struct fsl_enet_mac *mac;
@@ -678,22 +765,75 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
 
 	return 0;
 }
+#else /* CONFIG_DM_ETH */
+static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
+{
+#ifndef CONFIG_SYS_FMAN_V3
+	void *mdio;
+#endif
+
+	fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
+	if (!fm_eth->mac)
+		return -ENOMEM;
 
-static int init_phy(struct eth_device *dev)
+#ifndef CONFIG_SYS_FMAN_V3
+	mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
+	debug("MDIO %d @ %p\n", fm_eth->num, mdio);
+#endif
+
+	switch (fm_eth->mac_type) {
+#ifdef CONFIG_SYS_FMAN_V3
+	case FM_MEMAC:
+		init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
+		break;
+#else
+	case FM_DTSEC:
+		init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
+		break;
+	case FM_TGEC:
+		init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
+		break;
+#endif
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DM_ETH */
+
+static int init_phy(struct fm_eth *fm_eth)
 {
-	struct fm_eth *fm_eth = dev->priv;
 #ifdef CONFIG_PHYLIB
+	u32 supported = PHY_GBIT_FEATURES;
+#ifndef CONFIG_DM_ETH
 	struct phy_device *phydev = NULL;
-	u32 supported;
+#endif
+
+	if (fm_eth->type == FM_ETH_10G_E)
+		supported = PHY_10G_FEATURES;
+	if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
+		supported |= SUPPORTED_2500baseX_Full;
 #endif
 
 	if (fm_eth->type == FM_ETH_1G_E)
-		dtsec_init_phy(dev);
+		dtsec_init_phy(fm_eth);
 
+#ifdef CONFIG_DM_ETH
+#ifdef CONFIG_PHYLIB
+#ifdef CONFIG_DM_MDIO
+	fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
+	if (!fm_eth->phydev)
+		return -ENODEV;
+#endif
+	fm_eth->phydev->advertising &= supported;
+	fm_eth->phydev->supported &= supported;
+
+	phy_config(fm_eth->phydev);
+#endif
+#else /* CONFIG_DM_ETH */
 #ifdef CONFIG_PHYLIB
 	if (fm_eth->bus) {
-		phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
-					fm_eth->enet_if);
+		phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
+				     fm_eth->enet_if);
 		if (!phydev) {
 			printf("Failed to connect\n");
 			return -1;
@@ -711,7 +851,7 @@ static int init_phy(struct eth_device *dev)
 	} else {
 		supported = SUPPORTED_10000baseT_Full;
 
-		if (tgec_is_fibre(dev))
+		if (tgec_is_fibre(fm_eth))
 			phydev->port = PORT_FIBRE;
 	}
 
@@ -722,10 +862,11 @@ static int init_phy(struct eth_device *dev)
 
 	phy_config(phydev);
 #endif
-
+#endif /* CONFIG_DM_ETH */
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
 {
 	struct eth_device *dev;
@@ -784,7 +925,7 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
 	if (ret)
 		return ret;
 
-	init_phy(dev);
+	init_phy(fm_eth);
 
 	/* clear the ethernet address */
 	for (i = 0; i < 6; i++)
@@ -793,3 +934,201 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
 
 	return 0;
 }
+#else /* CONFIG_DM_ETH */
+#ifdef CONFIG_PHYLIB
+phy_interface_t fman_read_sys_if(struct udevice *dev)
+{
+	const char *if_str;
+
+	if_str = ofnode_read_string(dev->node, "phy-connection-type");
+	debug("MAC system interface mode %s\n", if_str);
+
+	return phy_get_interface_by_name(if_str);
+}
+#endif
+
+static int fm_eth_bind(struct udevice *dev)
+{
+	char mac_name[11];
+	u32 fm, num;
+
+	if (ofnode_read_u32(ofnode_get_parent(dev->node), "cell-index", &fm)) {
+		printf("FMan node property cell-index missing\n");
+		return -EINVAL;
+	}
+
+	if (dev && dev_read_u32(dev, "cell-index", &num)) {
+		printf("FMan MAC node property cell-index missing\n");
+		return -EINVAL;
+	}
+
+	sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
+	device_set_name(dev, mac_name);
+
+	debug("%s - binding %s\n", __func__, mac_name);
+
+	return 0;
+}
+
+static struct udevice *fm_get_internal_mdio(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle = {.node = ofnode_null()};
+	struct udevice *mdiodev;
+
+	if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
+				       0, 0, &phandle) ||
+	    !ofnode_valid(phandle.node)) {
+		if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
+					       0, 0, &phandle) ||
+		    !ofnode_valid(phandle.node)) {
+			printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
+			       dev->name);
+			return NULL;
+		}
+	}
+
+	if (uclass_get_device_by_ofnode(UCLASS_MDIO,
+					ofnode_get_parent(phandle.node),
+					&mdiodev)) {
+		printf("can't find MDIO bus for node %s\n",
+		       ofnode_get_name(ofnode_get_parent(phandle.node)));
+		return NULL;
+	}
+	debug("Found internal MDIO bus %p\n", mdiodev);
+
+	return mdiodev;
+}
+
+static int fm_eth_probe(struct udevice *dev)
+{
+	struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
+	struct ofnode_phandle_args args;
+	void *reg;
+	int ret, index;
+
+	debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
+	      (dev) ? dev->name : "-");
+
+	if (fm_eth->dev) {
+		printf("%s already probed, exit\n", (dev) ? dev->name : "-");
+		return 0;
+	}
+
+	fm_eth->dev = dev;
+	fm_eth->fm_index = fman_id(dev->parent);
+	reg = (void *)(uintptr_t)dev_read_addr(dev);
+	fm_eth->mac_type = dev_get_driver_data(dev);
+#ifdef CONFIG_PHYLIB
+	fm_eth->enet_if = fman_read_sys_if(dev);
+#else
+	fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
+	printf("%s: warning - unable to determine interface type\n", __func__);
+#endif
+	switch (fm_eth->mac_type) {
+#ifndef CONFIG_SYS_FMAN_V3
+	case FM_TGEC:
+		fm_eth->type = FM_ETH_10G_E;
+		break;
+	case FM_DTSEC:
+#else
+	case FM_MEMAC:
+		/* default to 1G, 10G is indicated by port property in dts */
+#endif
+		fm_eth->type = FM_ETH_1G_E;
+		break;
+	}
+
+	if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
+		printf("FMan MAC node property cell-index missing\n");
+		return -EINVAL;
+	}
+
+	if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
+				       0, 0, &args))
+		goto ports_ref_failure;
+	index = ofnode_read_u32_default(args.node, "cell-index", 0);
+	if (index <= 0)
+		goto ports_ref_failure;
+	fm_eth->rx_port = fman_port(dev->parent, index);
+
+	if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
+		fm_eth->type = FM_ETH_10G_E;
+
+	if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
+				       0, 1, &args))
+		goto ports_ref_failure;
+	index = ofnode_read_u32_default(args.node, "cell-index", 0);
+	if (index <= 0)
+		goto ports_ref_failure;
+	fm_eth->tx_port = fman_port(dev->parent, index);
+
+	/* set the ethernet max receive length */
+	fm_eth->max_rx_len = MAX_RXBUF_LEN;
+
+	switch (fm_eth->enet_if) {
+	case PHY_INTERFACE_MODE_QSGMII:
+		/* all PCS blocks are accessed on one controller */
+		if (fm_eth->num != 0)
+			break;
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_SGMII_2500:
+		fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
+		break;
+	default:
+		break;
+	}
+
+	/* init global mac structure */
+	ret = fm_eth_init_mac(fm_eth, reg);
+	if (ret)
+		return ret;
+
+	/* startup the FM im */
+	ret = fm_eth_startup(fm_eth);
+
+	if (!ret)
+		ret = init_phy(fm_eth);
+
+	return ret;
+
+ports_ref_failure:
+	printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
+	return -ENOENT;
+}
+
+static int fm_eth_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct eth_ops fm_eth_ops = {
+	.start = fm_eth_open,
+	.send = fm_eth_send,
+	.recv = fm_eth_recv,
+	.free_pkt = fm_eth_free_pkt,
+	.stop = fm_eth_halt,
+};
+
+static const struct udevice_id fm_eth_ids[] = {
+#ifdef CONFIG_SYS_FMAN_V3
+	{ .compatible = "fsl,fman-memac", .data = FM_MEMAC },
+#else
+	{ .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
+	{ .compatible = "fsl,fman-xgec", .data = FM_TGEC },
+#endif
+	{}
+};
+
+U_BOOT_DRIVER(eth_fman) = {
+	.name = "eth_fman",
+	.id = UCLASS_ETH,
+	.of_match = fm_eth_ids,
+	.bind = fm_eth_bind,
+	.probe = fm_eth_probe,
+	.remove = fm_eth_remove,
+	.ops = &fm_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct fm_eth),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif /* CONFIG_DM_ETH */

+ 80 - 0
drivers/net/fm/fm.c

@@ -9,6 +9,9 @@
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <u-boot/crc.h>
+#ifdef CONFIG_DM_ETH
+#include <dm.h>
+#endif
 
 #include "fm.h"
 #include <fsl_qe.h>		/* For struct qe_firmware */
@@ -529,3 +532,80 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 	return fm_init_bmi(index, &reg->fm_bmi_common);
 }
 #endif
+
+#ifdef CONFIG_DM_ETH
+struct fman_priv {
+	struct ccsr_fman *reg;
+	unsigned int fman_id;
+};
+
+static const struct udevice_id fman_ids[] = {
+	{ .compatible = "fsl,fman" },
+	{}
+};
+
+static int fman_probe(struct udevice *dev)
+{
+	struct fman_priv *priv = dev_get_priv(dev);
+
+	priv->reg = (struct ccsr_fman *)(uintptr_t)dev_read_addr(dev);
+
+	if (dev_read_u32(dev, "cell-index", &priv->fman_id)) {
+		printf("FMan node property cell-index missing\n");
+		return -EINVAL;
+	}
+
+	return fm_init_common(priv->fman_id, priv->reg);
+}
+
+static int fman_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+int fman_id(struct udevice *dev)
+{
+	struct fman_priv *priv = dev_get_priv(dev);
+
+	return priv->fman_id;
+}
+
+void *fman_port(struct udevice *dev, int num)
+{
+	struct fman_priv *priv = dev_get_priv(dev);
+
+	return &priv->reg->port[num - 1].fm_bmi;
+}
+
+void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num)
+{
+	struct fman_priv *priv = dev_get_priv(dev);
+	void *res = NULL;
+
+	switch (type) {
+#ifdef CONFIG_SYS_FMAN_V3
+	case FM_MEMAC:
+		res = &priv->reg->memac[num].fm_memac_mdio;
+		break;
+#else
+	case FM_DTSEC:
+		res = &priv->reg->mac_1g[num].fm_mdio.miimcfg;
+		break;
+	case FM_TGEC:
+		res = &priv->reg->mac_10g[num].fm_10gec_mdio;
+		break;
+#endif
+	}
+	return res;
+}
+
+U_BOOT_DRIVER(fman) = {
+	.name = "fman",
+	.id = UCLASS_SIMPLE_BUS,
+	.of_match = fman_ids,
+	.probe = fman_probe,
+	.remove = fman_remove,
+	.priv_auto_alloc_size = sizeof(struct fman_priv),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif /* CONFIG_DM_ETH */

+ 23 - 0
drivers/net/fm/fm.h

@@ -57,6 +57,18 @@ struct fm_port_bd {
 #define TxBD_READY		0x8000
 #define TxBD_LAST		BD_LAST
 
+#ifdef CONFIG_DM_ETH
+enum fm_mac_type {
+#ifdef CONFIG_SYS_FMAN_V3
+	FM_MEMAC,
+#else
+	FM_DTSEC,
+	FM_TGEC,
+#endif
+};
+#endif
+
+/* Fman ethernet private struct */
 /* Rx/Tx queue descriptor */
 struct fm_port_qd {
 	u16 gen;
@@ -101,6 +113,11 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
 phy_interface_t fman_port_enet_if(enum fm_port port);
 void fman_disable_port(enum fm_port port);
 void fman_enable_port(enum fm_port port);
+int fman_id(struct udevice *dev);
+void *fman_port(struct udevice *dev, int num);
+#ifdef CONFIG_DM_ETH
+void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num);
+#endif
 
 struct fsl_enet_mac {
 	void *base; /* MAC controller registers base address */
@@ -126,7 +143,13 @@ struct fm_eth {
 	struct mii_dev *bus;
 	struct phy_device *phydev;
 	int phyaddr;
+#ifndef CONFIG_DM_ETH
 	struct eth_device *dev;
+#else
+	enum fm_mac_type mac_type;
+	struct udevice *dev;
+	struct udevice *pcs_mdio;
+#endif
 	int max_rx_len;
 	struct fm_port_global_pram *rx_pram; /* Rx parameter table */
 	struct fm_port_global_pram *tx_pram; /* Tx parameter table */

+ 2 - 0
drivers/net/fm/init.c

@@ -15,6 +15,7 @@
 
 #include "fm.h"
 
+#ifndef CONFIG_DM_ETH
 struct fm_eth_info fm_info[] = {
 #if (CONFIG_SYS_NUM_FM1_DTSEC >= 1)
 	FM_DTSEC_INFO_INITIALIZER(1, 1),
@@ -380,3 +381,4 @@ int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
 
 	return 0;
 }
+#endif /* CONFIG_DM_ETH */

+ 1 - 0
drivers/net/fm/memac.c

@@ -137,6 +137,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
 void init_memac(struct fsl_enet_mac *mac, void *base,
 		void *phyregs, int max_rx_len)
 {
+	debug("%s: @ %p, mdio @ %p\n", __func__, base, phyregs);
 	mac->base = base;
 	mac->phyregs = phyregs;
 	mac->max_rx_len = max_rx_len;

+ 137 - 2
drivers/net/fm/memac_phy.c

@@ -22,6 +22,12 @@
 #define memac_setbits_32(a, v)	setbits_be32(a, v)
 #endif
 
+#ifdef CONFIG_DM_ETH
+struct fm_mdio_priv {
+	struct memac_mdio_controller *regs;
+};
+#endif
+
 static u32 memac_in_32(u32 *reg)
 {
 #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
@@ -39,10 +45,23 @@ static u32 memac_in_32(u32 *reg)
 int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
 			int regnum, u16 value)
 {
+	struct memac_mdio_controller *regs;
 	u32 mdio_ctl;
-	struct memac_mdio_controller *regs = bus->priv;
 	u32 c45 = 1; /* Default to 10G interface */
 
+#ifndef CONFIG_DM_ETH
+	regs = bus->priv;
+#else
+	struct fm_mdio_priv *priv;
+
+	if (!bus->priv)
+		return -EINVAL;
+	priv = dev_get_priv(bus->priv);
+	regs = priv->regs;
+	debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n",
+	      regs, port_addr, dev_addr, regnum, value);
+#endif
+
 	if (dev_addr == MDIO_DEVAD_NONE) {
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
@@ -84,13 +103,26 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 			int regnum)
 {
+	struct memac_mdio_controller *regs;
 	u32 mdio_ctl;
-	struct memac_mdio_controller *regs = bus->priv;
 	u32 c45 = 1;
 
+#ifndef CONFIG_DM_ETH
+	regs = bus->priv;
+#else
+	struct fm_mdio_priv *priv;
+
+	if (!bus->priv)
+		return -EINVAL;
+	priv = dev_get_priv(bus->priv);
+	regs = priv->regs;
+#endif
+
 	if (dev_addr == MDIO_DEVAD_NONE) {
+#ifndef CONFIG_DM_ETH
 		if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
 			return 0xffff;
+#endif
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
 		memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
@@ -133,6 +165,7 @@ int memac_mdio_reset(struct mii_dev *bus)
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
 {
 	struct mii_dev *bus = mdio_alloc();
@@ -167,3 +200,105 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
 
 	return mdio_register(bus);
 }
+
+#else /* CONFIG_DM_ETH */
+#if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO)
+static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+	struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
+						 NULL;
+
+	if (pdata && pdata->mii_bus)
+		return memac_mdio_read(pdata->mii_bus, addr, devad, reg);
+
+	return -1;
+}
+
+static int fm_mdio_write(struct udevice *dev, int addr, int devad, int reg,
+			 u16 val)
+{
+	struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
+						 NULL;
+
+	if (pdata && pdata->mii_bus)
+		return memac_mdio_write(pdata->mii_bus, addr, devad, reg, val);
+
+	return -1;
+}
+
+static int fm_mdio_reset(struct udevice *dev)
+{
+	struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
+						 NULL;
+
+	if (pdata && pdata->mii_bus)
+		return memac_mdio_reset(pdata->mii_bus);
+
+	return -1;
+}
+
+static const struct mdio_ops fm_mdio_ops = {
+	.read = fm_mdio_read,
+	.write = fm_mdio_write,
+	.reset = fm_mdio_reset,
+};
+
+static const struct udevice_id fm_mdio_ids[] = {
+	{ .compatible = "fsl,fman-memac-mdio" },
+	{}
+};
+
+static int fm_mdio_probe(struct udevice *dev)
+{
+	struct fm_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
+	struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
+						 NULL;
+
+	if (!dev) {
+		printf("%s dev = NULL\n", __func__);
+		return -1;
+	}
+	if (!priv) {
+		printf("dev_get_priv(dev %p) = NULL\n", dev);
+		return -1;
+	}
+	priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
+	debug("%s priv %p @ regs %p, pdata %p\n", __func__,
+	      priv, priv->regs, pdata);
+
+	/*
+	 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
+	 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
+	 * (much higher than 2.5MHz), violating the IEEE specs.
+	 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
+	 * is zero, so MDIO clock is disabled.
+	 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
+	 * be properly initialized.
+	 * The default NEG bit should be '1' as per FMANv3 RM, but on platforms
+	 * like T2080QDS, this bit default is '0', which leads to MDIO failure
+	 * on XAUI PHY, so set this bit definitely.
+	 */
+	if (priv && priv->regs && priv->regs->mdio_stat)
+		memac_setbits_32(&priv->regs->mdio_stat,
+				 MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
+
+	return 0;
+}
+
+static int fm_mdio_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+U_BOOT_DRIVER(fman_mdio) = {
+	.name = "fman_mdio",
+	.id = UCLASS_MDIO,
+	.of_match = fm_mdio_ids,
+	.probe = fm_mdio_probe,
+	.remove = fm_mdio_remove,
+	.ops = &fm_mdio_ops,
+	.priv_auto_alloc_size = sizeof(struct fm_mdio_priv),
+	.platdata_auto_alloc_size = sizeof(struct mdio_perdev_priv),
+};
+#endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */
+#endif /* CONFIG_DM_ETH */

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