fsl-lx2160a.dtsi 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP lx2160a SOC common device tree source
  4. *
  5. * Copyright 2018 NXP
  6. *
  7. */
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. / {
  10. compatible = "fsl,lx2160a";
  11. interrupt-parent = <&gic>;
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. memory@80000000 {
  15. device_type = "memory";
  16. reg = <0x00000000 0x80000000 0 0x80000000>;
  17. /* DRAM space - 1, size : 2 GB DRAM */
  18. };
  19. sysclk: sysclk {
  20. compatible = "fixed-clock";
  21. #clock-cells = <0>;
  22. clock-frequency = <100000000>;
  23. clock-output-names = "sysclk";
  24. };
  25. clockgen: clocking@1300000 {
  26. compatible = "fsl,ls2080a-clockgen";
  27. reg = <0 0x1300000 0 0xa0000>;
  28. #clock-cells = <2>;
  29. clocks = <&sysclk>;
  30. };
  31. gic: interrupt-controller@6000000 {
  32. compatible = "arm,gic-v3";
  33. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  34. <0x0 0x06200000 0 0x100000>; /* GICR */
  35. #interrupt-cells = <3>;
  36. interrupt-controller;
  37. interrupts = <1 9 0x4>;
  38. };
  39. timer {
  40. compatible = "arm,armv8-timer";
  41. interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  42. <1 14 0x8>, /* Physical NS PPI, active-low */
  43. <1 11 0x8>, /* Virtual PPI, active-low */
  44. <1 10 0x8>; /* Hypervisor PPI, active-low */
  45. };
  46. fspi: flexspi@20c0000 {
  47. compatible = "nxp,lx2160a-fspi";
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. reg = <0x0 0x20c0000 0x0 0x10000>,
  51. <0x0 0x20000000 0x0 0x10000000>;
  52. reg-names = "fspi_base", "fspi_mmap";
  53. clocks = <&clockgen 4 3>, <&clockgen 4 3>;
  54. clock-names = "fspi_en", "fspi";
  55. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  56. status = "disabled";
  57. };
  58. i2c0: i2c@2000000 {
  59. compatible = "fsl,vf610-i2c";
  60. #address-cells = <1>;
  61. #size-cells = <0>;
  62. reg = <0x0 0x2000000 0x0 0x10000>;
  63. interrupts = <0 34 4>;
  64. scl-gpio = <&gpio2 15 0>;
  65. status = "disabled";
  66. };
  67. i2c1: i2c@2010000 {
  68. compatible = "fsl,vf610-i2c";
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. reg = <0x0 0x2010000 0x0 0x10000>;
  72. interrupts = <0 34 4>;
  73. status = "disabled";
  74. };
  75. i2c2: i2c@2020000 {
  76. compatible = "fsl,vf610-i2c";
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. reg = <0x0 0x2020000 0x0 0x10000>;
  80. interrupts = <0 35 4>;
  81. status = "disabled";
  82. };
  83. i2c3: i2c@2030000 {
  84. compatible = "fsl,vf610-i2c";
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. reg = <0x0 0x2030000 0x0 0x10000>;
  88. interrupts = <0 35 4>;
  89. status = "disabled";
  90. };
  91. i2c4: i2c@2040000 {
  92. compatible = "fsl,vf610-i2c";
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. reg = <0x0 0x2040000 0x0 0x10000>;
  96. interrupts = <0 74 4>;
  97. scl-gpio = <&gpio2 16 0>;
  98. status = "disabled";
  99. };
  100. i2c5: i2c@2050000 {
  101. compatible = "fsl,vf610-i2c";
  102. #address-cells = <1>;
  103. #size-cells = <0>;
  104. reg = <0x0 0x2050000 0x0 0x10000>;
  105. interrupts = <0 74 4>;
  106. status = "disabled";
  107. };
  108. i2c6: i2c@2060000 {
  109. compatible = "fsl,vf610-i2c";
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. reg = <0x0 0x2060000 0x0 0x10000>;
  113. interrupts = <0 75 4>;
  114. status = "disabled";
  115. };
  116. i2c7: i2c@2070000 {
  117. compatible = "fsl,vf610-i2c";
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. reg = <0x0 0x2070000 0x0 0x10000>;
  121. interrupts = <0 75 4>;
  122. status = "disabled";
  123. };
  124. uart0: serial@21c0000 {
  125. compatible = "arm,pl011";
  126. reg = <0x0 0x21c0000 0x0 0x1000>;
  127. clocks = <&clockgen 4 0>;
  128. status = "disabled";
  129. };
  130. uart1: serial@21d0000 {
  131. compatible = "arm,pl011";
  132. reg = <0x0 0x21d0000 0x0 0x1000>;
  133. clocks = <&clockgen 4 0>;
  134. status = "disabled";
  135. };
  136. uart2: serial@21e0000 {
  137. compatible = "arm,pl011";
  138. reg = <0x0 0x21e0000 0x0 0x1000>;
  139. clocks = <&clockgen 4 0>;
  140. status = "disabled";
  141. };
  142. uart3: serial@21f0000 {
  143. compatible = "arm,pl011";
  144. reg = <0x0 0x21f0000 0x0 0x1000>;
  145. clocks = <&clockgen 4 0>;
  146. status = "disabled";
  147. };
  148. dspi0: dspi@2100000 {
  149. compatible = "fsl,vf610-dspi";
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. reg = <0x0 0x2100000 0x0 0x10000>;
  153. interrupts = <0 26 0x4>; /* Level high type */
  154. num-cs = <6>;
  155. };
  156. dspi1: dspi@2110000 {
  157. compatible = "fsl,vf610-dspi";
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. reg = <0x0 0x2110000 0x0 0x10000>;
  161. interrupts = <0 26 0x4>; /* Level high type */
  162. num-cs = <6>;
  163. };
  164. dspi2: dspi@2120000 {
  165. compatible = "fsl,vf610-dspi";
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. reg = <0x0 0x2120000 0x0 0x10000>;
  169. interrupts = <0 241 0x4>; /* Level high type */
  170. num-cs = <6>;
  171. };
  172. gpio2: gpio@2320000 {
  173. compatible = "fsl,qoriq-gpio";
  174. reg = <0x0 0x2320000 0x0 0x10000>;
  175. interrupts = <0 37 4>;
  176. gpio-controller;
  177. little-endian;
  178. #gpio-cells = <2>;
  179. interrupt-controller;
  180. #interrupt-cells = <2>;
  181. };
  182. usb0: usb3@3100000 {
  183. compatible = "fsl,layerscape-dwc3";
  184. reg = <0x0 0x3100000 0x0 0x10000>;
  185. interrupts = <0 80 0x4>; /* Level high type */
  186. dr_mode = "host";
  187. };
  188. usb1: usb3@3110000 {
  189. compatible = "fsl,layerscape-dwc3";
  190. reg = <0x0 0x3110000 0x0 0x10000>;
  191. interrupts = <0 81 0x4>; /* Level high type */
  192. dr_mode = "host";
  193. };
  194. esdhc0: esdhc@2140000 {
  195. compatible = "fsl,esdhc";
  196. reg = <0x0 0x2140000 0x0 0x10000>;
  197. interrupts = <0 28 0x4>; /* Level high type */
  198. clocks = <&clockgen 4 1>;
  199. voltage-ranges = <1800 1800 3300 3300>;
  200. sdhci,auto-cmd12;
  201. little-endian;
  202. bus-width = <4>;
  203. status = "disabled";
  204. };
  205. esdhc1: esdhc@2150000 {
  206. compatible = "fsl,esdhc";
  207. reg = <0x0 0x2150000 0x0 0x10000>;
  208. interrupts = <0 63 0x4>; /* Level high type */
  209. clocks = <&clockgen 4 1>;
  210. voltage-ranges = <1800 1800 3300 3300>;
  211. sdhci,auto-cmd12;
  212. non-removable;
  213. little-endian;
  214. bus-width = <4>;
  215. status = "disabled";
  216. };
  217. sata0: sata@3200000 {
  218. compatible = "fsl,ls2080a-ahci";
  219. reg = <0x0 0x3200000 0x0 0x10000>;
  220. interrupts = <0 133 4>;
  221. clocks = <&clockgen 4 3>;
  222. status = "disabled";
  223. };
  224. sata1: sata@3210000 {
  225. compatible = "fsl,ls2080a-ahci";
  226. reg = <0x0 0x3210000 0x0 0x10000>;
  227. interrupts = <0 136 4>;
  228. clocks = <&clockgen 4 3>;
  229. status = "disabled";
  230. };
  231. sata2: sata@3220000 {
  232. compatible = "fsl,ls2080a-ahci";
  233. reg = <0x0 0x3220000 0x0 0x10000>;
  234. interrupts = <0 97 4>;
  235. clocks = <&clockgen 4 3>;
  236. status = "disabled";
  237. };
  238. sata3: sata@3230000 {
  239. compatible = "fsl,ls2080a-ahci";
  240. reg = <0x0 0x3230000 0x0 0x10000>;
  241. interrupts = <0 100 4>;
  242. clocks = <&clockgen 4 3>;
  243. status = "disabled";
  244. };
  245. pcie@3400000 {
  246. compatible = "fsl,lx2160a-pcie";
  247. reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
  248. 0x00 0x03480000 0x0 0x40000 /* LUT registers */
  249. 0x00 0x034c0000 0x0 0x40000 /* PF control registers */
  250. 0x80 0x00000000 0x0 0x1000>; /* configuration space */
  251. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  252. #address-cells = <3>;
  253. #size-cells = <2>;
  254. device_type = "pci";
  255. bus-range = <0x0 0xff>;
  256. ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
  257. };
  258. pcie@3500000 {
  259. compatible = "fsl,lx2160a-pcie";
  260. reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
  261. 0x00 0x03580000 0x0 0x40000 /* LUT registers */
  262. 0x00 0x035c0000 0x0 0x40000 /* PF control registers */
  263. 0x88 0x00000000 0x0 0x1000>; /* configuration space */
  264. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  265. #address-cells = <3>;
  266. #size-cells = <2>;
  267. device_type = "pci";
  268. num-lanes = <2>;
  269. bus-range = <0x0 0xff>;
  270. ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
  271. };
  272. pcie@3600000 {
  273. compatible = "fsl,lx2160a-pcie";
  274. reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
  275. 0x00 0x03680000 0x0 0x40000 /* LUT registers */
  276. 0x00 0x036c0000 0x0 0x40000 /* PF control registers */
  277. 0x90 0x00000000 0x0 0x1000>; /* configuration space */
  278. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  279. #address-cells = <3>;
  280. #size-cells = <2>;
  281. device_type = "pci";
  282. bus-range = <0x0 0xff>;
  283. ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
  284. };
  285. pcie@3700000 {
  286. compatible = "fsl,lx2160a-pcie";
  287. reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
  288. 0x00 0x03780000 0x0 0x40000 /* LUT registers */
  289. 0x00 0x037c0000 0x0 0x40000 /* PF control registers */
  290. 0x98 0x00000000 0x0 0x1000>; /* configuration space */
  291. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  292. #address-cells = <3>;
  293. #size-cells = <2>;
  294. device_type = "pci";
  295. bus-range = <0x0 0xff>;
  296. ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
  297. };
  298. pcie@3800000 {
  299. compatible = "fsl,lx2160a-pcie";
  300. reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
  301. 0x00 0x03880000 0x0 0x40000 /* LUT registers */
  302. 0x00 0x038c0000 0x0 0x40000 /* PF control registers */
  303. 0xa0 0x00000000 0x0 0x1000>; /* configuration space */
  304. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  305. #address-cells = <3>;
  306. #size-cells = <2>;
  307. device_type = "pci";
  308. bus-range = <0x0 0xff>;
  309. ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
  310. };
  311. pcie@3900000 {
  312. compatible = "fsl,lx2160a-pcie";
  313. reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
  314. 0x00 0x03980000 0x0 0x40000 /* LUT registers */
  315. 0x00 0x039c0000 0x0 0x40000 /* PF control registers */
  316. 0xa8 0x00000000 0x0 0x1000>; /* configuration space */
  317. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  318. #address-cells = <3>;
  319. #size-cells = <2>;
  320. device_type = "pci";
  321. bus-range = <0x0 0xff>;
  322. ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
  323. };
  324. fsl_mc: fsl-mc@80c000000 {
  325. compatible = "fsl,qoriq-mc", "simple-mfd";
  326. reg = <0x00000008 0x0c000000 0 0x40>,
  327. <0x00000000 0x08340000 0 0x40000>;
  328. #address-cells = <3>;
  329. #size-cells = <1>;
  330. /*
  331. * Region type 0x0 - MC portals
  332. * Region type 0x1 - QBMAN portals
  333. */
  334. ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
  335. 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
  336. dpmacs {
  337. compatible = "simple-mfd";
  338. #address-cells = <1>;
  339. #size-cells = <0>;
  340. dpmac3: dpmac@3 {
  341. compatible = "fsl,qoriq-mc-dpmac";
  342. reg = <0x3>;
  343. status = "disabled";
  344. };
  345. dpmac4: dpmac@4 {
  346. compatible = "fsl,qoriq-mc-dpmac";
  347. reg = <0x4>;
  348. status = "disabled";
  349. };
  350. dpmac17: dpmac@11 {
  351. compatible = "fsl,qoriq-mc-dpmac";
  352. reg = <0x11>;
  353. status = "disabled";
  354. };
  355. dpmac18: dpmac@12 {
  356. compatible = "fsl,qoriq-mc-dpmac";
  357. reg = <0x12>;
  358. status = "disabled";
  359. };
  360. };
  361. };
  362. /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
  363. emdio1: mdio@8b96000 {
  364. compatible = "fsl,ls-mdio";
  365. reg = <0x0 0x8b96000 0x0 0x1000>;
  366. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  367. #address-cells = <1>;
  368. #size-cells = <0>;
  369. status = "disabled";
  370. };
  371. /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
  372. emdio2: mdio@8b97000 {
  373. compatible = "fsl,ls-mdio";
  374. reg = <0x0 0x8b97000 0x0 0x1000>;
  375. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  376. #address-cells = <1>;
  377. #size-cells = <0>;
  378. status = "disabled";
  379. };
  380. };