fsl-lx2160a-rdb.dts 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP LX2160ARDB device tree source
  4. *
  5. * Author: Priyanka Jain <priyanka.jain@nxp.com>
  6. * Sriram Dash <sriram.dash@nxp.com>
  7. *
  8. * Copyright 2018 NXP
  9. *
  10. */
  11. /dts-v1/;
  12. #include "fsl-lx2160a.dtsi"
  13. / {
  14. model = "NXP Layerscape LX2160ARDB Board";
  15. compatible = "fsl,lx2160ardb", "fsl,lx2160a";
  16. aliases {
  17. spi0 = &fspi;
  18. };
  19. };
  20. &dpmac3 {
  21. status = "okay";
  22. phy-handle = <&aquantia_phy1>;
  23. phy-connection-type = "usxgmii";
  24. };
  25. &dpmac4 {
  26. status = "okay";
  27. phy-handle = <&aquantia_phy2>;
  28. phy-connection-type = "usxgmii";
  29. };
  30. &dpmac17 {
  31. status = "okay";
  32. phy-handle = <&rgmii_phy1>;
  33. phy-connection-type = "rgmii-id";
  34. };
  35. &dpmac18 {
  36. status = "okay";
  37. phy-handle = <&rgmii_phy2>;
  38. phy-connection-type = "rgmii-id";
  39. };
  40. &emdio1 {
  41. status = "okay";
  42. rgmii_phy1: ethernet-phy@1 {
  43. /* AR8035 PHY - "compatible" property not strictly needed */
  44. compatible = "ethernet-phy-id004d.d072";
  45. reg = <0x1>;
  46. /* Poll mode - no "interrupts" property defined */
  47. };
  48. rgmii_phy2: ethernet-phy@2 {
  49. /* AR8035 PHY - "compatible" property not strictly needed */
  50. compatible = "ethernet-phy-id004d.d072";
  51. reg = <0x2>;
  52. /* Poll mode - no "interrupts" property defined */
  53. };
  54. aquantia_phy1: ethernet-phy@4 {
  55. /* AQR107 PHY - "compatible" property not strictly needed */
  56. compatible = "ethernet-phy-ieee802.3-c45";
  57. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  58. reg = <0x4>;
  59. };
  60. aquantia_phy2: ethernet-phy@5 {
  61. /* AQR107 PHY - "compatible" property not strictly needed */
  62. compatible = "ethernet-phy-ieee802.3-c45";
  63. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  64. reg = <0x5>;
  65. };
  66. };
  67. &esdhc0 {
  68. status = "okay";
  69. };
  70. &esdhc1 {
  71. status = "okay";
  72. mmc-hs200-1_8v;
  73. };
  74. &fspi {
  75. status = "okay";
  76. mt35xu512aba0: flash@0 {
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. compatible = "jedec,spi-nor";
  80. spi-max-frequency = <50000000>;
  81. reg = <0>;
  82. spi-rx-bus-width = <8>;
  83. spi-tx-bus-width = <1>;
  84. };
  85. mt35xu512aba1: flash@1 {
  86. #address-cells = <1>;
  87. #size-cells = <1>;
  88. compatible = "jedec,spi-nor";
  89. spi-max-frequency = <50000000>;
  90. reg = <1>;
  91. spi-rx-bus-width = <8>;
  92. spi-tx-bus-width = <1>;
  93. };
  94. };
  95. &i2c0 {
  96. status = "okay";
  97. u-boot,dm-pre-reloc;
  98. };
  99. &i2c4 {
  100. status = "okay";
  101. rtc@51 {
  102. compatible = "pcf2127-rtc";
  103. reg = <0x51>;
  104. };
  105. };
  106. &sata0 {
  107. status = "okay";
  108. };
  109. &sata1 {
  110. status = "okay";
  111. };
  112. &sata2 {
  113. status = "okay";
  114. };
  115. &sata3 {
  116. status = "okay";
  117. };