ls1046afrwy.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <fdt_support.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <asm/arch/soc.h>
  12. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  13. #include <hwconfig.h>
  14. #include <ahci.h>
  15. #include <mmc.h>
  16. #include <scsi.h>
  17. #include <fm_eth.h>
  18. #include <fsl_csu.h>
  19. #include <fsl_esdhc.h>
  20. #include <fsl_sec.h>
  21. #include <fsl_dspi.h>
  22. #define LS1046A_PORSR1_REG 0x1EE0000
  23. #define BOOT_SRC_SD 0x20000000
  24. #define BOOT_SRC_MASK 0xFF800000
  25. #define BOARD_REV_GPIO_SHIFT 17
  26. #define BOARD_REV_MASK 0x03
  27. #define USB2_SEL_MASK 0x00000100
  28. #define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
  29. (((word) & 0x00ff0000) >> 8) | \
  30. (((word) & 0x0000ff00) << 8) | \
  31. (((word) & 0x000000ff) << 24))
  32. #define SPI_MCR_REG 0x2100000
  33. DECLARE_GLOBAL_DATA_PTR;
  34. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  35. {
  36. int ret;
  37. #ifdef CONFIG_DM_I2C
  38. struct udevice *dev;
  39. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  40. 1, &dev);
  41. if (ret) {
  42. printf("%s: Cannot find udev for a bus %d\n", __func__,
  43. bus_num);
  44. return ret;
  45. }
  46. ret = dm_i2c_write(dev, 0, &ch, 1);
  47. #else
  48. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  49. #endif
  50. if (ret) {
  51. puts("PCA: failed to select proper channel\n");
  52. return ret;
  53. }
  54. return 0;
  55. }
  56. static inline void demux_select_usb2(void)
  57. {
  58. u32 val;
  59. struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
  60. val = in_be32(&pgpio->gpdir);
  61. val |= USB2_SEL_MASK;
  62. out_be32(&pgpio->gpdir, val);
  63. val = in_be32(&pgpio->gpdat);
  64. val |= USB2_SEL_MASK;
  65. out_be32(&pgpio->gpdat, val);
  66. }
  67. static inline void set_spi_cs_signal_inactive(void)
  68. {
  69. /* default: all CS signals inactive state is high */
  70. uint mcr_val;
  71. uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
  72. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  73. mcr_val = in_be32(SPI_MCR_REG);
  74. mcr_val |= DSPI_MCR_HALT;
  75. out_be32(SPI_MCR_REG, mcr_val);
  76. out_be32(SPI_MCR_REG, mcr_cfg_val);
  77. mcr_val = in_be32(SPI_MCR_REG);
  78. mcr_val &= ~DSPI_MCR_HALT;
  79. out_be32(SPI_MCR_REG, mcr_val);
  80. }
  81. int board_early_init_f(void)
  82. {
  83. fsl_lsch2_early_init_f();
  84. return 0;
  85. }
  86. static inline uint8_t get_board_version(void)
  87. {
  88. struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
  89. /* GPIO 13 and GPIO 14 are used for Board Rev */
  90. u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
  91. & BOARD_REV_MASK;
  92. /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */
  93. u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
  94. return val;
  95. }
  96. int checkboard(void)
  97. {
  98. static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
  99. u32 boot_src;
  100. u8 rev;
  101. rev = get_board_version();
  102. switch (rev) {
  103. case 0x00:
  104. puts("Board: LS1046AFRWY, Rev: A, boot from ");
  105. break;
  106. case 0x01:
  107. puts("Board: LS1046AFRWY, Rev: B, boot from ");
  108. break;
  109. default:
  110. puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
  111. break;
  112. }
  113. boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
  114. if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
  115. puts("SD\n");
  116. else
  117. puts("QSPI\n");
  118. printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
  119. return 0;
  120. }
  121. int board_init(void)
  122. {
  123. #ifdef CONFIG_NXP_ESBC
  124. /*
  125. * In case of Secure Boot, the IBR configures the SMMU
  126. * to allow only Secure transactions.
  127. * SMMU must be reset in bypass mode.
  128. * Set the ClientPD bit and Clear the USFCFG Bit
  129. */
  130. u32 val;
  131. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  132. out_le32(SMMU_SCR0, val);
  133. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  134. out_le32(SMMU_NSCR0, val);
  135. #endif
  136. #ifdef CONFIG_FSL_CAAM
  137. sec_init();
  138. #endif
  139. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  140. return 0;
  141. }
  142. int board_setup_core_volt(u32 vdd)
  143. {
  144. return 0;
  145. }
  146. void config_board_mux(void)
  147. {
  148. #ifdef CONFIG_HAS_FSL_XHCI_USB
  149. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  150. u32 usb_pwrfault;
  151. /*
  152. * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
  153. * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
  154. */
  155. out_be32(&scfg->rcwpmuxcr0, 0x3300);
  156. #ifdef CONFIG_HAS_FSL_IIC3
  157. /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
  158. out_be32(&scfg->rcwpmuxcr0, 0x0000);
  159. #endif
  160. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  161. usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
  162. SCFG_USBPWRFAULT_USB3_SHIFT) |
  163. (SCFG_USBPWRFAULT_DEDICATED <<
  164. SCFG_USBPWRFAULT_USB2_SHIFT) |
  165. (SCFG_USBPWRFAULT_SHARED <<
  166. SCFG_USBPWRFAULT_USB1_SHIFT);
  167. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  168. #ifndef CONFIG_HAS_FSL_IIC3
  169. /*
  170. * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
  171. * to select I2C3_USB2_SEL_IO
  172. * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
  173. * I2C3 header (default)
  174. * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
  175. * USB2 port
  176. * programmed to select USB2 by setting GPIO3_23 output to one
  177. */
  178. demux_select_usb2();
  179. #endif
  180. #endif
  181. set_spi_cs_signal_inactive();
  182. }
  183. #ifdef CONFIG_MISC_INIT_R
  184. int misc_init_r(void)
  185. {
  186. config_board_mux();
  187. return 0;
  188. }
  189. #endif
  190. int ft_board_setup(void *blob, bd_t *bd)
  191. {
  192. u64 base[CONFIG_NR_DRAM_BANKS];
  193. u64 size[CONFIG_NR_DRAM_BANKS];
  194. /* fixup DT for the two DDR banks */
  195. base[0] = gd->bd->bi_dram[0].start;
  196. size[0] = gd->bd->bi_dram[0].size;
  197. base[1] = gd->bd->bi_dram[1].start;
  198. size[1] = gd->bd->bi_dram[1].size;
  199. fdt_fixup_memory_banks(blob, base, size, 2);
  200. ft_cpu_setup(blob, bd);
  201. #ifdef CONFIG_SYS_DPAA_FMAN
  202. #ifndef CONFIG_DM_ETH
  203. fdt_fixup_fman_ethernet(blob);
  204. #endif
  205. #endif
  206. fdt_fixup_icid(blob);
  207. return 0;
  208. }