fsl-ls2088a-rdb-qspi.dts 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP ls2080a RDB board device tree source for QSPI-boot
  4. *
  5. * Author: Priyanka Jain <priyanka.jain@nxp.com>
  6. *
  7. * Copyright 2017 NXP
  8. */
  9. /dts-v1/;
  10. #include "fsl-ls2080a.dtsi"
  11. / {
  12. model = "Freescale Layerscape 2080a RDB Board";
  13. compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
  14. aliases {
  15. spi0 = &qspi;
  16. spi1 = &dspi;
  17. };
  18. };
  19. &dpmac1 {
  20. status = "okay";
  21. phy-handle = <&mdio1_phy1>;
  22. phy-connection-type = "xfi";
  23. };
  24. &dpmac2 {
  25. status = "okay";
  26. phy-handle = <&mdio1_phy2>;
  27. phy-connection-type = "xfi";
  28. };
  29. &dpmac3 {
  30. status = "okay";
  31. phy-handle = <&mdio1_phy3>;
  32. phy-connection-type = "xfi";
  33. };
  34. &dpmac4 {
  35. status = "okay";
  36. phy-handle = <&mdio1_phy4>;
  37. phy-connection-type = "xfi";
  38. };
  39. &dpmac5 {
  40. status = "okay";
  41. phy-handle = <&mdio2_phy1>;
  42. phy-connection-type = "xfi";
  43. };
  44. &dpmac6 {
  45. status = "okay";
  46. phy-handle = <&mdio2_phy2>;
  47. phy-connection-type = "xfi";
  48. };
  49. &dpmac7 {
  50. status = "okay";
  51. phy-handle = <&mdio2_phy3>;
  52. phy-connection-type = "xfi";
  53. };
  54. &dpmac8 {
  55. status = "okay";
  56. phy-handle = <&mdio2_phy4>;
  57. phy-connection-type = "xfi";
  58. };
  59. &emdio1 {
  60. status = "okay";
  61. /* CS4340 PHYs */
  62. mdio1_phy1: emdio1_phy@1 {
  63. reg = <0x10>;
  64. };
  65. mdio1_phy2: emdio1_phy@2 {
  66. reg = <0x11>;
  67. };
  68. mdio1_phy3: emdio1_phy@3 {
  69. reg = <0x12>;
  70. };
  71. mdio1_phy4: emdio1_phy@4 {
  72. reg = <0x13>;
  73. };
  74. };
  75. &emdio2 {
  76. status = "okay";
  77. /* AQR405 PHYs */
  78. mdio2_phy1: emdio2_phy@1 {
  79. compatible = "ethernet-phy-ieee802.3-c45";
  80. reg = <0x0>;
  81. };
  82. mdio2_phy2: emdio2_phy@2 {
  83. compatible = "ethernet-phy-ieee802.3-c45";
  84. reg = <0x1>;
  85. };
  86. mdio2_phy3: emdio2_phy@3 {
  87. compatible = "ethernet-phy-ieee802.3-c45";
  88. reg = <0x2>;
  89. };
  90. mdio2_phy4: emdio2_phy@4 {
  91. compatible = "ethernet-phy-ieee802.3-c45";
  92. reg = <0x3>;
  93. };
  94. };
  95. &dspi {
  96. bus-num = <0>;
  97. status = "okay";
  98. dflash0: n25q512a {
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. compatible = "jedec,spi-nor";
  102. spi-max-frequency = <3000000>;
  103. spi-cpol;
  104. spi-cpha;
  105. reg = <0>;
  106. };
  107. };
  108. &qspi {
  109. bus-num = <0>;
  110. status = "okay";
  111. qflash0: s25fs512s@0 {
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. compatible = "jedec,spi-nor";
  115. spi-max-frequency = <50000000>;
  116. reg = <0>;
  117. };
  118. qflash1: s25fs512s@1 {
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. compatible = "jedec,spi-nor";
  122. spi-max-frequency = <50000000>;
  123. reg = <1>;
  124. };
  125. };
  126. &i2c0 {
  127. status = "okay";
  128. u-boot,dm-pre-reloc;
  129. pca9547@75 {
  130. compatible = "nxp,pca9547";
  131. reg = <0x75>;
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. i2c@1 {
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. reg = <0x01>;
  138. rtc@68 {
  139. compatible = "dallas,ds3232";
  140. reg = <0x68>;
  141. };
  142. };
  143. };
  144. };
  145. &sata {
  146. status = "okay";
  147. };