soc.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <clock_legacy.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <fsl_immap.h>
  11. #include <fsl_ifc.h>
  12. #include <init.h>
  13. #include <linux/sizes.h>
  14. #include <asm/arch/fsl_serdes.h>
  15. #include <asm/arch/soc.h>
  16. #include <asm/io.h>
  17. #include <asm/global_data.h>
  18. #include <asm/arch-fsl-layerscape/config.h>
  19. #include <asm/arch-fsl-layerscape/ns_access.h>
  20. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  21. #include <asm/gic-v3.h>
  22. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  23. #include <fsl_csu.h>
  24. #endif
  25. #ifdef CONFIG_SYS_FSL_DDR
  26. #include <fsl_ddr_sdram.h>
  27. #include <fsl_ddr.h>
  28. #endif
  29. #ifdef CONFIG_CHAIN_OF_TRUST
  30. #include <fsl_validate.h>
  31. #endif
  32. #include <fsl_immap.h>
  33. #ifdef CONFIG_TFABOOT
  34. #include <env_internal.h>
  35. #endif
  36. #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #endif
  39. #ifdef CONFIG_GIC_V3_ITS
  40. #define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
  41. #define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
  42. #define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
  43. PROPTABLE_MAX_SZ, SZ_1M)
  44. static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
  45. {
  46. u32 phandle;
  47. int err;
  48. struct fdt_memory gic_rd_tables;
  49. gic_rd_tables.start = base;
  50. gic_rd_tables.end = base + size - 1;
  51. err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
  52. &phandle);
  53. if (err < 0)
  54. debug("%s: failed to add reserved memory: %d\n", __func__, err);
  55. return err;
  56. }
  57. int ls_gic_rd_tables_init(void *blob)
  58. {
  59. u64 gic_lpi_base;
  60. int ret;
  61. gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
  62. ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
  63. if (ret)
  64. return ret;
  65. ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
  66. if (ret)
  67. debug("%s: failed to init gic-lpi-tables\n", __func__);
  68. return ret;
  69. }
  70. #endif
  71. bool soc_has_dp_ddr(void)
  72. {
  73. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  74. u32 svr = gur_in32(&gur->svr);
  75. /* LS2085A, LS2088A, LS2048A has DP_DDR */
  76. if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
  77. (SVR_SOC_VER(svr) == SVR_LS2088A) ||
  78. (SVR_SOC_VER(svr) == SVR_LS2048A))
  79. return true;
  80. return false;
  81. }
  82. bool soc_has_aiop(void)
  83. {
  84. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  85. u32 svr = gur_in32(&gur->svr);
  86. /* LS2085A has AIOP */
  87. if (SVR_SOC_VER(svr) == SVR_LS2085A)
  88. return true;
  89. return false;
  90. }
  91. static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
  92. {
  93. scfg_clrsetbits32(scfg + offset / 4,
  94. 0xF << 6,
  95. SCFG_USB_TXVREFTUNE << 6);
  96. }
  97. static void erratum_a009008(void)
  98. {
  99. #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  100. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  101. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  102. defined(CONFIG_ARCH_LS1012A)
  103. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
  104. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  105. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
  106. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
  107. #endif
  108. #elif defined(CONFIG_ARCH_LS2080A)
  109. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
  110. #endif
  111. #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  112. }
  113. static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
  114. {
  115. scfg_clrbits32(scfg + offset / 4,
  116. SCFG_USB_SQRXTUNE_MASK << 23);
  117. }
  118. static void erratum_a009798(void)
  119. {
  120. #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  121. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  122. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  123. defined(CONFIG_ARCH_LS1012A)
  124. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
  125. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  126. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
  127. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
  128. #endif
  129. #elif defined(CONFIG_ARCH_LS2080A)
  130. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
  131. #endif
  132. #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  133. }
  134. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  135. defined(CONFIG_ARCH_LS1012A)
  136. static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
  137. {
  138. scfg_clrsetbits32(scfg + offset / 4,
  139. 0x7F << 9,
  140. SCFG_USB_PCSTXSWINGFULL << 9);
  141. }
  142. #endif
  143. static void erratum_a008997(void)
  144. {
  145. #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  146. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  147. defined(CONFIG_ARCH_LS1012A)
  148. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  149. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
  150. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  151. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
  152. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
  153. #endif
  154. #elif defined(CONFIG_ARCH_LS1028A)
  155. clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
  156. 0x7F << 11,
  157. DCSR_USB_PCSTXSWINGFULL << 11);
  158. #endif
  159. #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  160. }
  161. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  162. defined(CONFIG_ARCH_LS1012A)
  163. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  164. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  165. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  166. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  167. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  168. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  169. defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
  170. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  171. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  172. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  173. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  174. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  175. #endif
  176. static void erratum_a009007(void)
  177. {
  178. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  179. defined(CONFIG_ARCH_LS1012A)
  180. void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
  181. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  182. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  183. usb_phy = (void __iomem *)SCFG_USB_PHY2;
  184. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  185. usb_phy = (void __iomem *)SCFG_USB_PHY3;
  186. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  187. #endif
  188. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  189. defined(CONFIG_ARCH_LS1028A)
  190. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  191. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  192. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  193. #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
  194. }
  195. #if defined(CONFIG_FSL_LSCH3)
  196. static void erratum_a050106(void)
  197. {
  198. #if defined(CONFIG_ARCH_LX2160A)
  199. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  200. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  201. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  202. #endif
  203. }
  204. /*
  205. * This erratum requires setting a value to eddrtqcr1 to
  206. * optimal the DDR performance.
  207. */
  208. static void erratum_a008336(void)
  209. {
  210. #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  211. u32 *eddrtqcr1;
  212. #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
  213. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  214. if (fsl_ddr_get_version(0) == 0x50200)
  215. out_le32(eddrtqcr1, 0x63b30002);
  216. #endif
  217. #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
  218. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  219. if (fsl_ddr_get_version(0) == 0x50200)
  220. out_le32(eddrtqcr1, 0x63b30002);
  221. #endif
  222. #endif
  223. }
  224. /*
  225. * This erratum requires a register write before being Memory
  226. * controller 3 being enabled.
  227. */
  228. static void erratum_a008514(void)
  229. {
  230. #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
  231. u32 *eddrtqcr1;
  232. #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
  233. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  234. out_le32(eddrtqcr1, 0x63b20002);
  235. #endif
  236. #endif
  237. }
  238. #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  239. #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
  240. static unsigned long get_internval_val_mhz(void)
  241. {
  242. char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
  243. /*
  244. * interval is the number of platform cycles(MHz) between
  245. * wake up events generated by EPU.
  246. */
  247. ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
  248. if (interval)
  249. interval_mhz = simple_strtoul(interval, NULL, 10);
  250. return interval_mhz;
  251. }
  252. void erratum_a009635(void)
  253. {
  254. u32 val;
  255. unsigned long interval_mhz = get_internval_val_mhz();
  256. if (!interval_mhz)
  257. return;
  258. val = in_le32(DCSR_CGACRE5);
  259. writel(val | 0x00000200, DCSR_CGACRE5);
  260. val = in_le32(EPU_EPCMPR5);
  261. writel(interval_mhz, EPU_EPCMPR5);
  262. val = in_le32(EPU_EPCCR5);
  263. writel(val | 0x82820000, EPU_EPCCR5);
  264. val = in_le32(EPU_EPSMCR5);
  265. writel(val | 0x002f0000, EPU_EPSMCR5);
  266. val = in_le32(EPU_EPECR5);
  267. writel(val | 0x20000000, EPU_EPECR5);
  268. val = in_le32(EPU_EPGCR);
  269. writel(val | 0x80000000, EPU_EPGCR);
  270. }
  271. #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
  272. static void erratum_rcw_src(void)
  273. {
  274. #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
  275. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  276. u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
  277. u32 val;
  278. val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  279. val &= ~DCFG_PORSR1_RCW_SRC;
  280. val |= DCFG_PORSR1_RCW_SRC_NOR;
  281. out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
  282. #endif
  283. }
  284. #define I2C_DEBUG_REG 0x6
  285. #define I2C_GLITCH_EN 0x8
  286. /*
  287. * This erratum requires setting glitch_en bit to enable
  288. * digital glitch filter to improve clock stability.
  289. */
  290. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  291. static void erratum_a009203(void)
  292. {
  293. #ifdef CONFIG_SYS_I2C
  294. u8 __iomem *ptr;
  295. #ifdef I2C1_BASE_ADDR
  296. ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
  297. writeb(I2C_GLITCH_EN, ptr);
  298. #endif
  299. #ifdef I2C2_BASE_ADDR
  300. ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
  301. writeb(I2C_GLITCH_EN, ptr);
  302. #endif
  303. #ifdef I2C3_BASE_ADDR
  304. ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
  305. writeb(I2C_GLITCH_EN, ptr);
  306. #endif
  307. #ifdef I2C4_BASE_ADDR
  308. ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
  309. writeb(I2C_GLITCH_EN, ptr);
  310. #endif
  311. #endif
  312. }
  313. #endif
  314. void bypass_smmu(void)
  315. {
  316. u32 val;
  317. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  318. out_le32(SMMU_SCR0, val);
  319. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  320. out_le32(SMMU_NSCR0, val);
  321. }
  322. void fsl_lsch3_early_init_f(void)
  323. {
  324. erratum_rcw_src();
  325. #ifdef CONFIG_FSL_IFC
  326. init_early_memctl_regs(); /* tighten IFC timing */
  327. #endif
  328. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  329. erratum_a009203();
  330. #endif
  331. erratum_a008514();
  332. erratum_a008336();
  333. erratum_a009008();
  334. erratum_a009798();
  335. erratum_a008997();
  336. erratum_a009007();
  337. erratum_a050106();
  338. #ifdef CONFIG_CHAIN_OF_TRUST
  339. /* In case of Secure Boot, the IBR configures the SMMU
  340. * to allow only Secure transactions.
  341. * SMMU must be reset in bypass mode.
  342. * Set the ClientPD bit and Clear the USFCFG Bit
  343. */
  344. if (fsl_check_boot_mode_secure() == 1)
  345. bypass_smmu();
  346. #endif
  347. #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
  348. defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
  349. set_icids();
  350. #endif
  351. }
  352. /* Get VDD in the unit mV from voltage ID */
  353. int get_core_volt_from_fuse(void)
  354. {
  355. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  356. int vdd;
  357. u32 fusesr;
  358. u8 vid;
  359. /* get the voltage ID from fuse status register */
  360. fusesr = in_le32(&gur->dcfg_fusesr);
  361. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  362. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
  363. FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
  364. if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
  365. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
  366. FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
  367. }
  368. debug("%s: VID = 0x%x\n", __func__, vid);
  369. switch (vid) {
  370. case 0x00: /* VID isn't supported */
  371. vdd = -EINVAL;
  372. debug("%s: The VID feature is not supported\n", __func__);
  373. break;
  374. case 0x08: /* 0.9V silicon */
  375. vdd = 900;
  376. break;
  377. case 0x10: /* 1.0V silicon */
  378. vdd = 1000;
  379. break;
  380. default: /* Other core voltage */
  381. vdd = -EINVAL;
  382. debug("%s: The VID(%x) isn't supported\n", __func__, vid);
  383. break;
  384. }
  385. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  386. return vdd;
  387. }
  388. #elif defined(CONFIG_FSL_LSCH2)
  389. static void erratum_a009929(void)
  390. {
  391. #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
  392. struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  393. u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
  394. u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
  395. rstrqmr1 |= 0x00000400;
  396. gur_out32(&gur->rstrqmr1, rstrqmr1);
  397. writel(0x01000000, dcsr_cop_ccp);
  398. #endif
  399. }
  400. /*
  401. * This erratum requires setting a value to eddrtqcr1 to optimal
  402. * the DDR performance. The eddrtqcr1 register is in SCFG space
  403. * of LS1043A and the offset is 0x157_020c.
  404. */
  405. #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
  406. && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  407. #error A009660 and A008514 can not be both enabled.
  408. #endif
  409. static void erratum_a009660(void)
  410. {
  411. #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
  412. u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
  413. out_be32(eddrtqcr1, 0x63b20042);
  414. #endif
  415. }
  416. static void erratum_a008850_early(void)
  417. {
  418. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  419. /* part 1 of 2 */
  420. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  421. CONFIG_SYS_CCI400_OFFSET);
  422. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  423. /* Skip if running at lower exception level */
  424. if (current_el() < 3)
  425. return;
  426. /* disables propagation of barrier transactions to DDRC from CCI400 */
  427. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
  428. /* disable the re-ordering in DDRC */
  429. ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  430. #endif
  431. }
  432. void erratum_a008850_post(void)
  433. {
  434. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  435. /* part 2 of 2 */
  436. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  437. CONFIG_SYS_CCI400_OFFSET);
  438. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  439. u32 tmp;
  440. /* Skip if running at lower exception level */
  441. if (current_el() < 3)
  442. return;
  443. /* enable propagation of barrier transactions to DDRC from CCI400 */
  444. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  445. /* enable the re-ordering in DDRC */
  446. tmp = ddr_in32(&ddr->eor);
  447. tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  448. ddr_out32(&ddr->eor, tmp);
  449. #endif
  450. }
  451. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  452. void erratum_a010315(void)
  453. {
  454. int i;
  455. for (i = PCIE1; i <= PCIE4; i++)
  456. if (!is_serdes_configured(i)) {
  457. debug("PCIe%d: disabled all R/W permission!\n", i);
  458. set_pcie_ns_access(i, 0);
  459. }
  460. }
  461. #endif
  462. static void erratum_a010539(void)
  463. {
  464. #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
  465. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  466. u32 porsr1;
  467. porsr1 = in_be32(&gur->porsr1);
  468. porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
  469. out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  470. porsr1);
  471. out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
  472. #endif
  473. }
  474. /* Get VDD in the unit mV from voltage ID */
  475. int get_core_volt_from_fuse(void)
  476. {
  477. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  478. int vdd;
  479. u32 fusesr;
  480. u8 vid;
  481. fusesr = in_be32(&gur->dcfg_fusesr);
  482. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  483. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
  484. FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
  485. if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
  486. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
  487. FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
  488. }
  489. debug("%s: VID = 0x%x\n", __func__, vid);
  490. switch (vid) {
  491. case 0x00: /* VID isn't supported */
  492. vdd = -EINVAL;
  493. debug("%s: The VID feature is not supported\n", __func__);
  494. break;
  495. case 0x08: /* 0.9V silicon */
  496. vdd = 900;
  497. break;
  498. case 0x10: /* 1.0V silicon */
  499. vdd = 1000;
  500. break;
  501. default: /* Other core voltage */
  502. vdd = -EINVAL;
  503. printf("%s: The VID(%x) isn't supported\n", __func__, vid);
  504. break;
  505. }
  506. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  507. return vdd;
  508. }
  509. __weak int board_switch_core_volt(u32 vdd)
  510. {
  511. return 0;
  512. }
  513. static int setup_core_volt(u32 vdd)
  514. {
  515. return board_setup_core_volt(vdd);
  516. }
  517. #ifdef CONFIG_SYS_FSL_DDR
  518. static void ddr_enable_0v9_volt(bool en)
  519. {
  520. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  521. u32 tmp;
  522. tmp = ddr_in32(&ddr->ddr_cdr1);
  523. if (en)
  524. tmp |= DDR_CDR1_V0PT9_EN;
  525. else
  526. tmp &= ~DDR_CDR1_V0PT9_EN;
  527. ddr_out32(&ddr->ddr_cdr1, tmp);
  528. }
  529. #endif
  530. int setup_chip_volt(void)
  531. {
  532. int vdd;
  533. vdd = get_core_volt_from_fuse();
  534. /* Nothing to do for silicons doesn't support VID */
  535. if (vdd < 0)
  536. return vdd;
  537. if (setup_core_volt(vdd))
  538. printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
  539. #ifdef CONFIG_SYS_HAS_SERDES
  540. if (setup_serdes_volt(vdd))
  541. printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
  542. #endif
  543. #ifdef CONFIG_SYS_FSL_DDR
  544. if (vdd == 900)
  545. ddr_enable_0v9_volt(true);
  546. #endif
  547. return 0;
  548. }
  549. #ifdef CONFIG_FSL_PFE
  550. void init_pfe_scfg_dcfg_regs(void)
  551. {
  552. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  553. u32 ecccr2;
  554. out_be32(&scfg->pfeasbcr,
  555. in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
  556. out_be32(&scfg->pfebsbcr,
  557. in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
  558. /* CCI-400 QoS settings for PFE */
  559. out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
  560. | SCFG_WR_QOS1_PFE2_QOS));
  561. out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
  562. | SCFG_RD_QOS1_PFE2_QOS));
  563. ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
  564. out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
  565. ecccr2 | (unsigned int)DISABLE_PFE_ECC);
  566. }
  567. #endif
  568. void fsl_lsch2_early_init_f(void)
  569. {
  570. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  571. CONFIG_SYS_CCI400_OFFSET);
  572. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  573. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  574. enum boot_src src;
  575. #endif
  576. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  577. enable_layerscape_ns_access();
  578. #endif
  579. #ifdef CONFIG_FSL_IFC
  580. init_early_memctl_regs(); /* tighten IFC timing */
  581. #endif
  582. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  583. src = get_boot_src();
  584. if (src != BOOT_SOURCE_QSPI_NOR)
  585. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  586. #else
  587. #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
  588. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  589. #endif
  590. #endif
  591. /* Make SEC reads and writes snoopable */
  592. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  593. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  594. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  595. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
  596. SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
  597. SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  598. SCFG_SNPCNFGCR_SATAWRSNP);
  599. #elif defined(CONFIG_ARCH_LS1012A)
  600. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  601. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  602. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  603. SCFG_SNPCNFGCR_SATAWRSNP);
  604. #else
  605. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  606. SCFG_SNPCNFGCR_SECWRSNP |
  607. SCFG_SNPCNFGCR_SATARDSNP |
  608. SCFG_SNPCNFGCR_SATAWRSNP);
  609. #endif
  610. /*
  611. * Enable snoop requests and DVM message requests for
  612. * Slave insterface S4 (A53 core cluster)
  613. */
  614. if (current_el() == 3) {
  615. out_le32(&cci->slave[4].snoop_ctrl,
  616. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  617. }
  618. /*
  619. * Program Central Security Unit (CSU) to grant access
  620. * permission for USB 2.0 controller
  621. */
  622. #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
  623. if (current_el() == 3)
  624. set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
  625. #endif
  626. /* Erratum */
  627. erratum_a008850_early(); /* part 1 of 2 */
  628. erratum_a009929();
  629. erratum_a009660();
  630. erratum_a010539();
  631. erratum_a009008();
  632. erratum_a009798();
  633. erratum_a008997();
  634. erratum_a009007();
  635. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  636. set_icids();
  637. #endif
  638. }
  639. #endif
  640. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  641. int fspi_ahb_init(void)
  642. {
  643. /* Enable 4bytes address support and fast read */
  644. u32 *fspi_lut, lut_key, *fspi_key;
  645. fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
  646. fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
  647. lut_key = in_be32(fspi_key);
  648. if (lut_key == SYS_NXP_FSPI_LUTKEY) {
  649. /* That means the register is BE */
  650. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  651. /* Unlock the lut table */
  652. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  653. /* Create READ LUT */
  654. out_be32(fspi_lut, 0x0820040c);
  655. out_be32(fspi_lut + 1, 0x24003008);
  656. out_be32(fspi_lut + 2, 0x00000000);
  657. /* Lock the lut table */
  658. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  659. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  660. } else {
  661. /* That means the register is LE */
  662. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  663. /* Unlock the lut table */
  664. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  665. /* Create READ LUT */
  666. out_le32(fspi_lut, 0x0820040c);
  667. out_le32(fspi_lut + 1, 0x24003008);
  668. out_le32(fspi_lut + 2, 0x00000000);
  669. /* Lock the lut table */
  670. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  671. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  672. }
  673. return 0;
  674. }
  675. #endif
  676. #ifdef CONFIG_QSPI_AHB_INIT
  677. /* Enable 4bytes address support and fast read */
  678. int qspi_ahb_init(void)
  679. {
  680. u32 *qspi_lut, lut_key, *qspi_key;
  681. qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
  682. qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
  683. lut_key = in_be32(qspi_key);
  684. if (lut_key == 0x5af05af0) {
  685. /* That means the register is BE */
  686. out_be32(qspi_key, 0x5af05af0);
  687. /* Unlock the lut table */
  688. out_be32(qspi_key + 1, 0x00000002);
  689. out_be32(qspi_lut, 0x0820040c);
  690. out_be32(qspi_lut + 1, 0x1c080c08);
  691. out_be32(qspi_lut + 2, 0x00002400);
  692. /* Lock the lut table */
  693. out_be32(qspi_key, 0x5af05af0);
  694. out_be32(qspi_key + 1, 0x00000001);
  695. } else {
  696. /* That means the register is LE */
  697. out_le32(qspi_key, 0x5af05af0);
  698. /* Unlock the lut table */
  699. out_le32(qspi_key + 1, 0x00000002);
  700. out_le32(qspi_lut, 0x0820040c);
  701. out_le32(qspi_lut + 1, 0x1c080c08);
  702. out_le32(qspi_lut + 2, 0x00002400);
  703. /* Lock the lut table */
  704. out_le32(qspi_key, 0x5af05af0);
  705. out_le32(qspi_key + 1, 0x00000001);
  706. }
  707. return 0;
  708. }
  709. #endif
  710. #ifdef CONFIG_TFABOOT
  711. #define MAX_BOOTCMD_SIZE 512
  712. int fsl_setenv_bootcmd(void)
  713. {
  714. int ret;
  715. enum boot_src src = get_boot_src();
  716. char bootcmd_str[MAX_BOOTCMD_SIZE];
  717. switch (src) {
  718. #ifdef IFC_NOR_BOOTCOMMAND
  719. case BOOT_SOURCE_IFC_NOR:
  720. sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
  721. break;
  722. #endif
  723. #ifdef QSPI_NOR_BOOTCOMMAND
  724. case BOOT_SOURCE_QSPI_NOR:
  725. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  726. break;
  727. #endif
  728. #ifdef XSPI_NOR_BOOTCOMMAND
  729. case BOOT_SOURCE_XSPI_NOR:
  730. sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
  731. break;
  732. #endif
  733. #ifdef IFC_NAND_BOOTCOMMAND
  734. case BOOT_SOURCE_IFC_NAND:
  735. sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
  736. break;
  737. #endif
  738. #ifdef QSPI_NAND_BOOTCOMMAND
  739. case BOOT_SOURCE_QSPI_NAND:
  740. sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
  741. break;
  742. #endif
  743. #ifdef XSPI_NAND_BOOTCOMMAND
  744. case BOOT_SOURCE_XSPI_NAND:
  745. sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
  746. break;
  747. #endif
  748. #ifdef SD_BOOTCOMMAND
  749. case BOOT_SOURCE_SD_MMC:
  750. sprintf(bootcmd_str, SD_BOOTCOMMAND);
  751. break;
  752. #endif
  753. #ifdef SD2_BOOTCOMMAND
  754. case BOOT_SOURCE_SD_MMC2:
  755. sprintf(bootcmd_str, SD2_BOOTCOMMAND);
  756. break;
  757. #endif
  758. default:
  759. #ifdef QSPI_NOR_BOOTCOMMAND
  760. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  761. #endif
  762. break;
  763. }
  764. ret = env_set("bootcmd", bootcmd_str);
  765. if (ret) {
  766. printf("Failed to set bootcmd: ret = %d\n", ret);
  767. return ret;
  768. }
  769. return 0;
  770. }
  771. int fsl_setenv_mcinitcmd(void)
  772. {
  773. int ret = 0;
  774. enum boot_src src = get_boot_src();
  775. switch (src) {
  776. #ifdef IFC_MC_INIT_CMD
  777. case BOOT_SOURCE_IFC_NAND:
  778. case BOOT_SOURCE_IFC_NOR:
  779. ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
  780. break;
  781. #endif
  782. #ifdef QSPI_MC_INIT_CMD
  783. case BOOT_SOURCE_QSPI_NAND:
  784. case BOOT_SOURCE_QSPI_NOR:
  785. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  786. break;
  787. #endif
  788. #ifdef XSPI_MC_INIT_CMD
  789. case BOOT_SOURCE_XSPI_NAND:
  790. case BOOT_SOURCE_XSPI_NOR:
  791. ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
  792. break;
  793. #endif
  794. #ifdef SD_MC_INIT_CMD
  795. case BOOT_SOURCE_SD_MMC:
  796. ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
  797. break;
  798. #endif
  799. #ifdef SD2_MC_INIT_CMD
  800. case BOOT_SOURCE_SD_MMC2:
  801. ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
  802. break;
  803. #endif
  804. default:
  805. #ifdef QSPI_MC_INIT_CMD
  806. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  807. #endif
  808. break;
  809. }
  810. if (ret) {
  811. printf("Failed to set mcinitcmd: ret = %d\n", ret);
  812. return ret;
  813. }
  814. return 0;
  815. }
  816. #endif
  817. #ifdef CONFIG_BOARD_LATE_INIT
  818. __weak int fsl_board_late_init(void)
  819. {
  820. return 0;
  821. }
  822. int board_late_init(void)
  823. {
  824. #ifdef CONFIG_CHAIN_OF_TRUST
  825. fsl_setenv_chain_of_trust();
  826. #endif
  827. #ifdef CONFIG_TFABOOT
  828. /*
  829. * check if gd->env_addr is default_environment; then setenv bootcmd
  830. * and mcinitcmd.
  831. */
  832. #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
  833. if (gd->env_addr == (ulong)&default_environment[0]) {
  834. #else
  835. if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
  836. #endif
  837. fsl_setenv_bootcmd();
  838. fsl_setenv_mcinitcmd();
  839. }
  840. /*
  841. * If the boot mode is secure, default environment is not present then
  842. * setenv command needs to be run by default
  843. */
  844. #ifdef CONFIG_CHAIN_OF_TRUST
  845. if ((fsl_check_boot_mode_secure() == 1)) {
  846. fsl_setenv_bootcmd();
  847. fsl_setenv_mcinitcmd();
  848. }
  849. #endif
  850. #endif
  851. #ifdef CONFIG_QSPI_AHB_INIT
  852. qspi_ahb_init();
  853. #endif
  854. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  855. fspi_ahb_init();
  856. #endif
  857. return fsl_board_late_init();
  858. }
  859. #endif