memac_phy.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. * Andy Fleming <afleming@gmail.com>
  5. * Roy Zang <tie-fei.zang@freescale.com>
  6. * Some part is taken from tsec.c
  7. */
  8. #include <common.h>
  9. #include <miiphy.h>
  10. #include <phy.h>
  11. #include <asm/io.h>
  12. #include <fsl_memac.h>
  13. #include <fm_eth.h>
  14. #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  15. #define memac_out_32(a, v) out_le32(a, v)
  16. #define memac_clrbits_32(a, v) clrbits_le32(a, v)
  17. #define memac_setbits_32(a, v) setbits_le32(a, v)
  18. #else
  19. #define memac_out_32(a, v) out_be32(a, v)
  20. #define memac_clrbits_32(a, v) clrbits_be32(a, v)
  21. #define memac_setbits_32(a, v) setbits_be32(a, v)
  22. #endif
  23. #ifdef CONFIG_DM_ETH
  24. struct fm_mdio_priv {
  25. struct memac_mdio_controller *regs;
  26. };
  27. #endif
  28. static u32 memac_in_32(u32 *reg)
  29. {
  30. #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  31. return in_le32(reg);
  32. #else
  33. return in_be32(reg);
  34. #endif
  35. }
  36. /*
  37. * Write value to the PHY for this device to the register at regnum, waiting
  38. * until the write is done before it returns. All PHY configuration has to be
  39. * done through the TSEC1 MIIM regs
  40. */
  41. int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
  42. int regnum, u16 value)
  43. {
  44. struct memac_mdio_controller *regs;
  45. u32 mdio_ctl;
  46. u32 c45 = 1; /* Default to 10G interface */
  47. #ifndef CONFIG_DM_ETH
  48. regs = bus->priv;
  49. #else
  50. struct fm_mdio_priv *priv;
  51. if (!bus->priv)
  52. return -EINVAL;
  53. priv = dev_get_priv(bus->priv);
  54. regs = priv->regs;
  55. debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n",
  56. regs, port_addr, dev_addr, regnum, value);
  57. #endif
  58. if (dev_addr == MDIO_DEVAD_NONE) {
  59. c45 = 0; /* clause 22 */
  60. dev_addr = regnum & 0x1f;
  61. memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
  62. } else
  63. memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
  64. /* Wait till the bus is free */
  65. while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  66. ;
  67. /* Set the port and dev addr */
  68. mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
  69. memac_out_32(&regs->mdio_ctl, mdio_ctl);
  70. /* Set the register address */
  71. if (c45)
  72. memac_out_32(&regs->mdio_addr, regnum & 0xffff);
  73. /* Wait till the bus is free */
  74. while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  75. ;
  76. /* Write the value to the register */
  77. memac_out_32(&regs->mdio_data, MDIO_DATA(value));
  78. /* Wait till the MDIO write is complete */
  79. while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
  80. ;
  81. return 0;
  82. }
  83. /*
  84. * Reads from register regnum in the PHY for device dev, returning the value.
  85. * Clears miimcom first. All PHY configuration has to be done through the
  86. * TSEC1 MIIM regs
  87. */
  88. int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
  89. int regnum)
  90. {
  91. struct memac_mdio_controller *regs;
  92. u32 mdio_ctl;
  93. u32 c45 = 1;
  94. #ifndef CONFIG_DM_ETH
  95. regs = bus->priv;
  96. #else
  97. struct fm_mdio_priv *priv;
  98. if (!bus->priv)
  99. return -EINVAL;
  100. priv = dev_get_priv(bus->priv);
  101. regs = priv->regs;
  102. #endif
  103. if (dev_addr == MDIO_DEVAD_NONE) {
  104. #ifndef CONFIG_DM_ETH
  105. if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
  106. return 0xffff;
  107. #endif
  108. c45 = 0; /* clause 22 */
  109. dev_addr = regnum & 0x1f;
  110. memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
  111. } else
  112. memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
  113. /* Wait till the bus is free */
  114. while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  115. ;
  116. /* Set the Port and Device Addrs */
  117. mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
  118. memac_out_32(&regs->mdio_ctl, mdio_ctl);
  119. /* Set the register address */
  120. if (c45)
  121. memac_out_32(&regs->mdio_addr, regnum & 0xffff);
  122. /* Wait till the bus is free */
  123. while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  124. ;
  125. /* Initiate the read */
  126. mdio_ctl |= MDIO_CTL_READ;
  127. memac_out_32(&regs->mdio_ctl, mdio_ctl);
  128. /* Wait till the MDIO write is complete */
  129. while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
  130. ;
  131. /* Return all Fs if nothing was there */
  132. if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
  133. return 0xffff;
  134. return memac_in_32(&regs->mdio_data) & 0xffff;
  135. }
  136. int memac_mdio_reset(struct mii_dev *bus)
  137. {
  138. return 0;
  139. }
  140. #ifndef CONFIG_DM_ETH
  141. int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
  142. {
  143. struct mii_dev *bus = mdio_alloc();
  144. if (!bus) {
  145. printf("Failed to allocate FM TGEC MDIO bus\n");
  146. return -1;
  147. }
  148. bus->read = memac_mdio_read;
  149. bus->write = memac_mdio_write;
  150. bus->reset = memac_mdio_reset;
  151. strcpy(bus->name, info->name);
  152. bus->priv = info->regs;
  153. /*
  154. * On some platforms like B4860, default value of MDIO_CLK_DIV bits
  155. * in mdio_stat(mdio_cfg) register generates MDIO clock too high
  156. * (much higher than 2.5MHz), violating the IEEE specs.
  157. * On other platforms like T1040, default value of MDIO_CLK_DIV bits
  158. * is zero, so MDIO clock is disabled.
  159. * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
  160. * be properly initialized.
  161. * NEG bit default should be '1' as per FMAN-v3 RM, but on platform
  162. * like T2080QDS, this bit default is '0', which leads to MDIO failure
  163. * on XAUI PHY, so set this bit definitely.
  164. */
  165. memac_setbits_32(
  166. &((struct memac_mdio_controller *)info->regs)->mdio_stat,
  167. MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
  168. return mdio_register(bus);
  169. }
  170. #else /* CONFIG_DM_ETH */
  171. #if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO)
  172. static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg)
  173. {
  174. struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
  175. NULL;
  176. if (pdata && pdata->mii_bus)
  177. return memac_mdio_read(pdata->mii_bus, addr, devad, reg);
  178. return -1;
  179. }
  180. static int fm_mdio_write(struct udevice *dev, int addr, int devad, int reg,
  181. u16 val)
  182. {
  183. struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
  184. NULL;
  185. if (pdata && pdata->mii_bus)
  186. return memac_mdio_write(pdata->mii_bus, addr, devad, reg, val);
  187. return -1;
  188. }
  189. static int fm_mdio_reset(struct udevice *dev)
  190. {
  191. struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
  192. NULL;
  193. if (pdata && pdata->mii_bus)
  194. return memac_mdio_reset(pdata->mii_bus);
  195. return -1;
  196. }
  197. static const struct mdio_ops fm_mdio_ops = {
  198. .read = fm_mdio_read,
  199. .write = fm_mdio_write,
  200. .reset = fm_mdio_reset,
  201. };
  202. static const struct udevice_id fm_mdio_ids[] = {
  203. { .compatible = "fsl,fman-memac-mdio" },
  204. {}
  205. };
  206. static int fm_mdio_probe(struct udevice *dev)
  207. {
  208. struct fm_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
  209. struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
  210. NULL;
  211. if (!dev) {
  212. printf("%s dev = NULL\n", __func__);
  213. return -1;
  214. }
  215. if (!priv) {
  216. printf("dev_get_priv(dev %p) = NULL\n", dev);
  217. return -1;
  218. }
  219. priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
  220. debug("%s priv %p @ regs %p, pdata %p\n", __func__,
  221. priv, priv->regs, pdata);
  222. /*
  223. * On some platforms like B4860, default value of MDIO_CLK_DIV bits
  224. * in mdio_stat(mdio_cfg) register generates MDIO clock too high
  225. * (much higher than 2.5MHz), violating the IEEE specs.
  226. * On other platforms like T1040, default value of MDIO_CLK_DIV bits
  227. * is zero, so MDIO clock is disabled.
  228. * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
  229. * be properly initialized.
  230. * The default NEG bit should be '1' as per FMANv3 RM, but on platforms
  231. * like T2080QDS, this bit default is '0', which leads to MDIO failure
  232. * on XAUI PHY, so set this bit definitely.
  233. */
  234. if (priv && priv->regs && priv->regs->mdio_stat)
  235. memac_setbits_32(&priv->regs->mdio_stat,
  236. MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
  237. return 0;
  238. }
  239. static int fm_mdio_remove(struct udevice *dev)
  240. {
  241. return 0;
  242. }
  243. U_BOOT_DRIVER(fman_mdio) = {
  244. .name = "fman_mdio",
  245. .id = UCLASS_MDIO,
  246. .of_match = fm_mdio_ids,
  247. .probe = fm_mdio_probe,
  248. .remove = fm_mdio_remove,
  249. .ops = &fm_mdio_ops,
  250. .priv_auto_alloc_size = sizeof(struct fm_mdio_priv),
  251. .platdata_auto_alloc_size = sizeof(struct mdio_perdev_priv),
  252. };
  253. #endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */
  254. #endif /* CONFIG_DM_ETH */