eth.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. * Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #ifdef CONFIG_DM_ETH
  10. #include <dm.h>
  11. #include <dm/ofnode.h>
  12. #include <linux/compat.h>
  13. #include <phy_interface.h>
  14. #endif
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <hwconfig.h>
  18. #include <fm_eth.h>
  19. #include <fsl_mdio.h>
  20. #include <miiphy.h>
  21. #include <phy.h>
  22. #include <fsl_dtsec.h>
  23. #include <fsl_tgec.h>
  24. #include <fsl_memac.h>
  25. #include "fm.h"
  26. #ifndef CONFIG_DM_ETH
  27. static struct eth_device *devlist[NUM_FM_PORTS];
  28. static int num_controllers;
  29. #endif
  30. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
  31. #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
  32. TBIANA_FULL_DUPLEX)
  33. #define TBIANA_SGMII_ACK 0x4001
  34. #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
  35. TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
  36. /* Configure the TBI for SGMII operation */
  37. static void dtsec_configure_serdes(struct fm_eth *priv)
  38. {
  39. #ifdef CONFIG_SYS_FMAN_V3
  40. u32 value;
  41. struct mii_dev bus;
  42. bool sgmii_2500 = (priv->enet_if ==
  43. PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
  44. int i = 0, j;
  45. #ifndef CONFIG_DM_ETH
  46. bus.priv = priv->mac->phyregs;
  47. #else
  48. bus.priv = priv->pcs_mdio;
  49. #endif
  50. bus.read = memac_mdio_read;
  51. bus.write = memac_mdio_write;
  52. bus.reset = memac_mdio_reset;
  53. qsgmii_loop:
  54. /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
  55. if (sgmii_2500)
  56. value = PHY_SGMII_CR_PHY_RESET |
  57. PHY_SGMII_IF_SPEED_GIGABIT |
  58. PHY_SGMII_IF_MODE_SGMII;
  59. else
  60. value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
  61. for (j = 0; j <= 3; j++)
  62. debug("dump PCS reg %#x: %#x\n", j,
  63. memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
  64. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
  65. /* Dev ability according to SGMII specification */
  66. value = PHY_SGMII_DEV_ABILITY_SGMII;
  67. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
  68. if (sgmii_2500) {
  69. /* Adjust link timer for 2.5G SGMII,
  70. * 1.6 ms in units of 3.2 ns:
  71. * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
  72. */
  73. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
  74. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
  75. } else {
  76. /* Adjust link timer for SGMII,
  77. * 1.6 ms in units of 8 ns:
  78. * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
  79. */
  80. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
  81. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
  82. }
  83. /* Restart AN */
  84. value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
  85. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
  86. if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
  87. i++;
  88. goto qsgmii_loop;
  89. }
  90. #else
  91. struct dtsec *regs = priv->mac->base;
  92. struct tsec_mii_mng *phyregs = priv->mac->phyregs;
  93. /*
  94. * Access TBI PHY registers at given TSEC register offset as
  95. * opposed to the register offset used for external PHY accesses
  96. */
  97. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
  98. TBICON_CLK_SELECT);
  99. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
  100. TBIANA_SGMII_ACK);
  101. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
  102. TBI_CR, TBICR_SETTINGS);
  103. #endif
  104. }
  105. static void dtsec_init_phy(struct fm_eth *fm_eth)
  106. {
  107. #ifndef CONFIG_SYS_FMAN_V3
  108. struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
  109. /* Assign a Physical address to the TBI */
  110. out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
  111. #endif
  112. if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
  113. fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
  114. fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
  115. dtsec_configure_serdes(fm_eth);
  116. }
  117. #ifndef CONFIG_DM_ETH
  118. #ifdef CONFIG_PHYLIB
  119. static int tgec_is_fibre(struct fm_eth *fm)
  120. {
  121. char phyopt[20];
  122. sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
  123. return hwconfig_arg_cmp(phyopt, "xfi");
  124. }
  125. #endif
  126. #endif /* CONFIG_DM_ETH */
  127. #endif
  128. static u16 muram_readw(u16 *addr)
  129. {
  130. ulong base = (ulong)addr & ~0x3UL;
  131. u32 val32 = in_be32((void *)base);
  132. int byte_pos;
  133. u16 ret;
  134. byte_pos = (ulong)addr & 0x3UL;
  135. if (byte_pos)
  136. ret = (u16)(val32 & 0x0000ffff);
  137. else
  138. ret = (u16)((val32 & 0xffff0000) >> 16);
  139. return ret;
  140. }
  141. static void muram_writew(u16 *addr, u16 val)
  142. {
  143. ulong base = (ulong)addr & ~0x3UL;
  144. u32 org32 = in_be32((void *)base);
  145. u32 val32;
  146. int byte_pos;
  147. byte_pos = (ulong)addr & 0x3UL;
  148. if (byte_pos)
  149. val32 = (org32 & 0xffff0000) | val;
  150. else
  151. val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
  152. out_be32((void *)base, val32);
  153. }
  154. static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
  155. {
  156. int timeout = 1000000;
  157. clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
  158. /* wait until the rx port is not busy */
  159. while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
  160. ;
  161. if (!timeout)
  162. printf("%s - timeout\n", __func__);
  163. }
  164. static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
  165. {
  166. /* set BMI to independent mode, Rx port disable */
  167. out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
  168. /* clear FOF in IM case */
  169. out_be32(&rx_port->fmbm_rim, 0);
  170. /* Rx frame next engine -RISC */
  171. out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
  172. /* Rx command attribute - no order, MR[3] = 1 */
  173. clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
  174. setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
  175. /* enable Rx statistic counters */
  176. out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
  177. /* disable Rx performance counters */
  178. out_be32(&rx_port->fmbm_rpc, 0);
  179. }
  180. static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
  181. {
  182. int timeout = 1000000;
  183. clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
  184. /* wait until the tx port is not busy */
  185. while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
  186. ;
  187. if (!timeout)
  188. printf("%s - timeout\n", __func__);
  189. }
  190. static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
  191. {
  192. /* set BMI to independent mode, Tx port disable */
  193. out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
  194. /* Tx frame next engine -RISC */
  195. out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
  196. out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
  197. /* Tx command attribute - no order, MR[3] = 1 */
  198. clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
  199. setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
  200. /* enable Tx statistic counters */
  201. out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
  202. /* disable Tx performance counters */
  203. out_be32(&tx_port->fmbm_tpc, 0);
  204. }
  205. static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
  206. {
  207. struct fm_port_global_pram *pram;
  208. u32 pram_page_offset;
  209. void *rx_bd_ring_base;
  210. void *rx_buf_pool;
  211. u32 bd_ring_base_lo, bd_ring_base_hi;
  212. u32 buf_lo, buf_hi;
  213. struct fm_port_bd *rxbd;
  214. struct fm_port_qd *rxqd;
  215. struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
  216. int i;
  217. /* alloc global parameter ram at MURAM */
  218. pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
  219. FM_PRAM_SIZE, FM_PRAM_ALIGN);
  220. if (!pram) {
  221. printf("%s: No muram for Rx global parameter\n", __func__);
  222. return -ENOMEM;
  223. }
  224. fm_eth->rx_pram = pram;
  225. /* parameter page offset to MURAM */
  226. pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
  227. /* enable global mode- snooping data buffers and BDs */
  228. out_be32(&pram->mode, PRAM_MODE_GLOBAL);
  229. /* init the Rx queue descriptor pionter */
  230. out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
  231. /* set the max receive buffer length, power of 2 */
  232. muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
  233. /* alloc Rx buffer descriptors from main memory */
  234. rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
  235. * RX_BD_RING_SIZE);
  236. if (!rx_bd_ring_base)
  237. return -ENOMEM;
  238. memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
  239. * RX_BD_RING_SIZE);
  240. /* alloc Rx buffer from main memory */
  241. rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
  242. if (!rx_buf_pool)
  243. return -ENOMEM;
  244. memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
  245. debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
  246. /* save them to fm_eth */
  247. fm_eth->rx_bd_ring = rx_bd_ring_base;
  248. fm_eth->cur_rxbd = rx_bd_ring_base;
  249. fm_eth->rx_buf = rx_buf_pool;
  250. /* init Rx BDs ring */
  251. rxbd = (struct fm_port_bd *)rx_bd_ring_base;
  252. for (i = 0; i < RX_BD_RING_SIZE; i++) {
  253. muram_writew(&rxbd->status, RxBD_EMPTY);
  254. muram_writew(&rxbd->len, 0);
  255. buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
  256. i * MAX_RXBUF_LEN));
  257. buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
  258. i * MAX_RXBUF_LEN));
  259. muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
  260. out_be32(&rxbd->buf_ptr_lo, buf_lo);
  261. rxbd++;
  262. }
  263. /* set the Rx queue descriptor */
  264. rxqd = &pram->rxqd;
  265. muram_writew(&rxqd->gen, 0);
  266. bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
  267. bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
  268. muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
  269. out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
  270. muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
  271. * RX_BD_RING_SIZE);
  272. muram_writew(&rxqd->offset_in, 0);
  273. muram_writew(&rxqd->offset_out, 0);
  274. /* set IM parameter ram pointer to Rx Frame Queue ID */
  275. out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
  276. return 0;
  277. }
  278. static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
  279. {
  280. struct fm_port_global_pram *pram;
  281. u32 pram_page_offset;
  282. void *tx_bd_ring_base;
  283. u32 bd_ring_base_lo, bd_ring_base_hi;
  284. struct fm_port_bd *txbd;
  285. struct fm_port_qd *txqd;
  286. struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
  287. int i;
  288. /* alloc global parameter ram at MURAM */
  289. pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
  290. FM_PRAM_SIZE, FM_PRAM_ALIGN);
  291. if (!pram) {
  292. printf("%s: No muram for Tx global parameter\n", __func__);
  293. return -ENOMEM;
  294. }
  295. fm_eth->tx_pram = pram;
  296. /* parameter page offset to MURAM */
  297. pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
  298. /* enable global mode- snooping data buffers and BDs */
  299. out_be32(&pram->mode, PRAM_MODE_GLOBAL);
  300. /* init the Tx queue descriptor pionter */
  301. out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
  302. /* alloc Tx buffer descriptors from main memory */
  303. tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
  304. * TX_BD_RING_SIZE);
  305. if (!tx_bd_ring_base)
  306. return -ENOMEM;
  307. memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
  308. * TX_BD_RING_SIZE);
  309. /* save it to fm_eth */
  310. fm_eth->tx_bd_ring = tx_bd_ring_base;
  311. fm_eth->cur_txbd = tx_bd_ring_base;
  312. /* init Tx BDs ring */
  313. txbd = (struct fm_port_bd *)tx_bd_ring_base;
  314. for (i = 0; i < TX_BD_RING_SIZE; i++) {
  315. muram_writew(&txbd->status, TxBD_LAST);
  316. muram_writew(&txbd->len, 0);
  317. muram_writew(&txbd->buf_ptr_hi, 0);
  318. out_be32(&txbd->buf_ptr_lo, 0);
  319. txbd++;
  320. }
  321. /* set the Tx queue decriptor */
  322. txqd = &pram->txqd;
  323. bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
  324. bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
  325. muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
  326. out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
  327. muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
  328. * TX_BD_RING_SIZE);
  329. muram_writew(&txqd->offset_in, 0);
  330. muram_writew(&txqd->offset_out, 0);
  331. /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
  332. out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
  333. return 0;
  334. }
  335. static int fm_eth_init(struct fm_eth *fm_eth)
  336. {
  337. int ret;
  338. ret = fm_eth_rx_port_parameter_init(fm_eth);
  339. if (ret)
  340. return ret;
  341. ret = fm_eth_tx_port_parameter_init(fm_eth);
  342. if (ret)
  343. return ret;
  344. return 0;
  345. }
  346. static int fm_eth_startup(struct fm_eth *fm_eth)
  347. {
  348. struct fsl_enet_mac *mac;
  349. int ret;
  350. mac = fm_eth->mac;
  351. /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
  352. ret = fm_eth_init(fm_eth);
  353. if (ret)
  354. return ret;
  355. /* setup the MAC controller */
  356. mac->init_mac(mac);
  357. /* For some reason we need to set SPEED_100 */
  358. if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
  359. (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
  360. (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
  361. mac->set_if_mode)
  362. mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
  363. /* init bmi rx port, IM mode and disable */
  364. bmi_rx_port_init(fm_eth->rx_port);
  365. /* init bmi tx port, IM mode and disable */
  366. bmi_tx_port_init(fm_eth->tx_port);
  367. return 0;
  368. }
  369. static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
  370. {
  371. struct fm_port_global_pram *pram;
  372. pram = fm_eth->tx_pram;
  373. /* graceful stop transmission of frames */
  374. setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
  375. sync();
  376. }
  377. static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
  378. {
  379. struct fm_port_global_pram *pram;
  380. pram = fm_eth->tx_pram;
  381. /* re-enable transmission of frames */
  382. clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
  383. sync();
  384. }
  385. #ifndef CONFIG_DM_ETH
  386. static int fm_eth_open(struct eth_device *dev, bd_t *bd)
  387. #else
  388. static int fm_eth_open(struct udevice *dev)
  389. #endif
  390. {
  391. #ifndef CONFIG_DM_ETH
  392. struct fm_eth *fm_eth = dev->priv;
  393. #else
  394. struct eth_pdata *pdata = dev_get_platdata(dev);
  395. struct fm_eth *fm_eth = dev_get_priv(dev);
  396. #endif
  397. unsigned char *enetaddr;
  398. struct fsl_enet_mac *mac;
  399. #ifdef CONFIG_PHYLIB
  400. int ret;
  401. #endif
  402. mac = fm_eth->mac;
  403. #ifndef CONFIG_DM_ETH
  404. enetaddr = &dev->enetaddr[0];
  405. #else
  406. enetaddr = pdata->enetaddr;
  407. #endif
  408. /* setup the MAC address */
  409. if (enetaddr[0] & 0x01) {
  410. printf("%s: MacAddress is multicast address\n", __func__);
  411. enetaddr[0] = 0;
  412. enetaddr[5] = fm_eth->num;
  413. }
  414. mac->set_mac_addr(mac, enetaddr);
  415. /* enable bmi Rx port */
  416. setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
  417. /* enable MAC rx/tx port */
  418. mac->enable_mac(mac);
  419. /* enable bmi Tx port */
  420. setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
  421. /* re-enable transmission of frame */
  422. fmc_tx_port_graceful_stop_disable(fm_eth);
  423. #ifdef CONFIG_PHYLIB
  424. if (fm_eth->phydev) {
  425. ret = phy_startup(fm_eth->phydev);
  426. if (ret) {
  427. #ifndef CONFIG_DM_ETH
  428. printf("%s: Could not initialize\n",
  429. fm_eth->phydev->dev->name);
  430. #else
  431. printf("%s: Could not initialize\n", dev->name);
  432. #endif
  433. return ret;
  434. }
  435. } else {
  436. return 0;
  437. }
  438. #else
  439. fm_eth->phydev->speed = SPEED_1000;
  440. fm_eth->phydev->link = 1;
  441. fm_eth->phydev->duplex = DUPLEX_FULL;
  442. #endif
  443. /* set the MAC-PHY mode */
  444. mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
  445. debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
  446. fm_eth->phydev->speed, fm_eth->phydev->link);
  447. if (!fm_eth->phydev->link)
  448. printf("%s: No link.\n", fm_eth->phydev->dev->name);
  449. return fm_eth->phydev->link ? 0 : -1;
  450. }
  451. #ifndef CONFIG_DM_ETH
  452. static void fm_eth_halt(struct eth_device *dev)
  453. #else
  454. static void fm_eth_halt(struct udevice *dev)
  455. #endif
  456. {
  457. struct fm_eth *fm_eth;
  458. struct fsl_enet_mac *mac;
  459. fm_eth = (struct fm_eth *)dev->priv;
  460. mac = fm_eth->mac;
  461. /* graceful stop the transmission of frames */
  462. fmc_tx_port_graceful_stop_enable(fm_eth);
  463. /* disable bmi Tx port */
  464. bmi_tx_port_disable(fm_eth->tx_port);
  465. /* disable MAC rx/tx port */
  466. mac->disable_mac(mac);
  467. /* disable bmi Rx port */
  468. bmi_rx_port_disable(fm_eth->rx_port);
  469. #ifdef CONFIG_PHYLIB
  470. if (fm_eth->phydev)
  471. phy_shutdown(fm_eth->phydev);
  472. #endif
  473. }
  474. #ifndef CONFIG_DM_ETH
  475. static int fm_eth_send(struct eth_device *dev, void *buf, int len)
  476. #else
  477. static int fm_eth_send(struct udevice *dev, void *buf, int len)
  478. #endif
  479. {
  480. struct fm_eth *fm_eth;
  481. struct fm_port_global_pram *pram;
  482. struct fm_port_bd *txbd, *txbd_base;
  483. u16 offset_in;
  484. int i;
  485. fm_eth = (struct fm_eth *)dev->priv;
  486. pram = fm_eth->tx_pram;
  487. txbd = fm_eth->cur_txbd;
  488. /* find one empty TxBD */
  489. for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
  490. udelay(100);
  491. if (i > 0x1000) {
  492. printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
  493. dev->name, muram_readw(&txbd->status));
  494. return 0;
  495. }
  496. }
  497. /* setup TxBD */
  498. muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
  499. out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
  500. muram_writew(&txbd->len, len);
  501. sync();
  502. muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
  503. sync();
  504. /* update TxQD, let RISC to send the packet */
  505. offset_in = muram_readw(&pram->txqd.offset_in);
  506. offset_in += sizeof(struct fm_port_bd);
  507. if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
  508. offset_in = 0;
  509. muram_writew(&pram->txqd.offset_in, offset_in);
  510. sync();
  511. /* wait for buffer to be transmitted */
  512. for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
  513. udelay(100);
  514. if (i > 0x10000) {
  515. printf("%s: Tx error, txbd->status = 0x%x\n",
  516. dev->name, muram_readw(&txbd->status));
  517. return 0;
  518. }
  519. }
  520. /* advance the TxBD */
  521. txbd++;
  522. txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
  523. if (txbd >= (txbd_base + TX_BD_RING_SIZE))
  524. txbd = txbd_base;
  525. /* update current txbd */
  526. fm_eth->cur_txbd = (void *)txbd;
  527. return 1;
  528. }
  529. static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
  530. struct fm_port_bd *rxbd)
  531. {
  532. struct fm_port_global_pram *pram;
  533. struct fm_port_bd *rxbd_base;
  534. u16 offset_out;
  535. pram = fm_eth->rx_pram;
  536. /* clear the RxBDs */
  537. muram_writew(&rxbd->status, RxBD_EMPTY);
  538. muram_writew(&rxbd->len, 0);
  539. sync();
  540. /* advance RxBD */
  541. rxbd++;
  542. rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
  543. if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
  544. rxbd = rxbd_base;
  545. /* update RxQD */
  546. offset_out = muram_readw(&pram->rxqd.offset_out);
  547. offset_out += sizeof(struct fm_port_bd);
  548. if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
  549. offset_out = 0;
  550. muram_writew(&pram->rxqd.offset_out, offset_out);
  551. sync();
  552. return rxbd;
  553. }
  554. #ifndef CONFIG_DM_ETH
  555. static int fm_eth_recv(struct eth_device *dev)
  556. #else
  557. static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  558. #endif
  559. {
  560. struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
  561. struct fm_port_bd *rxbd = fm_eth->cur_rxbd;
  562. u32 buf_lo, buf_hi;
  563. u16 status, len;
  564. int ret = -1;
  565. u8 *data;
  566. status = muram_readw(&rxbd->status);
  567. while (!(status & RxBD_EMPTY)) {
  568. if (!(status & RxBD_ERROR)) {
  569. buf_hi = muram_readw(&rxbd->buf_ptr_hi);
  570. buf_lo = in_be32(&rxbd->buf_ptr_lo);
  571. data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
  572. len = muram_readw(&rxbd->len);
  573. #ifndef CONFIG_DM_ETH
  574. net_process_received_packet(data, len);
  575. #else
  576. *packetp = data;
  577. return len;
  578. #endif
  579. } else {
  580. printf("%s: Rx error\n", dev->name);
  581. ret = 0;
  582. }
  583. /* free current bd, advance to next one */
  584. rxbd = fm_eth_free_one(fm_eth, rxbd);
  585. /* read next status */
  586. status = muram_readw(&rxbd->status);
  587. }
  588. fm_eth->cur_rxbd = (void *)rxbd;
  589. return ret;
  590. }
  591. #ifdef CONFIG_DM_ETH
  592. static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  593. {
  594. struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
  595. fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
  596. return 0;
  597. }
  598. #endif /* CONFIG_DM_ETH */
  599. #ifndef CONFIG_DM_ETH
  600. static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
  601. {
  602. struct fsl_enet_mac *mac;
  603. int num;
  604. void *base, *phyregs = NULL;
  605. num = fm_eth->num;
  606. #ifdef CONFIG_SYS_FMAN_V3
  607. #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  608. if (fm_eth->type == FM_ETH_10G_E) {
  609. /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
  610. * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
  611. * 10GEC1 uses mEMAC1 on T1024.
  612. * so it needs to change the num.
  613. */
  614. if (fm_eth->num >= 2)
  615. num -= 2;
  616. else
  617. num += 8;
  618. }
  619. #endif
  620. base = &reg->memac[num].fm_memac;
  621. phyregs = &reg->memac[num].fm_memac_mdio;
  622. #else
  623. /* Get the mac registers base address */
  624. if (fm_eth->type == FM_ETH_1G_E) {
  625. base = &reg->mac_1g[num].fm_dtesc;
  626. phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
  627. } else {
  628. base = &reg->mac_10g[num].fm_10gec;
  629. phyregs = &reg->mac_10g[num].fm_10gec_mdio;
  630. }
  631. #endif
  632. /* alloc mac controller */
  633. mac = malloc(sizeof(struct fsl_enet_mac));
  634. if (!mac)
  635. return -ENOMEM;
  636. memset(mac, 0, sizeof(struct fsl_enet_mac));
  637. /* save the mac to fm_eth struct */
  638. fm_eth->mac = mac;
  639. #ifdef CONFIG_SYS_FMAN_V3
  640. init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
  641. #else
  642. if (fm_eth->type == FM_ETH_1G_E)
  643. init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
  644. else
  645. init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
  646. #endif
  647. return 0;
  648. }
  649. #else /* CONFIG_DM_ETH */
  650. static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
  651. {
  652. #ifndef CONFIG_SYS_FMAN_V3
  653. void *mdio;
  654. #endif
  655. fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
  656. if (!fm_eth->mac)
  657. return -ENOMEM;
  658. #ifndef CONFIG_SYS_FMAN_V3
  659. mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
  660. debug("MDIO %d @ %p\n", fm_eth->num, mdio);
  661. #endif
  662. switch (fm_eth->mac_type) {
  663. #ifdef CONFIG_SYS_FMAN_V3
  664. case FM_MEMAC:
  665. init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
  666. break;
  667. #else
  668. case FM_DTSEC:
  669. init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
  670. break;
  671. case FM_TGEC:
  672. init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
  673. break;
  674. #endif
  675. }
  676. return 0;
  677. }
  678. #endif /* CONFIG_DM_ETH */
  679. static int init_phy(struct fm_eth *fm_eth)
  680. {
  681. #ifdef CONFIG_PHYLIB
  682. u32 supported = PHY_GBIT_FEATURES;
  683. #ifndef CONFIG_DM_ETH
  684. struct phy_device *phydev = NULL;
  685. #endif
  686. if (fm_eth->type == FM_ETH_10G_E)
  687. supported = PHY_10G_FEATURES;
  688. if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
  689. supported |= SUPPORTED_2500baseX_Full;
  690. #endif
  691. if (fm_eth->type == FM_ETH_1G_E)
  692. dtsec_init_phy(fm_eth);
  693. #ifdef CONFIG_DM_ETH
  694. #ifdef CONFIG_PHYLIB
  695. #ifdef CONFIG_DM_MDIO
  696. fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
  697. if (!fm_eth->phydev)
  698. return -ENODEV;
  699. #endif
  700. fm_eth->phydev->advertising &= supported;
  701. fm_eth->phydev->supported &= supported;
  702. phy_config(fm_eth->phydev);
  703. #endif
  704. #else /* CONFIG_DM_ETH */
  705. #ifdef CONFIG_PHYLIB
  706. if (fm_eth->bus) {
  707. phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
  708. fm_eth->enet_if);
  709. if (!phydev) {
  710. printf("Failed to connect\n");
  711. return -1;
  712. }
  713. } else {
  714. return 0;
  715. }
  716. if (fm_eth->type == FM_ETH_1G_E) {
  717. supported = (SUPPORTED_10baseT_Half |
  718. SUPPORTED_10baseT_Full |
  719. SUPPORTED_100baseT_Half |
  720. SUPPORTED_100baseT_Full |
  721. SUPPORTED_1000baseT_Full);
  722. } else {
  723. supported = SUPPORTED_10000baseT_Full;
  724. if (tgec_is_fibre(fm_eth))
  725. phydev->port = PORT_FIBRE;
  726. }
  727. phydev->supported &= supported;
  728. phydev->advertising = phydev->supported;
  729. fm_eth->phydev = phydev;
  730. phy_config(phydev);
  731. #endif
  732. #endif /* CONFIG_DM_ETH */
  733. return 0;
  734. }
  735. #ifndef CONFIG_DM_ETH
  736. int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
  737. {
  738. struct eth_device *dev;
  739. struct fm_eth *fm_eth;
  740. int i, num = info->num;
  741. int ret;
  742. /* alloc eth device */
  743. dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  744. if (!dev)
  745. return -ENOMEM;
  746. memset(dev, 0, sizeof(struct eth_device));
  747. /* alloc the FMan ethernet private struct */
  748. fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
  749. if (!fm_eth)
  750. return -ENOMEM;
  751. memset(fm_eth, 0, sizeof(struct fm_eth));
  752. /* save off some things we need from the info struct */
  753. fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
  754. fm_eth->num = num;
  755. fm_eth->type = info->type;
  756. fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
  757. fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
  758. /* set the ethernet max receive length */
  759. fm_eth->max_rx_len = MAX_RXBUF_LEN;
  760. /* init global mac structure */
  761. ret = fm_eth_init_mac(fm_eth, reg);
  762. if (ret)
  763. return ret;
  764. /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
  765. if (fm_eth->type == FM_ETH_1G_E)
  766. sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
  767. else
  768. sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
  769. devlist[num_controllers++] = dev;
  770. dev->iobase = 0;
  771. dev->priv = (void *)fm_eth;
  772. dev->init = fm_eth_open;
  773. dev->halt = fm_eth_halt;
  774. dev->send = fm_eth_send;
  775. dev->recv = fm_eth_recv;
  776. fm_eth->dev = dev;
  777. fm_eth->bus = info->bus;
  778. fm_eth->phyaddr = info->phy_addr;
  779. fm_eth->enet_if = info->enet_if;
  780. /* startup the FM im */
  781. ret = fm_eth_startup(fm_eth);
  782. if (ret)
  783. return ret;
  784. init_phy(fm_eth);
  785. /* clear the ethernet address */
  786. for (i = 0; i < 6; i++)
  787. dev->enetaddr[i] = 0;
  788. eth_register(dev);
  789. return 0;
  790. }
  791. #else /* CONFIG_DM_ETH */
  792. #ifdef CONFIG_PHYLIB
  793. phy_interface_t fman_read_sys_if(struct udevice *dev)
  794. {
  795. const char *if_str;
  796. if_str = ofnode_read_string(dev->node, "phy-connection-type");
  797. debug("MAC system interface mode %s\n", if_str);
  798. return phy_get_interface_by_name(if_str);
  799. }
  800. #endif
  801. static int fm_eth_bind(struct udevice *dev)
  802. {
  803. char mac_name[11];
  804. u32 fm, num;
  805. if (ofnode_read_u32(ofnode_get_parent(dev->node), "cell-index", &fm)) {
  806. printf("FMan node property cell-index missing\n");
  807. return -EINVAL;
  808. }
  809. if (dev && dev_read_u32(dev, "cell-index", &num)) {
  810. printf("FMan MAC node property cell-index missing\n");
  811. return -EINVAL;
  812. }
  813. sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
  814. device_set_name(dev, mac_name);
  815. debug("%s - binding %s\n", __func__, mac_name);
  816. return 0;
  817. }
  818. static struct udevice *fm_get_internal_mdio(struct udevice *dev)
  819. {
  820. struct ofnode_phandle_args phandle = {.node = ofnode_null()};
  821. struct udevice *mdiodev;
  822. if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
  823. 0, 0, &phandle) ||
  824. !ofnode_valid(phandle.node)) {
  825. if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
  826. 0, 0, &phandle) ||
  827. !ofnode_valid(phandle.node)) {
  828. printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
  829. dev->name);
  830. return NULL;
  831. }
  832. }
  833. if (uclass_get_device_by_ofnode(UCLASS_MDIO,
  834. ofnode_get_parent(phandle.node),
  835. &mdiodev)) {
  836. printf("can't find MDIO bus for node %s\n",
  837. ofnode_get_name(ofnode_get_parent(phandle.node)));
  838. return NULL;
  839. }
  840. debug("Found internal MDIO bus %p\n", mdiodev);
  841. return mdiodev;
  842. }
  843. static int fm_eth_probe(struct udevice *dev)
  844. {
  845. struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
  846. struct ofnode_phandle_args args;
  847. void *reg;
  848. int ret, index;
  849. debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
  850. (dev) ? dev->name : "-");
  851. if (fm_eth->dev) {
  852. printf("%s already probed, exit\n", (dev) ? dev->name : "-");
  853. return 0;
  854. }
  855. fm_eth->dev = dev;
  856. fm_eth->fm_index = fman_id(dev->parent);
  857. reg = (void *)(uintptr_t)dev_read_addr(dev);
  858. fm_eth->mac_type = dev_get_driver_data(dev);
  859. #ifdef CONFIG_PHYLIB
  860. fm_eth->enet_if = fman_read_sys_if(dev);
  861. #else
  862. fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
  863. printf("%s: warning - unable to determine interface type\n", __func__);
  864. #endif
  865. switch (fm_eth->mac_type) {
  866. #ifndef CONFIG_SYS_FMAN_V3
  867. case FM_TGEC:
  868. fm_eth->type = FM_ETH_10G_E;
  869. break;
  870. case FM_DTSEC:
  871. #else
  872. case FM_MEMAC:
  873. /* default to 1G, 10G is indicated by port property in dts */
  874. #endif
  875. fm_eth->type = FM_ETH_1G_E;
  876. break;
  877. }
  878. if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
  879. printf("FMan MAC node property cell-index missing\n");
  880. return -EINVAL;
  881. }
  882. if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
  883. 0, 0, &args))
  884. goto ports_ref_failure;
  885. index = ofnode_read_u32_default(args.node, "cell-index", 0);
  886. if (index <= 0)
  887. goto ports_ref_failure;
  888. fm_eth->rx_port = fman_port(dev->parent, index);
  889. if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
  890. fm_eth->type = FM_ETH_10G_E;
  891. if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
  892. 0, 1, &args))
  893. goto ports_ref_failure;
  894. index = ofnode_read_u32_default(args.node, "cell-index", 0);
  895. if (index <= 0)
  896. goto ports_ref_failure;
  897. fm_eth->tx_port = fman_port(dev->parent, index);
  898. /* set the ethernet max receive length */
  899. fm_eth->max_rx_len = MAX_RXBUF_LEN;
  900. switch (fm_eth->enet_if) {
  901. case PHY_INTERFACE_MODE_QSGMII:
  902. /* all PCS blocks are accessed on one controller */
  903. if (fm_eth->num != 0)
  904. break;
  905. case PHY_INTERFACE_MODE_SGMII:
  906. case PHY_INTERFACE_MODE_SGMII_2500:
  907. fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
  908. break;
  909. default:
  910. break;
  911. }
  912. /* init global mac structure */
  913. ret = fm_eth_init_mac(fm_eth, reg);
  914. if (ret)
  915. return ret;
  916. /* startup the FM im */
  917. ret = fm_eth_startup(fm_eth);
  918. if (!ret)
  919. ret = init_phy(fm_eth);
  920. return ret;
  921. ports_ref_failure:
  922. printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
  923. return -ENOENT;
  924. }
  925. static int fm_eth_remove(struct udevice *dev)
  926. {
  927. return 0;
  928. }
  929. static const struct eth_ops fm_eth_ops = {
  930. .start = fm_eth_open,
  931. .send = fm_eth_send,
  932. .recv = fm_eth_recv,
  933. .free_pkt = fm_eth_free_pkt,
  934. .stop = fm_eth_halt,
  935. };
  936. static const struct udevice_id fm_eth_ids[] = {
  937. #ifdef CONFIG_SYS_FMAN_V3
  938. { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
  939. #else
  940. { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
  941. { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
  942. #endif
  943. {}
  944. };
  945. U_BOOT_DRIVER(eth_fman) = {
  946. .name = "eth_fman",
  947. .id = UCLASS_ETH,
  948. .of_match = fm_eth_ids,
  949. .bind = fm_eth_bind,
  950. .probe = fm_eth_probe,
  951. .remove = fm_eth_remove,
  952. .ops = &fm_eth_ops,
  953. .priv_auto_alloc_size = sizeof(struct fm_eth),
  954. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  955. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  956. };
  957. #endif /* CONFIG_DM_ETH */