fm.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <malloc.h>
  9. #include <asm/io.h>
  10. #include <linux/errno.h>
  11. #include <u-boot/crc.h>
  12. #ifdef CONFIG_DM_ETH
  13. #include <dm.h>
  14. #endif
  15. #include "fm.h"
  16. #include <fsl_qe.h> /* For struct qe_firmware */
  17. #include <nand.h>
  18. #include <spi_flash.h>
  19. #include <mmc.h>
  20. #ifdef CONFIG_ARM64
  21. #include <asm/armv8/mmu.h>
  22. #include <asm/arch/cpu.h>
  23. #endif
  24. struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
  25. void *fm_muram_base(int fm_idx)
  26. {
  27. return muram[fm_idx].base;
  28. }
  29. void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
  30. {
  31. void *ret;
  32. ulong align_mask;
  33. size_t off;
  34. void *save;
  35. align_mask = align - 1;
  36. save = muram[fm_idx].alloc;
  37. off = (ulong)save & align_mask;
  38. if (off != 0)
  39. muram[fm_idx].alloc += (align - off);
  40. off = size & align_mask;
  41. if (off != 0)
  42. size += (align - off);
  43. if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
  44. muram[fm_idx].alloc = save;
  45. printf("%s: run out of ram.\n", __func__);
  46. return NULL;
  47. }
  48. ret = muram[fm_idx].alloc;
  49. muram[fm_idx].alloc += size;
  50. memset((void *)ret, 0, size);
  51. return ret;
  52. }
  53. static void fm_init_muram(int fm_idx, void *reg)
  54. {
  55. void *base = reg;
  56. muram[fm_idx].base = base;
  57. muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
  58. muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
  59. muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
  60. }
  61. /*
  62. * fm_upload_ucode - Fman microcode upload worker function
  63. *
  64. * This function does the actual uploading of an Fman microcode
  65. * to an Fman.
  66. */
  67. static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
  68. u32 *ucode, unsigned int size)
  69. {
  70. unsigned int i;
  71. unsigned int timeout = 1000000;
  72. /* enable address auto increase */
  73. out_be32(&imem->iadd, IRAM_IADD_AIE);
  74. /* write microcode to IRAM */
  75. for (i = 0; i < size / 4; i++)
  76. out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
  77. /* verify if the writing is over */
  78. out_be32(&imem->iadd, 0);
  79. while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
  80. ;
  81. if (!timeout)
  82. printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
  83. /* enable microcode from IRAM */
  84. out_be32(&imem->iready, IRAM_READY);
  85. }
  86. /*
  87. * Upload an Fman firmware
  88. *
  89. * This function is similar to qe_upload_firmware(), exception that it uploads
  90. * a microcode to the Fman instead of the QE.
  91. *
  92. * Because the process for uploading a microcode to the Fman is similar for
  93. * that of the QE, the QE firmware binary format is used for Fman microcode.
  94. * It should be possible to unify these two functions, but for now we keep them
  95. * separate.
  96. */
  97. static int fman_upload_firmware(int fm_idx,
  98. struct fm_imem *fm_imem,
  99. const struct qe_firmware *firmware)
  100. {
  101. unsigned int i;
  102. u32 crc;
  103. size_t calc_size = sizeof(struct qe_firmware);
  104. size_t length;
  105. const struct qe_header *hdr;
  106. if (!firmware) {
  107. printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
  108. return -EINVAL;
  109. }
  110. hdr = &firmware->header;
  111. length = be32_to_cpu(hdr->length);
  112. /* Check the magic */
  113. if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
  114. (hdr->magic[2] != 'F')) {
  115. printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
  116. firmware);
  117. return -EPERM;
  118. }
  119. /* Check the version */
  120. if (hdr->version != 1) {
  121. printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
  122. hdr->version);
  123. return -EPERM;
  124. }
  125. /* Validate some of the fields */
  126. if ((firmware->count != 1)) {
  127. printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
  128. return -EINVAL;
  129. }
  130. /* Validate the length and check if there's a CRC */
  131. calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
  132. for (i = 0; i < firmware->count; i++)
  133. /*
  134. * For situations where the second RISC uses the same microcode
  135. * as the first, the 'code_offset' and 'count' fields will be
  136. * zero, so it's okay to add those.
  137. */
  138. calc_size += sizeof(u32) *
  139. be32_to_cpu(firmware->microcode[i].count);
  140. /* Validate the length */
  141. if (length != calc_size + sizeof(u32)) {
  142. printf("Fman%u: Invalid length in firmware header\n",
  143. fm_idx + 1);
  144. return -EPERM;
  145. }
  146. /*
  147. * Validate the CRC. We would normally call crc32_no_comp(), but that
  148. * function isn't available unless you turn on JFFS support.
  149. */
  150. crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
  151. if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
  152. printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
  153. return -EIO;
  154. }
  155. /* Loop through each microcode. */
  156. for (i = 0; i < firmware->count; i++) {
  157. const struct qe_microcode *ucode = &firmware->microcode[i];
  158. /* Upload a microcode if it's present */
  159. if (be32_to_cpu(ucode->code_offset)) {
  160. u32 ucode_size;
  161. u32 *code;
  162. printf("Fman%u: Uploading microcode version %u.%u.%u\n",
  163. fm_idx + 1, ucode->major, ucode->minor,
  164. ucode->revision);
  165. code = (void *)firmware +
  166. be32_to_cpu(ucode->code_offset);
  167. ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
  168. fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
  169. }
  170. }
  171. return 0;
  172. }
  173. static u32 fm_assign_risc(int port_id)
  174. {
  175. u32 risc_sel, val;
  176. risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
  177. val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
  178. val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
  179. return val;
  180. }
  181. static void fm_init_fpm(struct fm_fpm *fpm)
  182. {
  183. int i, port_id;
  184. u32 val;
  185. setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
  186. FMFPEE_CER | FMFPEE_DER);
  187. /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
  188. /* offline/parser port */
  189. for (i = 0; i < MAX_NUM_OH_PORT; i++) {
  190. port_id = OH_PORT_ID_BASE + i;
  191. val = fm_assign_risc(port_id);
  192. out_be32(&fpm->fpmprc, val);
  193. }
  194. /* Rx 1G port */
  195. for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
  196. port_id = RX_PORT_1G_BASE + i;
  197. val = fm_assign_risc(port_id);
  198. out_be32(&fpm->fpmprc, val);
  199. }
  200. /* Tx 1G port */
  201. for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
  202. port_id = TX_PORT_1G_BASE + i;
  203. val = fm_assign_risc(port_id);
  204. out_be32(&fpm->fpmprc, val);
  205. }
  206. /* Rx 10G port */
  207. port_id = RX_PORT_10G_BASE;
  208. val = fm_assign_risc(port_id);
  209. out_be32(&fpm->fpmprc, val);
  210. /* Tx 10G port */
  211. port_id = TX_PORT_10G_BASE;
  212. val = fm_assign_risc(port_id);
  213. out_be32(&fpm->fpmprc, val);
  214. /* disable the dispatch limit in IM case */
  215. out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
  216. /* clear events */
  217. out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
  218. /* clear risc events */
  219. for (i = 0; i < 4; i++)
  220. out_be32(&fpm->fpmcev[i], 0xffffffff);
  221. /* clear error */
  222. out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
  223. }
  224. static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
  225. {
  226. int blk, i, port_id;
  227. u32 val;
  228. size_t offset;
  229. void *base;
  230. /* alloc free buffer pool in MURAM */
  231. base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
  232. if (!base) {
  233. printf("%s: no muram for free buffer pool\n", __func__);
  234. return -ENOMEM;
  235. }
  236. offset = base - fm_muram_base(fm_idx);
  237. /* Need 128KB total free buffer pool size */
  238. val = offset / 256;
  239. blk = FM_FREE_POOL_SIZE / 256;
  240. /* in IM, we must not begin from offset 0 in MURAM */
  241. val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
  242. out_be32(&bmi->fmbm_cfg1, val);
  243. /* disable all BMI interrupt */
  244. out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
  245. /* clear all events */
  246. out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
  247. /*
  248. * set port parameters - FMBM_PP_x
  249. * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
  250. * max dma 10G Rx/Tx=3, others is 1
  251. * set port FIFO size - FMBM_PFS_x
  252. * 4KB for all Rx and Tx ports
  253. */
  254. /* offline/parser port */
  255. for (i = 0; i < MAX_NUM_OH_PORT; i++) {
  256. port_id = OH_PORT_ID_BASE + i - 1;
  257. /* max tasks=1, max dma=1, no extra */
  258. out_be32(&bmi->fmbm_pp[port_id], 0);
  259. /* port FIFO size - 256 bytes, no extra */
  260. out_be32(&bmi->fmbm_pfs[port_id], 0);
  261. }
  262. /* Rx 1G port */
  263. for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
  264. port_id = RX_PORT_1G_BASE + i - 1;
  265. /* max tasks=4, max dma=1, no extra */
  266. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
  267. /* FIFO size - 4KB, no extra */
  268. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  269. }
  270. /* Tx 1G port FIFO size - 4KB, no extra */
  271. for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
  272. port_id = TX_PORT_1G_BASE + i - 1;
  273. /* max tasks=4, max dma=1, no extra */
  274. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
  275. /* FIFO size - 4KB, no extra */
  276. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  277. }
  278. /* Rx 10G port */
  279. port_id = RX_PORT_10G_BASE - 1;
  280. /* max tasks=12, max dma=3, no extra */
  281. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
  282. /* FIFO size - 4KB, no extra */
  283. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  284. /* Tx 10G port */
  285. port_id = TX_PORT_10G_BASE - 1;
  286. /* max tasks=12, max dma=3, no extra */
  287. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
  288. /* FIFO size - 4KB, no extra */
  289. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  290. /* initialize internal buffers data base (linked list) */
  291. out_be32(&bmi->fmbm_init, FMBM_INIT_START);
  292. return 0;
  293. }
  294. static void fm_init_qmi(struct fm_qmi_common *qmi)
  295. {
  296. /* disable all error interrupts */
  297. out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
  298. /* clear all error events */
  299. out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
  300. /* disable all interrupts */
  301. out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
  302. /* clear all interrupts */
  303. out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
  304. }
  305. /* Init common part of FM, index is fm num# like fm as above */
  306. #ifdef CONFIG_TFABOOT
  307. int fm_init_common(int index, struct ccsr_fman *reg)
  308. {
  309. int rc;
  310. void *addr = NULL;
  311. enum boot_src src = get_boot_src();
  312. if (src == BOOT_SOURCE_IFC_NOR) {
  313. addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
  314. CONFIG_SYS_FSL_IFC_BASE);
  315. #ifdef CONFIG_CMD_NAND
  316. } else if (src == BOOT_SOURCE_IFC_NAND) {
  317. size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
  318. addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  319. rc = nand_read(get_nand_dev_by_index(0),
  320. (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
  321. &fw_length, (u_char *)addr);
  322. if (rc == -EUCLEAN) {
  323. printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
  324. CONFIG_SYS_FMAN_FW_ADDR, rc);
  325. }
  326. #endif
  327. } else if (src == BOOT_SOURCE_QSPI_NOR) {
  328. struct spi_flash *ucode_flash;
  329. addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  330. int ret = 0;
  331. #ifdef CONFIG_DM_SPI_FLASH
  332. struct udevice *new;
  333. /* speed and mode will be read from DT */
  334. ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
  335. CONFIG_ENV_SPI_CS, 0, 0, &new);
  336. ucode_flash = dev_get_uclass_priv(new);
  337. #else
  338. ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
  339. CONFIG_ENV_SPI_CS,
  340. CONFIG_ENV_SPI_MAX_HZ,
  341. CONFIG_ENV_SPI_MODE);
  342. #endif
  343. if (!ucode_flash) {
  344. printf("SF: probe for ucode failed\n");
  345. } else {
  346. ret = spi_flash_read(ucode_flash,
  347. CONFIG_SYS_FMAN_FW_ADDR +
  348. CONFIG_SYS_FSL_QSPI_BASE,
  349. CONFIG_SYS_QE_FMAN_FW_LENGTH,
  350. addr);
  351. if (ret)
  352. printf("SF: read for ucode failed\n");
  353. spi_flash_free(ucode_flash);
  354. }
  355. } else if (src == BOOT_SOURCE_SD_MMC) {
  356. int dev = CONFIG_SYS_MMC_ENV_DEV;
  357. addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  358. u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
  359. u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
  360. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  361. if (!mmc) {
  362. printf("\nMMC cannot find device for ucode\n");
  363. } else {
  364. printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
  365. dev, blk, cnt);
  366. mmc_init(mmc);
  367. (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
  368. addr);
  369. }
  370. } else {
  371. addr = NULL;
  372. }
  373. /* Upload the Fman microcode if it's present */
  374. rc = fman_upload_firmware(index, &reg->fm_imem, addr);
  375. if (rc)
  376. return rc;
  377. env_set_addr("fman_ucode", addr);
  378. fm_init_muram(index, &reg->muram);
  379. fm_init_qmi(&reg->fm_qmi_common);
  380. fm_init_fpm(&reg->fm_fpm);
  381. /* clear DMA status */
  382. setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
  383. /* set DMA mode */
  384. setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
  385. return fm_init_bmi(index, &reg->fm_bmi_common);
  386. }
  387. #else
  388. int fm_init_common(int index, struct ccsr_fman *reg)
  389. {
  390. int rc;
  391. #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
  392. void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
  393. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
  394. size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
  395. void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  396. rc = nand_read(get_nand_dev_by_index(0),
  397. (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
  398. &fw_length, (u_char *)addr);
  399. if (rc == -EUCLEAN) {
  400. printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
  401. CONFIG_SYS_FMAN_FW_ADDR, rc);
  402. }
  403. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
  404. struct spi_flash *ucode_flash;
  405. void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  406. int ret = 0;
  407. #ifdef CONFIG_DM_SPI_FLASH
  408. struct udevice *new;
  409. /* speed and mode will be read from DT */
  410. ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  411. 0, 0, &new);
  412. ucode_flash = dev_get_uclass_priv(new);
  413. #else
  414. ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  415. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  416. #endif
  417. if (!ucode_flash)
  418. printf("SF: probe for ucode failed\n");
  419. else {
  420. ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
  421. CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
  422. if (ret)
  423. printf("SF: read for ucode failed\n");
  424. spi_flash_free(ucode_flash);
  425. }
  426. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
  427. int dev = CONFIG_SYS_MMC_ENV_DEV;
  428. void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  429. u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
  430. u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
  431. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  432. if (!mmc)
  433. printf("\nMMC cannot find device for ucode\n");
  434. else {
  435. printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
  436. dev, blk, cnt);
  437. mmc_init(mmc);
  438. (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
  439. addr);
  440. }
  441. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
  442. void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
  443. #else
  444. void *addr = NULL;
  445. #endif
  446. /* Upload the Fman microcode if it's present */
  447. rc = fman_upload_firmware(index, &reg->fm_imem, addr);
  448. if (rc)
  449. return rc;
  450. env_set_addr("fman_ucode", addr);
  451. fm_init_muram(index, &reg->muram);
  452. fm_init_qmi(&reg->fm_qmi_common);
  453. fm_init_fpm(&reg->fm_fpm);
  454. /* clear DMA status */
  455. setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
  456. /* set DMA mode */
  457. setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
  458. return fm_init_bmi(index, &reg->fm_bmi_common);
  459. }
  460. #endif
  461. #ifdef CONFIG_DM_ETH
  462. struct fman_priv {
  463. struct ccsr_fman *reg;
  464. unsigned int fman_id;
  465. };
  466. static const struct udevice_id fman_ids[] = {
  467. { .compatible = "fsl,fman" },
  468. {}
  469. };
  470. static int fman_probe(struct udevice *dev)
  471. {
  472. struct fman_priv *priv = dev_get_priv(dev);
  473. priv->reg = (struct ccsr_fman *)(uintptr_t)dev_read_addr(dev);
  474. if (dev_read_u32(dev, "cell-index", &priv->fman_id)) {
  475. printf("FMan node property cell-index missing\n");
  476. return -EINVAL;
  477. }
  478. return fm_init_common(priv->fman_id, priv->reg);
  479. }
  480. static int fman_remove(struct udevice *dev)
  481. {
  482. return 0;
  483. }
  484. int fman_id(struct udevice *dev)
  485. {
  486. struct fman_priv *priv = dev_get_priv(dev);
  487. return priv->fman_id;
  488. }
  489. void *fman_port(struct udevice *dev, int num)
  490. {
  491. struct fman_priv *priv = dev_get_priv(dev);
  492. return &priv->reg->port[num - 1].fm_bmi;
  493. }
  494. void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num)
  495. {
  496. struct fman_priv *priv = dev_get_priv(dev);
  497. void *res = NULL;
  498. switch (type) {
  499. #ifdef CONFIG_SYS_FMAN_V3
  500. case FM_MEMAC:
  501. res = &priv->reg->memac[num].fm_memac_mdio;
  502. break;
  503. #else
  504. case FM_DTSEC:
  505. res = &priv->reg->mac_1g[num].fm_mdio.miimcfg;
  506. break;
  507. case FM_TGEC:
  508. res = &priv->reg->mac_10g[num].fm_10gec_mdio;
  509. break;
  510. #endif
  511. }
  512. return res;
  513. }
  514. U_BOOT_DRIVER(fman) = {
  515. .name = "fman",
  516. .id = UCLASS_SIMPLE_BUS,
  517. .of_match = fman_ids,
  518. .probe = fman_probe,
  519. .remove = fman_remove,
  520. .priv_auto_alloc_size = sizeof(struct fman_priv),
  521. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  522. };
  523. #endif /* CONFIG_DM_ETH */