fsl-ls1028a.dtsi 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP ls1028a SOC common device tree source
  4. *
  5. * Copyright 2019 NXP
  6. *
  7. */
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. / {
  10. compatible = "fsl,ls1028a";
  11. interrupt-parent = <&gic>;
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. sysclk: sysclk {
  15. compatible = "fixed-clock";
  16. #clock-cells = <0>;
  17. clock-frequency = <100000000>;
  18. clock-output-names = "sysclk";
  19. };
  20. clockgen: clocking@1300000 {
  21. compatible = "fsl,ls1028a-clockgen";
  22. reg = <0x0 0x1300000 0x0 0xa0000>;
  23. #clock-cells = <2>;
  24. clocks = <&sysclk>;
  25. };
  26. memory@01080000 {
  27. device_type = "memory";
  28. reg = <0x00000000 0x01080000 0 0x80000000>;
  29. /* DRAM space - 1, size : 2 GB DRAM */
  30. };
  31. gic: interrupt-controller@6000000 {
  32. compatible = "arm,gic-v3";
  33. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  34. <0x0 0x06040000 0 0x40000>;
  35. #interrupt-cells = <3>;
  36. interrupt-controller;
  37. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
  38. IRQ_TYPE_LEVEL_LOW)>;
  39. };
  40. timer {
  41. compatible = "arm,armv8-timer";
  42. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  43. IRQ_TYPE_LEVEL_LOW)>,
  44. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  45. IRQ_TYPE_LEVEL_LOW)>,
  46. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  47. IRQ_TYPE_LEVEL_LOW)>,
  48. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  49. IRQ_TYPE_LEVEL_LOW)>;
  50. };
  51. fspi: flexspi@20c0000 {
  52. compatible = "nxp,lx2160a-fspi";
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. reg = <0x0 0x20c0000 0x0 0x10000>,
  56. <0x0 0x20000000 0x0 0x10000000>;
  57. reg-names = "fspi_base", "fspi_mmap";
  58. clocks = <&clockgen 4 3>, <&clockgen 4 3>;
  59. clock-names = "fspi_en", "fspi";
  60. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  61. status = "disabled";
  62. };
  63. serial0: serial@21c0500 {
  64. device_type = "serial";
  65. compatible = "fsl,ns16550", "ns16550a";
  66. reg = <0x0 0x21c0500 0x0 0x100>;
  67. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  68. status = "disabled";
  69. };
  70. serial1: serial@21c0600 {
  71. device_type = "serial";
  72. compatible = "fsl,ns16550", "ns16550a";
  73. reg = <0x0 0x21c0600 0x0 0x100>;
  74. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  75. status = "disabled";
  76. };
  77. pcie@3400000 {
  78. compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  79. reg = <0x00 0x03400000 0x0 0x80000
  80. 0x00 0x03480000 0x0 0x40000 /* lut registers */
  81. 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
  82. 0x80 0x00000000 0x0 0x20000>; /* configuration space */
  83. reg-names = "dbi", "lut", "ctrl", "config";
  84. #address-cells = <3>;
  85. #size-cells = <2>;
  86. device_type = "pci";
  87. num-lanes = <4>;
  88. bus-range = <0x0 0xff>;
  89. ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
  90. 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  91. };
  92. pcie@3500000 {
  93. compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  94. reg = <0x00 0x03500000 0x0 0x80000
  95. 0x00 0x03580000 0x0 0x40000 /* lut registers */
  96. 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
  97. 0x88 0x00000000 0x0 0x20000>; /* configuration space */
  98. reg-names = "dbi", "lut", "ctrl", "config";
  99. #address-cells = <3>;
  100. #size-cells = <2>;
  101. device_type = "pci";
  102. num-lanes = <4>;
  103. bus-range = <0x0 0xff>;
  104. ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
  105. 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  106. };
  107. pcie@1f0000000 {
  108. compatible = "pci-host-ecam-generic";
  109. /* ECAM bus 0, HW has more space reserved but not populated */
  110. bus-range = <0x0 0x0>;
  111. reg = <0x01 0xf0000000 0x0 0x100000>;
  112. #address-cells = <3>;
  113. #size-cells = <2>;
  114. device_type = "pci";
  115. ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
  116. enetc0: pci@0,0 {
  117. reg = <0x000000 0 0 0 0>;
  118. status = "disabled";
  119. };
  120. enetc1: pci@0,1 {
  121. reg = <0x000100 0 0 0 0>;
  122. status = "disabled";
  123. };
  124. enetc2: pci@0,2 {
  125. reg = <0x000200 0 0 0 0>;
  126. status = "okay";
  127. phy-mode = "internal";
  128. };
  129. mdio0: pci@0,3 {
  130. #address-cells=<0>;
  131. #size-cells=<1>;
  132. reg = <0x000300 0 0 0 0>;
  133. status = "disabled";
  134. };
  135. enetc6: pci@0,6 {
  136. reg = <0x000600 0 0 0 0>;
  137. status = "okay";
  138. phy-mode = "internal";
  139. };
  140. };
  141. i2c0: i2c@2000000 {
  142. compatible = "fsl,vf610-i2c";
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. reg = <0x0 0x2000000 0x0 0x10000>;
  146. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  147. clock-names = "i2c";
  148. clocks = <&clockgen 4 0>;
  149. status = "disabled";
  150. };
  151. i2c1: i2c@2010000 {
  152. compatible = "fsl,vf610-i2c";
  153. #address-cells = <1>;
  154. #size-cells = <0>;
  155. reg = <0x0 0x2010000 0x0 0x10000>;
  156. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  157. clock-names = "i2c";
  158. clocks = <&clockgen 4 0>;
  159. status = "disabled";
  160. };
  161. i2c2: i2c@2020000 {
  162. compatible = "fsl,vf610-i2c";
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. reg = <0x0 0x2020000 0x0 0x10000>;
  166. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  167. clock-names = "i2c";
  168. clocks = <&clockgen 4 0>;
  169. status = "disabled";
  170. };
  171. i2c3: i2c@2030000 {
  172. compatible = "fsl,vf610-i2c";
  173. #address-cells = <1>;
  174. #size-cells = <0>;
  175. reg = <0x0 0x2030000 0x0 0x10000>;
  176. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  177. clock-names = "i2c";
  178. clocks = <&clockgen 4 0>;
  179. status = "disabled";
  180. };
  181. i2c4: i2c@2040000 {
  182. compatible = "fsl,vf610-i2c";
  183. #address-cells = <1>;
  184. #size-cells = <0>;
  185. reg = <0x0 0x2040000 0x0 0x10000>;
  186. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  187. clock-names = "i2c";
  188. clocks = <&clockgen 4 0>;
  189. status = "disabled";
  190. };
  191. i2c5: i2c@2050000 {
  192. compatible = "fsl,vf610-i2c";
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. reg = <0x0 0x2050000 0x0 0x10000>;
  196. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  197. clock-names = "i2c";
  198. clocks = <&clockgen 4 0>;
  199. status = "disabled";
  200. };
  201. i2c6: i2c@2060000 {
  202. compatible = "fsl,vf610-i2c";
  203. #address-cells = <1>;
  204. #size-cells = <0>;
  205. reg = <0x0 0x2060000 0x0 0x10000>;
  206. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  207. clock-names = "i2c";
  208. clocks = <&clockgen 4 0>;
  209. status = "disabled";
  210. };
  211. i2c7: i2c@2070000 {
  212. compatible = "fsl,vf610-i2c";
  213. #address-cells = <1>;
  214. #size-cells = <0>;
  215. reg = <0x0 0x2070000 0x0 0x10000>;
  216. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  217. clock-names = "i2c";
  218. clocks = <&clockgen 4 0>;
  219. status = "disabled";
  220. };
  221. lpuart0: serial@2260000 {
  222. compatible = "fsl,ls1021a-lpuart";
  223. reg = <0x0 0x2260000 0x0 0x1000>;
  224. interrupts = <0 232 0x4>;
  225. clocks = <&sysclk>;
  226. clock-names = "ipg";
  227. little-endian;
  228. status = "disabled";
  229. };
  230. lpuart1: serial@2270000 {
  231. compatible = "fsl,ls1021a-lpuart";
  232. reg = <0x0 0x2270000 0x0 0x1000>;
  233. interrupts = <0 233 0x4>;
  234. clocks = <&sysclk>;
  235. clock-names = "ipg";
  236. little-endian;
  237. status = "disabled";
  238. };
  239. lpuart2: serial@2280000 {
  240. compatible = "fsl,ls1021a-lpuart";
  241. reg = <0x0 0x2280000 0x0 0x1000>;
  242. interrupts = <0 234 0x4>;
  243. clocks = <&sysclk>;
  244. clock-names = "ipg";
  245. little-endian;
  246. status = "disabled";
  247. };
  248. lpuart3: serial@2290000 {
  249. compatible = "fsl,ls1021a-lpuart";
  250. reg = <0x0 0x2290000 0x0 0x1000>;
  251. interrupts = <0 235 0x4>;
  252. clocks = <&sysclk>;
  253. clock-names = "ipg";
  254. little-endian;
  255. status = "disabled";
  256. };
  257. lpuart4: serial@22a0000 {
  258. compatible = "fsl,ls1021a-lpuart";
  259. reg = <0x0 0x22a0000 0x0 0x1000>;
  260. interrupts = <0 236 0x4>;
  261. clocks = <&sysclk>;
  262. clock-names = "ipg";
  263. little-endian;
  264. status = "disabled";
  265. };
  266. lpuart5: serial@22b0000 {
  267. compatible = "fsl,ls1021a-lpuart";
  268. reg = <0x0 0x22b0000 0x0 0x1000>;
  269. interrupts = <0 237 0x4>;
  270. clocks = <&sysclk>;
  271. clock-names = "ipg";
  272. little-endian;
  273. status = "disabled";
  274. };
  275. usb1: usb3@3100000 {
  276. compatible = "fsl,layerscape-dwc3";
  277. reg = <0x0 0x3100000 0x0 0x10000>;
  278. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  279. dr_mode = "host";
  280. status = "disabled";
  281. };
  282. usb2: usb3@3110000 {
  283. compatible = "fsl,layerscape-dwc3";
  284. reg = <0x0 0x3110000 0x0 0x10000>;
  285. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  286. dr_mode = "host";
  287. status = "disabled";
  288. };
  289. dspi0: dspi@2100000 {
  290. compatible = "fsl,vf610-dspi";
  291. #address-cells = <1>;
  292. #size-cells = <0>;
  293. reg = <0x0 0x2100000 0x0 0x10000>;
  294. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  295. clock-names = "dspi";
  296. clocks = <&clockgen 4 0>;
  297. num-cs = <5>;
  298. litte-endian;
  299. status = "disabled";
  300. };
  301. dspi1: dspi@2110000 {
  302. compatible = "fsl,vf610-dspi";
  303. #address-cells = <1>;
  304. #size-cells = <0>;
  305. reg = <0x0 0x2110000 0x0 0x10000>;
  306. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  307. clock-names = "dspi";
  308. clocks = <&clockgen 4 0>;
  309. num-cs = <5>;
  310. little-endian;
  311. status = "disabled";
  312. };
  313. dspi2: dspi@2120000 {
  314. compatible = "fsl,vf610-dspi";
  315. #address-cells = <1>;
  316. #size-cells = <0>;
  317. reg = <0x0 0x2120000 0x0 0x10000>;
  318. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  319. clock-names = "dspi";
  320. clocks = <&clockgen 4 0>;
  321. num-cs = <5>;
  322. little-endian;
  323. status = "disabled";
  324. };
  325. esdhc0: esdhc@2140000 {
  326. compatible = "fsl,esdhc";
  327. reg = <0x0 0x2140000 0x0 0x10000>;
  328. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  329. big-endian;
  330. bus-width = <4>;
  331. status = "disabled";
  332. };
  333. esdhc1: esdhc@2150000 {
  334. compatible = "fsl,esdhc";
  335. reg = <0x0 0x2150000 0x0 0x10000>;
  336. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  337. big-endian;
  338. non-removable;
  339. bus-width = <4>;
  340. status = "disabled";
  341. };
  342. sata: sata@3200000 {
  343. compatible = "fsl,ls1028a-ahci";
  344. reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
  345. 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
  346. reg-names = "sata-base", "ecc-addr";
  347. interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  348. status = "disabled";
  349. };
  350. cluster1_core0_watchdog: wdt@c000000 {
  351. compatible = "arm,sp805-wdt";
  352. reg = <0x0 0xc000000 0x0 0x1000>;
  353. };
  354. };