Kconfig 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612
  1. config ARCH_LS1012A
  2. bool
  3. select ARMV8_SET_SMPEN
  4. select ARM_ERRATA_855873 if !TFABOOT
  5. select FSL_LAYERSCAPE
  6. select FSL_LSCH2
  7. select SYS_FSL_SRDS_1
  8. select SYS_HAS_SERDES
  9. select SYS_FSL_DDR_BE
  10. select SYS_FSL_MMDC
  11. select SYS_FSL_ERRATUM_A010315
  12. select SYS_FSL_ERRATUM_A009798
  13. select SYS_FSL_ERRATUM_A008997
  14. select SYS_FSL_ERRATUM_A009007
  15. select SYS_FSL_ERRATUM_A009008
  16. select ARCH_EARLY_INIT_R
  17. select BOARD_EARLY_INIT_F
  18. select SYS_I2C_MXC
  19. select SYS_I2C_MXC_I2C1 if !DM_I2C
  20. select SYS_I2C_MXC_I2C2 if !DM_I2C
  21. imply PANIC_HANG
  22. config ARCH_LS1028A
  23. bool
  24. select ARMV8_SET_SMPEN
  25. select FSL_LSCH3
  26. select NXP_LSCH3_2
  27. select SYS_FSL_HAS_CCI400
  28. select SYS_FSL_SRDS_1
  29. select SYS_HAS_SERDES
  30. select SYS_FSL_DDR
  31. select SYS_FSL_DDR_LE
  32. select SYS_FSL_DDR_VER_50
  33. select SYS_FSL_HAS_DDR3
  34. select SYS_FSL_HAS_DDR4
  35. select SYS_FSL_HAS_SEC
  36. select SYS_FSL_SEC_COMPAT_5
  37. select SYS_FSL_SEC_LE
  38. select FSL_TZASC_1
  39. select ARCH_EARLY_INIT_R
  40. select BOARD_EARLY_INIT_F
  41. select SYS_I2C_MXC
  42. select SYS_FSL_ERRATUM_A008997
  43. select SYS_FSL_ERRATUM_A009007
  44. select SYS_FSL_ERRATUM_A008514 if !TFABOOT
  45. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  46. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  47. select SYS_FSL_ERRATUM_A050382
  48. select RESV_RAM if GIC_V3_ITS
  49. imply PANIC_HANG
  50. config ARCH_LS1043A
  51. bool
  52. select ARMV8_SET_SMPEN
  53. select ARM_ERRATA_855873 if !TFABOOT
  54. select FSL_LAYERSCAPE
  55. select FSL_LSCH2
  56. select SYS_FSL_SRDS_1
  57. select SYS_HAS_SERDES
  58. select SYS_FSL_DDR
  59. select SYS_FSL_DDR_BE
  60. select SYS_FSL_DDR_VER_50
  61. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  62. select SYS_FSL_ERRATUM_A008997
  63. select SYS_FSL_ERRATUM_A009007
  64. select SYS_FSL_ERRATUM_A009008
  65. select SYS_FSL_ERRATUM_A009660 if !TFABOOT
  66. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  67. select SYS_FSL_ERRATUM_A009798
  68. select SYS_FSL_ERRATUM_A009929
  69. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  70. select SYS_FSL_ERRATUM_A010315
  71. select SYS_FSL_ERRATUM_A010539
  72. select SYS_FSL_HAS_DDR3
  73. select SYS_FSL_HAS_DDR4
  74. select ARCH_EARLY_INIT_R
  75. select BOARD_EARLY_INIT_F
  76. select SYS_I2C_MXC if !DM_I2C
  77. select SYS_I2C_MXC_I2C1 if !DM_I2C
  78. select SYS_I2C_MXC_I2C2 if !DM_I2C
  79. select SYS_I2C_MXC_I2C3 if !DM_I2C
  80. select SYS_I2C_MXC_I2C4 if !DM_I2C
  81. imply CMD_PCI
  82. config ARCH_LS1046A
  83. bool
  84. select ARMV8_SET_SMPEN
  85. select FSL_LAYERSCAPE
  86. select FSL_LSCH2
  87. select SYS_FSL_SRDS_1
  88. select SYS_HAS_SERDES
  89. select SYS_FSL_DDR
  90. select SYS_FSL_DDR_BE
  91. select SYS_FSL_DDR_VER_50
  92. select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  93. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  94. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  95. select SYS_FSL_ERRATUM_A008997
  96. select SYS_FSL_ERRATUM_A009007
  97. select SYS_FSL_ERRATUM_A009008
  98. select SYS_FSL_ERRATUM_A009798
  99. select SYS_FSL_ERRATUM_A009801
  100. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  101. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  102. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  103. select SYS_FSL_ERRATUM_A010539
  104. select SYS_FSL_HAS_DDR4
  105. select SYS_FSL_SRDS_2
  106. select ARCH_EARLY_INIT_R
  107. select BOARD_EARLY_INIT_F
  108. select SYS_I2C_MXC if !DM_I2C
  109. select SYS_I2C_MXC_I2C1 if !DM_I2C
  110. select SYS_I2C_MXC_I2C2 if !DM_I2C
  111. select SYS_I2C_MXC_I2C3 if !DM_I2C
  112. select SYS_I2C_MXC_I2C4 if !DM_I2C
  113. imply SCSI
  114. imply SCSI_AHCI
  115. config ARCH_LS1088A
  116. bool
  117. select ARMV8_SET_SMPEN
  118. select ARM_ERRATA_855873 if !TFABOOT
  119. select FSL_LAYERSCAPE
  120. select FSL_LSCH3
  121. select SYS_FSL_SRDS_1
  122. select SYS_HAS_SERDES
  123. select SYS_FSL_DDR
  124. select SYS_FSL_DDR_LE
  125. select SYS_FSL_DDR_VER_50
  126. select SYS_FSL_EC1
  127. select SYS_FSL_EC2
  128. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  129. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  130. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  131. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  132. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  133. select SYS_FSL_ERRATUM_A009007
  134. select SYS_FSL_HAS_CCI400
  135. select SYS_FSL_HAS_DDR4
  136. select SYS_FSL_HAS_RGMII
  137. select SYS_FSL_HAS_SEC
  138. select SYS_FSL_SEC_COMPAT_5
  139. select SYS_FSL_SEC_LE
  140. select SYS_FSL_SRDS_1
  141. select SYS_FSL_SRDS_2
  142. select FSL_TZASC_1
  143. select FSL_TZASC_400
  144. select FSL_TZPC_BP147
  145. select ARCH_EARLY_INIT_R
  146. select BOARD_EARLY_INIT_F
  147. select SYS_I2C_MXC
  148. select SYS_I2C_MXC_I2C1 if !TFABOOT
  149. select SYS_I2C_MXC_I2C2 if !TFABOOT
  150. select SYS_I2C_MXC_I2C3 if !TFABOOT
  151. select SYS_I2C_MXC_I2C4 if !TFABOOT
  152. select RESV_RAM if GIC_V3_ITS
  153. imply SCSI
  154. imply PANIC_HANG
  155. config ARCH_LS2080A
  156. bool
  157. select ARMV8_SET_SMPEN
  158. select ARM_ERRATA_826974
  159. select ARM_ERRATA_828024
  160. select ARM_ERRATA_829520
  161. select ARM_ERRATA_833471
  162. select FSL_LAYERSCAPE
  163. select FSL_LSCH3
  164. select SYS_FSL_SRDS_1
  165. select SYS_HAS_SERDES
  166. select SYS_FSL_DDR
  167. select SYS_FSL_DDR_LE
  168. select SYS_FSL_DDR_VER_50
  169. select SYS_FSL_HAS_CCN504
  170. select SYS_FSL_HAS_DP_DDR
  171. select SYS_FSL_HAS_SEC
  172. select SYS_FSL_HAS_DDR4
  173. select SYS_FSL_SEC_COMPAT_5
  174. select SYS_FSL_SEC_LE
  175. select SYS_FSL_SRDS_2
  176. select FSL_TZASC_1
  177. select FSL_TZASC_2
  178. select FSL_TZASC_400
  179. select FSL_TZPC_BP147
  180. select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  181. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  182. select SYS_FSL_ERRATUM_A008514 if !TFABOOT
  183. select SYS_FSL_ERRATUM_A008585
  184. select SYS_FSL_ERRATUM_A008997
  185. select SYS_FSL_ERRATUM_A009007
  186. select SYS_FSL_ERRATUM_A009008
  187. select SYS_FSL_ERRATUM_A009635
  188. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  189. select SYS_FSL_ERRATUM_A009798
  190. select SYS_FSL_ERRATUM_A009801
  191. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  192. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  193. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  194. select SYS_FSL_ERRATUM_A009203
  195. select ARCH_EARLY_INIT_R
  196. select BOARD_EARLY_INIT_F
  197. select SYS_I2C_MXC
  198. select SYS_I2C_MXC_I2C1 if !TFABOOT
  199. select SYS_I2C_MXC_I2C2 if !TFABOOT
  200. select SYS_I2C_MXC_I2C3 if !TFABOOT
  201. select SYS_I2C_MXC_I2C4 if !TFABOOT
  202. select RESV_RAM if GIC_V3_ITS
  203. imply DISTRO_DEFAULTS
  204. imply PANIC_HANG
  205. config ARCH_LX2160A
  206. bool
  207. select ARMV8_SET_SMPEN
  208. select FSL_LSCH3
  209. select NXP_LSCH3_2
  210. select SYS_HAS_SERDES
  211. select SYS_FSL_SRDS_1
  212. select SYS_FSL_SRDS_2
  213. select SYS_NXP_SRDS_3
  214. select SYS_FSL_DDR
  215. select SYS_FSL_DDR_LE
  216. select SYS_FSL_DDR_VER_50
  217. select SYS_FSL_EC1
  218. select SYS_FSL_EC2
  219. select SYS_FSL_ERRATUM_A050106
  220. select SYS_FSL_HAS_RGMII
  221. select SYS_FSL_HAS_SEC
  222. select SYS_FSL_HAS_CCN508
  223. select SYS_FSL_HAS_DDR4
  224. select SYS_FSL_SEC_COMPAT_5
  225. select SYS_FSL_SEC_LE
  226. select ARCH_EARLY_INIT_R
  227. select BOARD_EARLY_INIT_F
  228. select SYS_I2C_MXC
  229. select RESV_RAM if GIC_V3_ITS
  230. imply DISTRO_DEFAULTS
  231. imply PANIC_HANG
  232. imply SCSI
  233. imply SCSI_AHCI
  234. config FSL_LSCH2
  235. bool
  236. select SYS_FSL_HAS_CCI400
  237. select SYS_FSL_HAS_SEC
  238. select SYS_FSL_SEC_COMPAT_5
  239. select SYS_FSL_SEC_BE
  240. config FSL_LSCH3
  241. select ARCH_MISC_INIT
  242. bool
  243. config NXP_LSCH3_2
  244. bool
  245. menu "Layerscape architecture"
  246. depends on FSL_LSCH2 || FSL_LSCH3
  247. config FSL_LAYERSCAPE
  248. bool
  249. config HAS_FEATURE_GIC64K_ALIGN
  250. bool
  251. default y if ARCH_LS1043A
  252. config HAS_FEATURE_ENHANCED_MSI
  253. bool
  254. default y if ARCH_LS1043A
  255. menu "Layerscape PPA"
  256. config FSL_LS_PPA
  257. bool "FSL Layerscape PPA firmware support"
  258. depends on !ARMV8_PSCI
  259. select ARMV8_SEC_FIRMWARE_SUPPORT
  260. select SEC_FIRMWARE_ARMV8_PSCI
  261. select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
  262. help
  263. The FSL Primary Protected Application (PPA) is a software component
  264. which is loaded during boot stage, and then remains resident in RAM
  265. and runs in the TrustZone after boot.
  266. Say y to enable it.
  267. config SPL_FSL_LS_PPA
  268. bool "FSL Layerscape PPA firmware support for SPL build"
  269. depends on !ARMV8_PSCI
  270. select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  271. select SEC_FIRMWARE_ARMV8_PSCI
  272. select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
  273. help
  274. The FSL Primary Protected Application (PPA) is a software component
  275. which is loaded during boot stage, and then remains resident in RAM
  276. and runs in the TrustZone after boot. This is to load PPA during SPL
  277. stage instead of the RAM version of U-Boot. Once PPA is initialized,
  278. the rest of U-Boot (including RAM version) runs at EL2.
  279. choice
  280. prompt "FSL Layerscape PPA firmware loading-media select"
  281. depends on FSL_LS_PPA
  282. default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
  283. default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
  284. default SYS_LS_PPA_FW_IN_XIP
  285. config SYS_LS_PPA_FW_IN_XIP
  286. bool "XIP"
  287. help
  288. Say Y here if the PPA firmware locate at XIP flash, such
  289. as NOR or QSPI flash.
  290. config SYS_LS_PPA_FW_IN_MMC
  291. bool "eMMC or SD Card"
  292. help
  293. Say Y here if the PPA firmware locate at eMMC/SD card.
  294. config SYS_LS_PPA_FW_IN_NAND
  295. bool "NAND"
  296. help
  297. Say Y here if the PPA firmware locate at NAND flash.
  298. endchoice
  299. config LS_PPA_ESBC_HDR_SIZE
  300. hex "Length of PPA ESBC header"
  301. depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
  302. default 0x2000
  303. help
  304. Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
  305. NAND to memory to validate PPA image.
  306. endmenu
  307. config SYS_FSL_ERRATUM_A008997
  308. bool "Workaround for USB PHY erratum A008997"
  309. config SYS_FSL_ERRATUM_A009007
  310. bool
  311. help
  312. Workaround for USB PHY erratum A009007
  313. config SYS_FSL_ERRATUM_A009008
  314. bool "Workaround for USB PHY erratum A009008"
  315. config SYS_FSL_ERRATUM_A009798
  316. bool "Workaround for USB PHY erratum A009798"
  317. config SYS_FSL_ERRATUM_A050106
  318. bool "Workaround for USB PHY erratum A050106"
  319. help
  320. USB3.0 Receiver needs to enable fixed equalization
  321. for each of PHY instances in an SOC. This is similar
  322. to erratum A-009007, but this one is for LX2160A,
  323. and the register value is different.
  324. config SYS_FSL_ERRATUM_A010315
  325. bool "Workaround for PCIe erratum A010315"
  326. config SYS_FSL_ERRATUM_A010539
  327. bool "Workaround for PIN MUX erratum A010539"
  328. config MAX_CPUS
  329. int "Maximum number of CPUs permitted for Layerscape"
  330. default 2 if ARCH_LS1028A
  331. default 4 if ARCH_LS1043A
  332. default 4 if ARCH_LS1046A
  333. default 16 if ARCH_LS2080A
  334. default 8 if ARCH_LS1088A
  335. default 16 if ARCH_LX2160A
  336. default 1
  337. help
  338. Set this number to the maximum number of possible CPUs in the SoC.
  339. SoCs may have multiple clusters with each cluster may have multiple
  340. ports. If some ports are reserved but higher ports are used for
  341. cores, count the reserved ports. This will allocate enough memory
  342. in spin table to properly handle all cores.
  343. config EMC2305
  344. bool "Fan controller"
  345. help
  346. Enable the EMC2305 fan controller for configuration of fan
  347. speed.
  348. config NXP_ESBC
  349. bool "NXP_ESBC"
  350. help
  351. Enable Freescale Secure Boot feature
  352. config QSPI_AHB_INIT
  353. bool "Init the QSPI AHB bus"
  354. help
  355. The default setting for QSPI AHB bus just support 3bytes addressing.
  356. But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
  357. bus for those flashes to support the full QSPI flash size.
  358. config FSPI_AHB_EN_4BYTE
  359. bool "Enable 4-byte Fast Read command for AHB mode"
  360. default n
  361. help
  362. The default setting for FlexSPI AHB bus just supports 3-byte addressing.
  363. But some FlexSPI flash sizes are up to 64MBytes.
  364. This flag enables fast read command for AHB mode and modifies required
  365. LUT to support full FlexSPI flash.
  366. config SYS_CCI400_OFFSET
  367. hex "Offset for CCI400 base"
  368. depends on SYS_FSL_HAS_CCI400
  369. default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
  370. default 0x180000 if FSL_LSCH2
  371. help
  372. Offset for CCI400 base
  373. CCI400 base addr = CCSRBAR + CCI400_OFFSET
  374. config SYS_FSL_IFC_BANK_COUNT
  375. int "Maximum banks of Integrated flash controller"
  376. depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
  377. default 4 if ARCH_LS1043A
  378. default 4 if ARCH_LS1046A
  379. default 8 if ARCH_LS2080A || ARCH_LS1088A
  380. config SYS_FSL_HAS_CCI400
  381. bool
  382. config SYS_FSL_HAS_CCN504
  383. bool
  384. config SYS_FSL_HAS_CCN508
  385. bool
  386. config SYS_FSL_HAS_DP_DDR
  387. bool
  388. config SYS_FSL_SRDS_1
  389. bool
  390. config SYS_FSL_SRDS_2
  391. bool
  392. config SYS_NXP_SRDS_3
  393. bool
  394. config SYS_HAS_SERDES
  395. bool
  396. config FSL_TZASC_1
  397. bool
  398. config FSL_TZASC_2
  399. bool
  400. config FSL_TZASC_400
  401. bool
  402. config FSL_TZPC_BP147
  403. bool
  404. endmenu
  405. menu "Layerscape clock tree configuration"
  406. depends on FSL_LSCH2 || FSL_LSCH3
  407. config SYS_FSL_CLK
  408. bool "Enable clock tree initialization"
  409. default y
  410. config CLUSTER_CLK_FREQ
  411. int "Reference clock of core cluster"
  412. depends on ARCH_LS1012A
  413. default 100000000
  414. help
  415. This number is the reference clock frequency of core PLL.
  416. For most platforms, the core PLL and Platform PLL have the same
  417. reference clock, but for some platforms, LS1012A for instance,
  418. they are provided sepatately.
  419. config SYS_FSL_PCLK_DIV
  420. int "Platform clock divider"
  421. default 1 if ARCH_LS1028A
  422. default 1 if ARCH_LS1043A
  423. default 1 if ARCH_LS1046A
  424. default 1 if ARCH_LS1088A
  425. default 2
  426. help
  427. This is the divider that is used to derive Platform clock from
  428. Platform PLL, in another word:
  429. Platform_clk = Platform_PLL_freq / this_divider
  430. config SYS_FSL_DSPI_CLK_DIV
  431. int "DSPI clock divider"
  432. default 1 if ARCH_LS1043A
  433. default 2
  434. help
  435. This is the divider that is used to derive DSPI clock from Platform
  436. clock, in another word DSPI_clk = Platform_clk / this_divider.
  437. config SYS_FSL_DUART_CLK_DIV
  438. int "DUART clock divider"
  439. default 1 if ARCH_LS1043A
  440. default 4 if ARCH_LX2160A
  441. default 2
  442. help
  443. This is the divider that is used to derive DUART clock from Platform
  444. clock, in another word DUART_clk = Platform_clk / this_divider.
  445. config SYS_FSL_I2C_CLK_DIV
  446. int "I2C clock divider"
  447. default 1 if ARCH_LS1043A
  448. default 4 if ARCH_LS1012A
  449. default 4 if ARCH_LS1028A
  450. default 8 if ARCH_LX2160A
  451. default 8 if ARCH_LS1088A
  452. default 2
  453. help
  454. This is the divider that is used to derive I2C clock from Platform
  455. clock, in another word I2C_clk = Platform_clk / this_divider.
  456. config SYS_FSL_IFC_CLK_DIV
  457. int "IFC clock divider"
  458. default 1 if ARCH_LS1043A
  459. default 4 if ARCH_LS1012A
  460. default 4 if ARCH_LS1028A
  461. default 8 if ARCH_LX2160A
  462. default 8 if ARCH_LS1088A
  463. default 2
  464. help
  465. This is the divider that is used to derive IFC clock from Platform
  466. clock, in another word IFC_clk = Platform_clk / this_divider.
  467. config SYS_FSL_LPUART_CLK_DIV
  468. int "LPUART clock divider"
  469. default 1 if ARCH_LS1043A
  470. default 2
  471. help
  472. This is the divider that is used to derive LPUART clock from Platform
  473. clock, in another word LPUART_clk = Platform_clk / this_divider.
  474. config SYS_FSL_SDHC_CLK_DIV
  475. int "SDHC clock divider"
  476. default 1 if ARCH_LS1043A
  477. default 1 if ARCH_LS1012A
  478. default 2
  479. help
  480. This is the divider that is used to derive SDHC clock from Platform
  481. clock, in another word SDHC_clk = Platform_clk / this_divider.
  482. config SYS_FSL_QMAN_CLK_DIV
  483. int "QMAN clock divider"
  484. default 1 if ARCH_LS1043A
  485. default 2
  486. help
  487. This is the divider that is used to derive QMAN clock from Platform
  488. clock, in another word QMAN_clk = Platform_clk / this_divider.
  489. endmenu
  490. config RESV_RAM
  491. bool
  492. help
  493. Reserve memory from the top, tracked by gd->arch.resv_ram. This
  494. reserved RAM can be used by special driver that resides in memory
  495. after U-Boot exits. It's up to implementation to allocate and allow
  496. access to this reserved memory. For example, the reserved RAM can
  497. be at the high end of physical memory. The reserve RAM may be
  498. excluded from memory bank(s) passed to OS, or marked as reserved.
  499. config SYS_FSL_EC1
  500. bool
  501. help
  502. Ethernet controller 1, this is connected to
  503. MAC17 for LX2160A or to MAC3 for other SoCs
  504. Provides DPAA2 capabilities
  505. config SYS_FSL_EC2
  506. bool
  507. help
  508. Ethernet controller 2, this is connected to
  509. MAC18 for LX2160A or to MAC4 for other SoCs
  510. Provides DPAA2 capabilities
  511. config SYS_FSL_ERRATUM_A008336
  512. bool
  513. config SYS_FSL_ERRATUM_A008514
  514. bool
  515. config SYS_FSL_ERRATUM_A008585
  516. bool
  517. config SYS_FSL_ERRATUM_A008850
  518. bool
  519. config SYS_FSL_ERRATUM_A009203
  520. bool
  521. config SYS_FSL_ERRATUM_A009635
  522. bool
  523. config SYS_FSL_ERRATUM_A009660
  524. bool
  525. config SYS_FSL_ERRATUM_A009929
  526. bool
  527. config SYS_FSL_ERRATUM_A050382
  528. bool
  529. config SYS_FSL_HAS_RGMII
  530. bool
  531. depends on SYS_FSL_EC1 || SYS_FSL_EC2
  532. config SPL_LDSCRIPT
  533. default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
  534. config HAS_FSL_XHCI_USB
  535. bool
  536. default y if ARCH_LS1043A || ARCH_LS1046A
  537. help
  538. For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
  539. pins, select it when the pins are assigned to USB.