fsl-ls1046a-rdb.dts 1.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  4. *
  5. * Copyright 2016, Freescale Semiconductor
  6. * Copyright 2020 NXP
  7. *
  8. * Mingkai Hu <Mingkai.hu@freescale.com>
  9. */
  10. /dts-v1/;
  11. /include/ "fsl-ls1046a.dtsi"
  12. / {
  13. model = "LS1046A RDB Board";
  14. aliases {
  15. spi0 = &qspi;
  16. };
  17. };
  18. &qspi {
  19. bus-num = <0>;
  20. status = "okay";
  21. qflash0: s25fs512s@0 {
  22. #address-cells = <1>;
  23. #size-cells = <1>;
  24. compatible = "jedec,spi-nor";
  25. spi-max-frequency = <50000000>;
  26. reg = <0>;
  27. };
  28. qflash1: s25fs512s@1 {
  29. #address-cells = <1>;
  30. #size-cells = <1>;
  31. compatible = "jedec,spi-nor";
  32. spi-max-frequency = <50000000>;
  33. reg = <1>;
  34. };
  35. };
  36. &sata {
  37. status = "okay";
  38. };
  39. &i2c0 {
  40. status = "okay";
  41. };
  42. &i2c3 {
  43. status = "okay";
  44. };
  45. #include "fsl-ls1046-post.dtsi"
  46. &fman0 {
  47. ethernet@e4000 {
  48. phy-handle = <&rgmii_phy1>;
  49. phy-connection-type = "rgmii-id";
  50. status = "okay";
  51. };
  52. ethernet@e6000 {
  53. phy-handle = <&rgmii_phy2>;
  54. phy-connection-type = "rgmii-id";
  55. status = "okay";
  56. };
  57. ethernet@e8000 {
  58. phy-handle = <&sgmii_phy1>;
  59. phy-connection-type = "sgmii";
  60. status = "okay";
  61. };
  62. ethernet@ea000 {
  63. phy-handle = <&sgmii_phy2>;
  64. phy-connection-type = "sgmii";
  65. status = "okay";
  66. };
  67. ethernet@f0000 { /* 10GEC1 */
  68. phy-handle = <&aqr106_phy>;
  69. phy-connection-type = "xgmii";
  70. status = "okay";
  71. };
  72. ethernet@f2000 { /* 10GEC2 */
  73. fixed-link = <0 1 1000 0 0>;
  74. phy-connection-type = "xgmii";
  75. status = "okay";
  76. };
  77. mdio@fc000 {
  78. rgmii_phy1: ethernet-phy@1 {
  79. reg = <0x1>;
  80. };
  81. rgmii_phy2: ethernet-phy@2 {
  82. reg = <0x2>;
  83. };
  84. sgmii_phy1: ethernet-phy@3 {
  85. reg = <0x3>;
  86. };
  87. sgmii_phy2: ethernet-phy@4 {
  88. reg = <0x4>;
  89. };
  90. };
  91. mdio@fd000 {
  92. aqr106_phy: ethernet-phy@0 {
  93. compatible = "ethernet-phy-ieee802.3-c45";
  94. interrupts = <0 131 4>;
  95. reg = <0x0>;
  96. };
  97. };
  98. };