fsl-ls2080a.dtsi 7.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281
  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Freescale ls2080a SOC common device tree source
  4. *
  5. * Copyright 2013-2015 Freescale Semiconductor, Inc.
  6. */
  7. / {
  8. compatible = "fsl,ls2080a";
  9. interrupt-parent = <&gic>;
  10. #address-cells = <2>;
  11. #size-cells = <2>;
  12. memory@80000000 {
  13. device_type = "memory";
  14. reg = <0x00000000 0x80000000 0 0x80000000>;
  15. /* DRAM space - 1, size : 2 GB DRAM */
  16. };
  17. gic: interrupt-controller@6000000 {
  18. compatible = "arm,gic-v3";
  19. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  20. <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  21. #interrupt-cells = <3>;
  22. interrupt-controller;
  23. interrupts = <1 9 0x4>;
  24. };
  25. timer {
  26. compatible = "arm,armv8-timer";
  27. interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  28. <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  29. <1 11 0x8>, /* Virtual PPI, active-low */
  30. <1 10 0x8>; /* Hypervisor PPI, active-low */
  31. };
  32. serial0: serial@21c0500 {
  33. device_type = "serial";
  34. compatible = "fsl,ns16550", "ns16550a";
  35. reg = <0x0 0x21c0500 0x0 0x100>;
  36. clock-frequency = <0>; /* Updated by bootloader */
  37. interrupts = <0 32 0x1>; /* edge triggered */
  38. };
  39. serial1: serial@21c0600 {
  40. device_type = "serial";
  41. compatible = "fsl,ns16550", "ns16550a";
  42. reg = <0x0 0x21c0600 0x0 0x100>;
  43. clock-frequency = <0>; /* Updated by bootloader */
  44. interrupts = <0 32 0x1>; /* edge triggered */
  45. };
  46. i2c0: i2c@2000000 {
  47. status = "disabled";
  48. compatible = "fsl,vf610-i2c";
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. reg = <0x0 0x2000000 0x0 0x10000>;
  52. interrupts = <0 34 0x4>; /* Level high type */
  53. };
  54. i2c1: i2c@2010000 {
  55. status = "disabled";
  56. compatible = "fsl,vf610-i2c";
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. reg = <0x0 0x2010000 0x0 0x10000>;
  60. interrupts = <0 34 0x4>; /* Level high type */
  61. };
  62. i2c2: i2c@2020000 {
  63. status = "disabled";
  64. compatible = "fsl,vf610-i2c";
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. reg = <0x0 0x2020000 0x0 0x10000>;
  68. interrupts = <0 35 0x4>; /* Level high type */
  69. };
  70. i2c3: i2c@2030000 {
  71. status = "disabled";
  72. compatible = "fsl,vf610-i2c";
  73. #address-cells = <1>;
  74. #size-cells = <0>;
  75. reg = <0x0 0x2030000 0x0 0x10000>;
  76. interrupts = <0 35 0x4>; /* Level high type */
  77. };
  78. dspi: dspi@2100000 {
  79. compatible = "fsl,vf610-dspi";
  80. #address-cells = <1>;
  81. #size-cells = <0>;
  82. reg = <0x0 0x2100000 0x0 0x10000>;
  83. interrupts = <0 26 0x4>; /* Level high type */
  84. num-cs = <6>;
  85. };
  86. qspi: quadspi@1550000 {
  87. compatible = "fsl,vf610-qspi";
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. reg = <0x0 0x20c0000 0x0 0x10000>,
  91. <0x0 0x20000000 0x0 0x10000000>;
  92. reg-names = "QuadSPI", "QuadSPI-memory";
  93. num-cs = <4>;
  94. };
  95. esdhc: esdhc@0 {
  96. compatible = "fsl,esdhc";
  97. reg = <0x0 0x2140000 0x0 0x10000>;
  98. interrupts = <0 28 0x4>; /* Level high type */
  99. little-endian;
  100. bus-width = <4>;
  101. };
  102. usb0: usb3@3100000 {
  103. compatible = "fsl,layerscape-dwc3";
  104. reg = <0x0 0x3100000 0x0 0x10000>;
  105. interrupts = <0 80 0x4>; /* Level high type */
  106. dr_mode = "host";
  107. };
  108. usb1: usb3@3110000 {
  109. compatible = "fsl,layerscape-dwc3";
  110. reg = <0x0 0x3110000 0x0 0x10000>;
  111. interrupts = <0 81 0x4>; /* Level high type */
  112. dr_mode = "host";
  113. };
  114. pcie@3400000 {
  115. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  116. reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
  117. 0x00 0x03480000 0x0 0x80000 /* lut registers */
  118. 0x10 0x00000000 0x0 0x20000>; /* configuration space */
  119. reg-names = "dbi", "lut", "config";
  120. #address-cells = <3>;
  121. #size-cells = <2>;
  122. device_type = "pci";
  123. num-lanes = <4>;
  124. bus-range = <0x0 0xff>;
  125. ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
  126. 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  127. };
  128. pcie@3500000 {
  129. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  130. reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
  131. 0x00 0x03580000 0x0 0x80000 /* lut registers */
  132. 0x12 0x00000000 0x0 0x20000>; /* configuration space */
  133. reg-names = "dbi", "lut", "config";
  134. #address-cells = <3>;
  135. #size-cells = <2>;
  136. device_type = "pci";
  137. num-lanes = <4>;
  138. bus-range = <0x0 0xff>;
  139. ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
  140. 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  141. };
  142. pcie@3600000 {
  143. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  144. reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
  145. 0x00 0x03680000 0x0 0x80000 /* lut registers */
  146. 0x14 0x00000000 0x0 0x20000>; /* configuration space */
  147. reg-names = "dbi", "lut", "config";
  148. #address-cells = <3>;
  149. #size-cells = <2>;
  150. device_type = "pci";
  151. num-lanes = <8>;
  152. bus-range = <0x0 0xff>;
  153. ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
  154. 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  155. };
  156. pcie@3700000 {
  157. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  158. reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
  159. 0x00 0x03780000 0x0 0x80000 /* lut registers */
  160. 0x16 0x00000000 0x0 0x20000>; /* configuration space */
  161. reg-names = "dbi", "lut", "config";
  162. #address-cells = <3>;
  163. #size-cells = <2>;
  164. device_type = "pci";
  165. num-lanes = <4>;
  166. bus-range = <0x0 0xff>;
  167. ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
  168. 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  169. };
  170. sata: sata@3200000 {
  171. compatible = "fsl,ls2080a-ahci";
  172. reg = <0x0 0x3200000 0x0 0x10000>;
  173. interrupts = <0 133 0x4>; /* Level high type */
  174. status = "disabled";
  175. };
  176. fsl_mc: fsl-mc@80c000000 {
  177. compatible = "fsl,qoriq-mc", "simple-mfd";
  178. reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
  179. <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
  180. #address-cells = <3>;
  181. #size-cells = <1>;
  182. /*
  183. * Region type 0x0 - MC portals
  184. * Region type 0x1 - QBMAN portals
  185. */
  186. ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
  187. 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
  188. dpmacs {
  189. compatible = "simple-mfd";
  190. #address-cells = <1>;
  191. #size-cells = <0>;
  192. dpmac1: dpmac@1 {
  193. compatible = "fsl,qoriq-mc-dpmac";
  194. reg = <0x1>;
  195. status = "disabled";
  196. };
  197. dpmac2: dpmac@2 {
  198. compatible = "fsl,qoriq-mc-dpmac";
  199. reg = <0x2>;
  200. status = "disabled";
  201. };
  202. dpmac3: dpmac@3 {
  203. compatible = "fsl,qoriq-mc-dpmac";
  204. reg = <0x3>;
  205. status = "disabled";
  206. };
  207. dpmac4: dpmac@4 {
  208. compatible = "fsl,qoriq-mc-dpmac";
  209. reg = <0x4>;
  210. status = "disabled";
  211. };
  212. dpmac5: dpmac@5 {
  213. compatible = "fsl,qoriq-mc-dpmac";
  214. reg = <0x5>;
  215. status = "disabled";
  216. };
  217. dpmac6: dpmac@6 {
  218. compatible = "fsl,qoriq-mc-dpmac";
  219. reg = <0x6>;
  220. status = "disabled";
  221. };
  222. dpmac7: dpmac@7 {
  223. compatible = "fsl,qoriq-mc-dpmac";
  224. reg = <0x7>;
  225. status = "disabled";
  226. };
  227. dpmac8: dpmac@8 {
  228. compatible = "fsl,qoriq-mc-dpmac";
  229. reg = <0x8>;
  230. status = "disabled";
  231. };
  232. };
  233. };
  234. emdio1: mdio@8B96000 {
  235. compatible = "fsl,ls-mdio";
  236. reg = <0x0 0x8B96000 0x0 0x1000>;
  237. #address-cells = <1>;
  238. #size-cells = <0>;
  239. status = "disabled";
  240. };
  241. emdio2: mdio@8B97000 {
  242. compatible = "fsl,ls-mdio";
  243. reg = <0x0 0x8B97000 0x0 0x1000>;
  244. #address-cells = <1>;
  245. #size-cells = <0>;
  246. status = "disabled";
  247. };
  248. };