fsl-ls1088a-rdb.dts 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP ls1088a RDB board device tree source
  4. *
  5. * Copyright 2017 NXP
  6. */
  7. /dts-v1/;
  8. #include "fsl-ls1088a.dtsi"
  9. / {
  10. model = "NXP Layerscape 1088a RDB Board";
  11. compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
  12. aliases {
  13. spi0 = &qspi;
  14. };
  15. };
  16. &dpmac1 {
  17. status = "okay";
  18. phy-connection-type = "xgmii";
  19. };
  20. &dpmac2 {
  21. status = "okay";
  22. phy-handle = <&mdio2_phy1>;
  23. phy-connection-type = "xgmii";
  24. };
  25. &dpmac3 {
  26. status = "okay";
  27. phy-handle = <&mdio1_phy5>;
  28. phy-connection-type = "qsgmii";
  29. };
  30. &dpmac4 {
  31. status = "okay";
  32. phy-handle = <&mdio1_phy6>;
  33. phy-connection-type = "qsgmii";
  34. };
  35. &dpmac5 {
  36. status = "okay";
  37. phy-handle = <&mdio1_phy7>;
  38. phy-connection-type = "qsgmii";
  39. };
  40. &dpmac6 {
  41. status = "okay";
  42. phy-handle = <&mdio1_phy8>;
  43. phy-connection-type = "qsgmii";
  44. };
  45. &dpmac7 {
  46. status = "okay";
  47. phy-handle = <&mdio1_phy1>;
  48. phy-connection-type = "qsgmii";
  49. };
  50. &dpmac8 {
  51. status = "okay";
  52. phy-handle = <&mdio1_phy2>;
  53. phy-connection-type = "qsgmii";
  54. };
  55. &dpmac9 {
  56. status = "okay";
  57. phy-handle = <&mdio1_phy3>;
  58. phy-connection-type = "qsgmii";
  59. };
  60. &dpmac10 {
  61. status = "okay";
  62. phy-handle = <&mdio1_phy4>;
  63. phy-connection-type = "qsgmii";
  64. };
  65. &emdio1 {
  66. status = "okay";
  67. /* Freescale F104 PHY1 */
  68. mdio1_phy1: emdio1_phy@1 {
  69. reg = <0x1c>;
  70. };
  71. mdio1_phy2: emdio1_phy@2 {
  72. reg = <0x1d>;
  73. };
  74. mdio1_phy3: emdio1_phy@3 {
  75. reg = <0x1e>;
  76. };
  77. mdio1_phy4: emdio1_phy@4 {
  78. reg = <0x1f>;
  79. };
  80. /* F104 PHY2 */
  81. mdio1_phy5: emdio1_phy@5 {
  82. reg = <0x0c>;
  83. };
  84. mdio1_phy6: emdio1_phy@6 {
  85. reg = <0x0d>;
  86. };
  87. mdio1_phy7: emdio1_phy@7 {
  88. reg = <0x0e>;
  89. };
  90. mdio1_phy8: emdio1_phy@8 {
  91. reg = <0x0f>;
  92. };
  93. };
  94. &emdio2 {
  95. status = "okay";
  96. /* Aquantia AQR105 10G PHY */
  97. mdio2_phy1: emdio2_phy@1 {
  98. compatible = "ethernet-phy-ieee802.3-c45";
  99. interrupts = <0 2 0x4>;
  100. reg = <0x0>;
  101. };
  102. };
  103. &i2c0 {
  104. status = "okay";
  105. u-boot,dm-pre-reloc;
  106. i2c-mux@77 {
  107. compatible = "nxp,pca9547";
  108. reg = <0x77>;
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. i2c@3 {
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. reg = <0x3>;
  115. rtc@51 {
  116. compatible = "pcf2127-rtc";
  117. reg = <0x51>;
  118. };
  119. };
  120. };
  121. };
  122. &qspi {
  123. bus-num = <0>;
  124. status = "okay";
  125. qflash0: s25fs512s@0 {
  126. #address-cells = <1>;
  127. #size-cells = <1>;
  128. compatible = "jedec,spi-nor";
  129. spi-max-frequency = <50000000>;
  130. reg = <0>;
  131. };
  132. qflash1: s25fs512s@1 {
  133. #address-cells = <1>;
  134. #size-cells = <1>;
  135. compatible = "jedec,spi-nor";
  136. spi-max-frequency = <50000000>;
  137. reg = <1>;
  138. };
  139. };
  140. &sata {
  141. status = "okay";
  142. };