ls2080ardb.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. * Copyright 2017 NXP
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <malloc.h>
  9. #include <errno.h>
  10. #include <netdev.h>
  11. #include <fsl_ifc.h>
  12. #include <fsl_ddr.h>
  13. #include <asm/io.h>
  14. #include <hwconfig.h>
  15. #include <fdt_support.h>
  16. #include <linux/libfdt.h>
  17. #include <fsl-mc/fsl_mc.h>
  18. #include <env_internal.h>
  19. #include <efi_loader.h>
  20. #include <i2c.h>
  21. #include <asm/arch/mmu.h>
  22. #include <asm/arch/soc.h>
  23. #include <asm/arch/ppa.h>
  24. #include <fsl_sec.h>
  25. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  26. #ifdef CONFIG_FSL_QIXIS
  27. #include "../common/qixis.h"
  28. #include "ls2080ardb_qixis.h"
  29. #endif
  30. #include "../common/vid.h"
  31. #define PIN_MUX_SEL_SDHC 0x00
  32. #define PIN_MUX_SEL_DSPI 0x0a
  33. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  34. DECLARE_GLOBAL_DATA_PTR;
  35. enum {
  36. MUX_TYPE_SDHC,
  37. MUX_TYPE_DSPI,
  38. };
  39. unsigned long long get_qixis_addr(void)
  40. {
  41. unsigned long long addr;
  42. if (gd->flags & GD_FLG_RELOC)
  43. addr = QIXIS_BASE_PHYS;
  44. else
  45. addr = QIXIS_BASE_PHYS_EARLY;
  46. /*
  47. * IFC address under 256MB is mapped to 0x30000000, any address above
  48. * is mapped to 0x5_10000000 up to 4GB.
  49. */
  50. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  51. return addr;
  52. }
  53. int checkboard(void)
  54. {
  55. #ifdef CONFIG_FSL_QIXIS
  56. u8 sw;
  57. #endif
  58. char buf[15];
  59. cpu_name(buf);
  60. printf("Board: %s-RDB, ", buf);
  61. #ifdef CONFIG_TARGET_LS2081ARDB
  62. #ifdef CONFIG_FSL_QIXIS
  63. sw = QIXIS_READ(arch);
  64. printf("Board version: %c, ", (sw & 0xf) + 'A');
  65. sw = QIXIS_READ(brdcfg[0]);
  66. sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
  67. switch (sw) {
  68. case 0:
  69. puts("boot from QSPI DEV#0\n");
  70. puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  71. break;
  72. case 1:
  73. puts("boot from QSPI DEV#1\n");
  74. puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  75. break;
  76. case 2:
  77. puts("boot from QSPI EMU\n");
  78. puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  79. break;
  80. case 3:
  81. puts("boot from QSPI EMU\n");
  82. puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  83. break;
  84. case 4:
  85. puts("boot from QSPI DEV#0\n");
  86. puts("QSPI_CSA_1 mapped to QSPI EMU\n");
  87. break;
  88. default:
  89. printf("invalid setting of SW%u\n", sw);
  90. break;
  91. }
  92. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  93. #endif
  94. puts("SERDES1 Reference : ");
  95. printf("Clock1 = 100MHz ");
  96. printf("Clock2 = 161.13MHz");
  97. #else
  98. #ifdef CONFIG_FSL_QIXIS
  99. sw = QIXIS_READ(arch);
  100. printf("Board Arch: V%d, ", sw >> 4);
  101. printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  102. sw = QIXIS_READ(brdcfg[0]);
  103. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  104. if (sw < 0x8)
  105. printf("vBank: %d\n", sw);
  106. else if (sw == 0x9)
  107. puts("NAND\n");
  108. else
  109. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  110. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  111. #endif
  112. puts("SERDES1 Reference : ");
  113. printf("Clock1 = 156.25MHz ");
  114. printf("Clock2 = 156.25MHz");
  115. #endif
  116. puts("\nSERDES2 Reference : ");
  117. printf("Clock1 = 100MHz ");
  118. printf("Clock2 = 100MHz\n");
  119. return 0;
  120. }
  121. unsigned long get_board_sys_clk(void)
  122. {
  123. #ifdef CONFIG_FSL_QIXIS
  124. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  125. switch (sysclk_conf & 0x0F) {
  126. case QIXIS_SYSCLK_83:
  127. return 83333333;
  128. case QIXIS_SYSCLK_100:
  129. return 100000000;
  130. case QIXIS_SYSCLK_125:
  131. return 125000000;
  132. case QIXIS_SYSCLK_133:
  133. return 133333333;
  134. case QIXIS_SYSCLK_150:
  135. return 150000000;
  136. case QIXIS_SYSCLK_160:
  137. return 160000000;
  138. case QIXIS_SYSCLK_166:
  139. return 166666666;
  140. }
  141. #endif
  142. return 100000000;
  143. }
  144. int select_i2c_ch_pca9547(u8 ch)
  145. {
  146. int ret;
  147. #ifndef CONFIG_DM_I2C
  148. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  149. #else
  150. struct udevice *dev;
  151. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  152. if (!ret)
  153. ret = dm_i2c_write(dev, 0, &ch, 1);
  154. #endif
  155. if (ret) {
  156. puts("PCA: failed to select proper channel\n");
  157. return ret;
  158. }
  159. return 0;
  160. }
  161. int i2c_multiplexer_select_vid_channel(u8 channel)
  162. {
  163. return select_i2c_ch_pca9547(channel);
  164. }
  165. int config_board_mux(int ctrl_type)
  166. {
  167. #ifdef CONFIG_FSL_QIXIS
  168. u8 reg5;
  169. reg5 = QIXIS_READ(brdcfg[5]);
  170. switch (ctrl_type) {
  171. case MUX_TYPE_SDHC:
  172. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
  173. break;
  174. case MUX_TYPE_DSPI:
  175. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
  176. break;
  177. default:
  178. printf("Wrong mux interface type\n");
  179. return -1;
  180. }
  181. QIXIS_WRITE(brdcfg[5], reg5);
  182. #endif
  183. return 0;
  184. }
  185. int board_init(void)
  186. {
  187. #ifdef CONFIG_FSL_MC_ENET
  188. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  189. #endif
  190. init_final_memctl_regs();
  191. #ifdef CONFIG_ENV_IS_NOWHERE
  192. gd->env_addr = (ulong)&default_environment[0];
  193. #endif
  194. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  195. #ifdef CONFIG_FSL_QIXIS
  196. QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
  197. #endif
  198. #ifdef CONFIG_FSL_CAAM
  199. sec_init();
  200. #endif
  201. #ifdef CONFIG_FSL_LS_PPA
  202. ppa_init();
  203. #endif
  204. #ifdef CONFIG_FSL_MC_ENET
  205. /* invert AQR405 IRQ pins polarity */
  206. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
  207. #endif
  208. #ifdef CONFIG_FSL_CAAM
  209. sec_init();
  210. #endif
  211. #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
  212. pci_init();
  213. #endif
  214. return 0;
  215. }
  216. int board_early_init_f(void)
  217. {
  218. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  219. i2c_early_init_f();
  220. #endif
  221. fsl_lsch3_early_init_f();
  222. return 0;
  223. }
  224. int misc_init_r(void)
  225. {
  226. char *env_hwconfig;
  227. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  228. u32 val;
  229. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  230. u32 svr = gur_in32(&gur->svr);
  231. val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
  232. env_hwconfig = env_get("hwconfig");
  233. if (hwconfig_f("dspi", env_hwconfig) &&
  234. DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
  235. config_board_mux(MUX_TYPE_DSPI);
  236. else
  237. config_board_mux(MUX_TYPE_SDHC);
  238. /*
  239. * LS2081ARDB RevF board has smart voltage translator
  240. * which needs to be programmed to enable high speed SD interface
  241. * by setting GPIO4_10 output to zero
  242. */
  243. #ifdef CONFIG_TARGET_LS2081ARDB
  244. out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
  245. in_le32(GPIO4_GPDIR_ADDR)));
  246. out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
  247. in_le32(GPIO4_GPDAT_ADDR)));
  248. #endif
  249. if (hwconfig("sdhc"))
  250. config_board_mux(MUX_TYPE_SDHC);
  251. if (adjust_vdd(0))
  252. printf("Warning: Adjusting core voltage failed.\n");
  253. /*
  254. * Default value of board env is based on filename which is
  255. * ls2080ardb. Modify board env for other supported SoCs
  256. */
  257. if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
  258. (SVR_SOC_VER(svr) == SVR_LS2048A))
  259. env_set("board", "ls2088ardb");
  260. else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
  261. (SVR_SOC_VER(svr) == SVR_LS2041A))
  262. env_set("board", "ls2081ardb");
  263. return 0;
  264. }
  265. void detail_board_ddr_info(void)
  266. {
  267. puts("\nDDR ");
  268. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  269. print_ddr_info(0);
  270. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  271. if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
  272. puts("\nDP-DDR ");
  273. print_size(gd->bd->bi_dram[2].size, "");
  274. print_ddr_info(CONFIG_DP_DDR_CTRL);
  275. }
  276. #endif
  277. }
  278. #ifdef CONFIG_FSL_MC_ENET
  279. void fdt_fixup_board_enet(void *fdt)
  280. {
  281. int offset;
  282. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  283. if (offset < 0)
  284. offset = fdt_path_offset(fdt, "/fsl-mc");
  285. if (offset < 0) {
  286. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  287. __func__, offset);
  288. return;
  289. }
  290. if (get_mc_boot_status() == 0 &&
  291. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  292. fdt_status_okay(fdt, offset);
  293. else
  294. fdt_status_fail(fdt, offset);
  295. }
  296. void board_quiesce_devices(void)
  297. {
  298. fsl_mc_ldpaa_exit(gd->bd);
  299. }
  300. #endif
  301. #ifdef CONFIG_OF_BOARD_SETUP
  302. void fsl_fdt_fixup_flash(void *fdt)
  303. {
  304. int offset;
  305. #ifdef CONFIG_TFABOOT
  306. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  307. u32 val;
  308. #endif
  309. /*
  310. * IFC and QSPI are muxed on board.
  311. * So disable IFC node in dts if QSPI is enabled or
  312. * disable QSPI node in dts in case QSPI is not enabled.
  313. */
  314. #ifdef CONFIG_TFABOOT
  315. enum boot_src src = get_boot_src();
  316. bool disable_ifc = false;
  317. switch (src) {
  318. case BOOT_SOURCE_IFC_NOR:
  319. disable_ifc = false;
  320. break;
  321. case BOOT_SOURCE_QSPI_NOR:
  322. disable_ifc = true;
  323. break;
  324. default:
  325. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  326. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  327. disable_ifc = true;
  328. break;
  329. }
  330. if (disable_ifc) {
  331. offset = fdt_path_offset(fdt, "/soc/ifc");
  332. if (offset < 0)
  333. offset = fdt_path_offset(fdt, "/ifc");
  334. } else {
  335. offset = fdt_path_offset(fdt, "/soc/quadspi");
  336. if (offset < 0)
  337. offset = fdt_path_offset(fdt, "/quadspi");
  338. }
  339. #else
  340. #ifdef CONFIG_FSL_QSPI
  341. offset = fdt_path_offset(fdt, "/soc/ifc");
  342. if (offset < 0)
  343. offset = fdt_path_offset(fdt, "/ifc");
  344. #else
  345. offset = fdt_path_offset(fdt, "/soc/quadspi");
  346. if (offset < 0)
  347. offset = fdt_path_offset(fdt, "/quadspi");
  348. #endif
  349. #endif
  350. if (offset < 0)
  351. return;
  352. fdt_status_disabled(fdt, offset);
  353. }
  354. int ft_board_setup(void *blob, bd_t *bd)
  355. {
  356. int i;
  357. u16 mc_memory_bank = 0;
  358. u64 *base;
  359. u64 *size;
  360. u64 mc_memory_base = 0;
  361. u64 mc_memory_size = 0;
  362. u16 total_memory_banks;
  363. ft_cpu_setup(blob, bd);
  364. fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
  365. if (mc_memory_base != 0)
  366. mc_memory_bank++;
  367. total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
  368. base = calloc(total_memory_banks, sizeof(u64));
  369. size = calloc(total_memory_banks, sizeof(u64));
  370. /* fixup DT for the two GPP DDR banks */
  371. base[0] = gd->bd->bi_dram[0].start;
  372. size[0] = gd->bd->bi_dram[0].size;
  373. base[1] = gd->bd->bi_dram[1].start;
  374. size[1] = gd->bd->bi_dram[1].size;
  375. #ifdef CONFIG_RESV_RAM
  376. /* reduce size if reserved memory is within this bank */
  377. if (gd->arch.resv_ram >= base[0] &&
  378. gd->arch.resv_ram < base[0] + size[0])
  379. size[0] = gd->arch.resv_ram - base[0];
  380. else if (gd->arch.resv_ram >= base[1] &&
  381. gd->arch.resv_ram < base[1] + size[1])
  382. size[1] = gd->arch.resv_ram - base[1];
  383. #endif
  384. if (mc_memory_base != 0) {
  385. for (i = 0; i <= total_memory_banks; i++) {
  386. if (base[i] == 0 && size[i] == 0) {
  387. base[i] = mc_memory_base;
  388. size[i] = mc_memory_size;
  389. break;
  390. }
  391. }
  392. }
  393. fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
  394. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  395. fsl_fdt_fixup_dr_usb(blob, bd);
  396. fsl_fdt_fixup_flash(blob);
  397. #ifdef CONFIG_FSL_MC_ENET
  398. fdt_fixup_board_enet(blob);
  399. #endif
  400. fdt_fixup_icid(blob);
  401. return 0;
  402. }
  403. #endif
  404. void qixis_dump_switch(void)
  405. {
  406. #ifdef CONFIG_FSL_QIXIS
  407. int i, nr_of_cfgsw;
  408. QIXIS_WRITE(cms[0], 0x00);
  409. nr_of_cfgsw = QIXIS_READ(cms[1]);
  410. puts("DIP switch settings dump:\n");
  411. for (i = 1; i <= nr_of_cfgsw; i++) {
  412. QIXIS_WRITE(cms[0], i);
  413. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  414. }
  415. #endif
  416. }
  417. /*
  418. * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
  419. * Both slots has 0x54, resulting 2nd slot unusable.
  420. */
  421. void update_spd_address(unsigned int ctrl_num,
  422. unsigned int slot,
  423. unsigned int *addr)
  424. {
  425. #ifndef CONFIG_TARGET_LS2081ARDB
  426. #ifdef CONFIG_FSL_QIXIS
  427. u8 sw;
  428. sw = QIXIS_READ(arch);
  429. if ((sw & 0xf) < 0x3) {
  430. if (ctrl_num == 1 && slot == 0)
  431. *addr = SPD_EEPROM_ADDRESS4;
  432. else if (ctrl_num == 1 && slot == 1)
  433. *addr = SPD_EEPROM_ADDRESS3;
  434. }
  435. #endif
  436. #endif
  437. }