ls1043ardb.c 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #include <asm/arch/soc.h>
  11. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  12. #include <fdt_support.h>
  13. #include <hwconfig.h>
  14. #include <ahci.h>
  15. #include <mmc.h>
  16. #include <scsi.h>
  17. #include <fm_eth.h>
  18. #include <fsl_esdhc.h>
  19. #include <fsl_ifc.h>
  20. #include <fsl_sec.h>
  21. #include "cpld.h"
  22. #ifdef CONFIG_U_QE
  23. #include <fsl_qe.h>
  24. #endif
  25. #include <asm/arch/ppa.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #ifdef CONFIG_TFABOOT
  28. struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  29. {
  30. "nor",
  31. CONFIG_SYS_NOR_CSPR,
  32. CONFIG_SYS_NOR_CSPR_EXT,
  33. CONFIG_SYS_NOR_AMASK,
  34. CONFIG_SYS_NOR_CSOR,
  35. {
  36. CONFIG_SYS_NOR_FTIM0,
  37. CONFIG_SYS_NOR_FTIM1,
  38. CONFIG_SYS_NOR_FTIM2,
  39. CONFIG_SYS_NOR_FTIM3
  40. },
  41. },
  42. {
  43. "nand",
  44. CONFIG_SYS_NAND_CSPR,
  45. CONFIG_SYS_NAND_CSPR_EXT,
  46. CONFIG_SYS_NAND_AMASK,
  47. CONFIG_SYS_NAND_CSOR,
  48. {
  49. CONFIG_SYS_NAND_FTIM0,
  50. CONFIG_SYS_NAND_FTIM1,
  51. CONFIG_SYS_NAND_FTIM2,
  52. CONFIG_SYS_NAND_FTIM3
  53. },
  54. },
  55. {
  56. "cpld",
  57. CONFIG_SYS_CPLD_CSPR,
  58. CONFIG_SYS_CPLD_CSPR_EXT,
  59. CONFIG_SYS_CPLD_AMASK,
  60. CONFIG_SYS_CPLD_CSOR,
  61. {
  62. CONFIG_SYS_CPLD_FTIM0,
  63. CONFIG_SYS_CPLD_FTIM1,
  64. CONFIG_SYS_CPLD_FTIM2,
  65. CONFIG_SYS_CPLD_FTIM3
  66. },
  67. }
  68. };
  69. struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  70. {
  71. "nand",
  72. CONFIG_SYS_NAND_CSPR,
  73. CONFIG_SYS_NAND_CSPR_EXT,
  74. CONFIG_SYS_NAND_AMASK,
  75. CONFIG_SYS_NAND_CSOR,
  76. {
  77. CONFIG_SYS_NAND_FTIM0,
  78. CONFIG_SYS_NAND_FTIM1,
  79. CONFIG_SYS_NAND_FTIM2,
  80. CONFIG_SYS_NAND_FTIM3
  81. },
  82. },
  83. {
  84. "nor",
  85. CONFIG_SYS_NOR_CSPR,
  86. CONFIG_SYS_NOR_CSPR_EXT,
  87. CONFIG_SYS_NOR_AMASK,
  88. CONFIG_SYS_NOR_CSOR,
  89. {
  90. CONFIG_SYS_NOR_FTIM0,
  91. CONFIG_SYS_NOR_FTIM1,
  92. CONFIG_SYS_NOR_FTIM2,
  93. CONFIG_SYS_NOR_FTIM3
  94. },
  95. },
  96. {
  97. "cpld",
  98. CONFIG_SYS_CPLD_CSPR,
  99. CONFIG_SYS_CPLD_CSPR_EXT,
  100. CONFIG_SYS_CPLD_AMASK,
  101. CONFIG_SYS_CPLD_CSOR,
  102. {
  103. CONFIG_SYS_CPLD_FTIM0,
  104. CONFIG_SYS_CPLD_FTIM1,
  105. CONFIG_SYS_CPLD_FTIM2,
  106. CONFIG_SYS_CPLD_FTIM3
  107. },
  108. }
  109. };
  110. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  111. {
  112. enum boot_src src = get_boot_src();
  113. if (src == BOOT_SOURCE_IFC_NAND)
  114. regs_info->regs = ifc_cfg_nand_boot;
  115. else
  116. regs_info->regs = ifc_cfg_nor_boot;
  117. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  118. }
  119. #endif
  120. int board_early_init_f(void)
  121. {
  122. fsl_lsch2_early_init_f();
  123. return 0;
  124. }
  125. #ifndef CONFIG_SPL_BUILD
  126. int checkboard(void)
  127. {
  128. #ifdef CONFIG_TFABOOT
  129. enum boot_src src = get_boot_src();
  130. #endif
  131. static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
  132. #ifndef CONFIG_SD_BOOT
  133. u8 cfg_rcw_src1, cfg_rcw_src2;
  134. u16 cfg_rcw_src;
  135. #endif
  136. u8 sd1refclk_sel;
  137. printf("Board: LS1043ARDB, boot from ");
  138. #ifdef CONFIG_TFABOOT
  139. if (src == BOOT_SOURCE_SD_MMC)
  140. puts("SD\n");
  141. else {
  142. #endif
  143. #ifdef CONFIG_SD_BOOT
  144. puts("SD\n");
  145. #else
  146. cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
  147. cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
  148. cpld_rev_bit(&cfg_rcw_src1);
  149. cfg_rcw_src = cfg_rcw_src1;
  150. cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
  151. if (cfg_rcw_src == 0x25)
  152. printf("vBank %d\n", CPLD_READ(vbank));
  153. else if (cfg_rcw_src == 0x106)
  154. puts("NAND\n");
  155. else
  156. printf("Invalid setting of SW4\n");
  157. #endif
  158. #ifdef CONFIG_TFABOOT
  159. }
  160. #endif
  161. printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
  162. CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
  163. puts("SERDES Reference Clocks:\n");
  164. sd1refclk_sel = CPLD_READ(sd1refclk_sel);
  165. printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
  166. return 0;
  167. }
  168. int board_init(void)
  169. {
  170. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  171. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  172. erratum_a010315();
  173. #endif
  174. #ifdef CONFIG_FSL_IFC
  175. init_final_memctl_regs();
  176. #endif
  177. #ifdef CONFIG_NXP_ESBC
  178. /* In case of Secure Boot, the IBR configures the SMMU
  179. * to allow only Secure transactions.
  180. * SMMU must be reset in bypass mode.
  181. * Set the ClientPD bit and Clear the USFCFG Bit
  182. */
  183. u32 val;
  184. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  185. out_le32(SMMU_SCR0, val);
  186. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  187. out_le32(SMMU_NSCR0, val);
  188. #endif
  189. #ifdef CONFIG_FSL_CAAM
  190. sec_init();
  191. #endif
  192. #ifdef CONFIG_FSL_LS_PPA
  193. ppa_init();
  194. #endif
  195. #ifdef CONFIG_U_QE
  196. u_qe_init();
  197. #endif
  198. /* invert AQR105 IRQ pins polarity */
  199. out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
  200. return 0;
  201. }
  202. int config_board_mux(void)
  203. {
  204. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  205. u32 usb_pwrfault;
  206. if (hwconfig("qe-hdlc")) {
  207. out_be32(&scfg->rcwpmuxcr0,
  208. (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
  209. printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
  210. in_be32(&scfg->rcwpmuxcr0));
  211. } else {
  212. #ifdef CONFIG_HAS_FSL_XHCI_USB
  213. out_be32(&scfg->rcwpmuxcr0, 0x3333);
  214. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  215. usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
  216. SCFG_USBPWRFAULT_USB3_SHIFT) |
  217. (SCFG_USBPWRFAULT_DEDICATED <<
  218. SCFG_USBPWRFAULT_USB2_SHIFT) |
  219. (SCFG_USBPWRFAULT_SHARED <<
  220. SCFG_USBPWRFAULT_USB1_SHIFT);
  221. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  222. #endif
  223. }
  224. return 0;
  225. }
  226. #if defined(CONFIG_MISC_INIT_R)
  227. int misc_init_r(void)
  228. {
  229. config_board_mux();
  230. return 0;
  231. }
  232. #endif
  233. void fdt_del_qe(void *blob)
  234. {
  235. int nodeoff = 0;
  236. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  237. "fsl,qe")) >= 0) {
  238. fdt_del_node(blob, nodeoff);
  239. }
  240. }
  241. int ft_board_setup(void *blob, bd_t *bd)
  242. {
  243. u64 base[CONFIG_NR_DRAM_BANKS];
  244. u64 size[CONFIG_NR_DRAM_BANKS];
  245. /* fixup DT for the two DDR banks */
  246. base[0] = gd->bd->bi_dram[0].start;
  247. size[0] = gd->bd->bi_dram[0].size;
  248. base[1] = gd->bd->bi_dram[1].start;
  249. size[1] = gd->bd->bi_dram[1].size;
  250. fdt_fixup_memory_banks(blob, base, size, 2);
  251. ft_cpu_setup(blob, bd);
  252. #ifdef CONFIG_SYS_DPAA_FMAN
  253. #ifndef CONFIG_DM_ETH
  254. fdt_fixup_fman_ethernet(blob);
  255. #endif
  256. #endif
  257. fdt_fixup_icid(blob);
  258. /*
  259. * qe-hdlc and usb multi-use the pins,
  260. * when set hwconfig to qe-hdlc, delete usb node.
  261. */
  262. if (hwconfig("qe-hdlc"))
  263. #ifdef CONFIG_HAS_FSL_XHCI_USB
  264. fdt_del_node_and_alias(blob, "usb1");
  265. #endif
  266. /*
  267. * qe just support qe-uart and qe-hdlc,
  268. * if qe-uart and qe-hdlc are not set in hwconfig,
  269. * delete qe node.
  270. */
  271. if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
  272. fdt_del_qe(blob);
  273. return 0;
  274. }
  275. u8 flash_read8(void *addr)
  276. {
  277. return __raw_readb(addr + 1);
  278. }
  279. void flash_write16(u16 val, void *addr)
  280. {
  281. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  282. __raw_writew(shftval, addr);
  283. }
  284. u16 flash_read16(void *addr)
  285. {
  286. u16 val = __raw_readw(addr);
  287. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  288. }
  289. #endif