soc.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017-2019 NXP
  4. * Copyright 2015 Freescale Semiconductor
  5. */
  6. #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
  7. #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
  8. #ifndef __ASSEMBLY__
  9. #include <linux/types.h>
  10. #ifdef CONFIG_FSL_LSCH2
  11. #include <asm/arch/immap_lsch2.h>
  12. #endif
  13. #ifdef CONFIG_FSL_LSCH3
  14. #include <asm/arch/immap_lsch3.h>
  15. #endif
  16. #endif
  17. #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
  18. #define gur_in32(a) in_le32(a)
  19. #define gur_out32(a, v) out_le32(a, v)
  20. #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
  21. #define gur_in32(a) in_be32(a)
  22. #define gur_out32(a, v) out_be32(a, v)
  23. #endif
  24. #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
  25. #define scfg_in32(a) in_le32(a)
  26. #define scfg_out32(a, v) out_le32(a, v)
  27. #define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
  28. #define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
  29. #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
  30. #define scfg_in32(a) in_be32(a)
  31. #define scfg_out32(a, v) out_be32(a, v)
  32. #define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
  33. #define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
  34. #endif
  35. #ifdef CONFIG_SYS_FSL_PEX_LUT_LE
  36. #define pex_lut_in32(a) in_le32(a)
  37. #define pex_lut_out32(a, v) out_le32(a, v)
  38. #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
  39. #define pex_lut_in32(a) in_be32(a)
  40. #define pex_lut_out32(a, v) out_be32(a, v)
  41. #endif
  42. #ifndef __ASSEMBLY__
  43. struct cpu_type {
  44. char name[15];
  45. u32 soc_ver;
  46. u32 num_cores;
  47. };
  48. #define CPU_TYPE_ENTRY(n, v, nc) \
  49. { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
  50. #ifdef CONFIG_TFABOOT
  51. #define SMC_DRAM_BANK_INFO (0xC200FF12)
  52. #define SIP_SVC_RCW 0xC200FF18
  53. phys_size_t tfa_get_dram_size(void);
  54. enum boot_src {
  55. BOOT_SOURCE_RESERVED = 0,
  56. BOOT_SOURCE_IFC_NOR,
  57. BOOT_SOURCE_IFC_NAND,
  58. BOOT_SOURCE_QSPI_NOR,
  59. BOOT_SOURCE_QSPI_NAND,
  60. BOOT_SOURCE_XSPI_NOR,
  61. BOOT_SOURCE_XSPI_NAND,
  62. BOOT_SOURCE_SD_MMC,
  63. BOOT_SOURCE_SD_MMC2,
  64. BOOT_SOURCE_I2C1_EXTENDED,
  65. };
  66. enum boot_src get_boot_src(void);
  67. #endif
  68. #endif
  69. #define SVR_WO_E 0xFFFFFE
  70. #define SVR_LS1012A 0x870400
  71. #define SVR_LS1043A 0x879200
  72. #define SVR_LS1023A 0x879208
  73. /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
  74. #define SVR_LS1043A_P23 0x879202
  75. #define SVR_LS1023A_P23 0x87920A
  76. #define SVR_LS1017A 0x870B24
  77. #define SVR_LS1018A 0x870B20
  78. #define SVR_LS1027A 0x870B04
  79. #define SVR_LS1028A 0x870B00
  80. #define SVR_LS1046A 0x870700
  81. #define SVR_LS1026A 0x870708
  82. #define SVR_LS1048A 0x870320
  83. #define SVR_LS1084A 0x870302
  84. #define SVR_LS1088A 0x870300
  85. #define SVR_LS1044A 0x870322
  86. #define SVR_LS2045A 0x870120
  87. #define SVR_LS2080A 0x870110
  88. #define SVR_LS2085A 0x870100
  89. #define SVR_LS2040A 0x870130
  90. #define SVR_LS2088A 0x870900
  91. #define SVR_LS2084A 0x870910
  92. #define SVR_LS2048A 0x870920
  93. #define SVR_LS2044A 0x870930
  94. #define SVR_LS2081A 0x870918
  95. #define SVR_LS2041A 0x870914
  96. #define SVR_LX2160A 0x873600
  97. #define SVR_LX2120A 0x873620
  98. #define SVR_LX2080A 0x873602
  99. #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
  100. #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
  101. #define SVR_REV(svr) (((svr) >> 0) & 0xff)
  102. #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
  103. #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
  104. #ifdef CONFIG_ARCH_LX2160A
  105. #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
  106. #endif
  107. #ifdef CONFIG_ARCH_LS1028A
  108. #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1))
  109. #endif
  110. #define IS_SVR_REV(svr, maj, min) \
  111. ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
  112. #define SVR_DEV(svr) ((svr) >> 8)
  113. #define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
  114. #ifndef __ASSEMBLY__
  115. #ifdef CONFIG_FSL_LSCH3
  116. void fsl_lsch3_early_init_f(void);
  117. int get_core_volt_from_fuse(void);
  118. #elif defined(CONFIG_FSL_LSCH2)
  119. void fsl_lsch2_early_init_f(void);
  120. int setup_chip_volt(void);
  121. /* Setup core vdd in unit mV */
  122. int board_setup_core_volt(u32 vdd);
  123. #ifdef CONFIG_FSL_PFE
  124. void init_pfe_scfg_dcfg_regs(void);
  125. #endif
  126. #endif
  127. #ifdef CONFIG_QSPI_AHB_INIT
  128. int qspi_ahb_init(void);
  129. #endif
  130. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  131. #define SYS_NXP_FSPI_LUTCR_LOCK 0x00000001
  132. #define SYS_NXP_FSPI_LUTCR_UNLOCK 0x00000002
  133. #define SYS_NXP_FSPI_LUTKEY 0x5AF05AF0
  134. int fspi_ahb_init(void);
  135. #endif
  136. void cpu_name(char *name);
  137. #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  138. void erratum_a009635(void);
  139. #endif
  140. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  141. void erratum_a010315(void);
  142. #endif
  143. bool soc_has_dp_ddr(void);
  144. bool soc_has_aiop(void);
  145. #ifdef CONFIG_GIC_V3_ITS
  146. int ls_gic_rd_tables_init(void *blob);
  147. #endif
  148. #endif
  149. #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */