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ARM Packages: Removed trailing spaces

Trailing spaces create issue/warning when generating/applying patches.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
Ronald Cron 9 lat temu
rodzic
commit
3402aac7d9
100 zmienionych plików z 1015 dodań i 1018 usunięć
  1. 7 7
      ArmPkg/Application/LinuxLoader/LinuxAtagLoader.inf
  2. 7 7
      ArmPkg/Application/LinuxLoader/LinuxFdtLoader.inf
  3. 5 5
      ArmPkg/ArmPkg.dsc
  4. 7 7
      ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf
  5. 7 7
      ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
  6. 7 7
      ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
  7. 7 7
      ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
  8. 1 1
      ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
  9. 17 17
      ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S
  10. 12 12
      ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm
  11. 9 9
      ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c
  12. 37 37
      ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S
  13. 39 39
      ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm
  14. 16 16
      ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c
  15. 23 23
      ArmPkg/Drivers/CpuDxe/CpuDxe.c
  16. 7 7
      ArmPkg/Drivers/CpuDxe/CpuDxe.h
  17. 5 5
      ArmPkg/Drivers/CpuDxe/CpuDxe.inf
  18. 9 9
      ArmPkg/Drivers/CpuPei/CpuPei.c
  19. 2 2
      ArmPkg/Drivers/CpuPei/CpuPei.inf
  20. 31 31
      ArmPkg/Drivers/TimerDxe/TimerDxe.c
  21. 9 10
      ArmPkg/Drivers/TimerDxe/TimerDxe.inf
  22. 17 17
      ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c
  23. 8 8
      ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
  24. 4 4
      ArmPkg/Include/AsmMacroIoLib.h
  25. 56 56
      ArmPkg/Include/AsmMacroIoLib.inc
  26. 1 1
      ArmPkg/Include/Chipset/ARM926EJ-S.h
  27. 7 7
      ArmPkg/Include/Chipset/ArmArchTimer.h
  28. 1 1
      ArmPkg/Include/Chipset/ArmV7.h
  29. 7 7
      ArmPkg/Include/Chipset/ArmV7Mmu.h
  30. 7 7
      ArmPkg/Include/Guid/ArmMpCoreInfo.h
  31. 10 10
      ArmPkg/Include/Library/ArmDisassemblerLib.h
  32. 15 15
      ArmPkg/Include/Library/ArmLib.h
  33. 2 2
      ArmPkg/Include/Library/DefaultExceptionHandlerLib.h
  34. 3 3
      ArmPkg/Include/Library/SemihostLib.h
  35. 6 6
      ArmPkg/Include/Library/UncachedMemoryAllocationLib.h
  36. 2 2
      ArmPkg/Include/Protocol/VirtualUncachedPages.h
  37. 9 9
      ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
  38. 2 2
      ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
  39. 51 51
      ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c
  40. 142 142
      ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c
  41. 38 38
      ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
  42. 10 10
      ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
  43. 1 1
      ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c
  44. 3 3
      ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf
  45. 7 7
      ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c
  46. 3 3
      ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf
  47. 2 2
      ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf
  48. 11 11
      ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
  49. 10 10
      ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
  50. 2 2
      ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
  51. 1 1
      ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
  52. 11 11
      ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
  53. 8 8
      ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
  54. 10 10
      ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
  55. 8 8
      ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
  56. 7 7
      ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
  57. 7 7
      ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
  58. 7 7
      ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
  59. 1 1
      ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S
  60. 1 1
      ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm
  61. 24 24
      ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
  62. 1 1
      ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h
  63. 3 3
      ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
  64. 4 4
      ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
  65. 9 9
      ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
  66. 16 16
      ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
  67. 21 21
      ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
  68. 23 23
      ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
  69. 3 3
      ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
  70. 4 4
      ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
  71. 1 1
      ArmPkg/Library/ArmLib/Common/ArmLib.c
  72. 3 3
      ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
  73. 10 10
      ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c
  74. 1 1
      ArmPkg/Library/ArmLib/Null/NullArmLib.c
  75. 5 5
      ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
  76. 3 3
      ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.inf
  77. 25 25
      ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S
  78. 25 25
      ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm
  79. 10 10
      ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S
  80. 10 10
      ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm
  81. 4 4
      ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
  82. 2 2
      ArmPkg/Library/BaseMemoryLibStm/CompareMemWrapper.c
  83. 2 2
      ArmPkg/Library/BaseMemoryLibStm/CopyMemWrapper.c
  84. 4 4
      ArmPkg/Library/BaseMemoryLibStm/MemLibGuid.c
  85. 1 1
      ArmPkg/Library/BaseMemoryLibStm/ScanMem16Wrapper.c
  86. 1 1
      ArmPkg/Library/BaseMemoryLibStm/ScanMem32Wrapper.c
  87. 1 1
      ArmPkg/Library/BaseMemoryLibStm/ScanMem64Wrapper.c
  88. 4 4
      ArmPkg/Library/BaseMemoryLibStm/ScanMem8Wrapper.c
  89. 1 1
      ArmPkg/Library/BaseMemoryLibStm/SetMemWrapper.c
  90. 2 2
      ArmPkg/Library/BaseMemoryLibStm/ZeroMemWrapper.c
  91. 5 5
      ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.S
  92. 5 5
      ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm
  93. 2 3
      ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S
  94. 4 5
      ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm
  95. 4 4
      ArmPkg/Library/BaseMemoryLibVstm/BaseMemoryLibVstm.inf
  96. 2 2
      ArmPkg/Library/BaseMemoryLibVstm/CompareMemWrapper.c
  97. 2 2
      ArmPkg/Library/BaseMemoryLibVstm/CopyMemWrapper.c
  98. 4 4
      ArmPkg/Library/BaseMemoryLibVstm/MemLibGuid.c
  99. 1 1
      ArmPkg/Library/BaseMemoryLibVstm/ScanMem16Wrapper.c
  100. 1 1
      ArmPkg/Library/BaseMemoryLibVstm/ScanMem32Wrapper.c

+ 7 - 7
ArmPkg/Application/LinuxLoader/LinuxAtagLoader.inf

@@ -1,13 +1,13 @@
 #/* @file
 #  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-#  
-#  This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http://opensource.org/licenses/bsd-license.php                                            
 #
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 #*/
 

+ 7 - 7
ArmPkg/Application/LinuxLoader/LinuxFdtLoader.inf

@@ -1,13 +1,13 @@
 #/* @file
 #  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-#  
-#  This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http://opensource.org/licenses/bsd-license.php                                            
 #
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 #*/
 

+ 5 - 5
ArmPkg/ArmPkg.dsc

@@ -31,13 +31,13 @@
 
 [BuildOptions]
   XCODE:*_*_ARM_PLATFORM_FLAGS  == -arch armv7
-  XCODE:RELEASE_*_*_CC_FLAGS     = -DMDEPKG_NDEBUG 
-  
+  XCODE:RELEASE_*_*_CC_FLAGS     = -DMDEPKG_NDEBUG
+
   GCC:*_*_ARM_PLATFORM_FLAGS    == -march=armv7-a -mfpu=neon
-  GCC:RELEASE_*_*_CC_FLAGS     = -DMDEPKG_NDEBUG 
+  GCC:RELEASE_*_*_CC_FLAGS     = -DMDEPKG_NDEBUG
 
   RVCT:*_*_ARM_PLATFORM_FLAGS  == --cpu Cortex-A8
-  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG 
+  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
 
 [LibraryClasses.common]
   BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
@@ -74,7 +74,7 @@
 
   BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
   FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
-  
+
   IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
 
 [LibraryClasses.ARM]

+ 7 - 7
ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf

@@ -1,13 +1,13 @@
 #/* @file
 #  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-#  
-#  This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http://opensource.org/licenses/bsd-license.php                                            
 #
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 #*/
 

+ 7 - 7
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf

@@ -1,13 +1,13 @@
 #/* @file
 #  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-#  
-#  This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http://opensource.org/licenses/bsd-license.php                                            
 #
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 #*/
 

+ 7 - 7
ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf

@@ -1,13 +1,13 @@
 #/* @file
 #  Copyright (c) 2011, ARM Limited. All rights reserved.
-#  
-#  This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http://opensource.org/licenses/bsd-license.php                                            
 #
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 #*/
 

+ 7 - 7
ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf

@@ -1,13 +1,13 @@
 #/* @file
 #  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-#  
-#  This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http://opensource.org/licenses/bsd-license.php                                            
 #
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 #*/
 

+ 1 - 1
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf

@@ -16,7 +16,7 @@
 [Defines]
   INF_VERSION                    = 0x00010005
   BASE_NAME                      = ArmGicDxe
-  FILE_GUID                      = DE371F7C-DEC4-4D21-ADF1-593ABCC15882 
+  FILE_GUID                      = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
   MODULE_TYPE                    = DXE_DRIVER
   VERSION_STRING                 = 1.0
 

+ 17 - 17
ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 #
@@ -52,7 +52,7 @@ ASM_PFX(ResetEntry):
   stmfd     SP!,{LR}                  @ Store the link register for the current mode
   sub       SP,SP,#0x20               @ Save space for SP, LR, PC, IFAR - CPSR
   stmfd     SP!,{R0-R12}              @ Store the register state
-  
+
   mov       R0,#0
   ldr       R1,ASM_PFX(CommonExceptionEntry)
   bx        R1
@@ -147,18 +147,18 @@ ASM_PFX(ExceptionHandlersEnd):
 
 ASM_PFX(AsmCommonExceptionEntry):
   mrc       p15, 0, R1, c6, c0, 2   @ Read IFAR
-  str       R1, [SP, #0x50]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR 
-  
+  str       R1, [SP, #0x50]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
+
   mrc       p15, 0, R1, c5, c0, 1   @ Read IFSR
   str       R1, [SP, #0x4c]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
-  
+
   mrc       p15, 0, R1, c6, c0, 0   @ Read DFAR
   str       R1, [SP, #0x48]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
-  
+
   mrc       p15, 0, R1, c5, c0, 0   @ Read DFSR
   str       R1, [SP, #0x44]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
-  
-  ldr       R1, [SP, #0x5c]         @ srsdb saved pre-exception CPSR on the stack 
+
+  ldr       R1, [SP, #0x5c]         @ srsdb saved pre-exception CPSR on the stack
   str       R1, [SP, #0x40]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
   and       r1, r1, #0x1f           @ Check to see if User or System Mode
   cmp       r1, #0x1f
@@ -167,25 +167,25 @@ ASM_PFX(AsmCommonExceptionEntry):
   ldmneed   r2, {lr}^               @ User or System mode, use unbanked register
   ldmneed   r2, {lr}                @ All other modes used banked register
 
-  ldr       R1, [SP, #0x58]         @ PC is the LR pushed by srsdb 
+  ldr       R1, [SP, #0x58]         @ PC is the LR pushed by srsdb
   str       R1, [SP, #0x3c]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
-  
-  sub       R1, SP, #0x60           @ We pused 0x60 bytes on the stack 
+
+  sub       R1, SP, #0x60           @ We pused 0x60 bytes on the stack
   str       R1, [SP, #0x34]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
-  
-                                              @ R0 is exception type 
+
+                                              @ R0 is exception type
   mov       R1,SP                             @ Prepare System Context pointer as an argument for the exception handler
   blx       ASM_PFX(CommonCExceptionHandler)  @ Call exception handler
-  
+
   ldr       R2,[SP,#0x40]           @ EFI_SYSTEM_CONTEXT_ARM.CPSR
-  str       R2,[SP,#0x5c]           @ Store it back to srsdb stack slot so it can be restored 
+  str       R2,[SP,#0x5c]           @ Store it back to srsdb stack slot so it can be restored
 
   ldr       R2,[SP,#0x3c]           @ EFI_SYSTEM_CONTEXT_ARM.PC
-  str       R2,[SP,#0x58]           @ Store it back to srsdb stack slot so it can be restored 
+  str       R2,[SP,#0x58]           @ Store it back to srsdb stack slot so it can be restored
 
   ldmfd     SP!,{R0-R12}            @ Restore general purpose registers
                                     @ Exception handler can not change SP or LR as we would blow chunks
-                                    
+
   add       SP,SP,#0x20             @ Clear out the remaining stack space
   ldmfd     SP!,{LR}                @ restore the link register for this context
   rfefd     SP!                     @ return from exception via srsdb stack slot

+ 12 - 12
ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm

@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ 
+//------------------------------------------------------------------------------
 //
 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 //
@@ -20,7 +20,7 @@
 
   PRESERVE8
   AREA  DxeExceptionHandlers, CODE, READONLY
-  
+
 ExceptionHandlersStart
 
 Reset
@@ -107,35 +107,35 @@ ExceptionHandlersEnd
 AsmCommonExceptionEntry
   mrc       p15, 0, r1, c6, c0, 2   ; Read IFAR
   stmfd     SP!,{R1}                ; Store the IFAR
-  
+
   mrc       p15, 0, r1, c5, c0, 1   ; Read IFSR
   stmfd     SP!,{R1}                ; Store the IFSR
-  
+
   mrc       p15, 0, r1, c6, c0, 0   ; Read DFAR
   stmfd     SP!,{R1}                ; Store the DFAR
-  
+
   mrc       p15, 0, r1, c5, c0, 0   ; Read DFSR
   stmfd     SP!,{R1}                ; Store the DFSR
-  
+
   mrs       R1,SPSR                 ; Read SPSR (which is the pre-exception CPSR)
   stmfd     SP!,{R1}                ; Store the SPSR
-  
+
   stmfd     SP!,{LR}                ; Store the link register (which is the pre-exception PC)
   stmfd     SP,{SP,LR}^             ; Store user/system mode stack pointer and link register
   nop                               ; Required by ARM architecture
   SUB       SP,SP,#0x08             ; Adjust stack pointer
   stmfd     SP!,{R2-R12}            ; Store general purpose registers
-  
+
   ldr       R3,[SP,#0x50]           ; Read saved R1 from the stack (it was saved by the exception entry routine)
   ldr       R2,[SP,#0x4C]           ; Read saved R0 from the stack (it was saved by the exception entry routine)
   stmfd     SP!,{R2-R3}             ; Store general purpose registers R0 and R1
-  
+
   mov       R1,SP                   ; Prepare System Context pointer as an argument for the exception handler
-  
+
   sub       SP,SP,#4                ; Adjust SP to preserve 8-byte alignment
   blx       CommonCExceptionHandler ; Call exception handler
   add       SP,SP,#4                ; Adjust SP back to where we were
-  
+
   ldr       R2,[SP,#0x40]           ; Load CPSR from context, in case it has changed
   MSR       SPSR_cxsf,R2            ; Store it back to the SPSR to be restored when exiting this handler
 
@@ -146,7 +146,7 @@ AsmCommonExceptionEntry
   ldmfd     SP!,{LR}                ; Restore the link register (which is the pre-exception PC)
   add       SP,SP,#0x1C             ; Clear out the remaining stack space
   movs      PC,LR                   ; Return from exception
-  
+
   END
 
 

+ 9 - 9
ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c

@@ -2,7 +2,7 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2014, ARM Limited. All rights reserved.<BR>
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -13,7 +13,7 @@
 
 **/
 
-#include "CpuDxe.h" 
+#include "CpuDxe.h"
 
 //FIXME: Will not compile on non-ARMv7 builds
 #include <Chipset/ArmV7.h>
@@ -45,9 +45,9 @@ EFI_EXCEPTION_CALLBACK  gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1];
 
 
 /**
-  This function registers and enables the handler specified by InterruptHandler for a processor 
-  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
-  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
+  This function registers and enables the handler specified by InterruptHandler for a processor
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
   The installed handler is called once for each processor interrupt or exception.
 
   @param  InterruptType    A pointer to the processor's current interrupt state. Set to TRUE if interrupts
@@ -102,7 +102,7 @@ CommonCExceptionHandler (
     DEBUG ((EFI_D_ERROR, "Unknown exception type %d from %08x\n", ExceptionType, SystemContext.SystemContextArm->PC));
     ASSERT (FALSE);
   }
-  
+
   if (ExceptionType == EXCEPT_ARM_SOFTWARE_INTERRUPT) {
     //
     // ARM JTAG debuggers some times use this vector, so it is not an error to get one
@@ -139,8 +139,8 @@ InitializeExceptions (
   Cpu->DisableInterrupt (Cpu);
 
   //
-  // EFI does not use the FIQ, but a debugger might so we must disable 
-  // as we take over the exception vectors. 
+  // EFI does not use the FIQ, but a debugger might so we must disable
+  // as we take over the exception vectors.
   //
   FiqEnabled = ArmGetFiqState ();
   ArmDisableFiq ();
@@ -224,7 +224,7 @@ InitializeExceptions (
   }
 
   if (IrqEnabled) {
-    // 
+    //
     // Restore interrupt state
     //
     Status = Cpu->EnableInterrupt (Cpu);

+ 37 - 37
ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # Use ARMv6 instruction to operate on a single stack
 #
@@ -22,7 +22,7 @@
 This is the stack constructed by the exception handler (low address to high address)
                 # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
   Reg   Offset
-  ===   ======              
+  ===   ======
   R0    0x00    # stmfd     SP!,{R0-R12}
   R1    0x04
   R2    0x08
@@ -44,14 +44,14 @@ This is the stack constructed by the exception handler (low address to high addr
   DFAR  0x48
   IFSR  0x4c
   IFAR  0x50
-  
+
   LR    0x54    # SVC Link register (we need to restore it)
-  
-  LR    0x58    # pushed by srsfd    
-  CPSR  0x5c    
+
+  LR    0x58    # pushed by srsfd
+  CPSR  0x5c
 
  */
- 
+
 
 GCC_ASM_EXPORT(ExceptionHandlersStart)
 GCC_ASM_EXPORT(ExceptionHandlersEnd)
@@ -103,7 +103,7 @@ ASM_PFX(ResetEntry):
   stmfd     SP!,{LR}                  @ Store the link register for the current mode
   sub       SP,SP,#0x20               @ Save space for SP, LR, PC, IFAR - CPSR
   stmfd     SP!,{R0-R12}              @ Store the register state
-  
+
   mov       R0,#0                     @ ExceptionType
   ldr       R1,ASM_PFX(CommonExceptionEntry)
   bx        R1
@@ -200,53 +200,53 @@ ASM_PFX(CommonExceptionEntry):
 ASM_PFX(ExceptionHandlersEnd):
 
 //
-// This code runs from CpuDxe driver loaded address. It is patched into 
+// This code runs from CpuDxe driver loaded address. It is patched into
 // CommonExceptionEntry.
 //
 ASM_PFX(AsmCommonExceptionEntry):
   mrc       p15, 0, R1, c6, c0, 2   @ Read IFAR
-  str       R1, [SP, #0x50]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR 
-  
+  str       R1, [SP, #0x50]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
+
   mrc       p15, 0, R1, c5, c0, 1   @ Read IFSR
   str       R1, [SP, #0x4c]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
-  
+
   mrc       p15, 0, R1, c6, c0, 0   @ Read DFAR
   str       R1, [SP, #0x48]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
-  
+
   mrc       p15, 0, R1, c5, c0, 0   @ Read DFSR
   str       R1, [SP, #0x44]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
-  
-  ldr       R1, [SP, #0x5c]         @ srsdb saved pre-exception CPSR on the stack 
+
+  ldr       R1, [SP, #0x5c]         @ srsdb saved pre-exception CPSR on the stack
   str       R1, [SP, #0x40]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
 
   add       R2, SP, #0x38           @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
   and       R3, R1, #0x1f           @ Check CPSR to see if User or System Mode
   cmp       R3, #0x1f               @ if ((CPSR == 0x10) || (CPSR == 0x1f))
-  cmpne     R3, #0x10               @   
+  cmpne     R3, #0x10               @
   stmeqed   R2, {lr}^               @   save unbanked lr
-                                    @ else 
+                                    @ else
   stmneed   R2, {lr}                @   save SVC lr
 
 
-  ldr       R5, [SP, #0x58]         @ PC is the LR pushed by srsfd 
+  ldr       R5, [SP, #0x58]         @ PC is the LR pushed by srsfd
                                     @ Check to see if we have to adjust for Thumb entry
   sub       r4, r0, #1              @ if (ExceptionType == 1 || ExceptionType == 2)) {
-  cmp       r4, #1                  @   // UND & SVC have differnt LR adjust for Thumb 
+  cmp       r4, #1                  @   // UND & SVC have differnt LR adjust for Thumb
   bhi       NoAdjustNeeded
-  
-  tst       r1, #0x20               @   if ((CPSR & T)) == T) {  // Thumb Mode on entry 
+
+  tst       r1, #0x20               @   if ((CPSR & T)) == T) {  // Thumb Mode on entry
   addne     R5, R5, #2              @     PC += 2;
   strne     R5,[SP,#0x58]           @ Update LR value pushed by srsfd
-  
+
 NoAdjustNeeded:
 
   str       R5, [SP, #0x3c]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
-  
+
   add       R1, SP, #0x60           @ We pushed 0x60 bytes on the stack
   str       R1, [SP, #0x34]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
-  
-                                    @ R0 is ExceptionType 
-  mov       R1,SP                   @ R1 is SystemContext 
+
+                                    @ R0 is ExceptionType
+  mov       R1,SP                   @ R1 is SystemContext
 
 #if (FixedPcdGet32(PcdVFPEnabled))
   vpush     {d0-d15}                @ save vstm registers in case they are used in optimizations
@@ -256,7 +256,7 @@ NoAdjustNeeded:
   tst       R4, #4
   subne     SP, SP, #4              @ Adjust SP if not 8-byte aligned
 
-/* 
+/*
 VOID
 EFIAPI
 CommonCExceptionHandler (
@@ -264,13 +264,13 @@ CommonCExceptionHandler (
   IN OUT EFI_SYSTEM_CONTEXT           SystemContext    R1
   )
 
-*/  
+*/
   blx       ASM_PFX(CommonCExceptionHandler)  @ Call exception handler
 
   mov       SP, R4                  @ Restore SP
 
 #if (FixedPcdGet32(PcdVFPEnabled))
-  vpop      {d0-d15}  
+  vpop      {d0-d15}
 #endif
 
   ldr       R1, [SP, #0x4c]         @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
@@ -278,26 +278,26 @@ CommonCExceptionHandler (
 
   ldr       R1, [SP, #0x44]         @ Restore EFI_SYSTEM_CONTEXT_ARM.DFSR
   mcr       p15, 0, R1, c5, c0, 0   @ Write DFSR
-  
+
   ldr       R1,[SP,#0x3c]           @ EFI_SYSTEM_CONTEXT_ARM.PC
-  str       R1,[SP,#0x58]           @ Store it back to srsfd stack slot so it can be restored 
+  str       R1,[SP,#0x58]           @ Store it back to srsfd stack slot so it can be restored
 
   ldr       R1,[SP,#0x40]           @ EFI_SYSTEM_CONTEXT_ARM.CPSR
-  str       R1,[SP,#0x5c]           @ Store it back to srsfd stack slot so it can be restored 
-  
+  str       R1,[SP,#0x5c]           @ Store it back to srsfd stack slot so it can be restored
+
   add       R3, SP, #0x54           @ Make R3 point to SVC LR saved on entry
   add       R2, SP, #0x38           @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
   and       R1, R1, #0x1f           @ Check to see if User or System Mode
   cmp       R1, #0x1f               @ if ((CPSR == 0x10) || (CPSR == 0x1f))
-  cmpne     R1, #0x10               @   
+  cmpne     R1, #0x10               @
   ldmeqed   R2, {lr}^               @   restore unbanked lr
                                     @ else
   ldmneed   R3, {lr}                @   restore SVC lr, via ldmfd SP!, {LR}
-  
+
   ldmfd     SP!,{R0-R12}            @ Restore general purpose registers
                                     @ Exception handler can not change SP
-                                    
+
   add       SP,SP,#0x20             @ Clear out the remaining stack space
   ldmfd     SP!,{LR}                @ restore the link register for this context
   rfefd     SP!                     @ return from exception via srsfd stack slot
-  
+

+ 39 - 39
ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm

@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ 
+//------------------------------------------------------------------------------
 //
 // Use ARMv6 instruction to operate on a single stack
 //
@@ -22,7 +22,7 @@
 This is the stack constructed by the exception handler (low address to high address)
                 # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
   Reg   Offset
-  ===   ======              
+  ===   ======
   R0    0x00    # stmfd     SP!,{R0-R12}
   R1    0x04
   R2    0x08
@@ -44,15 +44,15 @@ This is the stack constructed by the exception handler (low address to high addr
   DFAR  0x48
   IFSR  0x4c
   IFAR  0x50
-  
+
   LR    0x54    # SVC Link register (we need to restore it)
-  
-  LR    0x58    # pushed by srsfd    
-  CPSR  0x5c    
+
+  LR    0x58    # pushed by srsfd
+  CPSR  0x5c
 
  */
- 
- 
+
+
   EXPORT  ExceptionHandlersStart
   EXPORT  ExceptionHandlersEnd
   EXPORT  CommonExceptionEntry
@@ -61,7 +61,7 @@ This is the stack constructed by the exception handler (low address to high addr
 
   PRESERVE8
   AREA  DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5
-  
+
 //
 // This code gets copied to the ARM vector table
 // ExceptionHandlersStart - ExceptionHandlersEnd gets copied
@@ -98,7 +98,7 @@ ResetEntry
   stmfd     SP!,{LR}                  ; Store the link register for the current mode
   sub       SP,SP,#0x20               ; Save space for SP, LR, PC, IFAR - CPSR
   stmfd     SP!,{R0-R12}              ; Store the register state
-  
+
   mov       R0,#0                     ; ExceptionType
   ldr       R1,CommonExceptionEntry
   bx        R1
@@ -112,7 +112,7 @@ UndefinedInstructionEntry
   stmfd     SP!,{R0-R12}              ; Store the register state
 
   mov       R0,#1                     ; ExceptionType
-  ldr       R1,CommonExceptionEntry; 
+  ldr       R1,CommonExceptionEntry;
   bx        R1
 
 SoftwareInterruptEntry
@@ -195,53 +195,53 @@ CommonExceptionEntry
 ExceptionHandlersEnd
 
 //
-// This code runs from CpuDxe driver loaded address. It is patched into 
+// This code runs from CpuDxe driver loaded address. It is patched into
 // CommonExceptionEntry.
 //
 AsmCommonExceptionEntry
   mrc       p15, 0, R1, c6, c0, 2   ; Read IFAR
-  str       R1, [SP, #0x50]         ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR 
-  
+  str       R1, [SP, #0x50]         ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
+
   mrc       p15, 0, R1, c5, c0, 1   ; Read IFSR
   str       R1, [SP, #0x4c]         ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
-  
+
   mrc       p15, 0, R1, c6, c0, 0   ; Read DFAR
   str       R1, [SP, #0x48]         ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
-  
+
   mrc       p15, 0, R1, c5, c0, 0   ; Read DFSR
   str       R1, [SP, #0x44]         ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
-  
-  ldr       R1, [SP, #0x5c]         ; srsfd saved pre-exception CPSR on the stack 
+
+  ldr       R1, [SP, #0x5c]         ; srsfd saved pre-exception CPSR on the stack
   str       R1, [SP, #0x40]         ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
 
   add       R2, SP, #0x38           ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
   and       R3, R1, #0x1f           ; Check CPSR to see if User or System Mode
   cmp       R3, #0x1f               ; if ((CPSR == 0x10) || (CPSR == 0x1f))
-  cmpne     R3, #0x10               ;   
+  cmpne     R3, #0x10               ;
   stmeqed   R2, {lr}^               ;   save unbanked lr
-                                    ; else 
+                                    ; else
   stmneed   R2, {lr}                ;   save SVC lr
 
 
-  ldr       R5, [SP, #0x58]         ; PC is the LR pushed by srsfd 
+  ldr       R5, [SP, #0x58]         ; PC is the LR pushed by srsfd
                                     ; Check to see if we have to adjust for Thumb entry
   sub       r4, r0, #1              ; if (ExceptionType == 1 || ExceptionType == 2)) {
-  cmp       r4, #1                  ;   // UND & SVC have differnt LR adjust for Thumb 
+  cmp       r4, #1                  ;   // UND & SVC have differnt LR adjust for Thumb
   bhi       NoAdjustNeeded
-  
-  tst       r1, #0x20               ;   if ((CPSR & T)) == T) {  // Thumb Mode on entry 
+
+  tst       r1, #0x20               ;   if ((CPSR & T)) == T) {  // Thumb Mode on entry
   addne     R5, R5, #2              ;     PC += 2;
   strne     R5,[SP,#0x58]           ; Update LR value pushed by srsfd
-  
+
 NoAdjustNeeded
 
   str       R5, [SP, #0x3c]         ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC
-  
+
   add       R1, SP, #0x60           ; We pushed 0x60 bytes on the stack
   str       R1, [SP, #0x34]         ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP
-  
-                                    ; R0 is ExceptionType 
-  mov       R1,SP                   ; R1 is SystemContext 
+
+                                    ; R0 is ExceptionType
+  mov       R1,SP                   ; R1 is SystemContext
 
 #if (FixedPcdGet32(PcdVFPEnabled))
   vpush    {d0-d15}                 ; save vstm registers in case they are used in optimizations
@@ -251,7 +251,7 @@ NoAdjustNeeded
   tst       R4, #4
   subne     SP, SP, #4              ; Adjust SP if not 8-byte aligned
 
-/* 
+/*
 VOID
 EFIAPI
 CommonCExceptionHandler (
@@ -267,35 +267,35 @@ CommonCExceptionHandler (
 #if (FixedPcdGet32(PcdVFPEnabled))
   vpop      {d0-d15}
 #endif
-  
+
   ldr       R1, [SP, #0x4c]         ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
   mcr       p15, 0, R1, c5, c0, 1   ; Write IFSR
 
   ldr       R1, [SP, #0x44]         ; Restore EFI_SYSTEM_CONTEXT_ARM.DFSR
   mcr       p15, 0, R1, c5, c0, 0   ; Write DFSR
-  
+
   ldr       R1,[SP,#0x3c]           ; EFI_SYSTEM_CONTEXT_ARM.PC
-  str       R1,[SP,#0x58]           ; Store it back to srsfd stack slot so it can be restored 
+  str       R1,[SP,#0x58]           ; Store it back to srsfd stack slot so it can be restored
 
   ldr       R1,[SP,#0x40]           ; EFI_SYSTEM_CONTEXT_ARM.CPSR
-  str       R1,[SP,#0x5c]           ; Store it back to srsfd stack slot so it can be restored 
-  
+  str       R1,[SP,#0x5c]           ; Store it back to srsfd stack slot so it can be restored
+
   add       R3, SP, #0x54           ; Make R3 point to SVC LR saved on entry
   add       R2, SP, #0x38           ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
   and       R1, R1, #0x1f           ; Check to see if User or System Mode
   cmp       R1, #0x1f               ; if ((CPSR == 0x10) || (CPSR == 0x1f))
-  cmpne     R1, #0x10               ;   
+  cmpne     R1, #0x10               ;
   ldmeqed   R2, {lr}^               ;   restore unbanked lr
                                     ; else
   ldmneed   R3, {lr}                ;   restore SVC lr, via ldmfd SP!, {LR}
-  
+
   ldmfd     SP!,{R0-R12}            ; Restore general purpose registers
                                     ; Exception handler can not change SP
-                                    
+
   add       SP,SP,#0x20             ; Clear out the remaining stack space
   ldmfd     SP!,{LR}                ; restore the link register for this context
   rfefd     SP!                     ; return from exception via srsfd stack slot
-  
+
   END
 
 

+ 16 - 16
ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c

@@ -24,7 +24,7 @@ typedef UINT32    ARM_FIRST_LEVEL_DESCRIPTOR;
 // Second Level Descriptors
 typedef UINT32    ARM_PAGE_TABLE_ENTRY;
 
-EFI_STATUS 
+EFI_STATUS
 SectionToGcdAttributes (
   IN  UINT32  SectionAttributes,
   OUT UINT64  *GcdAttributes
@@ -418,12 +418,12 @@ UpdatePageEntries (
 
   // Calculate number of 4KB page table entries to change
   NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;
-  
+
   // Iterate for the number of 4KB pages to change
   Offset = 0;
   for(p = 0; p < NumPageEntries; p++) {
     // Calculate index into first level translation table for page table value
-    
+
     FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
     ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
 
@@ -435,9 +435,9 @@ UpdatePageEntries (
       Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
       if (EFI_ERROR(Status)) {
         // Exit for loop
-        break; 
-      } 
-      
+        break;
+      }
+
       // Re-read descriptor
       Descriptor = FirstLevelTable[FirstLevelIdx];
     }
@@ -462,7 +462,7 @@ UpdatePageEntries (
       // Make this virtual address point at a physical page
       PageTableEntry &= ~VirtualMask;
     }
-   
+
     if (CurrentPageTableEntry  != PageTableEntry) {
       Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));
       if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {
@@ -471,14 +471,14 @@ UpdatePageEntries (
         WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);
       }
 
-      // Only need to update if we are changing the entry  
-      PageTable[PageTableIndex] = PageTableEntry; 
+      // Only need to update if we are changing the entry
+      PageTable[PageTableIndex] = PageTableEntry;
       ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
     }
 
     Status = EFI_SUCCESS;
     Offset += TT_DESCRIPTOR_PAGE_SIZE;
-    
+
   } // End first level translation table loop
 
   return Status;
@@ -508,7 +508,7 @@ UpdateSectionEntries (
   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
   // EntryValue: values at bit positions specified by EntryMask
 
-  // Make sure we handle a section range that is unmapped 
+  // Make sure we handle a section range that is unmapped
   EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;
   EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
 
@@ -567,7 +567,7 @@ UpdateSectionEntries (
 
   // calculate number of 1MB first level entries this applies to
   NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;
-  
+
   // iterate through each descriptor
   for(i=0; i<NumSections; i++) {
     CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
@@ -578,7 +578,7 @@ UpdateSectionEntries (
       Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);
     } else {
       // still a section entry
-      
+
       // mask off appropriate fields
       Descriptor = CurrentDescriptor & ~EntryMask;
 
@@ -596,7 +596,7 @@ UpdateSectionEntries (
           WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);
         }
 
-        // Only need to update if we are changing the descriptor  
+        // Only need to update if we are changing the descriptor
         FirstLevelTable[FirstLevelIdx + i] = Descriptor;
         ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
       }
@@ -608,7 +608,7 @@ UpdateSectionEntries (
   return Status;
 }
 
-EFI_STATUS 
+EFI_STATUS
 ConvertSectionToPages (
   IN EFI_PHYSICAL_ADDRESS  BaseAddress
   )
@@ -673,7 +673,7 @@ SetMemoryAttributes (
   )
 {
   EFI_STATUS    Status;
-  
+
   if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
     // Is the base and length a multiple of 1 MB?
     DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));

+ 23 - 23
ArmPkg/Drivers/CpuDxe/CpuDxe.c

@@ -2,7 +2,7 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2011, ARM Limited. All rights reserved.
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -21,14 +21,14 @@ BOOLEAN mInterruptState   = FALSE;
 
 
 /**
-  This function flushes the range of addresses from Start to Start+Length 
-  from the processor's data cache. If Start is not aligned to a cache line 
-  boundary, then the bytes before Start to the preceding cache line boundary 
-  are also flushed. If Start+Length is not aligned to a cache line boundary, 
-  then the bytes past Start+Length to the end of the next cache line boundary 
-  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be 
-  supported. If the data cache is fully coherent with all DMA operations, then 
-  this function can just return EFI_SUCCESS. If the processor does not support 
+  This function flushes the range of addresses from Start to Start+Length
+  from the processor's data cache. If Start is not aligned to a cache line
+  boundary, then the bytes before Start to the preceding cache line boundary
+  are also flushed. If Start+Length is not aligned to a cache line boundary,
+  then the bytes past Start+Length to the end of the next cache line boundary
+  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+  supported. If the data cache is fully coherent with all DMA operations, then
+  this function can just return EFI_SUCCESS. If the processor does not support
   flushing a range of the data cache, then the entire data cache can be flushed.
 
   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
@@ -70,13 +70,13 @@ CpuFlushCpuDataCache (
     default:
       return EFI_INVALID_PARAMETER;
   }
-  
+
   return EFI_SUCCESS;
 }
 
 
 /**
-  This function enables interrupt processing by the processor. 
+  This function enables interrupt processing by the processor.
 
   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 
@@ -120,8 +120,8 @@ CpuDisableInterrupt (
 
 
 /**
-  This function retrieves the processor's current interrupt state a returns it in 
-  State. If interrupts are currently enabled, then TRUE is returned. If interrupts 
+  This function retrieves the processor's current interrupt state a returns it in
+  State. If interrupts are currently enabled, then TRUE is returned. If interrupts
   are currently disabled, then FALSE is returned.
 
   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
@@ -150,9 +150,9 @@ CpuGetInterruptState (
 
 /**
   This function generates an INIT on the processor. If this function succeeds, then the
-  processor will be reset, and control will not be returned to the caller. If InitType is 
-  not supported by this processor, or the processor cannot programmatically generate an 
-  INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error 
+  processor will be reset, and control will not be returned to the caller. If InitType is
+  not supported by this processor, or the processor cannot programmatically generate an
+  INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
   occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
 
   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
@@ -199,7 +199,7 @@ CpuGetTimerValue (
 
 /**
   Callback function for idle events.
- 
+
   @param  Event                 Event whose notification function is being invoked.
   @param  Context               The pointer to the notification function's context,
                                 which is implementation-dependent.
@@ -241,22 +241,22 @@ CpuDxeInitialize (
   EFI_STATUS  Status;
   EFI_EVENT    IdleLoopEvent;
 
-  InitializeExceptions (&mCpu);  
-  
+  InitializeExceptions (&mCpu);
+
   Status = gBS->InstallMultipleProtocolInterfaces (
-                &mCpuHandle, 
-                &gEfiCpuArchProtocolGuid,           &mCpu, 
+                &mCpuHandle,
+                &gEfiCpuArchProtocolGuid,           &mCpu,
                 &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,
                 NULL
                 );
-  
+
   //
   // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
   // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
   // after the protocol is installed
   //
   SyncCacheConfig (&mCpu);
-  
+
   // If the platform is a MPCore system then install the Configuration Table describing the
   // secondary core states
   if (ArmIsMpCore()) {

+ 7 - 7
ArmPkg/Drivers/CpuDxe/CpuDxe.h

@@ -48,9 +48,9 @@
 
 
 /**
-  This function registers and enables the handler specified by InterruptHandler for a processor 
-  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
-  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
+  This function registers and enables the handler specified by InterruptHandler for a processor
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
   The installed handler is called once for each processor interrupt or exception.
 
   @param  InterruptType    A pointer to the processor's current interrupt state. Set to TRUE if interrupts
@@ -75,9 +75,9 @@ RegisterInterruptHandler (
 
 
 /**
-  This function registers and enables the handler specified by InterruptHandler for a processor 
-  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
-  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
+  This function registers and enables the handler specified by InterruptHandler for a processor
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
   The installed handler is called once for each processor interrupt or exception.
 
   @param  InterruptType    A pointer to the processor's current interrupt state. Set to TRUE if interrupts
@@ -120,7 +120,7 @@ SyncCacheConfig (
   IN  EFI_CPU_ARCH_PROTOCOL *CpuProtocol
   );
 
-EFI_STATUS 
+EFI_STATUS
 ConvertSectionToPages (
   IN EFI_PHYSICAL_ADDRESS  BaseAddress
   );

+ 5 - 5
ArmPkg/Drivers/CpuDxe/CpuDxe.inf

@@ -1,7 +1,7 @@
 #/** @file
-#  
+#
 #  DXE CPU driver
-#  
+#
 #  Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
 #  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
 #
@@ -9,10 +9,10 @@
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
 #  http://opensource.org/licenses/bsd-license.php
-#  
+#
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#  
+#
 #**/
 
 [Defines]
@@ -83,7 +83,7 @@
 [Pcd.common]
   gArmTokenSpaceGuid.PcdVFPEnabled
   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
-  
+
 [FeaturePcd.common]
   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport
   gArmTokenSpaceGuid.PcdRelocateVectorTable

+ 9 - 9
ArmPkg/Drivers/CpuPei/CpuPei.c

@@ -4,18 +4,18 @@ Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
 Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>
 Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>
 
-This program and the accompanying materials                          
-are licensed and made available under the terms and conditions of the BSD License         
-which accompanies this distribution.  The full text of the license may be found at        
-http://opensource.org/licenses/bsd-license.php                                            
-                                                                                          
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 Module Name:
 
   MemoryInit.c
-   
+
 Abstract:
 
   PEIM to provide fake memory init
@@ -51,7 +51,7 @@ Arguments:
 
   FileHandle  - Handle of the file being invoked.
   PeiServices - Describes the list of possible PEI Services.
-    
+
 Returns:
 
   Status -  EFI_SUCCESS if the boot mode could be set

+ 2 - 2
ArmPkg/Drivers/CpuPei/CpuPei.inf

@@ -45,7 +45,7 @@
 
 [Ppis]
   gArmMpCoreInfoPpiGuid
-  
+
 [Guids]
   gArmMpCoreInfoGuid
 
@@ -55,4 +55,4 @@
 
 [Depex]
   gEfiPeiMemoryDiscoveredPpiGuid
-  
+

+ 31 - 31
ArmPkg/Drivers/TimerDxe/TimerDxe.c

@@ -40,16 +40,16 @@ UINT64 mTimerPeriod = 0;
 EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
 
 /**
-  This function registers the handler NotifyFunction so it is called every time 
-  the timer interrupt fires.  It also passes the amount of time since the last 
-  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the 
-  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is 
-  returned.  If the CPU does not support registering a timer interrupt handler, 
-  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a handler 
-  when a handler is already registered, then EFI_ALREADY_STARTED is returned.  
-  If an attempt is made to unregister a handler when a handler is not registered, 
-  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to 
-  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR 
+  This function registers the handler NotifyFunction so it is called every time
+  the timer interrupt fires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
+  returned.  If the CPU does not support registering a timer interrupt handler,
+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not registered,
+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
   is returned.
 
   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
@@ -102,17 +102,17 @@ ExitBootServicesEvent (
 
 /**
 
-  This function adjusts the period of timer interrupts to the value specified 
-  by TimerPeriod.  If the timer period is updated, then the selected timer 
-  period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned.  If 
-  the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.  
-  If an error occurs while attempting to update the timer period, then the 
-  timer hardware will be put back in its state prior to this call, and 
-  EFI_DEVICE_ERROR is returned.  If TimerPeriod is 0, then the timer interrupt 
-  is disabled.  This is not the same as disabling the CPU's interrupts.  
-  Instead, it must either turn off the timer hardware, or it must adjust the 
-  interrupt controller so that a CPU interrupt is not generated when the timer 
-  interrupt fires. 
+  This function adjusts the period of timer interrupts to the value specified
+  by TimerPeriod.  If the timer period is updated, then the selected timer
+  period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned.  If
+  the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+  If an error occurs while attempting to update the timer period, then the
+  timer hardware will be put back in its state prior to this call, and
+  EFI_DEVICE_ERROR is returned.  If TimerPeriod is 0, then the timer interrupt
+  is disabled.  This is not the same as disabling the CPU's interrupts.
+  Instead, it must either turn off the timer hardware, or it must adjust the
+  interrupt controller so that a CPU interrupt is not generated when the timer
+  interrupt fires.
 
   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
   @param  TimerPeriod      The rate to program the timer interrupt in 100 nS units. If
@@ -136,7 +136,7 @@ TimerDriverSetTimerPeriod (
   )
 {
   UINT64      TimerTicks;
-  
+
   // Always disable the timer
   ArmArchTimerDisableTimer ();
 
@@ -158,9 +158,9 @@ TimerDriverSetTimerPeriod (
 }
 
 /**
-  This function retrieves the period of timer interrupts in 100 ns units, 
-  returns that value in TimerPeriod, and returns EFI_SUCCESS.  If TimerPeriod 
-  is NULL, then EFI_INVALID_PARAMETER is returned.  If a TimerPeriod of 0 is 
+  This function retrieves the period of timer interrupts in 100 ns units,
+  returns that value in TimerPeriod, and returns EFI_SUCCESS.  If TimerPeriod
+  is NULL, then EFI_INVALID_PARAMETER is returned.  If a TimerPeriod of 0 is
   returned, then the timer is currently disabled.
 
   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
@@ -188,12 +188,12 @@ TimerDriverGetTimerPeriod (
 }
 
 /**
-  This function generates a soft timer interrupt. If the platform does not support soft 
-  timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. 
-  If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() 
-  service, then a soft timer interrupt will be generated. If the timer interrupt is 
-  enabled when this service is called, then the registered handler will be invoked. The 
-  registered handler should not be able to distinguish a hardware-generated timer 
+  This function generates a soft timer interrupt. If the platform does not support soft
+  timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+  If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+  service, then a soft timer interrupt will be generated. If the timer interrupt is
+  enabled when this service is called, then the registered handler will be invoked. The
+  registered handler should not be able to distinguish a hardware-generated timer
   interrupt from a software-generated timer interrupt.
 
   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.

+ 9 - 10
ArmPkg/Drivers/TimerDxe/TimerDxe.inf

@@ -1,22 +1,22 @@
 #/** @file
-#  
+#
 #    Component description file for Timer DXE module
-#  
+#
 #  Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
 #  http://opensource.org/licenses/bsd-license.php
-#  
+#
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#  
+#
 #**/
 
 [Defines]
   INF_VERSION                    = 0x00010005
   BASE_NAME                      = ArmTimerDxe
-  FILE_GUID                      = 49ea041e-6752-42ca-b0b1-7344fe2546b7 
+  FILE_GUID                      = 49ea041e-6752-42ca-b0b1-7344fe2546b7
   MODULE_TYPE                    = DXE_DRIVER
   VERSION_STRING                 = 1.0
 
@@ -40,20 +40,19 @@
   BaseMemoryLib
   DebugLib
   UefiDriverEntryPoint
-  IoLib  
+  IoLib
 
 [Guids]
 
 [Protocols]
-  gEfiTimerArchProtocolGuid  
+  gEfiTimerArchProtocolGuid
   gHardwareInterruptProtocolGuid
 
 [Pcd.common]
   gEmbeddedTokenSpaceGuid.PcdTimerPeriod
-  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum  
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
-  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz  
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
 
 [Depex]
   gHardwareInterruptProtocolGuid
-  

+ 17 - 17
ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c

@@ -21,7 +21,7 @@
 #include <Guid/FileSystemVolumeLabelInfo.h>
 
 #include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h> 
+#include <Library/BaseMemoryLib.h>
 #include <Library/DebugLib.h>
 #include <Library/MemoryAllocationLib.h>
 #include <Library/SemihostLib.h>
@@ -129,7 +129,7 @@ VolumeOpen (
   )
 {
   SEMIHOST_FCB *RootFcb = NULL;
-  
+
   if (Root == NULL) {
     return EFI_INVALID_PARAMETER;
   }
@@ -138,7 +138,7 @@ VolumeOpen (
   if (RootFcb == NULL) {
     return EFI_OUT_OF_RESOURCES;
   }
-  
+
   RootFcb->IsRoot = TRUE;
   RootFcb->Info.Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;
 
@@ -212,7 +212,7 @@ FileOpen (
     if (EFI_ERROR(Status)) {
       return Status;
     }
-    
+
     IsRoot = FALSE;
   }
 
@@ -267,7 +267,7 @@ FileClose (
       FreeFCB (Fcb);
     }
   }
-  
+
   return Status;
 }
 
@@ -357,7 +357,7 @@ FileWrite (
     *BufferSize -= WriteSize;
     Fcb->Position += *BufferSize;
   }
-  
+
   return Status;
 }
 
@@ -368,7 +368,7 @@ FileGetPosition (
   )
 {
   SEMIHOST_FCB *Fcb = NULL;
-    
+
   if (Position == NULL) {
     return EFI_INVALID_PARAMETER;
   }
@@ -447,11 +447,11 @@ GetFileInfo (
     Info->FileName[0]  = L'\0';
   } else {
     for (Index = 0; Index < NameSize; Index++) {
-      Info->FileName[Index] = Fcb->FileName[Index];            
+      Info->FileName[Index] = Fcb->FileName[Index];
     }
   }
 
-  *BufferSize = ResultSize;    
+  *BufferSize = ResultSize;
 
   return EFI_SUCCESS;
 }
@@ -467,11 +467,11 @@ GetFilesystemInfo (
   EFI_FILE_SYSTEM_INFO    *Info = NULL;
   EFI_STATUS              Status;
   UINTN                   ResultSize = SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (mSemihostFsLabel);
-    
+
   if (*BufferSize >= ResultSize) {
     ZeroMem (Buffer, ResultSize);
     Status = EFI_SUCCESS;
-        
+
     Info = Buffer;
 
     Info->Size       = ResultSize;
@@ -485,7 +485,7 @@ GetFilesystemInfo (
     Status = EFI_BUFFER_TOO_SMALL;
   }
 
-  *BufferSize = ResultSize;    
+  *BufferSize = ResultSize;
   return Status;
 }
 
@@ -500,9 +500,9 @@ FileGetInfo (
   SEMIHOST_FCB *Fcb;
   EFI_STATUS   Status;
   UINTN        ResultSize;
-  
+
   Fcb = SEMIHOST_FCB_FROM_THIS(File);
-  
+
   if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid) != 0) {
     Status = GetFilesystemInfo (Fcb, BufferSize, Buffer);
   } else if (CompareGuid (InformationType, &gEfiFileInfoGuid) != 0) {
@@ -596,8 +596,8 @@ SemihostFsEntryPoint (
     }
 
     Status = gBS->InstallMultipleProtocolInterfaces (
-                    &gInstallHandle, 
-                    &gEfiSimpleFileSystemProtocolGuid, &gSemihostFs, 
+                    &gInstallHandle,
+                    &gEfiSimpleFileSystemProtocolGuid, &gSemihostFs,
                     &gEfiDevicePathProtocolGuid,       &gDevicePath,
                     NULL
                     );
@@ -606,6 +606,6 @@ SemihostFsEntryPoint (
       FreePool (mSemihostFsLabel);
     }
   }
- 
+
   return Status;
 }

+ 8 - 8
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf

@@ -4,13 +4,13 @@
 #  Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
 #  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
 #
-#  This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http://opensource.org/licenses/bsd-license.php                                            
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
 #
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 #**/
 
@@ -25,7 +25,7 @@
 
 [Sources.ARM, Sources.AARCH64]
   Arm/SemihostFs.c
-  
+
 [Packages]
   MdePkg/MdePkg.dec
   ArmPkg/ArmPkg.dec
@@ -45,4 +45,4 @@
 [Protocols]
   gEfiSimpleFileSystemProtocolGuid
   gEfiDevicePathProtocolGuid
-  
+

+ 4 - 4
ArmPkg/Include/AsmMacroIoLib.h

@@ -159,7 +159,7 @@ _InitializePrimaryStackEnd:
   ldr  r1, =Address ;              \
   ldr  r0, =Data    ;              \
   str  r0, [r1]
-    
+
 #define MmioOr32(Address, OrData) \
   ldr  r1, =Address ;             \
   ldr  r2, =OrData  ;             \
@@ -181,7 +181,7 @@ _InitializePrimaryStackEnd:
   and  r0, r0, r2   ;                             \
   ldr  r2, =OrData  ;                             \
   orr  r0, r0, r2   ;                             \
-  str  r0, [r1]         
+  str  r0, [r1]
 
 #define MmioWriteFromReg32(Address, Reg) \
   ldr  r1, =Address ;                    \
@@ -235,7 +235,7 @@ _InitializePrimaryStackEnd:
 #else
 
 //
-// Use ARM assembly macros, form armasam 
+// Use ARM assembly macros, form armasam
 //
 //  Less magic in the macros if ldr reg, =expr works
 //
@@ -251,7 +251,7 @@ _InitializePrimaryStackEnd:
 
 // returns Data in R0 and Address in R1, and OrData in r2
 #define MmioOr32(Address, OrData) MmioOr32Macro Address, OrData
-  
+
 
 // returns _Data in R0 and _Address in R1, and _OrData in r2
 

+ 56 - 56
ArmPkg/Include/AsmMacroIoLib.inc

@@ -5,81 +5,81 @@
 ;  Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
 ;  Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
 ;
-;  This program and the accompanying materials                          
-;  are licensed and made available under the terms and conditions of the BSD License         
-;  which accompanies this distribution.  The full text of the license may be found at        
-;  http://opensource.org/licenses/bsd-license.php                                            
-;                                                                                            
-;  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-;  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.  
+;  This program and the accompanying materials
+;  are licensed and made available under the terms and conditions of the BSD License
+;  which accompanies this distribution.  The full text of the license may be found at
+;  http://opensource.org/licenses/bsd-license.php
+;
+;  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+;  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ;
 ;**/
 
 
-  MACRO 
-  MmioWrite32Macro $Address, $Data 
-  ldr  r1, = ($Address)                
-  ldr  r0, = ($Data)                 
-  str  r0, [r1]  
+  MACRO
+  MmioWrite32Macro $Address, $Data
+  ldr  r1, = ($Address)
+  ldr  r0, = ($Data)
+  str  r0, [r1]
   MEND
-    
-  MACRO 
-  MmioOr32Macro $Address, $OrData 
-  ldr  r1, =($Address)               
-  ldr  r2, =($OrData)                
-  ldr  r0, [r1]                      
-  orr  r0, r0, r2                    
-  str  r0, [r1] 
+
+  MACRO
+  MmioOr32Macro $Address, $OrData
+  ldr  r1, =($Address)
+  ldr  r2, =($OrData)
+  ldr  r0, [r1]
+  orr  r0, r0, r2
+  str  r0, [r1]
   MEND
 
-  MACRO 
-  MmioAnd32Macro $Address, $AndData 
-  ldr  r1, =($Address)                 
-  ldr  r2, =($AndData)                 
-  ldr  r0, [r1]                        
-  and  r0, r0, r2                      
-  str  r0, [r1] 
+  MACRO
+  MmioAnd32Macro $Address, $AndData
+  ldr  r1, =($Address)
+  ldr  r2, =($AndData)
+  ldr  r0, [r1]
+  and  r0, r0, r2
+  str  r0, [r1]
   MEND
 
-  MACRO 
-  MmioAndThenOr32Macro $Address, $AndData, $OrData 
-  ldr  r1, =($Address)                         
-  ldr  r0, [r1]                                        
-  ldr  r2, =($AndData)                                 
-  and  r0, r0, r2                                      
-  ldr  r2, =($OrData)                                  
-  orr  r0, r0, r2                                      
-  str  r0, [r1]          
+  MACRO
+  MmioAndThenOr32Macro $Address, $AndData, $OrData
+  ldr  r1, =($Address)
+  ldr  r0, [r1]
+  ldr  r2, =($AndData)
+  and  r0, r0, r2
+  ldr  r2, =($OrData)
+  orr  r0, r0, r2
+  str  r0, [r1]
   MEND
 
-  MACRO 
-  MmioWriteFromReg32Macro $Address, $Reg 
-  ldr  r1, =($Address)   
-  str  $Reg, [r1]        
+  MACRO
+  MmioWriteFromReg32Macro $Address, $Reg
+  ldr  r1, =($Address)
+  str  $Reg, [r1]
   MEND
 
-  MACRO 
-  MmioRead32Macro $Address   
-  ldr  r1, =($Address)         
-  ldr  r0, [r1]   
+  MACRO
+  MmioRead32Macro $Address
+  ldr  r1, =($Address)
+  ldr  r0, [r1]
+  MEND
+
+  MACRO
+  MmioReadToReg32Macro $Address, $Reg
+  ldr  r1, =($Address)
+  ldr  $Reg, [r1]
   MEND
 
-  MACRO 
-  MmioReadToReg32Macro $Address, $Reg 
-  ldr  r1, =($Address)                   
-  ldr  $Reg, [r1]        
+  MACRO
+  LoadConstantMacro $Data
+  ldr  r0, =($Data)
   MEND
 
-  MACRO 
-  LoadConstantMacro $Data 
-  ldr  r0, =($Data) 
+  MACRO
+  LoadConstantToRegMacro $Data, $Reg
+  ldr  $Reg, =($Data)
   MEND
 
-  MACRO 
-  LoadConstantToRegMacro $Data, $Reg 
-  ldr  $Reg, =($Data) 
-  MEND 
-  
   ; The reserved place must be 8-bytes aligned for pushing 64-bit variable on the stack
   ; Note: Global Size will be modified
   MACRO

+ 1 - 1
ArmPkg/Include/Chipset/ARM926EJ-S.h

@@ -58,7 +58,7 @@
 #define TT_DESCRIPTOR_SECTION_WRITE_BACK          (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \
                                                    TT_DESCRIPTOR_SECTION_DOMAIN(0)                    | \
                                                    TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK      | \
-                                                   TT_DESCRIPTOR_TYPE_SECTION)                                                   
+                                                   TT_DESCRIPTOR_TYPE_SECTION)
 #define TT_DESCRIPTOR_SECTION_WRITE_THROUGH       (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \
                                                    TT_DESCRIPTOR_SECTION_DOMAIN(0)                    | \
                                                    TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH   | \

+ 7 - 7
ArmPkg/Include/Chipset/ArmArchTimer.h

@@ -1,14 +1,14 @@
 /** @file
 *
 *  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-*  
-*  This program and the accompanying materials                          
-*  are licensed and made available under the terms and conditions of the BSD License         
-*  which accompanies this distribution.  The full text of the license may be found at        
-*  http://opensource.org/licenses/bsd-license.php                                            
 *
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 *
 **/
 

+ 1 - 1
ArmPkg/Include/Chipset/ArmV7.h

@@ -94,7 +94,7 @@ ArmEnableSWPInstruction (
   VOID
   );
 
-UINTN 
+UINTN
 EFIAPI
 ArmReadCbar (
   VOID

+ 7 - 7
ArmPkg/Include/Chipset/ArmV7Mmu.h

@@ -1,14 +1,14 @@
 /** @file
 *
 *  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-*  
-*  This program and the accompanying materials                          
-*  are licensed and made available under the terms and conditions of the BSD License         
-*  which accompanies this distribution.  The full text of the license may be found at        
-*  http://opensource.org/licenses/bsd-license.php                                            
 *
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 *
 **/
 

+ 7 - 7
ArmPkg/Include/Guid/ArmMpCoreInfo.h

@@ -1,14 +1,14 @@
 /** @file
 *
 *  Copyright (c) 2011, ARM Limited. All rights reserved.
-*  
-*  This program and the accompanying materials                          
-*  are licensed and made available under the terms and conditions of the BSD License         
-*  which accompanies this distribution.  The full text of the license may be found at        
-*  http://opensource.org/licenses/bsd-license.php                                            
 *
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 *
 **/
 

+ 10 - 10
ArmPkg/Include/Library/ArmDisassemblerLib.h

@@ -16,19 +16,19 @@
 #define __ARM_DISASSEBLER_LIB_H__
 
 /**
-  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to 
-  point to next instructin. 
-  
-  We cheat and only decode instructions that access 
+  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
+  point to next instructin.
+
+  We cheat and only decode instructions that access
   memory. If the instruction is not found we dump the instruction in hex.
-   
-  @param  OpCodePtrPtr  Pointer to pointer of ARM Thumb instruction to disassemble.  
+
+  @param  OpCodePtrPtr  Pointer to pointer of ARM Thumb instruction to disassemble.
   @param  Thumb         TRUE for Thumb(2), FALSE for ARM instruction stream
   @param  Extended      TRUE dump hex for instruction too.
   @param  ItBlock       Size of IT Block
   @param  Buf           Buffer to sprintf disassembly into.
-  @param  Size          Size of Buf in bytes. 
-  
+  @param  Size          Size of Buf in bytes.
+
 **/
 VOID
 DisassembleInstruction (
@@ -39,5 +39,5 @@ DisassembleInstruction (
   OUT CHAR8     *Buf,
   OUT UINTN     Size
   );
-  
-#endif 
+
+#endif

+ 15 - 15
ArmPkg/Include/Library/ArmLib.h

@@ -148,43 +148,43 @@ EFIAPI
 ArmDataCachePresent (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmDataCacheSize (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmDataCacheAssociativity (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmDataCacheLineLength (
   VOID
   );
-  
+
 BOOLEAN
 EFIAPI
 ArmInstructionCachePresent (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheSize (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheAssociativity (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheLineLength (
@@ -311,7 +311,7 @@ EFIAPI
 ArmDisableInstructionCache (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmEnableMmu (
@@ -395,7 +395,7 @@ EFIAPI
 ArmDisableFiq (
   VOID
   );
-  
+
 BOOLEAN
 EFIAPI
 ArmGetFiqState (
@@ -407,14 +407,14 @@ EFIAPI
 ArmInvalidateTlb (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmUpdateTranslationTableEntry (
   IN  VOID     *TranslationTableEntry,
   IN  VOID     *Mva
   );
-  
+
 VOID
 EFIAPI
 ArmSetDomainAccessControl (
@@ -440,13 +440,13 @@ ArmConfigureMmu (
   OUT VOID                         **TranslationTableBase OPTIONAL,
   OUT UINTN                         *TranslationTableSize  OPTIONAL
   );
-  
+
 BOOLEAN
 EFIAPI
 ArmMmuEnabled (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmEnableBranchPrediction (
@@ -482,13 +482,13 @@ EFIAPI
 ArmDataMemoryBarrier (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmDataSyncronizationBarrier (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmInstructionSynchronizationBarrier (

+ 2 - 2
ArmPkg/Include/Library/DefaultExceptionHandlerLib.h

@@ -27,5 +27,5 @@ DefaultExceptionHandler (
   IN     EFI_EXCEPTION_TYPE           ExceptionType,
   IN OUT EFI_SYSTEM_CONTEXT           SystemContext
   );
-  
-#endif 
+
+#endif

+ 3 - 3
ArmPkg/Include/Library/SemihostLib.h

@@ -22,7 +22,7 @@
  *  about the semihosting interface.
  *
  */
- 
+
 #define SEMIHOST_FILE_MODE_READ     (0 << 2)
 #define SEMIHOST_FILE_MODE_WRITE    (1 << 2)
 #define SEMIHOST_FILE_MODE_APPEND   (2 << 2)
@@ -92,10 +92,10 @@ VOID
 SemihostWriteString (
   IN CHAR8 *String
   );
-  
+
 UINT32
 SemihostSystem (
   IN CHAR8 *CommandLine
   );
-  
+
 #endif // __SEMIHOSTING_H__

+ 6 - 6
ArmPkg/Include/Library/UncachedMemoryAllocationLib.h

@@ -121,7 +121,7 @@ UncachedAllocateReservedPages (
   If Buffer was not allocated with a page allocation function in the Memory Allocation Library,
   then ASSERT().
   If Pages is zero, then ASSERT().
- 
+
   @param  Buffer                Pointer to the buffer of pages to free.
   @param  Pages                 The number of 4 KB pages to free.
 
@@ -212,7 +212,7 @@ UncachedAllocateAlignedReservedPages (
   If Buffer was not allocated with an aligned page allocation function in the Memory Allocation
   Library, then ASSERT().
   If Pages is zero, then ASSERT().
-  
+
   @param  Buffer                Pointer to the buffer of pages to free.
   @param  Pages                 The number of 4 KB pages to free.
 
@@ -343,7 +343,7 @@ UncachedAllocateReservedZeroPool (
   allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
   is not enough memory remaining to satisfy the request, then NULL is returned.
   If Buffer is NULL, then ASSERT().
-  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). 
+  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
 
   @param  AllocationSize        The number of bytes to allocate and zero.
   @param  Buffer                The buffer to copy to the allocated buffer.
@@ -366,7 +366,7 @@ UncachedAllocateCopyPool (
   allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
   is not enough memory remaining to satisfy the request, then NULL is returned.
   If Buffer is NULL, then ASSERT().
-  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). 
+  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
 
   @param  AllocationSize        The number of bytes to allocate and zero.
   @param  Buffer                The buffer to copy to the allocated buffer.
@@ -389,7 +389,7 @@ UncachedAllocateRuntimeCopyPool (
   allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
   is not enough memory remaining to satisfy the request, then NULL is returned.
   If Buffer is NULL, then ASSERT().
-  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). 
+  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
 
   @param  AllocationSize        The number of bytes to allocate and zero.
   @param  Buffer                The buffer to copy to the allocated buffer.
@@ -639,7 +639,7 @@ UncachedAllocateAlignedReservedCopyPool (
   );
 
 /**
-  Frees a buffer that was previously allocated with one of the aligned pool allocation functions 
+  Frees a buffer that was previously allocated with one of the aligned pool allocation functions
   in the Memory Allocation Library.
 
   Frees the buffer specified by Buffer.  Buffer must have been allocated on a previous call to the

+ 2 - 2
ArmPkg/Include/Protocol/VirtualUncachedPages.h

@@ -37,7 +37,7 @@ EFI_STATUS
   IN  EFI_PHYSICAL_ADDRESS              VirtualMask,
   OUT UINT64                            *Attributes     OPTIONAL
   );
-  
+
 typedef
 EFI_STATUS
 (EFIAPI *FREE_CONVERTED_PAGES) (
@@ -57,4 +57,4 @@ struct _VIRTUAL_UNCACHED_PAGES_PROTOCOL {
 
 extern EFI_GUID gVirtualUncachedPagesProtocolGuid;
 
-#endif  
+#endif

+ 9 - 9
ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf

@@ -1,14 +1,14 @@
 #/** @file
-#  
+#
 #  Copyright (c) 2011-2012, ARM Limited. All rights reserved.<BR>
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
 #  http://opensource.org/licenses/bsd-license.php
-#  
+#
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#  
+#
 #**/
 
 [Defines]
@@ -17,7 +17,7 @@
   FILE_GUID                      = 82da1b44-d2d6-4a7d-bbf0-a0cb67964034
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = TimerLib 
+  LIBRARY_CLASS                  = TimerLib
   CONSTRUCTOR                    = TimerConstructor
 
 [Sources.common]
@@ -27,18 +27,18 @@
   MdePkg/MdePkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   ArmPkg/ArmPkg.dec
-  
+
 
 [LibraryClasses]
   DebugLib
   IoLib
   ArmLib
-  BaseLib    
-  
+  BaseLib
+
 [Protocols]
-  
+
 [Guids]
- 
+
 [Pcd]
   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
 

+ 2 - 2
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c

@@ -2,7 +2,7 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,7 +27,7 @@ CacheRangeOperation (
   UINTN ArmCacheLineLength         = ArmDataCacheLineLength();
   UINTN ArmCacheLineAlignmentMask  = ArmCacheLineLength - 1;
   UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
-  
+
   if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
     ArmDrainWriteBuffer ();
     CacheOperation ();

+ 51 - 51
ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c

@@ -2,7 +2,7 @@
   Default exception handler
 
   Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -90,7 +90,7 @@ MRegList (
   UINTN     Index, Start, End;
   CHAR8     *Str;
   BOOLEAN   First;
- 
+
   Str = mMregListStr;
   *Str = '\0';
   AsciiStrCat  (Str, "{");
@@ -100,13 +100,13 @@ MRegList (
       for (Index++; ((OpCode & (1 << Index)) != 0) && Index <= 15; Index++) {
         End = Index;
       }
-      
+
       if (!First) {
         AsciiStrCat  (Str, ",");
       } else {
         First = FALSE;
       }
-      
+
       if (Start == End) {
         AsciiStrCat  (Str, gReg[Start]);
         AsciiStrCat  (Str, ", ");
@@ -121,7 +121,7 @@ MRegList (
     AsciiStrCat  (Str, "ERROR");
   }
   AsciiStrCat  (Str, "}");
-  
+
   // BugBug: Make caller pass in buffer it is cleaner
   return mMregListStr;
 }
@@ -145,17 +145,17 @@ RotateRight (
 
 
 /**
-  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to 
-  point to next instructin. 
-  
-  We cheat and only decode instructions that access 
+  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
+  point to next instructin.
+
+  We cheat and only decode instructions that access
   memory. If the instruction is not found we dump the instruction in hex.
-   
-  @param  OpCodePtr   Pointer to pointer of ARM instruction to disassemble.  
+
+  @param  OpCodePtr   Pointer to pointer of ARM instruction to disassemble.
   @param  Buf         Buffer to sprintf disassembly into.
-  @param  Size        Size of Buf in bytes. 
+  @param  Size        Size of Buf in bytes.
   @param  Extended    TRUE dump hex for instruction too.
-  
+
 **/
 VOID
 DisassembleArmInstruction (
@@ -177,7 +177,7 @@ DisassembleArmInstruction (
   P = (OpCode & BIT24) == BIT24;
   U = (OpCode & BIT23) == BIT23;
   B = (OpCode & BIT22) == BIT22;  // Also called S
-  W = (OpCode & BIT21) == BIT21;  
+  W = (OpCode & BIT21) == BIT21;
   L = (OpCode & BIT20) == BIT20;
   S = (OpCode & BIT6) == BIT6;
   H = (OpCode & BIT5) == BIT5;
@@ -195,27 +195,27 @@ DisassembleArmInstruction (
   // LDREX, STREX
   if ((OpCode  & 0x0fe000f0) == 0x01800090) {
     if (L) {
-      // A4.1.27  LDREX{<cond>} <Rd>, [<Rn>] 
-      AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);   
+      // A4.1.27  LDREX{<cond>} <Rd>, [<Rn>]
+      AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
     } else {
      // A4.1.103  STREX{<cond>} <Rd>, <Rm>, [<Rn>]
-      AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);   
-    } 
+      AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
+    }
     return;
   }
-  
+
   // LDM/STM
   if ((OpCode  & 0x0e000000) == 0x08000000) {
     if (L) {
       // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
       // A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
       // A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
-      AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));   
+      AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
     } else {
       // A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
       // A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
-      AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));   
-    }   
+      AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
+    }
     return;
   }
 
@@ -225,7 +225,7 @@ DisassembleArmInstruction (
     if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
       Index = AsciiSPrint (Buf, Size, "PLD");
     } else {
-      Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]); 
+      Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);
     }
     if (P) {
       if (!I) {
@@ -256,7 +256,7 @@ DisassembleArmInstruction (
         } else {
           Type = "ROR";
         }
-          
+
         AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
       }
     } else {  // !P
@@ -287,13 +287,13 @@ DisassembleArmInstruction (
         } else {
           Type = "ROR";
         }
-          
+
         AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);
       }
     }
-    return;  
+    return;
   }
-  
+
   if ((OpCode  & 0x0e000000) == 0x00000000) {
     // LDR/STR address mode 3
     // LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
@@ -314,8 +314,8 @@ DisassembleArmInstruction (
         Root = "STR%aD %a ";
       }
     }
-  
-    Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]); 
+
+    Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
 
     S = (OpCode & BIT6) == BIT6;
     H = (OpCode & BIT5) == BIT5;
@@ -350,7 +350,7 @@ DisassembleArmInstruction (
     AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);
     return;
   }
-  
+
   if ((OpCode  & 0xfe5f0f00) == 0xf84d0500) {
     // A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
     AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));
@@ -362,13 +362,13 @@ DisassembleArmInstruction (
     AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));
     return;
   }
-  
+
   if ((OpCode  & 0xfff000f0) == 0xe1200070) {
     // A4.1.7 BKPT <immed_16>
     AsciiSPrint (Buf, Size, "BKPT %x", ((OpCode >> 8) | (OpCode & 0xf)) & 0xffff);
     return;
-  }  
-  
+  }
+
   if ((OpCode  & 0xfff10020) == 0xf1000000) {
     // A4.1.16 CPS<effect> <iflags> {, #<mode>}
     if (((OpCode >> 6) & 0x7) == 0) {
@@ -381,19 +381,19 @@ DisassembleArmInstruction (
       }
     }
     return;
-  }  
-    
+  }
+
   if ((OpCode  & 0x0f000000) == 0x0f000000) {
     // A4.1.107 SWI{<cond>} <immed_24>
     AsciiSPrint (Buf, Size, "SWI%a %x", COND (OpCode), OpCode & 0x00ffffff);
     return;
-  }  
+  }
 
   if ((OpCode  & 0x0fb00000) == 0x01000000) {
     // A4.1.38 MRS{<cond>} <Rd>, CPSR  MRS{<cond>} <Rd>, SPSR
     AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");
     return;
-  }  
+  }
 
 
   if ((OpCode  & 0x0db00000) == 0x03200000) {
@@ -406,14 +406,14 @@ DisassembleArmInstruction (
       AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);
     }
     return;
-  }  
+  }
 
   if ((OpCode  & 0xff000010) == 0xfe000000) {
     // A4.1.13 CDP{<cond>} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
     AsciiSPrint (Buf, Size, "CDP%a 0x%x, 0x%x, CR%d, CR%d, CR%d, 0x%x", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, Rn, Rd, Rm, (OpCode >> 5) &0x7);
     return;
   }
-  
+
   if ((OpCode  & 0x0e000000) == 0x0c000000) {
     // A4.1.19 LDC and A4.1.96 SDC
     if ((OpCode & 0xf0000000) == 0xf0000000) {
@@ -421,36 +421,36 @@ DisassembleArmInstruction (
     } else {
       Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ",  L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
     }
-    
+
     if (!P) {
-      if (!W) { 
+      if (!W) {
         // A5.5.5.5 [<Rn>], <option>
-      AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff); 
+      AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
       } else {
         // A.5.5.4  [<Rn>], #+/-<offset_8>*4
-      AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff); 
+      AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);
       }
     } else {
       // A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
-      AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W)); 
+      AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));
     }
-    
+
   }
-  
+
   if ((OpCode  & 0x0f000010) == 0x0e000010) {
-    // A4.1.32 MRC2, MCR2 
+    // A4.1.32 MRC2, MCR2
     AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
-    return;    
+    return;
   }
 
   if ((OpCode  & 0x0ff00000) == 0x0c400000) {
-    // A4.1.33 MRRC2, MCRR2 
+    // A4.1.33 MRRC2, MCRR2
     AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
-    return;    
+    return;
   }
 
   AsciiSPrint (Buf, Size, "Faulting OpCode 0x%08x", OpCode);
-  
+
   *OpCodePtr += 1;
   return;
 }

+ 142 - 142
ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c

@@ -1,15 +1,15 @@
 /** @file
   Thumb Dissassembler. Still a work in progress.
 
-  Wrong output is a bug, so please fix it. 
+  Wrong output is a bug, so please fix it.
   Hex output means there is not yet an entry or a decode bug.
-  gOpThumb[] are Thumb 16-bit, and gOpThumb2[] work on the 32-bit 
-  16-bit stream of Thumb2 instruction. Then there are big case 
+  gOpThumb[] are Thumb 16-bit, and gOpThumb2[] work on the 32-bit
+  16-bit stream of Thumb2 instruction. Then there are big case
   statements to print everything out. If you are adding instructions
   try to reuse existing case entries if possible.
 
   Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -32,13 +32,13 @@ extern CHAR8 *gReg[];
 // Thumb address modes
 #define LOAD_STORE_FORMAT1            1
 #define LOAD_STORE_FORMAT1_H        101
-#define LOAD_STORE_FORMAT1_B        111 
+#define LOAD_STORE_FORMAT1_B        111
 #define LOAD_STORE_FORMAT2            2
 #define LOAD_STORE_FORMAT3            3
 #define LOAD_STORE_FORMAT4            4
-#define LOAD_STORE_MULTIPLE_FORMAT1   5 
-#define PUSH_FORMAT                   6 
-#define POP_FORMAT                  106 
+#define LOAD_STORE_MULTIPLE_FORMAT1   5
+#define PUSH_FORMAT                   6
+#define POP_FORMAT                  106
 #define IMMED_8                       7
 #define CONDITIONAL_BRANCH            8
 #define UNCONDITIONAL_BRANCH          9
@@ -93,8 +93,8 @@ extern CHAR8 *gReg[];
 #define THUMB2_4REGS                230
 #define ADD_IMM12_1REG              231
 #define THUMB2_IMM16                232
-#define MRC_THUMB2                  233 
-#define MRRC_THUMB2                 234 
+#define MRC_THUMB2                  233
+#define MRRC_THUMB2                 234
 #define THUMB2_MRS                  235
 #define THUMB2_MSR                  236
 
@@ -118,7 +118,7 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
   { "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },
   { "ADD" , 0x4400, 0xff00, DATA_FORMAT8 },   // A8.6.9
   { "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },
-  { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP }, 
+  { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },
   { "ADD" , 0xb000, 0xff80, DATA_FORMAT7 },
 
   { "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },
@@ -156,7 +156,7 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
   { "LDRH"  , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
   { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },  // STR <Rt>, [<Rn>, <Rm>]
   { "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
- 
+
   { "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 },   // LSL with imm5 == 0 is a MOVS, so this must go before LSL
   { "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },
   { "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },
@@ -212,8 +212,8 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
 
 THUMB_INSTRUCTIONS gOpThumb2[] = {
 //Instruct  OpCode      OpCode Mask  Addressig Mode
-  
-  { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2    },  // ADDR <Rd>, <label> ;Needs to go before ADDW 
+
+  { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2    },  // ADDR <Rd>, <label> ;Needs to go before ADDW
   { "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2    },  // CMN <Rn>, #<const> ;Needs to go before ADD
   { "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG },  // CMN <Rn>, <Rm> {,<shift> #<const>}
   { "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2    },  // CMP <Rn>, #<const>
@@ -225,7 +225,7 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
   { "MOV",  0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV  <Rd>, #<const>
   { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 },   // MOVW <Rd>, #<const>
   { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 },   // MOVT <Rd>, #<const>
-  
+
   { "ADC",  0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S}  <Rd>, <Rn>, #<const>
   { "ADC",  0xeb400000, 0xffe08000, ADD_IMM5  }, // ADC{S}  <Rd>, <Rn>, <Rm> {,<shift> #<const>}
   { "ADD",  0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S}  <Rd>, <Rn>, #<const>
@@ -249,11 +249,11 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
   { "SUB",  0xeba00000, 0xffe08000, ADD_IMM5  }, // SUB{S}  <Rd>, <Rn>, <Rm> {,<shift> #<const>}
 
   { "ASR",  0xea4f0020, 0xffef8030, ASR_IMM5 },  // ARS  <Rd>, <Rm> #<const>} imm3:imm2
-  { "ASR",  0xfa40f000, 0xffe0f0f0, ASR_3REG },  // ARS  <Rd>, <Rn>, <Rm> 
+  { "ASR",  0xfa40f000, 0xffe0f0f0, ASR_3REG },  // ARS  <Rd>, <Rn>, <Rm>
   { "LSR",  0xea4f0010, 0xffef8030, ASR_IMM5 },  // LSR  <Rd>, <Rm> #<const>} imm3:imm2
-  { "LSR",  0xfa20f000, 0xffe0f0f0, ASR_3REG },  // LSR  <Rd>, <Rn>, <Rm> 
+  { "LSR",  0xfa20f000, 0xffe0f0f0, ASR_3REG },  // LSR  <Rd>, <Rn>, <Rm>
   { "ROR",  0xea4f0030, 0xffef8030, ASR_IMM5 },  // ROR  <Rd>, <Rm> #<const>} imm3:imm2
-  { "ROR",  0xfa60f000, 0xffe0f0f0, ASR_3REG },  // ROR  <Rd>, <Rn>, <Rm> 
+  { "ROR",  0xfa60f000, 0xffe0f0f0, ASR_3REG },  // ROR  <Rd>, <Rn>, <Rm>
 
   { "BFC",  0xf36f0000, 0xffff8010, BFC_THUMB2 },   // BFC  <Rd>, #<lsb>, #<width>
   { "BIC",  0xf3600000, 0xfff08010, BFC_THUMB2 },   // BIC  <Rn>, <Rd>, #<lsb>, #<width>
@@ -317,19 +317,19 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
   { "STMDB", 0xe9800000, 0xffd0a000,  STM_FORMAT },      // STMDB <Rn>{!},<registers>
   { "LDM"  , 0xe8900000, 0xffd02000,  STM_FORMAT },      // LDM <Rn>{!},<registers>
   { "LDMDB", 0xe9100000, 0xffd02000,  STM_FORMAT },      // LDMDB <Rn>{!},<registers>
-  
+
   { "LDR",   0xf8d00000, 0xfff00000,  LDM_REG_IMM12 },          // LDR   <rt>, [<rn>, {, #<imm12>]}
   { "LDRB",  0xf8900000, 0xfff00000,  LDM_REG_IMM12 },          // LDRB  <rt>, [<rn>, {, #<imm12>]}
   { "LDRH",  0xf8b00000, 0xfff00000,  LDM_REG_IMM12 },          // LDRH  <rt>, [<rn>, {, #<imm12>]}
   { "LDRSB", 0xf9900000, 0xfff00000,  LDM_REG_IMM12 },          // LDRSB <rt>, [<rn>, {, #<imm12>]}
   { "LDRSH", 0xf9b00000, 0xfff00000,  LDM_REG_IMM12 },          // LDRSH <rt>, [<rn>, {, #<imm12>]}
 
-  { "LDR",   0xf85f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDR   <Rt>, <label> 
-  { "LDRB",  0xf81f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDRB  <Rt>, <label> 
-  { "LDRH",  0xf83f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDRH  <Rt>, <label> 
-  { "LDRSB", 0xf91f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDRSB <Rt>, <label> 
-  { "LDRSH", 0xf93f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDRSB <Rt>, <label> 
-  
+  { "LDR",   0xf85f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDR   <Rt>, <label>
+  { "LDRB",  0xf81f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDRB  <Rt>, <label>
+  { "LDRH",  0xf83f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDRH  <Rt>, <label>
+  { "LDRSB", 0xf91f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDRSB <Rt>, <label>
+  { "LDRSH", 0xf93f0000, 0xff7f0000,  LDM_REG_IMM12_SIGNED },   // LDRSB <Rt>, <label>
+
   { "LDR",   0xf8500000, 0xfff00fc0,  LDM_REG_INDIRECT_LSL },   // LDR   <rt>, [<rn>, <rm> {, LSL #<imm2>]}
   { "LDRB",  0xf8100000, 0xfff00fc0,  LDM_REG_INDIRECT_LSL },   // LDRB  <rt>, [<rn>, <rm> {, LSL #<imm2>]}
   { "LDRH",  0xf8300000, 0xfff00fc0,  LDM_REG_INDIRECT_LSL },   // LDRH  <rt>, [<rn>, <rm> {, LSL #<imm2>]}
@@ -339,25 +339,25 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
   { "LDR",   0xf8500800, 0xfff00800,  LDM_REG_IMM8 },           // LDR    <rt>, [<rn>, {, #<imm8>]}
   { "LDRBT", 0xf8100e00, 0xfff00f00,  LDM_REG_IMM8 },           // LDRBT  <rt>, [<rn>, {, #<imm8>]}
   { "LDRHT", 0xf8300e00, 0xfff00f00,  LDM_REG_IMM8 },           // LDRHT  <rt>, [<rn>, {, #<imm8>]}
-  { "LDRSB", 0xf9100800, 0xfff00800,  LDM_REG_IMM8 },           // LDRHT  <rt>, [<rn>, {, #<imm8>]}  {!} form? 
-  { "LDRSBT",0xf9100e00, 0xfff00f00,  LDM_REG_IMM8 },           // LDRHBT <rt>, [<rn>, {, #<imm8>]}  {!} form? 
-  { "LDRSH" ,0xf9300800, 0xfff00800,  LDM_REG_IMM8 },           // LDRSH  <rt>, [<rn>, {, #<imm8>]}  
-  { "LDRSHT",0xf9300e00, 0xfff00f00,  LDM_REG_IMM8 },           // LDRSHT <rt>, [<rn>, {, #<imm8>]}   
-  { "LDRT",  0xf8500e00, 0xfff00f00,  LDM_REG_IMM8 },           // LDRT   <rt>, [<rn>, {, #<imm8>]}    
+  { "LDRSB", 0xf9100800, 0xfff00800,  LDM_REG_IMM8 },           // LDRHT  <rt>, [<rn>, {, #<imm8>]}  {!} form?
+  { "LDRSBT",0xf9100e00, 0xfff00f00,  LDM_REG_IMM8 },           // LDRHBT <rt>, [<rn>, {, #<imm8>]}  {!} form?
+  { "LDRSH" ,0xf9300800, 0xfff00800,  LDM_REG_IMM8 },           // LDRSH  <rt>, [<rn>, {, #<imm8>]}
+  { "LDRSHT",0xf9300e00, 0xfff00f00,  LDM_REG_IMM8 },           // LDRSHT <rt>, [<rn>, {, #<imm8>]}
+  { "LDRT",  0xf8500e00, 0xfff00f00,  LDM_REG_IMM8 },           // LDRT   <rt>, [<rn>, {, #<imm8>]}
 
   { "LDRD",  0xe8500000, 0xfe500000,  LDRD_REG_IMM8_SIGNED },   // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
   { "LDRD",  0xe8500000, 0xfe500000,  LDRD_REG_IMM8       },    // LDRD <rt>, <rt2>, <label>
-   
-  { "LDREX",  0xe8500f00, 0xfff00f00,  LDM_REG_IMM8 },           // LDREX <Rt>, [Rn, {#imm8}]]                     
-  { "LDREXB", 0xe8d00f4f, 0xfff00fff,  LDREXB  },                // LDREXB <Rt>, [<Rn>]                     
-  { "LDREXH", 0xe8d00f5f, 0xfff00fff,  LDREXB  },                // LDREXH <Rt>, [<Rn>]                     
- 
-  { "LDREXD", 0xe8d00f4f, 0xfff00fff,  LDREXD  },                // LDREXD <Rt>, <Rt2>, [<Rn>]                     
-
-  { "STR",   0xf8c00000, 0xfff00000,  LDM_REG_IMM12 },          // STR   <rt>, [<rn>, {, #<imm12>]}  
+
+  { "LDREX",  0xe8500f00, 0xfff00f00,  LDM_REG_IMM8 },           // LDREX <Rt>, [Rn, {#imm8}]]
+  { "LDREXB", 0xe8d00f4f, 0xfff00fff,  LDREXB  },                // LDREXB <Rt>, [<Rn>]
+  { "LDREXH", 0xe8d00f5f, 0xfff00fff,  LDREXB  },                // LDREXH <Rt>, [<Rn>]
+
+  { "LDREXD", 0xe8d00f4f, 0xfff00fff,  LDREXD  },                // LDREXD <Rt>, <Rt2>, [<Rn>]
+
+  { "STR",   0xf8c00000, 0xfff00000,  LDM_REG_IMM12 },          // STR   <rt>, [<rn>, {, #<imm12>]}
   { "STRB",  0xf8800000, 0xfff00000,  LDM_REG_IMM12 },          // STRB  <rt>, [<rn>, {, #<imm12>]}
   { "STRH",  0xf8a00000, 0xfff00000,  LDM_REG_IMM12 },          // STRH  <rt>, [<rn>, {, #<imm12>]}
- 
+
   { "STR",   0xf8400000, 0xfff00fc0,  LDM_REG_INDIRECT_LSL },   // STR   <rt>, [<rn>, <rm> {, LSL #<imm2>]}
   { "STRB",  0xf8000000, 0xfff00fc0,  LDM_REG_INDIRECT_LSL },   // STRB  <rt>, [<rn>, <rm> {, LSL #<imm2>]}
   { "STRH",  0xf8200000, 0xfff00fc0,  LDM_REG_INDIRECT_LSL },   // STRH  <rt>, [<rn>, <rm> {, LSL #<imm2>]}
@@ -366,15 +366,15 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
   { "STRH",  0xf8200800, 0xfff00800,  LDM_REG_IMM8 },           // STRH   <rt>, [<rn>, {, #<imm8>]}
   { "STRBT", 0xf8000e00, 0xfff00f00,  LDM_REG_IMM8 },           // STRBT  <rt>, [<rn>, {, #<imm8>]}
   { "STRHT", 0xf8200e00, 0xfff00f00,  LDM_REG_IMM8 },           // STRHT  <rt>, [<rn>, {, #<imm8>]}
-  { "STRT",  0xf8400e00, 0xfff00f00,  LDM_REG_IMM8 },           // STRT   <rt>, [<rn>, {, #<imm8>]}    
+  { "STRT",  0xf8400e00, 0xfff00f00,  LDM_REG_IMM8 },           // STRT   <rt>, [<rn>, {, #<imm8>]}
 
   { "STRD",  0xe8400000, 0xfe500000,  LDRD_REG_IMM8_SIGNED },    // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
 
-  { "STREX",  0xe8400f00, 0xfff00f00,  LDM_REG_IMM8 },           // STREX <Rt>, [Rn, {#imm8}]]                     
-  { "STREXB", 0xe8c00f4f, 0xfff00fff,  LDREXB  },                // STREXB <Rd>, <Rt>, [<Rn>]                     
-  { "STREXH", 0xe8c00f5f, 0xfff00fff,  LDREXB  },                // STREXH <Rd>, <Rt>, [<Rn>]                     
- 
-  { "STREXD", 0xe8d00f4f, 0xfff00fff,  LDREXD  },                // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]                     
+  { "STREX",  0xe8400f00, 0xfff00f00,  LDM_REG_IMM8 },           // STREX <Rt>, [Rn, {#imm8}]]
+  { "STREXB", 0xe8c00f4f, 0xfff00fff,  LDREXB  },                // STREXB <Rd>, <Rt>, [<Rn>]
+  { "STREXH", 0xe8c00f5f, 0xfff00fff,  LDREXB  },                // STREXH <Rd>, <Rt>, [<Rn>]
+
+  { "STREXD", 0xe8d00f4f, 0xfff00fff,  LDREXD  },                // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]
 
   { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT },       // SRSDB<c> SP{!},#<mode>
   { "SRS"  , 0xe98dc000, 0xffdffff0, SRS_FORMAT },       // SRS{IA}<c> SP{!},#<mode>
@@ -399,24 +399,24 @@ ThumbMRegList (
   UINTN     Index, Start, End;
   CHAR8     *Str;
   BOOLEAN   First;
- 
+
   Str = mThumbMregListStr;
   *Str = '\0';
   AsciiStrCat  (Str, "{");
-  
+
   for (Index = 0, First = TRUE; Index <= 15; Index++) {
     if ((RegBitMask & (1 << Index)) != 0) {
       Start = End = Index;
       for (Index++; ((RegBitMask & (1 << Index)) != 0) && (Index <= 9); Index++) {
         End = Index;
       }
-      
+
       if (!First) {
         AsciiStrCat  (Str, ",");
       } else {
         First = FALSE;
       }
-      
+
       if (Start == End) {
         AsciiStrCat  (Str, gReg[Start]);
       } else {
@@ -430,7 +430,7 @@ ThumbMRegList (
     AsciiStrCat  (Str, "ERROR");
   }
   AsciiStrCat  (Str, "}");
-  
+
   // BugBug: Make caller pass in buffer it is cleaner
   return mThumbMregListStr;
 }
@@ -444,17 +444,17 @@ SignExtend32 (
   if (((Data & TopBit) == 0) || (TopBit == BIT31)) {
     return Data;
   }
- 
+
   do {
     TopBit <<= 1;
-    Data |= TopBit; 
+    Data |= TopBit;
   } while ((TopBit & BIT31) != BIT31);
 
   return Data;
 }
 
 //
-// Some instructions specify the PC is always considered aligned 
+// Some instructions specify the PC is always considered aligned
 // The PC is after the instruction that is excuting. So you pass
 // in the instruction address and you get back the aligned answer
 //
@@ -467,17 +467,17 @@ PCAlign4 (
 }
 
 /**
-  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to 
-  point to next instructin. 
-  
-  We cheat and only decode instructions that access 
+  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
+  point to next instructin.
+
+  We cheat and only decode instructions that access
   memory. If the instruction is not found we dump the instruction in hex.
-   
-  @param  OpCodePtrPtr  Pointer to pointer of ARM Thumb instruction to disassemble.  
+
+  @param  OpCodePtrPtr  Pointer to pointer of ARM Thumb instruction to disassemble.
   @param  Buf           Buffer to sprintf disassembly into.
-  @param  Size          Size of Buf in bytes. 
+  @param  Size          Size of Buf in bytes.
   @param  Extended    TRUE dump hex for instruction too.
-  
+
 **/
 VOID
 DisassembleThumbInstruction (
@@ -499,12 +499,12 @@ DisassembleThumbInstruction (
   UINT32  PC, Target, msbit, lsbit;
   CHAR8   *Cond;
   BOOLEAN S, J1, J2, P, U, W;
-  UINT32  coproc, opc1, opc2, CRd, CRn, CRm; 
+  UINT32  coproc, opc1, opc2, CRd, CRn, CRm;
   UINT32  Mask;
 
   OpCodePtr = *OpCodePtrPtr;
   OpCode = **OpCodePtrPtr;
-  
+
   // Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.
   OpCode32 = (((UINT32)OpCode) << 16) | *(OpCodePtr + 1);
 
@@ -519,7 +519,7 @@ DisassembleThumbInstruction (
 
   // Increment by the minimum instruction size, Thumb2 could be bigger
   *OpCodePtrPtr += 1;
-  
+
   // Manage IT Block ItFlag TRUE means we are in an IT block
   /*if (*ItBlock != 0) {
     ItFlag = TRUE;
@@ -531,58 +531,58 @@ DisassembleThumbInstruction (
   for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {
     if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {
       if (Extended) {
-        Offset = AsciiSPrint (Buf, Size, "0x%04x       %-6a", OpCode, gOpThumb[Index].Start);   
+        Offset = AsciiSPrint (Buf, Size, "0x%04x       %-6a", OpCode, gOpThumb[Index].Start);
       } else {
-        Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);   
+        Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);
       }
       switch (gOpThumb[Index].AddressMode) {
       case LOAD_STORE_FORMAT1:
         // A6.5.1  <Rd>, [<Rn>, #<5_bit_offset>]
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
         return;
       case LOAD_STORE_FORMAT1_H:
         // A6.5.1  <Rd>, [<Rn>, #<5_bit_offset>]
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);
         return;
       case LOAD_STORE_FORMAT1_B:
         // A6.5.1  <Rd>, [<Rn>, #<5_bit_offset>]
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);
         return;
 
       case LOAD_STORE_FORMAT2:
         // A6.5.1  <Rd>, [<Rn>, <Rm>]
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
         return;
       case LOAD_STORE_FORMAT3:
         // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
         Target = (OpCode & 0xff) << 2;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);
         return;
       case LOAD_STORE_FORMAT4:
         // Rt, [SP, #imm8]
         Target = (OpCode & 0xff) << 2;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);
         return;
-      
+
       case LOAD_STORE_MULTIPLE_FORMAT1:
         // <Rn>!, {r0-r7}
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));
         return;
- 
+
       case POP_FORMAT:
         // POP {r0-r7,pc}
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));
         return;
 
       case PUSH_FORMAT:
         // PUSH {r0-r7,lr}
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));
         return;
 
-      
+
       case IMMED_8:
         // A6.7 <immed_8>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
         return;
 
       case CONDITIONAL_BRANCH:
@@ -591,83 +591,83 @@ DisassembleThumbInstruction (
         Cond = gCondition[(OpCode >> 8) & 0xf];
         Buf[Offset-5] = *Cond++;
         Buf[Offset-4] = *Cond;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x",  PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x",  PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
         return;
       case UNCONDITIONAL_BRANCH_SHORT:
         // A6.3.2 B  <target_address>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
         return;
- 
+
       case BRANCH_EXCHANGE:
         // A6.3.3 BX|BLX <Rm>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
         return;
 
       case DATA_FORMAT1:
         // A6.4.3  <Rd>, <Rn>, <Rm>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
         return;
       case DATA_FORMAT2:
         // A6.4.3  <Rd>, <Rn>, #3_bit_immed
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
         return;
       case DATA_FORMAT3:
         // A6.4.3  <Rd>|<Rn>, #imm8
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
         return;
       case DATA_FORMAT4:
         // A6.4.3  <Rd>|<Rm>, #immed_5
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
         return;
       case DATA_FORMAT5:
         // A6.4.3  <Rd>|<Rm>, <Rm>|<Rs>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
         return;
       case DATA_FORMAT6_SP:
         // A6.4.3  <Rd>, <reg>, #<8_Bit_immed>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
         return;
       case DATA_FORMAT6_PC:
         // A6.4.3  <Rd>, <reg>, #<8_Bit_immed>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
         return;
       case DATA_FORMAT7:
         // A6.4.3  SP, SP, #<7_Bit_immed>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);
         return;
       case DATA_FORMAT8:
         // A6.4.3  <Rd>|<Rn>, <Rm>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
         return;
-      
+
       case CPS_FORMAT:
         // A7.1.24
-        AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a",  ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");   
+        AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a",  ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
         return;
 
       case ENDIAN_FORMAT:
         // A7.1.24
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");
         return;
 
       case DATA_CBZ:
         // CB{N}Z <Rn>, <Lable>
         Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);
         return;
 
       case ADR_FORMAT:
         // ADR <Rd>, <Label>
         Target = (OpCode & 0xff) << 2;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
         return;
 
       case IT_BLOCK:
         // ITSTATE = cond:mask   OpCode[7:4]:OpCode[3:0]
         // ITSTATE[7:5] == cond[3:1]
-        // ITSTATE[4] == 1st Instruction cond[0]  
-        // ITSTATE[3] == 2st Instruction cond[0]  
-        // ITSTATE[2] == 3st Instruction cond[0]  
+        // ITSTATE[4] == 1st Instruction cond[0]
+        // ITSTATE[3] == 2st Instruction cond[0]
+        // ITSTATE[2] == 3st Instruction cond[0]
         // ITSTATE[1] == 4st Instruction cond[0]
         // ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions
         // 1st one  in ITSTATE low bits defines the number of instructions
@@ -684,13 +684,13 @@ DisassembleThumbInstruction (
         } else if ((OpCode & 0xf) == 0x8) {
           *ItBlock = 1;
         }
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);
         return;
       }
     }
   }
 
-  
+
   // Thumb2 are 32-bit instructions
   *OpCodePtrPtr += 1;
   Rt  = (OpCode32 >> 12) & 0xf;
@@ -701,9 +701,9 @@ DisassembleThumbInstruction (
   for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {
     if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {
       if (Extended) {
-        Offset = AsciiSPrint (Buf, Size, "0x%04x   %-6a", OpCode32, gOpThumb2[Index].Start);   
+        Offset = AsciiSPrint (Buf, Size, "0x%04x   %-6a", OpCode32, gOpThumb2[Index].Start);
       } else {
-        Offset = AsciiSPrint (Buf, Size, "   %-6a", gOpThumb2[Index].Start);   
+        Offset = AsciiSPrint (Buf, Size, "   %-6a", gOpThumb2[Index].Start);
       }
       switch (gOpThumb2[Index].AddressMode) {
       case B_T3:
@@ -716,7 +716,7 @@ DisassembleThumbInstruction (
         Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0;  // J1
         Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0;  // S
         Target = SignExtend32 (Target, BIT20);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
         return;
       case B_T4:
         // S:I1:I2:imm10:imm11:0
@@ -728,7 +728,7 @@ DisassembleThumbInstruction (
         Target |= (!(J1 ^ S) ? BIT23 : 0);  // I1
         Target |= (S ? BIT24 : 0);  // S
         Target = SignExtend32 (Target, BIT24);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
         return;
 
       case BL_T2:
@@ -741,7 +741,7 @@ DisassembleThumbInstruction (
         Target |= (!(J1 ^ S) ? BIT24 : 0);  // I1
         Target |= (S ? BIT25 : 0);  // S
         Target = SignExtend32 (Target, BIT25);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);   
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);
         return;
 
       case POP_T2:
@@ -750,7 +750,7 @@ DisassembleThumbInstruction (
         return;
 
       case POP_T3:
-        // <register> 
+        // <register>
         AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);
         return;
 
@@ -762,7 +762,7 @@ DisassembleThumbInstruction (
 
       case LDM_REG_IMM12_SIGNED:
         // <rt>, <label>
-        Target = OpCode32 & 0xfff; 
+        Target = OpCode32 & 0xfff;
         if ((OpCode32 & BIT23) == 0) {
           // U == 0 means subtrack, U == 1 means add
           Target = -Target;
@@ -779,7 +779,7 @@ DisassembleThumbInstruction (
           AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);
         }
         return;
-      
+
       case LDM_REG_IMM12:
         // <rt>, [<rn>, {, #<imm12>]}
         Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
@@ -810,7 +810,7 @@ DisassembleThumbInstruction (
       case LDRD_REG_IMM8_SIGNED:
         // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
         P = (OpCode32 & BIT24) == BIT24;  // index = P
-        U = (OpCode32 & BIT23) == BIT23;  
+        U = (OpCode32 & BIT23) == BIT23;
         W = (OpCode32 & BIT21) == BIT21;
         Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
         if (P) {
@@ -826,9 +826,9 @@ DisassembleThumbInstruction (
         }
         return;
 
-      case LDRD_REG_IMM8: 
-        // LDRD <rt>, <rt2>, <label>   
-        Target = (OpCode32 & 0xff) << 2; 
+      case LDRD_REG_IMM8:
+        // LDRD <rt>, <rt2>, <label>
+        Target = (OpCode32 & 0xff) << 2;
         if ((OpCode32 & BIT23) == 0) {
           // U == 0 means subtrack, U == 1 means add
           Target = -Target;
@@ -845,7 +845,7 @@ DisassembleThumbInstruction (
         // LDREXD <Rt>, <Rt2>, [<Rn>]
         AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);
         return;
-      
+
       case SRS_FORMAT:
         // SP{!}, #<mode>
         W = (OpCode32 & BIT21) == BIT21;
@@ -857,14 +857,14 @@ DisassembleThumbInstruction (
         W = (OpCode32 & BIT21) == BIT21;
         AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");
         return;
-      
+
       case ADD_IMM12:
         // ADD{S} <Rd>, <Rn>, #<const>   i:imm3:imm8
         if ((OpCode32 & BIT20) == BIT20) {
           Buf[Offset - 3] = 'S';  // assume %-6a
         }
         Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);
         return;
 
       case ADD_IMM12_1REG:
@@ -873,14 +873,14 @@ DisassembleThumbInstruction (
           Buf[Offset - 3] = 'S';  // assume %-6a
         }
         Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
         return;
 
       case THUMB2_IMM16:
         // MOVW <Rd>, #<const>   i:imm3:imm8
         Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
         Target |= ((OpCode32 >> 4) & 0xf0000);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
         return;
 
       case ADD_IMM5:
@@ -889,18 +889,18 @@ DisassembleThumbInstruction (
           Buf[Offset - 3] = 'S';  // assume %-6a
         }
         Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
-        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]); 
+        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
         if (Target != 0) {
-          AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target); 
+          AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
         }
         return;
 
       case ADD_IMM5_2REG:
         // CMP  <Rn>, <Rm> {,LSL #<const>} imm3:imm2
         Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
-        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]); 
+        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);
         if (Target != 0) {
-          AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target); 
+          AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
         }
 
 
@@ -910,7 +910,7 @@ DisassembleThumbInstruction (
           Buf[Offset - 3] = 'S';  // assume %-6a
         }
         Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);
         return;
 
       case ASR_3REG:
@@ -918,7 +918,7 @@ DisassembleThumbInstruction (
         if ((OpCode32 & BIT20) == BIT20) {
           Buf[Offset - 3] = 'S';  // assume %-6a
         }
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);
         return;
 
       case ADR_THUMB2:
@@ -929,13 +929,13 @@ DisassembleThumbInstruction (
         } else {
           Target = PCAlign4 (PC) + Target;
         }
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
         return;
 
       case CMN_THUMB2:
         // CMN <Rn>, #<const>}
         Target = (OpCode32 & 0xff) | ((OpCode >> 4) && 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target); 
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);
         return;
 
       case BFC_THUMB2:
@@ -944,11 +944,11 @@ DisassembleThumbInstruction (
         lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) &  0x1c);
         if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
           // BFC <Rd>, #<lsb>, #<width>
-          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1); 
+          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);
         } else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
-          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1); 
+          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);
         } else {
-          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1); 
+          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);
         }
         return;
 
@@ -977,7 +977,7 @@ DisassembleThumbInstruction (
         if (opc2 != 0) {
           AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
         }
-        return;  
+        return;
 
       case MRRC_THUMB2:
         // MRC  <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
@@ -986,7 +986,7 @@ DisassembleThumbInstruction (
         CRn    = (OpCode32 >> 16) & 0xf;
         CRm    = OpCode32 & 0xf;
         Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);
-        return;  
+        return;
 
       case THUMB2_2REGS:
         // <Rd>, <Rm>
@@ -1002,7 +1002,7 @@ DisassembleThumbInstruction (
         // MRS <Rd>, CPSR
         AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);
         return;
-        
+
       case THUMB2_MSR:
         // MRS CPSR_<fields>, <Rd>
         Target = (OpCode32 >> 10) & 3;
@@ -1031,19 +1031,19 @@ DisassembleArmInstruction (
 
 
 /**
-  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to 
-  point to next instructin. 
-  
-  We cheat and only decode instructions that access 
+  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
+  point to next instructin.
+
+  We cheat and only decode instructions that access
   memory. If the instruction is not found we dump the instruction in hex.
-   
-  @param  OpCodePtrPtr  Pointer to pointer of ARM Thumb instruction to disassemble.  
+
+  @param  OpCodePtrPtr  Pointer to pointer of ARM Thumb instruction to disassemble.
   @param  Thumb         TRUE for Thumb(2), FALSE for ARM instruction stream
   @param  Extended      TRUE dump hex for instruction too.
   @param  ItBlock       Size of IT Block
   @param  Buf           Buffer to sprintf disassembly into.
-  @param  Size          Size of Buf in bytes. 
-  
+  @param  Size          Size of Buf in bytes.
+
 **/
 VOID
 DisassembleInstruction (
@@ -1061,4 +1061,4 @@ DisassembleInstruction (
     DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);
   }
 }
- 
+

+ 38 - 38
ArmPkg/Library/ArmDmaLib/ArmDmaLib.c

@@ -2,7 +2,7 @@
   Generic ARM implementation of DmaLib.h
 
   Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -39,25 +39,25 @@ typedef struct {
 EFI_CPU_ARCH_PROTOCOL      *gCpu;
 UINTN                      gCacheAlignment = 0;
 
-/**                                                                 
+/**
   Provides the DMA controller-specific addresses needed to access system memory.
-  
+
   Operation is relative to the DMA bus master.
-            
+
   @param  Operation             Indicates if the bus master is going to read or write to system memory.
   @param  HostAddress           The system memory address to map to the DMA controller.
   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
-                                that were mapped.                                                 
+                                that were mapped.
   @param  DeviceAddress         The resulting map address for the bus master controller to use to
-                                access the hosts HostAddress.                                        
+                                access the hosts HostAddress.
   @param  Mapping               A resulting value to pass to Unmap().
-                                  
+
   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
-  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.                                
+  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
-                                   
+
 **/
 EFI_STATUS
 EFIAPI
@@ -89,7 +89,7 @@ DmaMap (
   if (Map == NULL) {
     return  EFI_OUT_OF_RESOURCES;
   }
-  
+
   *Mapping = Map;
 
   if ((((UINTN)HostAddress & (gCacheAlignment - 1)) != 0) ||
@@ -145,15 +145,15 @@ DmaMap (
 }
 
 
-/**                                                                 
+/**
   Completes the DmaMapBusMasterRead(), DmaMapBusMasterWrite(), or DmaMapBusMasterCommonBuffer()
   operation and releases any corresponding resources.
-            
+
   @param  Mapping               The mapping value returned from DmaMap*().
-                                  
+
   @retval EFI_SUCCESS           The range was unmapped.
   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
-                                   
+
 **/
 EFI_STATUS
 EFIAPI
@@ -162,21 +162,21 @@ DmaUnmap (
   )
 {
   MAP_INFO_INSTANCE *Map;
-  
+
   if (Mapping == NULL) {
     ASSERT (FALSE);
     return EFI_INVALID_PARAMETER;
   }
-  
+
   Map = (MAP_INFO_INSTANCE *)Mapping;
-  
+
   if (Map->DoubleBuffer) {
     if ((Map->Operation == MapOperationBusMasterWrite) || (Map->Operation == MapOperationBusMasterCommonBuffer)) {
       CopyMem ((VOID *)(UINTN)Map->HostAddress, (VOID *)(UINTN)Map->DeviceAddress, Map->NumberOfBytes);
     }
-    
+
     DmaFreeBuffer (EFI_SIZE_TO_PAGES (Map->NumberOfBytes), (VOID *)(UINTN)Map->DeviceAddress);
-  
+
   } else {
     if (Map->Operation == MapOperationBusMasterWrite) {
       //
@@ -185,28 +185,28 @@ DmaUnmap (
       gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
     }
   }
-  
+
   FreePool (Map);
 
   return EFI_SUCCESS;
 }
 
-/**                                                                 
+/**
   Allocates pages that are suitable for an DmaMap() of type MapOperationBusMasterCommonBuffer.
-  mapping.                                                                       
-            
+  mapping.
+
   @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
-                                EfiRuntimeServicesData.                               
-  @param  Pages                 The number of pages to allocate.                                
+                                EfiRuntimeServicesData.
+  @param  Pages                 The number of pages to allocate.
   @param  HostAddress           A pointer to store the base system memory address of the
-                                allocated range.                                        
+                                allocated range.
 
                                 @retval EFI_SUCCESS           The requested memory pages were allocated.
   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
-                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.                     
+                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.  
-                                   
+  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
+
 **/
 EFI_STATUS
 EFIAPI
@@ -237,16 +237,16 @@ DmaAllocateBuffer (
 }
 
 
-/**                                                                 
+/**
   Frees memory that was allocated with DmaAllocateBuffer().
-            
-  @param  Pages                 The number of pages to free.                                
-  @param  HostAddress           The base system memory address of the allocated range.                                    
-                                  
+
+  @param  Pages                 The number of pages to free.
+  @param  HostAddress           The base system memory address of the allocated range.
+
   @retval EFI_SUCCESS           The requested memory pages were freed.
   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
                                 was not allocated with DmaAllocateBuffer().
-                                     
+
 **/
 EFI_STATUS
 EFIAPI
@@ -257,8 +257,8 @@ DmaFreeBuffer (
 {
   if (HostAddress == NULL) {
      return EFI_INVALID_PARAMETER;
-  } 
-  
+  }
+
   UncachedFreePages (HostAddress, Pages);
   return EFI_SUCCESS;
 }
@@ -278,7 +278,7 @@ ArmDmaLibConstructor (
   ASSERT_EFI_ERROR(Status);
 
   gCacheAlignment = ArmDataCacheLineLength ();
-  
+
   return Status;
 }
 

+ 10 - 10
ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf

@@ -1,14 +1,14 @@
 #/** @file
-#  
+#
 #  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
 #  http://opensource.org/licenses/bsd-license.php
-#  
+#
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#  
+#
 #**/
 
 [Defines]
@@ -17,7 +17,7 @@
   FILE_GUID                      = F1BD6B36-B705-43aa-8A28-33F58ED85EFB
   MODULE_TYPE                    = UEFI_DRIVER
   VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = DmaLib 
+  LIBRARY_CLASS                  = DmaLib
   CONSTRUCTOR                    = ArmDmaLibConstructor
 
 [Sources.common]
@@ -27,7 +27,7 @@
   MdePkg/MdePkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   ArmPkg/ArmPkg.dec
-  
+
 
 [LibraryClasses]
   DebugLib
@@ -37,14 +37,14 @@
   IoLib
   BaseMemoryLib
   ArmLib
-  
-  
+
+
 [Protocols]
   gEfiCpuArchProtocolGuid
-  
+
 [Guids]
- 
+
 [Pcd]
 
 [Depex]
-  gEfiCpuArchProtocolGuid
+  gEfiCpuArchProtocolGuid

+ 1 - 1
ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c

@@ -2,7 +2,7 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at

+ 3 - 3
ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf

@@ -25,11 +25,11 @@
   ../Common/Arm/ArmLibSupport.S    | GCC
   ../Common/Arm/ArmLibSupport.asm  | RVCT
   ../Common/ArmLib.c
-  
+
   Arm11Support.S    | GCC
   Arm11Support.asm  | RVCT
 
-  Arm11Lib.c  
+  Arm11Lib.c
   Arm11LibMem.c
   ../Arm9/Arm9CacheInformation.c
 
@@ -39,7 +39,7 @@
 
 [LibraryClasses]
   MemoryAllocationLib
-  
+
 [Protocols]
   gEfiCpuArchProtocolGuid
 

+ 7 - 7
ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c

@@ -2,7 +2,7 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -29,7 +29,7 @@ FillTranslationTable (
   UINTN   Index;
   UINT32  Attributes;
   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
-  
+
   switch (MemoryRegion->Attributes) {
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
@@ -53,10 +53,10 @@ FillTranslationTable (
       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
       break;
   }
-  
+
   Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
   Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
-  
+
   for (Index = 0; Index < Sections; Index++)
   {
     *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
@@ -84,7 +84,7 @@ ArmConfigureMmu (
   if (TranslationTableBase != NULL) {
     *TranslationTableBase = TranslationTable;
   }
-  
+
   if (TranslationTableBase != NULL) {
     *TranslationTableSize = TRANSLATION_TABLE_SIZE;
   }
@@ -109,7 +109,7 @@ ArmConfigureMmu (
   }
 
   ArmSetTTBR0(TranslationTable);
-    
+
   ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
                             DOMAIN_ACCESS_CONTROL_NONE(14) |
                             DOMAIN_ACCESS_CONTROL_NONE(13) |
@@ -126,7 +126,7 @@ ArmConfigureMmu (
                             DOMAIN_ACCESS_CONTROL_NONE( 2) |
                             DOMAIN_ACCESS_CONTROL_NONE( 1) |
                             DOMAIN_ACCESS_CONTROL_MANAGER(0));
-    
+
   ArmEnableInstructionCache();
   ArmEnableDataCache();
   ArmEnableMmu();

+ 3 - 3
ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf

@@ -25,11 +25,11 @@
   ../Common/Arm/ArmLibSupport.S    | GCC
   ../Common/Arm/ArmLibSupport.asm  | RVCT
   ../Common/ArmLib.c
-  
+
   Arm11Support.S    | GCC
   Arm11Support.asm  | RVCT
 
-  Arm11Lib.c  
+  Arm11Lib.c
   Arm11LibMem.c
   ../Arm9/Arm9CacheInformation.c
 
@@ -39,7 +39,7 @@
 
 [LibraryClasses]
   PrePiLib
-  
+
 [Protocols]
   gEfiCpuArchProtocolGuid
 

+ 2 - 2
ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf

@@ -25,10 +25,10 @@
   ../Common/Arm/ArmLibSupport.S    | GCC
   ../Common/Arm/ArmLibSupport.asm  | RVCT
   ../Common/ArmLib.c
-  
+
   Arm11Support.S    | GCC
   Arm11Support.asm  | RVCT
-  
+
   Arm11Lib.c
   ../Arm9/Arm9CacheInformation.c
 

+ 11 - 11
ArmPkg/Library/ArmLib/Arm11/Arm11Support.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 # Copyright (c) 2011, ARM Limited. All rights reserved.
@@ -73,12 +73,12 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb):
   bx lr
 
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line                                           
+  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
   bx      lr
 
 
 ASM_PFX(ArmCleanDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     
+  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
   bx      lr
 
 
@@ -135,7 +135,7 @@ ASM_PFX(ArmEnableDataCache):
   orr     R0,R0,R1              @Set C bit
   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
   bx      LR
-    
+
 ASM_PFX(ArmDisableDataCache):
   LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON
   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
@@ -149,7 +149,7 @@ ASM_PFX(ArmEnableInstructionCache):
   orr     R0,R0,R1             @Set I bit
   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
   bx      LR
-  
+
 ASM_PFX(ArmDisableInstructionCache):
   ldr     R1,=IC_ON
   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
@@ -171,17 +171,17 @@ ASM_PFX(ArmDisableBranchPrediction):
 
 ASM_PFX(ArmDataMemoryBarrier):
   mov R0, #0
-  mcr P15, #0, R0, C7, C10, #5 
+  mcr P15, #0, R0, C7, C10, #5
   bx      LR
-  
+
 ASM_PFX(ArmDataSyncronizationBarrier):
   mov R0, #0
-  mcr P15, #0, R0, C7, C10, #4 
+  mcr P15, #0, R0, C7, C10, #4
   bx      LR
-  
+
 ASM_PFX(ArmInstructionSynchronizationBarrier):
   mov R0, #0
-  mcr P15, #0, R0, C7, C5, #4 
+  mcr P15, #0, R0, C7, C5, #4
   bx      LR
 
 ASM_PFX(ArmSetLowVectors):
@@ -206,7 +206,7 @@ ASM_PFX(ArmIsMpCore):
   cmp     r0, r1
   movne   r0, #0
   pop     { r1 }
-  bx      lr     
+  bx      lr
 
 ASM_PFX(ArmCallWFI):
   wfi

+ 10 - 10
ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm

@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ 
+//------------------------------------------------------------------------------
 //
 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 //
@@ -43,12 +43,12 @@ XP_ON       EQU     ( 0x1:SHL:23 )
 
 
 ArmInvalidateDataCacheEntryByMVA
-  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
+  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
   bx      lr
 
 
 ArmCleanDataCacheEntryByMVA
-  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
+  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
   bx      lr
 
 
@@ -105,7 +105,7 @@ ArmEnableDataCache
   ORR     R0,R0,R1              ;Set C bit
   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
   BX      LR
-    
+
 ArmDisableDataCache
   LDR     R1,=DC_ON
   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
@@ -119,7 +119,7 @@ ArmEnableInstructionCache
   ORR     R0,R0,R1             ;Set I bit
   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
   BX      LR
-  
+
 ArmDisableInstructionCache
   LDR     R1,=IC_ON
   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
@@ -141,17 +141,17 @@ ArmDisableBranchPrediction
 
 ASM_PFX(ArmDataMemoryBarrier):
   mov R0, #0
-  mcr P15, #0, R0, C7, C10, #5 
+  mcr P15, #0, R0, C7, C10, #5
   bx      LR
-  
+
 ASM_PFX(ArmDataSyncronizationBarrier):
   mov R0, #0
-  mcr P15, #0, R0, C7, C10, #4 
+  mcr P15, #0, R0, C7, C10, #4
   bx      LR
-  
+
 ASM_PFX(ArmInstructionSynchronizationBarrier):
   MOV R0, #0
-  MCR P15, #0, R0, C7, C5, #4 
+  MCR P15, #0, R0, C7, C5, #4
   bx      LR
 
     END

+ 2 - 2
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf

@@ -28,7 +28,7 @@
 
   Arm9Support.S    | GCC
   Arm9Support.asm  | RVCT
-  
+
   Arm9Lib.c
   Arm9CacheInformation.c
 
@@ -38,7 +38,7 @@
 
 [LibraryClasses]
   MemoryAllocationLib
-  
+
 [Protocols]
   gEfiCpuArchProtocolGuid
 

+ 1 - 1
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf

@@ -28,7 +28,7 @@
 
   Arm9Support.S    | GCC
   Arm9Support.asm  | RVCT
-  
+
   Arm9Lib.c
   Arm9CacheInformation.c
 

+ 11 - 11
ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c

@@ -56,7 +56,7 @@ ArmDataCachePresent (
     default:                return FALSE;
   }
 }
-  
+
 UINTN
 EFIAPI
 ArmDataCacheSize (
@@ -65,16 +65,16 @@ ArmDataCacheSize (
 {
   switch (DATA_CACHE_SIZE (ArmCacheInfo ()))
   {
-    case CACHE_SIZE_4_KB:   return   4 * 1024;      
+    case CACHE_SIZE_4_KB:   return   4 * 1024;
     case CACHE_SIZE_8_KB:   return   8 * 1024;
-    case CACHE_SIZE_16_KB:  return  16 * 1024;      
+    case CACHE_SIZE_16_KB:  return  16 * 1024;
     case CACHE_SIZE_32_KB:  return  32 * 1024;
     case CACHE_SIZE_64_KB:  return  64 * 1024;
     case CACHE_SIZE_128_KB: return 128 * 1024;
     default:                return   0;
   }
 }
-  
+
 UINTN
 EFIAPI
 ArmDataCacheAssociativity (
@@ -88,7 +88,7 @@ ArmDataCacheAssociativity (
     default:                          return 0;
   }
 }
-  
+
 UINTN
 EFIAPI
 ArmDataCacheLineLength (
@@ -101,7 +101,7 @@ ArmDataCacheLineLength (
     default:                         return  0;
   }
 }
-  
+
 BOOLEAN
 EFIAPI
 ArmInstructionCachePresent (
@@ -115,7 +115,7 @@ ArmInstructionCachePresent (
     default:                return FALSE;
   }
 }
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheSize (
@@ -124,16 +124,16 @@ ArmInstructionCacheSize (
 {
   switch (INSTRUCTION_CACHE_SIZE (ArmCacheInfo ()))
   {
-    case CACHE_SIZE_4_KB:   return   4 * 1024;      
+    case CACHE_SIZE_4_KB:   return   4 * 1024;
     case CACHE_SIZE_8_KB:   return   8 * 1024;
-    case CACHE_SIZE_16_KB:  return  16 * 1024;      
+    case CACHE_SIZE_16_KB:  return  16 * 1024;
     case CACHE_SIZE_32_KB:  return  32 * 1024;
     case CACHE_SIZE_64_KB:  return  64 * 1024;
     case CACHE_SIZE_128_KB: return 128 * 1024;
     default:                return   0;
   }
 }
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheAssociativity (
@@ -148,7 +148,7 @@ ArmInstructionCacheAssociativity (
     default:                          return 0;
   }
 }
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheLineLength (

+ 8 - 8
ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c

@@ -2,7 +2,7 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -30,7 +30,7 @@ FillTranslationTable (
   UINTN   Index;
   UINT32  Attributes;
   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
-  
+
   switch (MemoryRegion->Attributes) {
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
@@ -49,13 +49,13 @@ FillTranslationTable (
       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
       break;
   }
-  
+
   Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
   Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
-  
+
   // The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
   ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
-  
+
   for (Index = 0; Index < Sections; Index++)
   {
     *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
@@ -83,7 +83,7 @@ ArmConfigureMmu (
   if (TranslationTableBase != NULL) {
     *TranslationTableBase = TranslationTable;
   }
-  
+
   if (TranslationTableBase != NULL) {
     *TranslationTableSize = TRANSLATION_TABLE_SIZE;
   }
@@ -108,7 +108,7 @@ ArmConfigureMmu (
   }
 
   ArmSetTTBR0(TranslationTable);
-    
+
   ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
                             DOMAIN_ACCESS_CONTROL_NONE(14) |
                             DOMAIN_ACCESS_CONTROL_NONE(13) |
@@ -125,7 +125,7 @@ ArmConfigureMmu (
                             DOMAIN_ACCESS_CONTROL_NONE( 2) |
                             DOMAIN_ACCESS_CONTROL_NONE( 1) |
                             DOMAIN_ACCESS_CONTROL_MANAGER(0));
-    
+
   ArmEnableInstructionCache();
   ArmEnableDataCache();
   ArmEnableMmu();

+ 10 - 10
ArmPkg/Library/ArmLib/Arm9/Arm9Support.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 #
@@ -41,11 +41,11 @@ GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
 #------------------------------------------------------------------------------
 
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c6, 1   @ invalidate single data cache line                                           
+  mcr     p15, 0, r0, c7, c6, 1   @ invalidate single data cache line
   bx      lr
 
 ASM_PFX(ArmCleanDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c10, 1  @ clean single data cache line     
+  mcr     p15, 0, r0, c7, c10, 1  @ clean single data cache line
   bx      lr
 
 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
@@ -58,17 +58,17 @@ ASM_PFX(ArmEnableInstructionCache):
   orr    r0,r0,r1             @Set I bit
   mcr    p15,0,r0,c1,c0,0     @Write control register configuration data
   bx     LR
-  
+
 ASM_PFX(ArmDisableInstructionCache):
   ldr    r1,=IC_ON
   mrc    p15,0,r0,c1,c0,0     @Read control register configuration data
   bic    r0,r0,r1             @Clear I bit.
   mcr    p15,0,r0,c1,c0,0     @Write control register configuration data
   bx     LR
-  
+
 ASM_PFX(ArmInvalidateInstructionCache):
   mov     r0,#0
-  mcr     p15,0,r0,c7,c5,0     @Invalidate entire Instruction cache. 
+  mcr     p15,0,r0,c7,c5,0     @Invalidate entire Instruction cache.
                          @Also flushes the branch target cache.
   mov     r0,#0
   mcr     p15,0,r0,c7,c10,4    @Data write buffer
@@ -99,7 +99,7 @@ ASM_PFX(ArmEnableDataCache):
   orr     R0,R0,R1              @Set C bit
   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
   bx      LR
-  
+
 ASM_PFX(ArmDisableDataCache):
   ldr     R1,=DC_ON
   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
@@ -113,7 +113,7 @@ ASM_PFX(ArmCleanDataCache):
   mov     R0,#0
   mcr     p15,0,R0,c7,c10,4  @Drain write buffer
   bx      LR
-    
+
 ASM_PFX(ArmInvalidateDataCache):
   mov     R0,#0
   mcr     p15,0,R0,c7,c6,0        @Invalidate entire data cache
@@ -138,12 +138,12 @@ ASM_PFX(ArmDataMemoryBarrier):
   mov R0, #0
   mcr P15, #0, R0, C7, C10, #5    @ check if this is OK?
   bx      LR
-  
+
 ASM_PFX(ArmDataSyncronizationBarrier):
   mov R0, #0
   mcr P15, #0, R0, C7, C10, #4   @ check if this is OK?
   bx      LR
-  
+
 ASM_PFX(ArmInstructionSynchronizationBarrier):
   mov R0, #0
   mcr P15, #0, R0, C7, C5, #4     @ check if this is OK?

+ 8 - 8
ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm

@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ 
+//------------------------------------------------------------------------------
 //
 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 //
@@ -41,12 +41,12 @@ IC_ON       EQU     ( 0x1:SHL:12 )
 
 
 ArmInvalidateDataCacheEntryByMVA
-  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
+  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
   BX      lr
 
 
 ArmCleanDataCacheEntryByMVA
-  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
+  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line
   BX      lr
 
 
@@ -60,7 +60,7 @@ ArmEnableInstructionCache
   ORR     R0,R0,R1             ;Set I bit
   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
   BX      LR
-  
+
 ArmDisableInstructionCache
   LDR     R1,=IC_ON
   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
@@ -100,7 +100,7 @@ ArmEnableDataCache
   ORR     R0,R0,R1              ;Set C bit
   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
   BX      LR
-    
+
 ArmDisableDataCache
   LDR     R1,=DC_ON
   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
@@ -121,7 +121,7 @@ ArmInvalidateDataCache
   MOV     R0,#0
   MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
   BX      LR
-  
+
 ArmCleanInvalidateDataCache
   MRC     p15,0,r15,c7,c14,3
   BNE     ArmCleanInvalidateDataCache
@@ -139,12 +139,12 @@ ASM_PFX(ArmDataMemoryBarrier):
   mov R0, #0
   mcr P15, #0, R0, C7, C10, #5  ; Check to see if this is correct
   bx      LR
-  
+
 ASM_PFX(ArmDataSyncronizationBarrier):
   mov R0, #0
   mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
   bx      LR
-  
+
 ASM_PFX(ArmInstructionSynchronizationBarrier):
   MOV R0, #0
   MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct

+ 7 - 7
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 # Copyright (c) 2011-2013, ARM Limited. All rights reserved.
@@ -81,21 +81,21 @@ ASM_PFX(ArmDisableInterrupts):
   cpsid   if
   isb
   bx      LR
-  
-// UINT32 
+
+// UINT32
 // ReadCCSIDR (
 //   IN UINT32 CSSELR
-//   )  
+//   )
 ASM_PFX(ReadCCSIDR):
   mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)
   isb
   mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)
   bx  lr
-  
-// UINT32 
+
+// UINT32
 // ReadCLIDR (
 //   IN UINT32 CSSELR
-//   )  
+//   )
 ASM_PFX(ReadCLIDR):
   mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
   bx  lr

+ 7 - 7
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm

@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ 
+//------------------------------------------------------------------------------
 //
 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 // Copyright (c) 2011-2013, ARM Limited. All rights reserved.
@@ -80,21 +80,21 @@ ArmDisableInterrupts
   cpsid   if
   isb
   bx      LR
-  
-// UINT32 
+
+// UINT32
 // ReadCCSIDR (
 //   IN UINT32 CSSELR
-//   )  
+//   )
 ReadCCSIDR
   mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
   isb
   mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
   bx  lr
-  
-// UINT32 
+
+// UINT32
 // ReadCLIDR (
 //   IN UINT32 CSSELR
-//   )  
+//   )
 ReadCLIDR
   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
   bx  lr

+ 7 - 7
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c

@@ -1,14 +1,14 @@
 /** @file
 *
 *  Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-*  
-*  This program and the accompanying materials                          
-*  are licensed and made available under the terms and conditions of the BSD License         
-*  which accompanies this distribution.  The full text of the license may be found at        
-*  http://opensource.org/licenses/bsd-license.php                                            
 *
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 *
 **/
 

+ 1 - 1
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # Copyright (c) 2011, ARM Limited. All rights reserved.
 #

+ 1 - 1
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm

@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ 
+//------------------------------------------------------------------------------
 //
 // Copyright (c) 2011, ARM Limited. All rights reserved.
 //

+ 24 - 24
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c

@@ -2,7 +2,7 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -47,7 +47,7 @@ ArmDataCachePresent (
   )
 {
   UINT32 CLIDR = ReadCLIDR ();
-  
+
   if ((CLIDR & 0x2) == 0x2) {
     // Instruction cache exists
     return TRUE;
@@ -56,10 +56,10 @@ ArmDataCachePresent (
     // Unified cache
     return TRUE;
   }
-  
+
   return FALSE;
 }
-  
+
 UINTN
 EFIAPI
 ArmDataCacheSize (
@@ -70,15 +70,15 @@ ArmDataCacheSize (
   UINT32 Associativity;
   UINT32 LineSize;
   UINT32 CCSIDR = ReadCCSIDR (0);
-  
+
   LineSize      = (1 << ((CCSIDR & 0x7) + 2));
   Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
   NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
 
   // LineSize is in words (4 byte chunks)
-  return  NumSets * Associativity * LineSize * 4;      
+  return  NumSets * Associativity * LineSize * 4;
 }
-  
+
 UINTN
 EFIAPI
 ArmDataCacheAssociativity (
@@ -89,14 +89,14 @@ ArmDataCacheAssociativity (
 
   return ((CCSIDR >> 3) & 0x3ff) + 1;
 }
-  
+
 UINTN
 ArmDataCacheSets (
   VOID
   )
 {
   UINT32 CCSIDR = ReadCCSIDR (0);
-  
+
   return ((CCSIDR >> 13) & 0x7fff) + 1;
 }
 
@@ -111,7 +111,7 @@ ArmDataCacheLineLength (
   // * 4 converts to bytes
   return (1 << (CCSIDR + 2)) * 4;
 }
-  
+
 BOOLEAN
 EFIAPI
 ArmInstructionCachePresent (
@@ -119,7 +119,7 @@ ArmInstructionCachePresent (
   )
 {
   UINT32 CLIDR = ReadCLIDR ();
-  
+
   if ((CLIDR & 1) == 1) {
     // Instruction cache exists
     return TRUE;
@@ -128,10 +128,10 @@ ArmInstructionCachePresent (
     // Unified cache
     return TRUE;
   }
-  
+
   return FALSE;
 }
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheSize (
@@ -142,15 +142,15 @@ ArmInstructionCacheSize (
   UINT32 Associativity;
   UINT32 LineSize;
   UINT32 CCSIDR = ReadCCSIDR (1);
-  
+
   LineSize      = (1 << ((CCSIDR & 0x7) + 2));
   Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
   NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
 
   // LineSize is in words (4 byte chunks)
-  return  NumSets * Associativity * LineSize * 4;      
+  return  NumSets * Associativity * LineSize * 4;
 }
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheAssociativity (
@@ -162,7 +162,7 @@ ArmInstructionCacheAssociativity (
   return ((CCSIDR >> 3) & 0x3ff) + 1;
 //  return 4;
 }
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheSets (
@@ -170,7 +170,7 @@ ArmInstructionCacheSets (
   )
 {
   UINT32 CCSIDR = ReadCCSIDR (1);
-  
+
   return ((CCSIDR >> 13) & 0x7fff) + 1;
 }
 
@@ -198,11 +198,11 @@ ArmV7DataCacheOperation (
 
   SavedInterruptState = ArmGetInterruptState ();
   ArmDisableInterrupts ();
-  
+
   ArmV7AllDataCachesOperation (DataCacheOperation);
-  
+
   ArmDrainWriteBuffer ();
-  
+
   if (SavedInterruptState) {
     ArmEnableInterrupts ();
   }
@@ -218,11 +218,11 @@ ArmV7PoUDataCacheOperation (
 
   SavedInterruptState = ArmGetInterruptState ();
   ArmDisableInterrupts ();
-  
+
   ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
-  
+
   ArmDrainWriteBuffer ();
-  
+
   if (SavedInterruptState) {
     ArmEnableInterrupts ();
   }

+ 1 - 1
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h

@@ -27,6 +27,6 @@ VOID
 ArmV7AllDataCachesOperation (
   IN  ARM_V7_CACHE_OPERATION  DataCacheOperation
   );
-  
+
 #endif // __ARM_V7_LIB_H__
 

+ 3 - 3
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf

@@ -28,10 +28,10 @@
   ../Common/Arm/ArmLibSupport.S    | GCC
   ../Common/Arm/ArmLibSupport.asm  | RVCT
   ../Common/ArmLib.c
-  
+
   ArmV7Support.S    | GCC
   ArmV7Support.asm  | RVCT
-  
+
   ArmV7Lib.c
   ArmV7Mmu.c
 
@@ -45,7 +45,7 @@
 
 [LibraryClasses]
   MemoryAllocationLib
-  
+
 [Protocols]
   gEfiCpuArchProtocolGuid
 

+ 4 - 4
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf

@@ -28,13 +28,13 @@
   ../Common/Arm/ArmLibSupport.S    | GCC
   ../Common/Arm/ArmLibSupport.asm  | RVCT
   ../Common/ArmLib.c
-  
+
   ArmV7Support.S    | GCC
   ArmV7Support.asm  | RVCT
-  
+
   ArmV7Lib.c
   ArmV7Mmu.c
-  
+
   ArmV7ArchTimer.c
   ArmV7ArchTimerSupport.S    | GCC
   ArmV7ArchTimerSupport.asm  | RVCT
@@ -45,7 +45,7 @@
 
 [LibraryClasses]
   PrePiLib
-  
+
 [Protocols]
   gEfiCpuArchProtocolGuid
 

+ 9 - 9
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf

@@ -1,13 +1,13 @@
 #/* @file
 #  Copyright (c) 2011, ARM Limited. All rights reserved.
-#  
-#  This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http://opensource.org/licenses/bsd-license.php                                            
 #
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 #*/
 
@@ -26,12 +26,12 @@
   ../Common/Arm/ArmLibSupport.S    | GCC
   ../Common/Arm/ArmLibSupport.asm  | RVCT
   ../Common/ArmLib.c
-  
+
   ArmV7Support.S    | GCC
   ArmV7Support.asm  | RVCT
 
   ArmV7Lib.c
-  
+
   ArmV7ArchTimer.c
   ArmV7ArchTimerSupport.S    | GCC
   ArmV7ArchTimerSupport.asm    | RVCT

+ 16 - 16
ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c

@@ -2,18 +2,18 @@
 *  File managing the MMU for ARMv7 architecture
 *
 *  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-*  
-*  This program and the accompanying materials                          
-*  are licensed and made available under the terms and conditions of the BSD License         
-*  which accompanies this distribution.  The full text of the license may be found at        
-*  http://opensource.org/licenses/bsd-license.php                                            
 *
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 *
 **/
 
-#include <Uefi.h> 
+#include <Uefi.h>
 #include <Chipset/ArmV7.h>
 #include <Library/BaseMemoryLib.h>
 #include <Library/MemoryAllocationLib.h>
@@ -145,7 +145,7 @@ FillTranslationTable (
   UINT32  Attributes;
   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
   UINT32  RemainLength = MemoryRegion->Length;
-  
+
   ASSERT(MemoryRegion->Length > 0);
 
   switch (MemoryRegion->Attributes) {
@@ -177,7 +177,7 @@ FillTranslationTable (
       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
       break;
   }
-  
+
   // Get the first section entry for this mapping
   SectionEntry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
 
@@ -231,7 +231,7 @@ ArmConfigureMmu (
   if (TranslationTableBase != NULL) {
     *TranslationTableBase = TranslationTable;
   }
-  
+
   if (TranslationTableSize != NULL) {
     *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;
   }
@@ -251,13 +251,13 @@ ArmConfigureMmu (
   }
 
   // Translate the Memory Attributes into Translation Table Register Attributes
-  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || 
+  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
     TTBRAttributes = TTBR_NON_CACHEABLE;
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || 
+  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
     TTBRAttributes = TTBR_WRITE_BACK_ALLOC;
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || 
+  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
     TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;
   } else {
@@ -278,7 +278,7 @@ ArmConfigureMmu (
   ArmInvalidateInstructionCache ();
 
   ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
-    
+
   ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
                              DOMAIN_ACCESS_CONTROL_NONE(14) |
                              DOMAIN_ACCESS_CONTROL_NONE(13) |
@@ -295,7 +295,7 @@ ArmConfigureMmu (
                              DOMAIN_ACCESS_CONTROL_NONE( 2) |
                              DOMAIN_ACCESS_CONTROL_NONE( 1) |
                              DOMAIN_ACCESS_CONTROL_MANAGER(0));
-    
+
   ArmEnableInstructionCache();
   ArmEnableDataCache();
   ArmEnableMmu();

+ 21 - 21
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
@@ -63,13 +63,13 @@ GCC_ASM_EXPORT (ArmReadIdPfr1)
 
 
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line       
+  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
   dsb
   isb
   bx      lr
 
 ASM_PFX(ArmCleanDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     
+  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
   dsb
   isb
   bx      lr
@@ -83,21 +83,21 @@ ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
 
 
 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
-  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line    
+  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
   dsb
   isb
   bx      lr
 
 
 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
-  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line    
+  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
   dsb
   isb
   bx      lr
 
 
 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
-  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line    
+  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
   dsb
   isb
   bx      lr
@@ -141,7 +141,7 @@ ASM_PFX(ArmDisableCachesAndMmu):
 ASM_PFX(ArmMmuEnabled):
   mrc     p15,0,R0,c1,c0,0
   and     R0,R0,#1
-  bx      LR  
+  bx      LR
 
 ASM_PFX(ArmEnableDataCache):
   ldr     R1,=DC_ON
@@ -151,7 +151,7 @@ ASM_PFX(ArmEnableDataCache):
   dsb
   isb
   bx      LR
-    
+
 ASM_PFX(ArmDisableDataCache):
   ldr     R1,=DC_ON
   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
@@ -169,7 +169,7 @@ ASM_PFX(ArmEnableInstructionCache):
   dsb
   isb
   bx      LR
-  
+
 ASM_PFX(ArmDisableInstructionCache):
   ldr     R1,=IC_ON
   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
@@ -225,14 +225,14 @@ ASM_PFX(ArmV7AllDataCachesOperation):
   beq   L_Finished
   mov   R10, #0
 
-Loop1:   
+Loop1:
   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
   and   R12, R12, #7          @ get those 3 bits alone
   cmp   R12, #2
   blt   L_Skip                  @ no cache or only instruction cache at this level
   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
-  isb                           @ isb to sync the change to the CacheSizeID reg 
+  isb                           @ isb to sync the change to the CacheSizeID reg
   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
   and   R2, R12, #0x7           @ extract the line length field
   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
@@ -246,10 +246,10 @@ Loop1:
   sub   R7, R7, #1
   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 
-Loop2:   
+Loop2:
   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 
-Loop3:   
+Loop3:
   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
   orr   R0, R0, R7, LSL R2      @ factor in the index number
 
@@ -259,11 +259,11 @@ Loop3:
   bge   Loop3
   subs  R7, R7, #1              @ decrement the index
   bge   Loop2
-L_Skip:  
+L_Skip:
   add   R10, R10, #2            @ increment the cache number
   cmp   R3, R10
   bgt   Loop1
-  
+
 L_Finished:
   dsb
   ldmfd SP!, {r4-r12, lr}
@@ -285,7 +285,7 @@ Loop4:
   cmp   R12, #2
   blt   Skip2                   @ no cache or only instruction cache at this level
   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
-  isb                           @ isb to sync the change to the CacheSizeID reg 
+  isb                           @ isb to sync the change to the CacheSizeID reg
   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
   and   R2, R12, #0x7            @ extract the line length field
   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
@@ -312,7 +312,7 @@ Skip2:
   add   R10, R10, #2            @ increment the cache number
   cmp   R3, R10
   bgt   Loop4
-  
+
 Finished2:
   dsb
   ldmfd SP!, {r4-r12, lr}
@@ -321,12 +321,12 @@ Finished2:
 ASM_PFX(ArmDataMemoryBarrier):
   dmb
   bx      LR
-  
+
 ASM_PFX(ArmDataSyncronizationBarrier):
 ASM_PFX(ArmDrainWriteBuffer):
   dsb
   bx      LR
-  
+
 ASM_PFX(ArmInstructionSynchronizationBarrier):
   isb
   bx      LR
@@ -338,7 +338,7 @@ ASM_PFX(ArmReadVBar):
 
 ASM_PFX(ArmWriteVBar):
   # Set the Address of the Vector Table in the VBAR register
-  mcr     p15, 0, r0, c12, c0, 0 
+  mcr     p15, 0, r0, c12, c0, 0
   # Ensure the SCTLR.V bit is clear
   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
   bic     r0, r0, #0x00002000   @ clear V bit
@@ -376,7 +376,7 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb):
 ASM_PFX(ArmReadMpidr):
   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
   bx      lr
-  
+
 ASM_PFX(ArmReadTpidrurw):
   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
   bx      lr

+ 23 - 23
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ 
+//------------------------------------------------------------------------------
 //
 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
@@ -63,13 +63,13 @@ CTRL_I_BIT      EQU     (1 << 12)
 
 
 ArmInvalidateDataCacheEntryByMVA
-  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line       
+  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
   dsb
   isb
   bx      lr
 
 ArmCleanDataCacheEntryByMVA
-  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
+  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
   dsb
   isb
   bx      lr
@@ -83,21 +83,21 @@ ArmCleanInvalidateDataCacheEntryByMVA
 
 
 ArmInvalidateDataCacheEntryBySetWay
-  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line    
+  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
   dsb
   isb
   bx      lr
 
 
 ArmCleanInvalidateDataCacheEntryBySetWay
-  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line    
+  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
   dsb
   isb
   bx      lr
 
 
 ArmCleanDataCacheEntryBySetWay
-  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line    
+  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
   dsb
   isb
   bx      lr
@@ -150,7 +150,7 @@ ArmEnableDataCache
   dsb
   isb
   bx      LR
-    
+
 ArmDisableDataCache
   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
@@ -168,7 +168,7 @@ ArmEnableInstructionCache
   dsb
   isb
   bx      LR
-  
+
 ArmDisableInstructionCache
   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
@@ -223,14 +223,14 @@ ArmV7AllDataCachesOperation
   beq   Finished
   mov   R10, #0
 
-Loop1   
+Loop1
   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
   and   R12, R12, #7            ; get those 3 bits alone
   cmp   R12, #2
   blt   Skip                    ; no cache or only instruction cache at this level
   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
-  isb                           ; isb to sync the change to the CacheSizeID reg 
+  isb                           ; isb to sync the change to the CacheSizeID reg
   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
   and   R2, R12, #&7            ; extract the line length field
   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
@@ -240,10 +240,10 @@ Loop1
   ldr   R7, =0x00007FFF
   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 
-Loop2   
+Loop2
   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 
-Loop3   
+Loop3
   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
   orr   R0, R0, R7, LSL R2      ; factor in the index number
 
@@ -253,11 +253,11 @@ Loop3
   bge   Loop3
   subs  R7, R7, #1              ; decrement the index
   bge   Loop2
-Skip  
+Skip
   add   R10, R10, #2            ; increment the cache number
   cmp   R3, R10
   bgt   Loop1
-  
+
 Finished
   dsb
   ldmfd SP!, {r4-r12, lr}
@@ -272,14 +272,14 @@ ArmV7PerformPoUDataCacheOperation
   beq   Finished2
   mov   R10, #0
 
-Loop4   
+Loop4
   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
   and   R12, R12, #7            ; get those 3 bits alone
   cmp   R12, #2
   blt   Skip2                   ; no cache or only instruction cache at this level
   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
-  isb                           ; isb to sync the change to the CacheSizeID reg 
+  isb                           ; isb to sync the change to the CacheSizeID reg
   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
   and   R2, R12, #&7            ; extract the line length field
   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
@@ -289,10 +289,10 @@ Loop4
   ldr   R7, =0x00007FFF
   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 
-Loop5   
+Loop5
   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 
-Loop6   
+Loop6
   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
   orr   R0, R0, R7, LSL R2      ; factor in the index number
 
@@ -302,11 +302,11 @@ Loop6
   bge   Loop6
   subs  R7, R7, #1              ; decrement the index
   bge   Loop5
-Skip2  
+Skip2
   add   R10, R10, #2            ; increment the cache number
   cmp   R3, R10
   bgt   Loop4
-  
+
 Finished2
   dsb
   ldmfd SP!, {r4-r12, lr}
@@ -315,12 +315,12 @@ Finished2
 ArmDataMemoryBarrier
   dmb
   bx      LR
-  
+
 ArmDataSyncronizationBarrier
 ArmDrainWriteBuffer
   dsb
   bx      LR
-  
+
 ArmInstructionSynchronizationBarrier
   isb
   bx      LR
@@ -332,7 +332,7 @@ ArmReadVBar
 
 ArmWriteVBar
   // Set the Address of the Vector Table in the VBAR register
-  mcr     p15, 0, r0, c12, c0, 0 
+  mcr     p15, 0, r0, c12, c0, 0
   // Ensure the SCTLR.V bit is clear
   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
   bic     r0, r0, #0x00002000   ; clear V bit

+ 3 - 3
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
@@ -110,7 +110,7 @@ ASM_PFX(ArmWriteAuxCr):
 
 ASM_PFX(ArmReadAuxCr):
   mrc     p15, 0, r0, c1, c0, 1
-  bx      lr  
+  bx      lr
 
 ASM_PFX(ArmSetTTBR0):
   mcr     p15,0,r0,c2,c0,0
@@ -133,7 +133,7 @@ ASM_PFX(ArmGetTTBR0BaseAddress):
 ASM_PFX(ArmUpdateTranslationTableEntry):
   mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA
   dsb
-  mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA  
+  mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA
   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
   dsb
   isb

+ 4 - 4
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm

@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ 
+//------------------------------------------------------------------------------
 //
 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
@@ -14,7 +14,7 @@
 //------------------------------------------------------------------------------
 
 #include <AsmMacroIoLib.h>
-    
+
     INCLUDE AsmMacroIoLib.inc
 
 #ifdef ARM_CPU_ARMv6
@@ -110,7 +110,7 @@ ArmWriteAuxCr
 
 ArmReadAuxCr
   mrc     p15, 0, r0, c1, c0, 1
-  bx      lr  
+  bx      lr
 
 ArmSetTTBR0
   mcr     p15,0,r0,c2,c0,0
@@ -170,7 +170,7 @@ ArmReadMVBar
 ArmWriteMVBar
   mcr     p15, 0, r0, c12, c0, 1
   bx      lr
-  
+
 ArmCallWFE
   wfe
   bx      lr

+ 1 - 1
ArmPkg/Library/ArmLib/Common/ArmLib.c

@@ -2,7 +2,7 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at

+ 3 - 3
ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h

@@ -67,11 +67,11 @@ CPSRRead (
   VOID
   );
 
-UINT32 
+UINT32
 ReadCCSIDR (
   IN UINT32 CSSELR
-  );  
-  
+  );
+
 UINT32
 ReadCLIDR (
   VOID

+ 10 - 10
ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c

@@ -1,7 +1,7 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -41,16 +41,16 @@ ArmDataCachePresent (
 {
   return FALSE;
 }
-  
+
 UINTN
 EFIAPI
 ArmDataCacheSize (
   VOID
   )
 {
-  return 0;      
+  return 0;
 }
-  
+
 UINTN
 EFIAPI
 ArmDataCacheAssociativity (
@@ -59,7 +59,7 @@ ArmDataCacheAssociativity (
 {
   return 0;
 }
-  
+
 UINTN
 EFIAPI
 ArmDataCacheLineLength (
@@ -68,7 +68,7 @@ ArmDataCacheLineLength (
 {
   return 0;
 }
-  
+
 BOOLEAN
 EFIAPI
 ArmInstructionCachePresent (
@@ -77,16 +77,16 @@ ArmInstructionCachePresent (
 {
   return FALSE;
 }
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheSize (
   VOID
   )
 {
-  return 0;      
+  return 0;
 }
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheAssociativity (
@@ -95,7 +95,7 @@ ArmInstructionCacheAssociativity (
 {
   return 0;
 }
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheLineLength (

+ 1 - 1
ArmPkg/Library/ArmLib/Null/NullArmLib.c

@@ -1,7 +1,7 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at

+ 5 - 5
ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf

@@ -1,24 +1,24 @@
 #/** @file
-#  
+#
 #  Copyright (c) 2012-2013, ARM Ltd. All rights reserved.<BR>
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
 #  http://opensource.org/licenses/bsd-license.php
-#  
+#
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#  
+#
 #**/
 
 [Defines]
   INF_VERSION                    = 0x00010005
   BASE_NAME                      = ArmSmcLib
-  FILE_GUID                      = eb3f17d5-a3cc-4eac-8912-84162d0f79da 
+  FILE_GUID                      = eb3f17d5-a3cc-4eac-8912-84162d0f79da
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
   LIBRARY_CLASS                  = ArmSmcLib
-  
+
 [Sources.ARM]
   Arm/ArmSmc.asm    | RVCT
   Arm/ArmSmc.S      | GCC

+ 3 - 3
ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.inf

@@ -1,5 +1,5 @@
 #/** @file
-#  
+#
 #  ArmSmcLib when no SMC support is desired (might be the case for CPU without the
 #  Trustzone support / ARM Security Extension)
 #
@@ -8,7 +8,7 @@
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
 #  http://opensource.org/licenses/bsd-license.php
-#  
+#
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
@@ -21,7 +21,7 @@
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
   LIBRARY_CLASS                  = ArmSmcLib
-  
+
 [Sources.ARM]
   Arm/ArmSmcNull.asm    | RVCT
   Arm/ArmSmcNull.S      | GCC

+ 25 - 25
ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S

@@ -1,10 +1,10 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # CopyMem() worker for ARM
 #
 # This file started out as C code that did 64 bit moves if the buffer was
 # 32-bit aligned, else it does a byte copy. It also does a byte copy for
-# any trailing bytes. It was updated to do 32-byte copies using stm/ldm. 
+# any trailing bytes. It was updated to do 32-byte copies using stm/ldm.
 #
 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 # This program and the accompanying materials
@@ -20,7 +20,7 @@
 /**
   Copy Length bytes from Source to Destination. Overlap is OK.
 
-  This implementation 
+  This implementation
 
   @param  Destination Target of copy
   @param  Source      Place to copy from
@@ -48,7 +48,7 @@ ASM_PFX(InternalMemCopyMem):
   mov  r10, r0
   mov  r12, r2
   mov  r14, r1
-  
+
 memcopy_check_overlapped:
   cmp  r11, r1
   // If (dest < source)
@@ -61,10 +61,10 @@ memcopy_check_overlapped:
   cmp  r12, r3
   bcc  memcopy_check_optim_default
 
-  // If (length == 0)  
+  // If (length == 0)
   cmp  r12, #0
   beq  memcopy_end
-  
+
   b     memcopy_check_optim_overlap
 
 memcopy_check_optim_default:
@@ -79,7 +79,7 @@ memcopy_check_optim_default:
   movls  r0, #0
   andhi  r0, r3, #1
   b     memcopy_default
-    
+
 memcopy_check_optim_overlap:
   // r10 = dest_end, r14 = source_end
   add  r10, r11, r12
@@ -94,12 +94,12 @@ memcopy_check_optim_overlap:
   tst  r14, #0xF
   movne  r0, #0
   b  memcopy_overlapped
-  
+
 memcopy_overlapped_non_optim:
   // We read 1 byte from the end of the source buffer
   sub  r3, r14, #1
   sub  r12, r12, #1
-  ldrb  r3, [r3, #0]  
+  ldrb  r3, [r3, #0]
   sub  r2, r10, #1
   cmp  r12, #0
   // We write 1 byte at the end of the dest buffer
@@ -114,58 +114,58 @@ memcopy_overlapped:
   // Are we in the optimized case ?
   cmp  r0, #0
   beq  memcopy_overlapped_non_optim
-  
+
   // Optimized Overlapped - Read 32 bytes
   sub  r14, r14, #32
   sub  r12, r12, #32
   cmp  r12, #31
   ldmia  r14, {r2-r9}
-  
+
   // If length is less than 32 then disable optim
   movls  r0, #0
-  
+
   cmp  r12, #0
-  
-  // Optimized Overlapped - Write 32 bytes  
+
+  // Optimized Overlapped - Write 32 bytes
   sub  r10, r10, #32
   stmia  r10, {r2-r9}
-  
+
   // while (length != 0)
   bne  memcopy_overlapped
   b   memcopy_end
-  
+
 memcopy_default_non_optim:
   // Byte copy
-  ldrb  r3, [r14], #1  
+  ldrb  r3, [r14], #1
   sub  r12, r12, #1
   strb  r3, [r10], #1
-  
+
 memcopy_default:
   cmp  r12, #0
   beq  memcopy_end
-  
+
 // r10 = dest, r14 = source
 memcopy_default_loop:
   cmp  r0, #0
   beq  memcopy_default_non_optim
-  
+
   // Optimized memcopy - Read 32 Bytes
   sub  r12, r12, #32
   cmp  r12, #31
   ldmia  r14!, {r2-r9}
-  
+
   // If length is less than 32 then disable optim
   movls  r0, #0
-  
+
   cmp  r12, #0
-  
+
   // Optimized memcopy - Write 32 Bytes
   stmia  r10!, {r2-r9}
 
   // while (length != 0)
   bne  memcopy_default_loop
-  
+
 memcopy_end:
   mov  r0, r11
   ldmfd  sp!, {r4-r11, pc}
-  
+

+ 25 - 25
ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm

@@ -1,4 +1,4 @@
-;------------------------------------------------------------------------------ 
+;------------------------------------------------------------------------------
 ;
 ; CopyMem() worker for ARM
 ;
@@ -20,7 +20,7 @@
 /**
   Copy Length bytes from Source to Destination. Overlap is OK.
 
-  This implementation 
+  This implementation
 
   @param  Destination Target of copy
   @param  Source      Place to copy from
@@ -48,7 +48,7 @@ InternalMemCopyMem
   mov  r10, r0
   mov  r12, r2
   mov  r14, r1
-  
+
 memcopy_check_overlapped
   cmp  r11, r1
   // If (dest < source)
@@ -61,10 +61,10 @@ memcopy_check_overlapped
   cmp  r12, r3
   bcc  memcopy_check_optim_default
 
-  // If (length == 0)  
+  // If (length == 0)
   cmp  r12, #0
   beq  memcopy_end
-  
+
   b     memcopy_check_optim_overlap
 
 memcopy_check_optim_default
@@ -79,7 +79,7 @@ memcopy_check_optim_default
   movls  r0, #0
   andhi  r0, r3, #1
   b     memcopy_default
-    
+
 memcopy_check_optim_overlap
   // r10 = dest_end, r14 = source_end
   add  r10, r11, r12
@@ -94,12 +94,12 @@ memcopy_check_optim_overlap
   tst  r14, #0xF
   movne  r0, #0
   b  memcopy_overlapped
-  
+
 memcopy_overlapped_non_optim
   // We read 1 byte from the end of the source buffer
   sub  r3, r14, #1
   sub  r12, r12, #1
-  ldrb  r3, [r3, #0]  
+  ldrb  r3, [r3, #0]
   sub  r2, r10, #1
   cmp  r12, #0
   // We write 1 byte at the end of the dest buffer
@@ -114,60 +114,60 @@ memcopy_overlapped
   // Are we in the optimized case ?
   cmp  r0, #0
   beq  memcopy_overlapped_non_optim
-  
+
   // Optimized Overlapped - Read 32 bytes
   sub  r14, r14, #32
   sub  r12, r12, #32
   cmp  r12, #31
   ldmia  r14, {r2-r9}
-  
+
   // If length is less than 32 then disable optim
   movls  r0, #0
-  
+
   cmp  r12, #0
-  
-  // Optimized Overlapped - Write 32 bytes  
+
+  // Optimized Overlapped - Write 32 bytes
   sub  r10, r10, #32
   stmia  r10, {r2-r9}
-  
+
   // while (length != 0)
   bne  memcopy_overlapped
   b   memcopy_end
-  
+
 memcopy_default_non_optim
   // Byte copy
-  ldrb  r3, [r14], #1  
+  ldrb  r3, [r14], #1
   sub  r12, r12, #1
   strb  r3, [r10], #1
-  
+
 memcopy_default
   cmp  r12, #0
   beq  memcopy_end
-  
+
 // r10 = dest, r14 = source
 memcopy_default_loop
   cmp  r0, #0
   beq  memcopy_default_non_optim
-  
+
   // Optimized memcopy - Read 32 Bytes
   sub  r12, r12, #32
   cmp  r12, #31
   ldmia  r14!, {r2-r9}
-  
+
   // If length is less than 32 then disable optim
   movls  r0, #0
-  
+
   cmp  r12, #0
-  
+
   // Optimized memcopy - Write 32 Bytes
   stmia  r10!, {r2-r9}
 
   // while (length != 0)
   bne  memcopy_default_loop
-  
+
 memcopy_end
   mov  r0, r11
   ldmfd  sp!, {r4-r11, pc}
-  
+
   END
-  
+

+ 10 - 10
ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S

@@ -1,10 +1,10 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # SemMem() worker for ARM
 #
 # This file started out as C code that did 64 bit moves if the buffer was
 # 32-bit aligned, else it does a byte copy. It also does a byte copy for
-# any trailing bytes. It was updated to do 32-byte at a time. 
+# any trailing bytes. It was updated to do 32-byte at a time.
 #
 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 # This program and the accompanying materials
@@ -34,7 +34,7 @@ InternalMemSetMem (
   IN      UINT8                     Value
   )
 **/
-  
+
 .text
 .align 2
 GCC_ASM_EXPORT(InternalMemSetMem)
@@ -56,14 +56,14 @@ L32:
 L31:
   and   r4, r2, #0xff
   orr   r4, r4, r4, LSL #8
-  orr   r4, r4, r4, LSL #16  
+  orr   r4, r4, r4, LSL #16
   mov   r5, r4
   mov   r6, r4
-  mov   r7, r4 
-  mov   r8, r4 
-  mov   r9, r4 
-  mov   r10, r4 
-  mov   r11, r4 
+  mov   r7, r4
+  mov   r8, r4
+  mov   r9, r4
+  mov   r10, r4
+  mov   r11, r4
   b      L32
 L34:
   cmp      lr, #0
@@ -78,4 +78,4 @@ L43:
   cmp      r1, #0
   bne      L34
   ldmfd    sp!, {r4-r11, pc}
-  
+

+ 10 - 10
ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm

@@ -1,4 +1,4 @@
-;------------------------------------------------------------------------------ 
+;------------------------------------------------------------------------------
 ;
 ; SetMem() worker for ARM
 ;
@@ -33,9 +33,9 @@ InternalMemSetMem (
   IN      UINT8                     Value
   )
 **/
-  
+
   EXPORT InternalMemSetMem
-  
+
   AREA AsmMemStuff, CODE, READONLY
 
 InternalMemSetMem
@@ -55,14 +55,14 @@ L32
 L31
   and   r4, r2, #0xff
   orr   r4, r4, r4, LSL #8
-  orr   r4, r4, r4, LSL #16  
+  orr   r4, r4, r4, LSL #16
   mov   r5, r4
   mov   r6, r4
-  mov   r7, r4 
-  mov   r8, r4 
-  mov   r9, r4 
-  mov   r10, r4 
-  mov   r11, r4 
+  mov   r7, r4
+  mov   r8, r4
+  mov   r9, r4
+  mov   r10, r4
+  mov   r11, r4
   b      L32
 L34
   cmp      lr, #0
@@ -77,5 +77,5 @@ L43
   cmp      r1, #0
   bne      L34
   ldmfd    sp!, {r4-r11, pc}
-  
+
   END

+ 4 - 4
ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf

@@ -1,8 +1,8 @@
 ## @file
 #  Instance of Base Memory Library with some ARM ldm/stm assembly.
 #
-#  This is a copy of the MdePkg BaseMemoryLib with the CopyMem and 
-#  SetMem worker functions replaced with assembler that uses 
+#  This is a copy of the MdePkg BaseMemoryLib with the CopyMem and
+#  SetMem worker functions replaced with assembler that uses
 #  ldm/stm.
 #
 #  Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
@@ -25,7 +25,7 @@
   FILE_GUID                      = 4D466AF3-2380-448D-A337-E4033F29F3F7
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = BaseMemoryLib 
+  LIBRARY_CLASS                  = BaseMemoryLib
 
 
 #
@@ -46,7 +46,7 @@
   SetMemWrapper.c
   CopyMemWrapper.c
   MemLibGeneric.c
-  MemLibGuid.c  
+  MemLibGuid.c
   MemLibInternals.h
 
 [Sources.ARM]

+ 2 - 2
ArmPkg/Library/BaseMemoryLibStm/CompareMemWrapper.c

@@ -31,7 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   If all Length bytes of the two buffers are identical, then 0 is returned.  Otherwise, the
   value returned is the first mismatched byte in SourceBuffer subtracted from the first
   mismatched byte in DestinationBuffer.
-  
+
   If Length > 0 and DestinationBuffer is NULL, then ASSERT().
   If Length > 0 and SourceBuffer is NULL, then ASSERT().
   If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().
@@ -44,7 +44,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   @return 0                 All Length bytes of the two buffers are identical.
   @retval Non-zero          The first mismatched byte in SourceBuffer subtracted from the first
                             mismatched byte in DestinationBuffer.
-                            
+
 **/
 INTN
 EFIAPI

+ 2 - 2
ArmPkg/Library/BaseMemoryLibStm/CopyMemWrapper.c

@@ -2,7 +2,7 @@
   CopyMem() implementation.
 
   The following BaseMemoryLib instances contain the same copy of this file:
-  
+
     BaseMemoryLib
     BaseMemoryLibMmx
     BaseMemoryLibSse2
@@ -31,7 +31,7 @@
   This function copies Length bytes from SourceBuffer to DestinationBuffer, and returns
   DestinationBuffer.  The implementation must be reentrant, and it must handle the case
   where SourceBuffer overlaps DestinationBuffer.
-  
+
   If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT().
 

+ 4 - 4
ArmPkg/Library/BaseMemoryLibStm/MemLibGuid.c

@@ -2,7 +2,7 @@
   Implementation of GUID functions.
 
   The following BaseMemoryLib instances contain the same copy of this file:
-  
+
     BaseMemoryLib
     BaseMemoryLibMmx
     BaseMemoryLibSse2
@@ -30,7 +30,7 @@
 
   This function copies the contents of the 128-bit GUID specified by SourceGuid to
   DestinationGuid, and returns DestinationGuid.
-  
+
   If DestinationGuid is NULL, then ASSERT().
   If SourceGuid is NULL, then ASSERT().
 
@@ -63,7 +63,7 @@ CopyGuid (
 
   This function compares Guid1 to Guid2.  If the GUIDs are identical then TRUE is returned.
   If there are any bit differences in the two GUIDs, then FALSE is returned.
-  
+
   If Guid1 is NULL, then ASSERT().
   If Guid2 is NULL, then ASSERT().
 
@@ -93,7 +93,7 @@ CompareGuid (
   GUID value that matches Guid.  If a match is found, then a pointer to the matching
   GUID in the target buffer is returned.  If no match is found, then NULL is returned.
   If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 32-bit boundary, then ASSERT().
   If Length is not aligned on a 128-bit boundary, then ASSERT().

+ 1 - 1
ArmPkg/Library/BaseMemoryLibStm/ScanMem16Wrapper.c

@@ -33,7 +33,7 @@
   address to the highest address for a 16-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 16-bit boundary, then ASSERT().
   If Length is not aligned on a 16-bit boundary, then ASSERT().

+ 1 - 1
ArmPkg/Library/BaseMemoryLibStm/ScanMem32Wrapper.c

@@ -32,7 +32,7 @@
   address to the highest address for a 32-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 32-bit boundary, then ASSERT().
   If Length is not aligned on a 32-bit boundary, then ASSERT().

+ 1 - 1
ArmPkg/Library/BaseMemoryLibStm/ScanMem64Wrapper.c

@@ -33,7 +33,7 @@
   address to the highest address for a 64-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 64-bit boundary, then ASSERT().
   If Length is not aligned on a 64-bit boundary, then ASSERT().

+ 4 - 4
ArmPkg/Library/BaseMemoryLibStm/ScanMem8Wrapper.c

@@ -33,7 +33,7 @@
   address to the highest address for an 8-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
@@ -57,19 +57,19 @@ ScanMem8 (
   }
   ASSERT (Buffer != NULL);
   ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
- 
+
   return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);
 }
 
 /**
-  Scans a target buffer for a UINTN sized value, and returns a pointer to the matching 
+  Scans a target buffer for a UINTN sized value, and returns a pointer to the matching
   UINTN sized value in the target buffer.
 
   This function searches the target buffer specified by Buffer and Length from the lowest
   address to the highest address for a UINTN sized value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a UINTN boundary, then ASSERT().
   If Length is not aligned on a UINTN boundary, then ASSERT().

+ 1 - 1
ArmPkg/Library/BaseMemoryLibStm/SetMemWrapper.c

@@ -29,7 +29,7 @@
   Fills a target buffer with a byte value, and returns the target buffer.
 
   This function fills Length bytes of Buffer with Value, and returns Buffer.
-  
+
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   @param  Buffer    Memory to set.

+ 2 - 2
ArmPkg/Library/BaseMemoryLibStm/ZeroMemWrapper.c

@@ -11,7 +11,7 @@
     BaseMemoryLibOptPei
     PeiMemoryLib
     UefiMemoryLib
-    
+
   Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -29,7 +29,7 @@
   Fills a target buffer with zeros, and returns the target buffer.
 
   This function fills Length bytes of Buffer with zeros, and returns Buffer.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 

+ 5 - 5
ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # CopyMem() worker for ARM
 #
@@ -20,7 +20,7 @@
 /**
   Copy Length bytes from Source to Destination. Overlap is OK.
 
-  This implementation 
+  This implementation
 
   @param  Destination Target of copy
   @param  Source      Place to copy from
@@ -81,7 +81,7 @@ L16:
   bne  L29
   sub  r3, lr, #1
   sub  ip, ip, #1
-  ldrb  r3, [r3, #0]  
+  ldrb  r3, [r3, #0]
   sub  r2, r9, #1
   cmp  ip, #0
   sub  r9, r9, #1
@@ -90,7 +90,7 @@ L16:
   bne  L16
   b   L7
 L11:
-  ldrb  r3, [lr], #1  
+  ldrb  r3, [lr], #1
   sub  ip, ip, #1
   strb  r3, [r9], #1
 L26:
@@ -111,4 +111,4 @@ L7:
   mov  r0, r4
   ldmfd  sp!, {r4, r9, pc}
 
-  
+

+ 5 - 5
ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm

@@ -1,4 +1,4 @@
-;------------------------------------------------------------------------------ 
+;------------------------------------------------------------------------------
 ;
 ; CopyMem() worker for ARM
 ;
@@ -20,7 +20,7 @@
 /**
   Copy Length bytes from Source to Destination. Overlap is OK.
 
-  This implementation 
+  This implementation
 
   @param  Destination Target of copy
   @param  Source      Place to copy from
@@ -81,7 +81,7 @@ L16
   bne  L29
   sub  r3, lr, #1
   sub  ip, ip, #1
-  ldrb  r3, [r3, #0]  
+  ldrb  r3, [r3, #0]
   sub  r2, r9, #1
   cmp  ip, #0
   sub  r9, r9, #1
@@ -90,7 +90,7 @@ L16
   bne  L16
   b   L7
 L11
-  ldrb  r3, [lr], #1  
+  ldrb  r3, [lr], #1
   sub  ip, ip, #1
   strb  r3, [r9], #1
 L26
@@ -112,4 +112,4 @@ L7
   ldmfd  sp!, {r4, r9, pc}
 
   END
-  
+

+ 2 - 3
ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S

@@ -1,4 +1,4 @@
-#------------------------------------------------------------------------------ 
+#------------------------------------------------------------------------------
 #
 # SemMem() worker for ARM
 #
@@ -34,7 +34,7 @@ InternalMemSetMem (
   IN      UINT8                     Value
   )
 **/
-  
+
 .text
 .align 2
 GCC_ASM_EXPORT(InternalMemSetMem)
@@ -77,4 +77,3 @@ L43:
   cmp      r1, #0
   bne      L34
   ldmfd    sp!, {pc}
-  

+ 4 - 5
ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm

@@ -1,4 +1,4 @@
-;------------------------------------------------------------------------------ 
+;------------------------------------------------------------------------------
 ;
 ; SetMem() worker for ARM
 ;
@@ -33,9 +33,9 @@ InternalMemSetMem (
   IN      UINT8                     Value
   )
 **/
-  
+
   EXPORT InternalMemSetMem
-  
+
   AREA AsmMemStuff, CODE, READONLY
 
 InternalMemSetMem
@@ -75,6 +75,5 @@ L43
   cmp      r1, #0
   bne      L34
   ldmfd    sp!, {pc}
-  
+
   END
-  

+ 4 - 4
ArmPkg/Library/BaseMemoryLibVstm/BaseMemoryLibVstm.inf

@@ -1,8 +1,8 @@
 ## @file
 #  Instance of Base Memory Library with some ARM vldm/vstm assembly.
 #
-#  This is a copy of the MdePkg BaseMemoryLib with the CopyMem and 
-#  SetMem worker functions replaced with assembler that uses 
+#  This is a copy of the MdePkg BaseMemoryLib with the CopyMem and
+#  SetMem worker functions replaced with assembler that uses
 #  vldm/vstm (part of NEON SIMD, optional in ARMv7-A).
 #
 #  Note: You need to enable NEON in SEC to use this library
@@ -32,7 +32,7 @@
   FILE_GUID                      = 09EE1E8D-7A2E-4573-8117-68A18569C1F5
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = BaseMemoryLib 
+  LIBRARY_CLASS                  = BaseMemoryLib
 
 
 #
@@ -52,7 +52,7 @@
   SetMemWrapper.c
   CopyMemWrapper.c
   MemLibGeneric.c
-  MemLibGuid.c  
+  MemLibGuid.c
   MemLibInternals.h
   Arm/CopyMem.asm
   Arm/CopyMem.S

+ 2 - 2
ArmPkg/Library/BaseMemoryLibVstm/CompareMemWrapper.c

@@ -31,7 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   If all Length bytes of the two buffers are identical, then 0 is returned.  Otherwise, the
   value returned is the first mismatched byte in SourceBuffer subtracted from the first
   mismatched byte in DestinationBuffer.
-  
+
   If Length > 0 and DestinationBuffer is NULL, then ASSERT().
   If Length > 0 and SourceBuffer is NULL, then ASSERT().
   If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().
@@ -44,7 +44,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   @return 0                 All Length bytes of the two buffers are identical.
   @retval Non-zero          The first mismatched byte in SourceBuffer subtracted from the first
                             mismatched byte in DestinationBuffer.
-                            
+
 **/
 INTN
 EFIAPI

+ 2 - 2
ArmPkg/Library/BaseMemoryLibVstm/CopyMemWrapper.c

@@ -2,7 +2,7 @@
   CopyMem() implementation.
 
   The following BaseMemoryLib instances contain the same copy of this file:
-  
+
     BaseMemoryLib
     BaseMemoryLibMmx
     BaseMemoryLibSse2
@@ -31,7 +31,7 @@
   This function copies Length bytes from SourceBuffer to DestinationBuffer, and returns
   DestinationBuffer.  The implementation must be reentrant, and it must handle the case
   where SourceBuffer overlaps DestinationBuffer.
-  
+
   If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT().
 

+ 4 - 4
ArmPkg/Library/BaseMemoryLibVstm/MemLibGuid.c

@@ -2,7 +2,7 @@
   Implementation of GUID functions.
 
   The following BaseMemoryLib instances contain the same copy of this file:
-  
+
     BaseMemoryLib
     BaseMemoryLibMmx
     BaseMemoryLibSse2
@@ -30,7 +30,7 @@
 
   This function copies the contents of the 128-bit GUID specified by SourceGuid to
   DestinationGuid, and returns DestinationGuid.
-  
+
   If DestinationGuid is NULL, then ASSERT().
   If SourceGuid is NULL, then ASSERT().
 
@@ -63,7 +63,7 @@ CopyGuid (
 
   This function compares Guid1 to Guid2.  If the GUIDs are identical then TRUE is returned.
   If there are any bit differences in the two GUIDs, then FALSE is returned.
-  
+
   If Guid1 is NULL, then ASSERT().
   If Guid2 is NULL, then ASSERT().
 
@@ -93,7 +93,7 @@ CompareGuid (
   GUID value that matches Guid.  If a match is found, then a pointer to the matching
   GUID in the target buffer is returned.  If no match is found, then NULL is returned.
   If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 32-bit boundary, then ASSERT().
   If Length is not aligned on a 128-bit boundary, then ASSERT().

+ 1 - 1
ArmPkg/Library/BaseMemoryLibVstm/ScanMem16Wrapper.c

@@ -33,7 +33,7 @@
   address to the highest address for a 16-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 16-bit boundary, then ASSERT().
   If Length is not aligned on a 16-bit boundary, then ASSERT().

+ 1 - 1
ArmPkg/Library/BaseMemoryLibVstm/ScanMem32Wrapper.c

@@ -32,7 +32,7 @@
   address to the highest address for a 32-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 32-bit boundary, then ASSERT().
   If Length is not aligned on a 32-bit boundary, then ASSERT().

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