ArmLibSupportV7.S 2.6 KB

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  1. #------------------------------------------------------------------------------
  2. #
  3. # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  4. # Copyright (c) 2011-2013, ARM Limited. All rights reserved.
  5. #
  6. # This program and the accompanying materials
  7. # are licensed and made available under the terms and conditions of the BSD License
  8. # which accompanies this distribution. The full text of the license may be found at
  9. # http://opensource.org/licenses/bsd-license.php
  10. #
  11. # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12. # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13. #
  14. #------------------------------------------------------------------------------
  15. #include <AsmMacroIoLib.h>
  16. .text
  17. .align 2
  18. GCC_ASM_EXPORT(ArmIsMpCore)
  19. GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
  20. GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
  21. GCC_ASM_EXPORT(ArmEnableIrq)
  22. GCC_ASM_EXPORT(ArmDisableIrq)
  23. GCC_ASM_EXPORT(ArmEnableFiq)
  24. GCC_ASM_EXPORT(ArmDisableFiq)
  25. GCC_ASM_EXPORT(ArmEnableInterrupts)
  26. GCC_ASM_EXPORT(ArmDisableInterrupts)
  27. GCC_ASM_EXPORT(ReadCCSIDR)
  28. GCC_ASM_EXPORT(ReadCLIDR)
  29. GCC_ASM_EXPORT(ArmReadNsacr)
  30. GCC_ASM_EXPORT(ArmWriteNsacr)
  31. #------------------------------------------------------------------------------
  32. ASM_PFX(ArmIsMpCore):
  33. mrc p15,0,R0,c0,c0,5
  34. // Get Multiprocessing extension (bit31) & U bit (bit30)
  35. and R0, R0, #0xC0000000
  36. // if bit30 == 0 then the processor is part of a multiprocessor system)
  37. and R0, R0, #0x80000000
  38. bx LR
  39. ASM_PFX(ArmEnableAsynchronousAbort):
  40. cpsie a
  41. isb
  42. bx LR
  43. ASM_PFX(ArmDisableAsynchronousAbort):
  44. cpsid a
  45. isb
  46. bx LR
  47. ASM_PFX(ArmEnableIrq):
  48. cpsie i
  49. isb
  50. bx LR
  51. ASM_PFX(ArmDisableIrq):
  52. cpsid i
  53. isb
  54. bx LR
  55. ASM_PFX(ArmEnableFiq):
  56. cpsie f
  57. isb
  58. bx LR
  59. ASM_PFX(ArmDisableFiq):
  60. cpsid f
  61. isb
  62. bx LR
  63. ASM_PFX(ArmEnableInterrupts):
  64. cpsie if
  65. isb
  66. bx LR
  67. ASM_PFX(ArmDisableInterrupts):
  68. cpsid if
  69. isb
  70. bx LR
  71. // UINT32
  72. // ReadCCSIDR (
  73. // IN UINT32 CSSELR
  74. // )
  75. ASM_PFX(ReadCCSIDR):
  76. mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
  77. isb
  78. mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
  79. bx lr
  80. // UINT32
  81. // ReadCLIDR (
  82. // IN UINT32 CSSELR
  83. // )
  84. ASM_PFX(ReadCLIDR):
  85. mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
  86. bx lr
  87. ASM_PFX(ArmReadNsacr):
  88. mrc p15, 0, r0, c1, c1, 2
  89. bx lr
  90. ASM_PFX(ArmWriteNsacr):
  91. mcr p15, 0, r0, c1, c1, 2
  92. bx lr
  93. ASM_FUNCTION_REMOVE_IF_UNREFERENCED