Arm9Support.asm 4.5 KB

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  1. //------------------------------------------------------------------------------
  2. //
  3. // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  4. //
  5. // This program and the accompanying materials
  6. // are licensed and made available under the terms and conditions of the BSD License
  7. // which accompanies this distribution. The full text of the license may be found at
  8. // http://opensource.org/licenses/bsd-license.php
  9. //
  10. // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12. //
  13. //------------------------------------------------------------------------------
  14. EXPORT ArmCleanInvalidateDataCache
  15. EXPORT ArmCleanDataCache
  16. EXPORT ArmInvalidateDataCache
  17. EXPORT ArmInvalidateInstructionCache
  18. EXPORT ArmInvalidateDataCacheEntryByMVA
  19. EXPORT ArmCleanDataCacheEntryByMVA
  20. EXPORT ArmCleanInvalidateDataCacheEntryByMVA
  21. EXPORT ArmEnableMmu
  22. EXPORT ArmDisableMmu
  23. EXPORT ArmMmuEnabled
  24. EXPORT ArmEnableDataCache
  25. EXPORT ArmDisableDataCache
  26. EXPORT ArmEnableInstructionCache
  27. EXPORT ArmDisableInstructionCache
  28. EXPORT ArmEnableBranchPrediction
  29. EXPORT ArmDisableBranchPrediction
  30. EXPORT ArmDataMemoryBarrier
  31. EXPORT ArmDataSyncronizationBarrier
  32. EXPORT ArmInstructionSynchronizationBarrier
  33. DC_ON EQU ( 0x1:SHL:2 )
  34. IC_ON EQU ( 0x1:SHL:12 )
  35. AREA ArmCacheLib, CODE, READONLY
  36. PRESERVE8
  37. ArmInvalidateDataCacheEntryByMVA
  38. MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
  39. BX lr
  40. ArmCleanDataCacheEntryByMVA
  41. MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
  42. BX lr
  43. ArmCleanInvalidateDataCacheEntryByMVA
  44. MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
  45. BX lr
  46. ArmEnableInstructionCache
  47. LDR R1,=IC_ON
  48. MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
  49. ORR R0,R0,R1 ;Set I bit
  50. MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
  51. BX LR
  52. ArmDisableInstructionCache
  53. LDR R1,=IC_ON
  54. MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
  55. BIC R0,R0,R1 ;Clear I bit.
  56. MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
  57. BX LR
  58. ArmInvalidateInstructionCache
  59. MOV R0,#0
  60. MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
  61. MOV R0,#0
  62. MCR p15,0,R0,c7,c10,4 ;Drain write buffer
  63. BX LR
  64. ArmEnableMmu
  65. mrc p15,0,R0,c1,c0,0
  66. orr R0,R0,#1
  67. mcr p15,0,R0,c1,c0,0
  68. bx LR
  69. ArmMmuEnabled
  70. mrc p15,0,R0,c1,c0,0
  71. and R0,R0,#1
  72. bx LR
  73. ArmDisableMmu
  74. mrc p15,0,R0,c1,c0,0
  75. bic R0,R0,#1
  76. mcr p15,0,R0,c1,c0,0
  77. mov R0,#0
  78. mcr p15,0,R0,c7,c10,4 ;Drain write buffer
  79. bx LR
  80. ArmEnableDataCache
  81. LDR R1,=DC_ON
  82. MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
  83. ORR R0,R0,R1 ;Set C bit
  84. MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
  85. BX LR
  86. ArmDisableDataCache
  87. LDR R1,=DC_ON
  88. MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
  89. BIC R0,R0,R1 ;Clear C bit
  90. MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
  91. BX LR
  92. ArmCleanDataCache
  93. MRC p15,0,r15,c7,c10,3
  94. BNE ArmCleanDataCache
  95. MOV R0,#0
  96. MCR p15,0,R0,c7,c10,4 ;Drain write buffer
  97. BX LR
  98. ArmInvalidateDataCache
  99. MOV R0,#0
  100. MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
  101. MOV R0,#0
  102. MCR p15,0,R0,c7,c10,4 ;Drain write buffer
  103. BX LR
  104. ArmCleanInvalidateDataCache
  105. MRC p15,0,r15,c7,c14,3
  106. BNE ArmCleanInvalidateDataCache
  107. MOV R0,#0
  108. MCR p15,0,R0,c7,c10,4 ;Drain write buffer
  109. BX LR
  110. ArmEnableBranchPrediction
  111. bx LR ;Branch prediction is not supported.
  112. ArmDisableBranchPrediction
  113. bx LR ;Branch prediction is not supported.
  114. ASM_PFX(ArmDataMemoryBarrier):
  115. mov R0, #0
  116. mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct
  117. bx LR
  118. ASM_PFX(ArmDataSyncronizationBarrier):
  119. mov R0, #0
  120. mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
  121. bx LR
  122. ASM_PFX(ArmInstructionSynchronizationBarrier):
  123. MOV R0, #0
  124. MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct
  125. bx LR
  126. END