ArmV7.h 3.6 KB

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  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
  4. This program and the accompanying materials
  5. are licensed and made available under the terms and conditions of the BSD License
  6. which accompanies this distribution. The full text of the license may be found at
  7. http://opensource.org/licenses/bsd-license.php
  8. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10. **/
  11. #ifndef __ARM_V7_H__
  12. #define __ARM_V7_H__
  13. #include <Chipset/ArmV7Mmu.h>
  14. #include <Chipset/ArmArchTimer.h>
  15. // ARM Interrupt ID in Exception Table
  16. #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
  17. // ID_PFR1 - ARM Processor Feature Register 1 definitions
  18. #define ARM_PFR1_SEC (0xFUL << 4)
  19. #define ARM_PFR1_TIMER (0xFUL << 16)
  20. #define ARM_PFR1_GIC (0xFUL << 28)
  21. // Domain Access Control Register
  22. #define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
  23. #define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
  24. #define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
  25. #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
  26. #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
  27. // CPSR - Coprocessor Status Register definitions
  28. #define CPSR_MODE_USER 0x10
  29. #define CPSR_MODE_FIQ 0x11
  30. #define CPSR_MODE_IRQ 0x12
  31. #define CPSR_MODE_SVC 0x13
  32. #define CPSR_MODE_ABORT 0x17
  33. #define CPSR_MODE_HYP 0x1A
  34. #define CPSR_MODE_UNDEFINED 0x1B
  35. #define CPSR_MODE_SYSTEM 0x1F
  36. #define CPSR_MODE_MASK 0x1F
  37. #define CPSR_ASYNC_ABORT (1 << 8)
  38. #define CPSR_IRQ (1 << 7)
  39. #define CPSR_FIQ (1 << 6)
  40. // CPACR - Coprocessor Access Control Register definitions
  41. #define CPACR_CP_DENIED(cp) 0x00
  42. #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
  43. #define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
  44. #define CPACR_ASEDIS (1 << 31)
  45. #define CPACR_D32DIS (1 << 30)
  46. #define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
  47. // NSACR - Non-Secure Access Control Register definitions
  48. #define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
  49. #define NSACR_NSD32DIS (1 << 14)
  50. #define NSACR_NSASEDIS (1 << 15)
  51. #define NSACR_PLE (1 << 16)
  52. #define NSACR_TL (1 << 17)
  53. #define NSACR_NS_SMP (1 << 18)
  54. #define NSACR_RFR (1 << 19)
  55. // SCR - Secure Configuration Register definitions
  56. #define SCR_NS (1 << 0)
  57. #define SCR_IRQ (1 << 1)
  58. #define SCR_FIQ (1 << 2)
  59. #define SCR_EA (1 << 3)
  60. #define SCR_FW (1 << 4)
  61. #define SCR_AW (1 << 5)
  62. // MIDR - Main ID Register definitions
  63. #define ARM_CPU_TYPE_MASK 0xFFF
  64. #define ARM_CPU_TYPE_AEMv8 0xD0F
  65. #define ARM_CPU_TYPE_A53 0xD03
  66. #define ARM_CPU_TYPE_A57 0xD07
  67. #define ARM_CPU_TYPE_A15 0xC0F
  68. #define ARM_CPU_TYPE_A9 0xC09
  69. #define ARM_CPU_TYPE_A5 0xC05
  70. #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
  71. #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  72. #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
  73. VOID
  74. EFIAPI
  75. ArmEnableSWPInstruction (
  76. VOID
  77. );
  78. UINTN
  79. EFIAPI
  80. ArmReadCbar (
  81. VOID
  82. );
  83. UINTN
  84. EFIAPI
  85. ArmReadTpidrurw (
  86. VOID
  87. );
  88. VOID
  89. EFIAPI
  90. ArmWriteTpidrurw (
  91. UINTN Value
  92. );
  93. UINT32
  94. EFIAPI
  95. ArmReadNsacr (
  96. VOID
  97. );
  98. VOID
  99. EFIAPI
  100. ArmWriteNsacr (
  101. IN UINT32 Nsacr
  102. );
  103. #endif // __ARM_V7_H__