ArmV7Support.asm 13 KB

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  1. //------------------------------------------------------------------------------
  2. //
  3. // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
  4. // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
  5. //
  6. // This program and the accompanying materials
  7. // are licensed and made available under the terms and conditions of the BSD License
  8. // which accompanies this distribution. The full text of the license may be found at
  9. // http://opensource.org/licenses/bsd-license.php
  10. //
  11. // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12. // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13. //
  14. //------------------------------------------------------------------------------
  15. EXPORT ArmInvalidateInstructionCache
  16. EXPORT ArmInvalidateDataCacheEntryByMVA
  17. EXPORT ArmCleanDataCacheEntryByMVA
  18. EXPORT ArmCleanInvalidateDataCacheEntryByMVA
  19. EXPORT ArmInvalidateDataCacheEntryBySetWay
  20. EXPORT ArmCleanDataCacheEntryBySetWay
  21. EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
  22. EXPORT ArmDrainWriteBuffer
  23. EXPORT ArmEnableMmu
  24. EXPORT ArmDisableMmu
  25. EXPORT ArmDisableCachesAndMmu
  26. EXPORT ArmMmuEnabled
  27. EXPORT ArmEnableDataCache
  28. EXPORT ArmDisableDataCache
  29. EXPORT ArmEnableInstructionCache
  30. EXPORT ArmDisableInstructionCache
  31. EXPORT ArmEnableSWPInstruction
  32. EXPORT ArmEnableBranchPrediction
  33. EXPORT ArmDisableBranchPrediction
  34. EXPORT ArmSetLowVectors
  35. EXPORT ArmSetHighVectors
  36. EXPORT ArmV7AllDataCachesOperation
  37. EXPORT ArmV7PerformPoUDataCacheOperation
  38. EXPORT ArmDataMemoryBarrier
  39. EXPORT ArmDataSyncronizationBarrier
  40. EXPORT ArmInstructionSynchronizationBarrier
  41. EXPORT ArmReadVBar
  42. EXPORT ArmWriteVBar
  43. EXPORT ArmEnableVFP
  44. EXPORT ArmCallWFI
  45. EXPORT ArmReadCbar
  46. EXPORT ArmInvalidateInstructionAndDataTlb
  47. EXPORT ArmReadMpidr
  48. EXPORT ArmReadTpidrurw
  49. EXPORT ArmWriteTpidrurw
  50. EXPORT ArmIsArchTimerImplemented
  51. EXPORT ArmReadIdPfr1
  52. AREA ArmV7Support, CODE, READONLY
  53. PRESERVE8
  54. DC_ON EQU ( 0x1:SHL:2 )
  55. IC_ON EQU ( 0x1:SHL:12 )
  56. CTRL_M_BIT EQU (1 << 0)
  57. CTRL_C_BIT EQU (1 << 2)
  58. CTRL_B_BIT EQU (1 << 7)
  59. CTRL_I_BIT EQU (1 << 12)
  60. ArmInvalidateDataCacheEntryByMVA
  61. mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
  62. dsb
  63. isb
  64. bx lr
  65. ArmCleanDataCacheEntryByMVA
  66. mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
  67. dsb
  68. isb
  69. bx lr
  70. ArmCleanInvalidateDataCacheEntryByMVA
  71. mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
  72. dsb
  73. isb
  74. bx lr
  75. ArmInvalidateDataCacheEntryBySetWay
  76. mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
  77. dsb
  78. isb
  79. bx lr
  80. ArmCleanInvalidateDataCacheEntryBySetWay
  81. mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
  82. dsb
  83. isb
  84. bx lr
  85. ArmCleanDataCacheEntryBySetWay
  86. mcr p15, 0, r0, c7, c10, 2 ; Clean this line
  87. dsb
  88. isb
  89. bx lr
  90. ArmInvalidateInstructionCache
  91. mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
  92. isb
  93. bx LR
  94. ArmEnableMmu
  95. mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
  96. orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
  97. mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
  98. dsb
  99. isb
  100. bx LR
  101. ArmDisableMmu
  102. mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
  103. bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
  104. mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
  105. mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
  106. mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
  107. dsb
  108. isb
  109. bx LR
  110. ArmDisableCachesAndMmu
  111. mrc p15, 0, r0, c1, c0, 0 ; Get control register
  112. bic r0, r0, #CTRL_M_BIT ; Disable MMU
  113. bic r0, r0, #CTRL_C_BIT ; Disable D Cache
  114. bic r0, r0, #CTRL_I_BIT ; Disable I Cache
  115. mcr p15, 0, r0, c1, c0, 0 ; Write control register
  116. dsb
  117. isb
  118. bx LR
  119. ArmMmuEnabled
  120. mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
  121. and R0,R0,#1
  122. bx LR
  123. ArmEnableDataCache
  124. ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
  125. mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
  126. orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
  127. mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
  128. dsb
  129. isb
  130. bx LR
  131. ArmDisableDataCache
  132. ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
  133. mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
  134. bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
  135. mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
  136. dsb
  137. isb
  138. bx LR
  139. ArmEnableInstructionCache
  140. ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
  141. mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
  142. orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
  143. mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
  144. dsb
  145. isb
  146. bx LR
  147. ArmDisableInstructionCache
  148. ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
  149. mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
  150. BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
  151. mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
  152. isb
  153. bx LR
  154. ArmEnableSWPInstruction
  155. mrc p15, 0, r0, c1, c0, 0
  156. orr r0, r0, #0x00000400
  157. mcr p15, 0, r0, c1, c0, 0
  158. isb
  159. bx LR
  160. ArmEnableBranchPrediction
  161. mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  162. orr r0, r0, #0x00000800 ;
  163. mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  164. dsb
  165. isb
  166. bx LR
  167. ArmDisableBranchPrediction
  168. mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  169. bic r0, r0, #0x00000800 ;
  170. mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  171. dsb
  172. isb
  173. bx LR
  174. ArmSetLowVectors
  175. mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  176. bic r0, r0, #0x00002000 ; clear V bit
  177. mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  178. isb
  179. bx LR
  180. ArmSetHighVectors
  181. mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  182. orr r0, r0, #0x00002000 ; Set V bit
  183. mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  184. isb
  185. bx LR
  186. ArmV7AllDataCachesOperation
  187. stmfd SP!,{r4-r12, LR}
  188. mov R1, R0 ; Save Function call in R1
  189. mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
  190. ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
  191. mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
  192. beq Finished
  193. mov R10, #0
  194. Loop1
  195. add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
  196. mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
  197. and R12, R12, #7 ; get those 3 bits alone
  198. cmp R12, #2
  199. blt Skip ; no cache or only instruction cache at this level
  200. mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
  201. isb ; isb to sync the change to the CacheSizeID reg
  202. mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
  203. and R2, R12, #&7 ; extract the line length field
  204. add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
  205. ldr R4, =0x3FF
  206. ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
  207. clz R5, R4 ; R5 is the bit position of the way size increment
  208. ldr R7, =0x00007FFF
  209. ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
  210. Loop2
  211. mov R9, R4 ; R9 working copy of the max way size (right aligned)
  212. Loop3
  213. orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
  214. orr R0, R0, R7, LSL R2 ; factor in the index number
  215. blx R1
  216. subs R9, R9, #1 ; decrement the way number
  217. bge Loop3
  218. subs R7, R7, #1 ; decrement the index
  219. bge Loop2
  220. Skip
  221. add R10, R10, #2 ; increment the cache number
  222. cmp R3, R10
  223. bgt Loop1
  224. Finished
  225. dsb
  226. ldmfd SP!, {r4-r12, lr}
  227. bx LR
  228. ArmV7PerformPoUDataCacheOperation
  229. stmfd SP!,{r4-r12, LR}
  230. mov R1, R0 ; Save Function call in R1
  231. mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
  232. ands R3, R6, #&38000000 ; Mask out all but Level of Unification (LoU)
  233. mov R3, R3, LSR #26 ; Cache level value (naturally aligned)
  234. beq Finished2
  235. mov R10, #0
  236. Loop4
  237. add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
  238. mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
  239. and R12, R12, #7 ; get those 3 bits alone
  240. cmp R12, #2
  241. blt Skip2 ; no cache or only instruction cache at this level
  242. mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
  243. isb ; isb to sync the change to the CacheSizeID reg
  244. mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
  245. and R2, R12, #&7 ; extract the line length field
  246. add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
  247. ldr R4, =0x3FF
  248. ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
  249. clz R5, R4 ; R5 is the bit position of the way size increment
  250. ldr R7, =0x00007FFF
  251. ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
  252. Loop5
  253. mov R9, R4 ; R9 working copy of the max way size (right aligned)
  254. Loop6
  255. orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
  256. orr R0, R0, R7, LSL R2 ; factor in the index number
  257. blx R1
  258. subs R9, R9, #1 ; decrement the way number
  259. bge Loop6
  260. subs R7, R7, #1 ; decrement the index
  261. bge Loop5
  262. Skip2
  263. add R10, R10, #2 ; increment the cache number
  264. cmp R3, R10
  265. bgt Loop4
  266. Finished2
  267. dsb
  268. ldmfd SP!, {r4-r12, lr}
  269. bx LR
  270. ArmDataMemoryBarrier
  271. dmb
  272. bx LR
  273. ArmDataSyncronizationBarrier
  274. ArmDrainWriteBuffer
  275. dsb
  276. bx LR
  277. ArmInstructionSynchronizationBarrier
  278. isb
  279. bx LR
  280. ArmReadVBar
  281. // Set the Address of the Vector Table in the VBAR register
  282. mrc p15, 0, r0, c12, c0, 0
  283. bx lr
  284. ArmWriteVBar
  285. // Set the Address of the Vector Table in the VBAR register
  286. mcr p15, 0, r0, c12, c0, 0
  287. // Ensure the SCTLR.V bit is clear
  288. mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
  289. bic r0, r0, #0x00002000 ; clear V bit
  290. mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
  291. isb
  292. bx lr
  293. ArmEnableVFP
  294. // Read CPACR (Coprocessor Access Control Register)
  295. mrc p15, 0, r0, c1, c0, 2
  296. // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
  297. orr r0, r0, #0x00f00000
  298. // Write back CPACR (Coprocessor Access Control Register)
  299. mcr p15, 0, r0, c1, c0, 2
  300. isb
  301. // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
  302. mov r0, #0x40000000
  303. mcr p10,#0x7,r0,c8,c0,#0
  304. bx lr
  305. ArmCallWFI
  306. wfi
  307. bx lr
  308. //Note: Return 0 in Uniprocessor implementation
  309. ArmReadCbar
  310. mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
  311. bx lr
  312. ArmInvalidateInstructionAndDataTlb
  313. mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
  314. dsb
  315. bx lr
  316. ArmReadMpidr
  317. mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
  318. bx lr
  319. ArmReadTpidrurw
  320. mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
  321. bx lr
  322. ArmWriteTpidrurw
  323. mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
  324. bx lr
  325. ArmIsArchTimerImplemented
  326. mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
  327. and r0, r0, #0x000F0000
  328. bx lr
  329. ArmReadIdPfr1
  330. mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
  331. bx lr
  332. END