Arm11LibMem.c 4.6 KB

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  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
  4. This program and the accompanying materials
  5. are licensed and made available under the terms and conditions of the BSD License
  6. which accompanies this distribution. The full text of the license may be found at
  7. http://opensource.org/licenses/bsd-license.php
  8. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10. **/
  11. #include <Chipset/ARM1176JZ-S.h>
  12. #include <Library/ArmLib.h>
  13. #include <Library/BaseMemoryLib.h>
  14. #include <Library/MemoryAllocationLib.h>
  15. VOID
  16. FillTranslationTable (
  17. IN UINT32 *TranslationTable,
  18. IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
  19. )
  20. {
  21. UINT32 *Entry;
  22. UINTN Sections;
  23. UINTN Index;
  24. UINT32 Attributes;
  25. UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
  26. switch (MemoryRegion->Attributes) {
  27. case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
  28. Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
  29. break;
  30. case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
  31. Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
  32. break;
  33. case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
  34. Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
  35. break;
  36. case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
  37. Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
  38. break;
  39. case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
  40. Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
  41. break;
  42. case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
  43. Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
  44. break;
  45. default:
  46. Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
  47. break;
  48. }
  49. Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
  50. Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
  51. for (Index = 0; Index < Sections; Index++)
  52. {
  53. *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
  54. PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
  55. }
  56. }
  57. RETURN_STATUS
  58. EFIAPI
  59. ArmConfigureMmu (
  60. IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
  61. OUT VOID **TranslationTableBase OPTIONAL,
  62. OUT UINTN *TranslationTableSize OPTIONAL
  63. )
  64. {
  65. VOID *TranslationTable;
  66. // Allocate pages for translation table.
  67. TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
  68. if (TranslationTable == NULL) {
  69. return RETURN_OUT_OF_RESOURCES;
  70. }
  71. TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
  72. if (TranslationTableBase != NULL) {
  73. *TranslationTableBase = TranslationTable;
  74. }
  75. if (TranslationTableBase != NULL) {
  76. *TranslationTableSize = TRANSLATION_TABLE_SIZE;
  77. }
  78. ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
  79. ArmCleanInvalidateDataCache();
  80. ArmInvalidateInstructionCache();
  81. ArmInvalidateTlb();
  82. ArmDisableDataCache();
  83. ArmDisableInstructionCache();
  84. ArmDisableMmu();
  85. // Make sure nothing sneaked into the cache
  86. ArmCleanInvalidateDataCache();
  87. ArmInvalidateInstructionCache();
  88. while (MemoryTable->Length != 0) {
  89. FillTranslationTable(TranslationTable, MemoryTable);
  90. MemoryTable++;
  91. }
  92. ArmSetTTBR0(TranslationTable);
  93. ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
  94. DOMAIN_ACCESS_CONTROL_NONE(14) |
  95. DOMAIN_ACCESS_CONTROL_NONE(13) |
  96. DOMAIN_ACCESS_CONTROL_NONE(12) |
  97. DOMAIN_ACCESS_CONTROL_NONE(11) |
  98. DOMAIN_ACCESS_CONTROL_NONE(10) |
  99. DOMAIN_ACCESS_CONTROL_NONE( 9) |
  100. DOMAIN_ACCESS_CONTROL_NONE( 8) |
  101. DOMAIN_ACCESS_CONTROL_NONE( 7) |
  102. DOMAIN_ACCESS_CONTROL_NONE( 6) |
  103. DOMAIN_ACCESS_CONTROL_NONE( 5) |
  104. DOMAIN_ACCESS_CONTROL_NONE( 4) |
  105. DOMAIN_ACCESS_CONTROL_NONE( 3) |
  106. DOMAIN_ACCESS_CONTROL_NONE( 2) |
  107. DOMAIN_ACCESS_CONTROL_NONE( 1) |
  108. DOMAIN_ACCESS_CONTROL_MANAGER(0));
  109. ArmEnableInstructionCache();
  110. ArmEnableDataCache();
  111. ArmEnableMmu();
  112. return RETURN_SUCCESS;
  113. }