ArmLib.h 9.6 KB

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  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
  4. This program and the accompanying materials
  5. are licensed and made available under the terms and conditions of the BSD License
  6. which accompanies this distribution. The full text of the license may be found at
  7. http://opensource.org/licenses/bsd-license.php
  8. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10. **/
  11. #ifndef __ARM_LIB__
  12. #define __ARM_LIB__
  13. #include <Uefi/UefiBaseType.h>
  14. #ifdef MDE_CPU_ARM
  15. #ifdef ARM_CPU_ARMv6
  16. #include <Chipset/ARM1176JZ-S.h>
  17. #else
  18. #include <Chipset/ArmV7.h>
  19. #endif
  20. #elif defined(MDE_CPU_AARCH64)
  21. #include <Chipset/AArch64.h>
  22. #else
  23. #error "Unknown chipset."
  24. #endif
  25. typedef enum {
  26. ARM_CACHE_TYPE_WRITE_BACK,
  27. ARM_CACHE_TYPE_UNKNOWN
  28. } ARM_CACHE_TYPE;
  29. typedef enum {
  30. ARM_CACHE_ARCHITECTURE_UNIFIED,
  31. ARM_CACHE_ARCHITECTURE_SEPARATE,
  32. ARM_CACHE_ARCHITECTURE_UNKNOWN
  33. } ARM_CACHE_ARCHITECTURE;
  34. typedef struct {
  35. ARM_CACHE_TYPE Type;
  36. ARM_CACHE_ARCHITECTURE Architecture;
  37. BOOLEAN DataCachePresent;
  38. UINTN DataCacheSize;
  39. UINTN DataCacheAssociativity;
  40. UINTN DataCacheLineLength;
  41. BOOLEAN InstructionCachePresent;
  42. UINTN InstructionCacheSize;
  43. UINTN InstructionCacheAssociativity;
  44. UINTN InstructionCacheLineLength;
  45. } ARM_CACHE_INFO;
  46. /**
  47. * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  48. *
  49. * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  50. * be used in Secure World to distinguished Secure to Non-Secure memory.
  51. */
  52. typedef enum {
  53. ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  54. ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  55. ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  56. ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  57. ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  58. ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  59. ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  60. ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  61. } ARM_MEMORY_REGION_ATTRIBUTES;
  62. #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  63. typedef struct {
  64. EFI_PHYSICAL_ADDRESS PhysicalBase;
  65. EFI_VIRTUAL_ADDRESS VirtualBase;
  66. UINT64 Length;
  67. ARM_MEMORY_REGION_ATTRIBUTES Attributes;
  68. } ARM_MEMORY_REGION_DESCRIPTOR;
  69. typedef VOID (*CACHE_OPERATION)(VOID);
  70. typedef VOID (*LINE_OPERATION)(UINTN);
  71. //
  72. // ARM Processor Mode
  73. //
  74. typedef enum {
  75. ARM_PROCESSOR_MODE_USER = 0x10,
  76. ARM_PROCESSOR_MODE_FIQ = 0x11,
  77. ARM_PROCESSOR_MODE_IRQ = 0x12,
  78. ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  79. ARM_PROCESSOR_MODE_ABORT = 0x17,
  80. ARM_PROCESSOR_MODE_HYP = 0x1A,
  81. ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
  82. ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
  83. ARM_PROCESSOR_MODE_MASK = 0x1F
  84. } ARM_PROCESSOR_MODE;
  85. //
  86. // ARM Cpu IDs
  87. //
  88. #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
  89. #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
  90. #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
  91. #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
  92. #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
  93. #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
  94. #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
  95. #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
  96. #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
  97. #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
  98. #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
  99. #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
  100. //
  101. // ARM MP Core IDs
  102. //
  103. #define ARM_CORE_MASK 0xFF
  104. #define ARM_CLUSTER_MASK (0xFF << 8)
  105. #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
  106. #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
  107. #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
  108. #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
  109. ARM_CACHE_TYPE
  110. EFIAPI
  111. ArmCacheType (
  112. VOID
  113. );
  114. ARM_CACHE_ARCHITECTURE
  115. EFIAPI
  116. ArmCacheArchitecture (
  117. VOID
  118. );
  119. VOID
  120. EFIAPI
  121. ArmCacheInformation (
  122. OUT ARM_CACHE_INFO *CacheInfo
  123. );
  124. BOOLEAN
  125. EFIAPI
  126. ArmDataCachePresent (
  127. VOID
  128. );
  129. UINTN
  130. EFIAPI
  131. ArmDataCacheSize (
  132. VOID
  133. );
  134. UINTN
  135. EFIAPI
  136. ArmDataCacheAssociativity (
  137. VOID
  138. );
  139. UINTN
  140. EFIAPI
  141. ArmDataCacheLineLength (
  142. VOID
  143. );
  144. BOOLEAN
  145. EFIAPI
  146. ArmInstructionCachePresent (
  147. VOID
  148. );
  149. UINTN
  150. EFIAPI
  151. ArmInstructionCacheSize (
  152. VOID
  153. );
  154. UINTN
  155. EFIAPI
  156. ArmInstructionCacheAssociativity (
  157. VOID
  158. );
  159. UINTN
  160. EFIAPI
  161. ArmInstructionCacheLineLength (
  162. VOID
  163. );
  164. UINTN
  165. EFIAPI
  166. ArmIsArchTimerImplemented (
  167. VOID
  168. );
  169. UINTN
  170. EFIAPI
  171. ArmReadIdPfr0 (
  172. VOID
  173. );
  174. UINTN
  175. EFIAPI
  176. ArmReadIdPfr1 (
  177. VOID
  178. );
  179. UINTN
  180. EFIAPI
  181. ArmCacheInfo (
  182. VOID
  183. );
  184. BOOLEAN
  185. EFIAPI
  186. ArmIsMpCore (
  187. VOID
  188. );
  189. VOID
  190. EFIAPI
  191. ArmInvalidateDataCache (
  192. VOID
  193. );
  194. VOID
  195. EFIAPI
  196. ArmCleanInvalidateDataCache (
  197. VOID
  198. );
  199. VOID
  200. EFIAPI
  201. ArmCleanDataCache (
  202. VOID
  203. );
  204. VOID
  205. EFIAPI
  206. ArmCleanDataCacheToPoU (
  207. VOID
  208. );
  209. VOID
  210. EFIAPI
  211. ArmInvalidateInstructionCache (
  212. VOID
  213. );
  214. VOID
  215. EFIAPI
  216. ArmInvalidateDataCacheEntryByMVA (
  217. IN UINTN Address
  218. );
  219. VOID
  220. EFIAPI
  221. ArmCleanDataCacheEntryByMVA (
  222. IN UINTN Address
  223. );
  224. VOID
  225. EFIAPI
  226. ArmCleanInvalidateDataCacheEntryByMVA (
  227. IN UINTN Address
  228. );
  229. VOID
  230. EFIAPI
  231. ArmInvalidateDataCacheEntryBySetWay (
  232. IN UINTN SetWayFormat
  233. );
  234. VOID
  235. EFIAPI
  236. ArmCleanDataCacheEntryBySetWay (
  237. IN UINTN SetWayFormat
  238. );
  239. VOID
  240. EFIAPI
  241. ArmCleanInvalidateDataCacheEntryBySetWay (
  242. IN UINTN SetWayFormat
  243. );
  244. VOID
  245. EFIAPI
  246. ArmEnableDataCache (
  247. VOID
  248. );
  249. VOID
  250. EFIAPI
  251. ArmDisableDataCache (
  252. VOID
  253. );
  254. VOID
  255. EFIAPI
  256. ArmEnableInstructionCache (
  257. VOID
  258. );
  259. VOID
  260. EFIAPI
  261. ArmDisableInstructionCache (
  262. VOID
  263. );
  264. VOID
  265. EFIAPI
  266. ArmEnableMmu (
  267. VOID
  268. );
  269. VOID
  270. EFIAPI
  271. ArmDisableMmu (
  272. VOID
  273. );
  274. VOID
  275. EFIAPI
  276. ArmEnableCachesAndMmu (
  277. VOID
  278. );
  279. VOID
  280. EFIAPI
  281. ArmDisableCachesAndMmu (
  282. VOID
  283. );
  284. VOID
  285. EFIAPI
  286. ArmInvalidateInstructionAndDataTlb (
  287. VOID
  288. );
  289. VOID
  290. EFIAPI
  291. ArmEnableInterrupts (
  292. VOID
  293. );
  294. UINTN
  295. EFIAPI
  296. ArmDisableInterrupts (
  297. VOID
  298. );
  299. BOOLEAN
  300. EFIAPI
  301. ArmGetInterruptState (
  302. VOID
  303. );
  304. VOID
  305. EFIAPI
  306. ArmEnableAsynchronousAbort (
  307. VOID
  308. );
  309. UINTN
  310. EFIAPI
  311. ArmDisableAsynchronousAbort (
  312. VOID
  313. );
  314. VOID
  315. EFIAPI
  316. ArmEnableIrq (
  317. VOID
  318. );
  319. UINTN
  320. EFIAPI
  321. ArmDisableIrq (
  322. VOID
  323. );
  324. VOID
  325. EFIAPI
  326. ArmEnableFiq (
  327. VOID
  328. );
  329. UINTN
  330. EFIAPI
  331. ArmDisableFiq (
  332. VOID
  333. );
  334. BOOLEAN
  335. EFIAPI
  336. ArmGetFiqState (
  337. VOID
  338. );
  339. VOID
  340. EFIAPI
  341. ArmInvalidateTlb (
  342. VOID
  343. );
  344. VOID
  345. EFIAPI
  346. ArmUpdateTranslationTableEntry (
  347. IN VOID *TranslationTableEntry,
  348. IN VOID *Mva
  349. );
  350. VOID
  351. EFIAPI
  352. ArmSetDomainAccessControl (
  353. IN UINT32 Domain
  354. );
  355. VOID
  356. EFIAPI
  357. ArmSetTTBR0 (
  358. IN VOID *TranslationTableBase
  359. );
  360. VOID *
  361. EFIAPI
  362. ArmGetTTBR0BaseAddress (
  363. VOID
  364. );
  365. RETURN_STATUS
  366. EFIAPI
  367. ArmConfigureMmu (
  368. IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
  369. OUT VOID **TranslationTableBase OPTIONAL,
  370. OUT UINTN *TranslationTableSize OPTIONAL
  371. );
  372. BOOLEAN
  373. EFIAPI
  374. ArmMmuEnabled (
  375. VOID
  376. );
  377. VOID
  378. EFIAPI
  379. ArmEnableBranchPrediction (
  380. VOID
  381. );
  382. VOID
  383. EFIAPI
  384. ArmDisableBranchPrediction (
  385. VOID
  386. );
  387. VOID
  388. EFIAPI
  389. ArmSetLowVectors (
  390. VOID
  391. );
  392. VOID
  393. EFIAPI
  394. ArmSetHighVectors (
  395. VOID
  396. );
  397. VOID
  398. EFIAPI
  399. ArmDrainWriteBuffer (
  400. VOID
  401. );
  402. VOID
  403. EFIAPI
  404. ArmDataMemoryBarrier (
  405. VOID
  406. );
  407. VOID
  408. EFIAPI
  409. ArmDataSyncronizationBarrier (
  410. VOID
  411. );
  412. VOID
  413. EFIAPI
  414. ArmInstructionSynchronizationBarrier (
  415. VOID
  416. );
  417. VOID
  418. EFIAPI
  419. ArmWriteVBar (
  420. IN UINTN VectorBase
  421. );
  422. UINTN
  423. EFIAPI
  424. ArmReadVBar (
  425. VOID
  426. );
  427. VOID
  428. EFIAPI
  429. ArmWriteAuxCr (
  430. IN UINT32 Bit
  431. );
  432. UINT32
  433. EFIAPI
  434. ArmReadAuxCr (
  435. VOID
  436. );
  437. VOID
  438. EFIAPI
  439. ArmSetAuxCrBit (
  440. IN UINT32 Bits
  441. );
  442. VOID
  443. EFIAPI
  444. ArmUnsetAuxCrBit (
  445. IN UINT32 Bits
  446. );
  447. VOID
  448. EFIAPI
  449. ArmCallSEV (
  450. VOID
  451. );
  452. VOID
  453. EFIAPI
  454. ArmCallWFE (
  455. VOID
  456. );
  457. VOID
  458. EFIAPI
  459. ArmCallWFI (
  460. VOID
  461. );
  462. UINTN
  463. EFIAPI
  464. ArmReadMpidr (
  465. VOID
  466. );
  467. UINTN
  468. EFIAPI
  469. ArmReadMidr (
  470. VOID
  471. );
  472. UINT32
  473. EFIAPI
  474. ArmReadCpacr (
  475. VOID
  476. );
  477. VOID
  478. EFIAPI
  479. ArmWriteCpacr (
  480. IN UINT32 Access
  481. );
  482. VOID
  483. EFIAPI
  484. ArmEnableVFP (
  485. VOID
  486. );
  487. /**
  488. Get the Secure Configuration Register value
  489. @return Value read from the Secure Configuration Register
  490. **/
  491. UINT32
  492. EFIAPI
  493. ArmReadScr (
  494. VOID
  495. );
  496. /**
  497. Set the Secure Configuration Register
  498. @param Value Value to write to the Secure Configuration Register
  499. **/
  500. VOID
  501. EFIAPI
  502. ArmWriteScr (
  503. IN UINT32 Value
  504. );
  505. UINT32
  506. EFIAPI
  507. ArmReadMVBar (
  508. VOID
  509. );
  510. VOID
  511. EFIAPI
  512. ArmWriteMVBar (
  513. IN UINT32 VectorMonitorBase
  514. );
  515. UINT32
  516. EFIAPI
  517. ArmReadSctlr (
  518. VOID
  519. );
  520. UINTN
  521. EFIAPI
  522. ArmReadHVBar (
  523. VOID
  524. );
  525. VOID
  526. EFIAPI
  527. ArmWriteHVBar (
  528. IN UINTN HypModeVectorBase
  529. );
  530. //
  531. // Helper functions for accessing CPU ACTLR
  532. //
  533. UINTN
  534. EFIAPI
  535. ArmReadCpuActlr (
  536. VOID
  537. );
  538. VOID
  539. EFIAPI
  540. ArmWriteCpuActlr (
  541. IN UINTN Val
  542. );
  543. VOID
  544. EFIAPI
  545. ArmSetCpuActlrBit (
  546. IN UINTN Bits
  547. );
  548. VOID
  549. EFIAPI
  550. ArmUnsetCpuActlrBit (
  551. IN UINTN Bits
  552. );
  553. #endif // __ARM_LIB__