ArmV7Lib.c 4.6 KB

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  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
  4. This program and the accompanying materials
  5. are licensed and made available under the terms and conditions of the BSD License
  6. which accompanies this distribution. The full text of the license may be found at
  7. http://opensource.org/licenses/bsd-license.php
  8. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10. **/
  11. #include <Uefi.h>
  12. #include <Chipset/ArmV7.h>
  13. #include <Library/ArmLib.h>
  14. #include <Library/BaseLib.h>
  15. #include <Library/IoLib.h>
  16. #include "ArmV7Lib.h"
  17. #include "ArmLibPrivate.h"
  18. ARM_CACHE_TYPE
  19. EFIAPI
  20. ArmCacheType (
  21. VOID
  22. )
  23. {
  24. return ARM_CACHE_TYPE_WRITE_BACK;
  25. }
  26. ARM_CACHE_ARCHITECTURE
  27. EFIAPI
  28. ArmCacheArchitecture (
  29. VOID
  30. )
  31. {
  32. UINT32 CLIDR = ReadCLIDR ();
  33. return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
  34. }
  35. BOOLEAN
  36. EFIAPI
  37. ArmDataCachePresent (
  38. VOID
  39. )
  40. {
  41. UINT32 CLIDR = ReadCLIDR ();
  42. if ((CLIDR & 0x2) == 0x2) {
  43. // Instruction cache exists
  44. return TRUE;
  45. }
  46. if ((CLIDR & 0x7) == 0x4) {
  47. // Unified cache
  48. return TRUE;
  49. }
  50. return FALSE;
  51. }
  52. UINTN
  53. EFIAPI
  54. ArmDataCacheSize (
  55. VOID
  56. )
  57. {
  58. UINT32 NumSets;
  59. UINT32 Associativity;
  60. UINT32 LineSize;
  61. UINT32 CCSIDR = ReadCCSIDR (0);
  62. LineSize = (1 << ((CCSIDR & 0x7) + 2));
  63. Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
  64. NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
  65. // LineSize is in words (4 byte chunks)
  66. return NumSets * Associativity * LineSize * 4;
  67. }
  68. UINTN
  69. EFIAPI
  70. ArmDataCacheAssociativity (
  71. VOID
  72. )
  73. {
  74. UINT32 CCSIDR = ReadCCSIDR (0);
  75. return ((CCSIDR >> 3) & 0x3ff) + 1;
  76. }
  77. UINTN
  78. ArmDataCacheSets (
  79. VOID
  80. )
  81. {
  82. UINT32 CCSIDR = ReadCCSIDR (0);
  83. return ((CCSIDR >> 13) & 0x7fff) + 1;
  84. }
  85. UINTN
  86. EFIAPI
  87. ArmDataCacheLineLength (
  88. VOID
  89. )
  90. {
  91. UINT32 CCSIDR = ReadCCSIDR (0) & 7;
  92. // * 4 converts to bytes
  93. return (1 << (CCSIDR + 2)) * 4;
  94. }
  95. BOOLEAN
  96. EFIAPI
  97. ArmInstructionCachePresent (
  98. VOID
  99. )
  100. {
  101. UINT32 CLIDR = ReadCLIDR ();
  102. if ((CLIDR & 1) == 1) {
  103. // Instruction cache exists
  104. return TRUE;
  105. }
  106. if ((CLIDR & 0x7) == 0x4) {
  107. // Unified cache
  108. return TRUE;
  109. }
  110. return FALSE;
  111. }
  112. UINTN
  113. EFIAPI
  114. ArmInstructionCacheSize (
  115. VOID
  116. )
  117. {
  118. UINT32 NumSets;
  119. UINT32 Associativity;
  120. UINT32 LineSize;
  121. UINT32 CCSIDR = ReadCCSIDR (1);
  122. LineSize = (1 << ((CCSIDR & 0x7) + 2));
  123. Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
  124. NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
  125. // LineSize is in words (4 byte chunks)
  126. return NumSets * Associativity * LineSize * 4;
  127. }
  128. UINTN
  129. EFIAPI
  130. ArmInstructionCacheAssociativity (
  131. VOID
  132. )
  133. {
  134. UINT32 CCSIDR = ReadCCSIDR (1);
  135. return ((CCSIDR >> 3) & 0x3ff) + 1;
  136. // return 4;
  137. }
  138. UINTN
  139. EFIAPI
  140. ArmInstructionCacheSets (
  141. VOID
  142. )
  143. {
  144. UINT32 CCSIDR = ReadCCSIDR (1);
  145. return ((CCSIDR >> 13) & 0x7fff) + 1;
  146. }
  147. UINTN
  148. EFIAPI
  149. ArmInstructionCacheLineLength (
  150. VOID
  151. )
  152. {
  153. UINT32 CCSIDR = ReadCCSIDR (1) & 7;
  154. // * 4 converts to bytes
  155. return (1 << (CCSIDR + 2)) * 4;
  156. // return 64;
  157. }
  158. VOID
  159. ArmV7DataCacheOperation (
  160. IN ARM_V7_CACHE_OPERATION DataCacheOperation
  161. )
  162. {
  163. UINTN SavedInterruptState;
  164. SavedInterruptState = ArmGetInterruptState ();
  165. ArmDisableInterrupts ();
  166. ArmV7AllDataCachesOperation (DataCacheOperation);
  167. ArmDrainWriteBuffer ();
  168. if (SavedInterruptState) {
  169. ArmEnableInterrupts ();
  170. }
  171. }
  172. VOID
  173. ArmV7PoUDataCacheOperation (
  174. IN ARM_V7_CACHE_OPERATION DataCacheOperation
  175. )
  176. {
  177. UINTN SavedInterruptState;
  178. SavedInterruptState = ArmGetInterruptState ();
  179. ArmDisableInterrupts ();
  180. ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
  181. ArmDrainWriteBuffer ();
  182. if (SavedInterruptState) {
  183. ArmEnableInterrupts ();
  184. }
  185. }
  186. VOID
  187. EFIAPI
  188. ArmInvalidateDataCache (
  189. VOID
  190. )
  191. {
  192. ArmDrainWriteBuffer ();
  193. ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
  194. }
  195. VOID
  196. EFIAPI
  197. ArmCleanInvalidateDataCache (
  198. VOID
  199. )
  200. {
  201. ArmDrainWriteBuffer ();
  202. ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
  203. }
  204. VOID
  205. EFIAPI
  206. ArmCleanDataCache (
  207. VOID
  208. )
  209. {
  210. ArmDrainWriteBuffer ();
  211. ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
  212. }
  213. VOID
  214. EFIAPI
  215. ArmCleanDataCacheToPoU (
  216. VOID
  217. )
  218. {
  219. ArmDrainWriteBuffer ();
  220. ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
  221. }