ArmLibSupport.S 5.0 KB

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  1. #------------------------------------------------------------------------------
  2. #
  3. # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  4. # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
  5. #
  6. # This program and the accompanying materials
  7. # are licensed and made available under the terms and conditions of the BSD License
  8. # which accompanies this distribution. The full text of the license may be found at
  9. # http://opensource.org/licenses/bsd-license.php
  10. #
  11. # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12. # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13. #
  14. #------------------------------------------------------------------------------
  15. #include <AsmMacroIoLib.h>
  16. #ifdef ARM_CPU_ARMv6
  17. // No memory barriers for ARMv6
  18. #define isb
  19. #define dsb
  20. #endif
  21. .text
  22. .align 2
  23. GCC_ASM_EXPORT(ArmReadMidr)
  24. GCC_ASM_EXPORT(ArmCacheInfo)
  25. GCC_ASM_EXPORT(ArmGetInterruptState)
  26. GCC_ASM_EXPORT(ArmGetFiqState)
  27. GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
  28. GCC_ASM_EXPORT(ArmSetTTBR0)
  29. GCC_ASM_EXPORT(ArmSetDomainAccessControl)
  30. GCC_ASM_EXPORT(CPSRMaskInsert)
  31. GCC_ASM_EXPORT(CPSRRead)
  32. GCC_ASM_EXPORT(ArmReadCpacr)
  33. GCC_ASM_EXPORT(ArmWriteCpacr)
  34. GCC_ASM_EXPORT(ArmWriteAuxCr)
  35. GCC_ASM_EXPORT(ArmReadAuxCr)
  36. GCC_ASM_EXPORT(ArmInvalidateTlb)
  37. GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
  38. GCC_ASM_EXPORT(ArmReadScr)
  39. GCC_ASM_EXPORT(ArmWriteScr)
  40. GCC_ASM_EXPORT(ArmReadMVBar)
  41. GCC_ASM_EXPORT(ArmWriteMVBar)
  42. GCC_ASM_EXPORT(ArmReadHVBar)
  43. GCC_ASM_EXPORT(ArmWriteHVBar)
  44. GCC_ASM_EXPORT(ArmCallWFE)
  45. GCC_ASM_EXPORT(ArmCallSEV)
  46. GCC_ASM_EXPORT(ArmReadSctlr)
  47. GCC_ASM_EXPORT(ArmReadCpuActlr)
  48. GCC_ASM_EXPORT(ArmWriteCpuActlr)
  49. #------------------------------------------------------------------------------
  50. ASM_PFX(ArmReadMidr):
  51. mrc p15,0,R0,c0,c0,0
  52. bx LR
  53. ASM_PFX(ArmCacheInfo):
  54. mrc p15,0,R0,c0,c0,1
  55. bx LR
  56. ASM_PFX(ArmGetInterruptState):
  57. mrs R0,CPSR
  58. tst R0,#0x80 @Check if IRQ is enabled.
  59. moveq R0,#1
  60. movne R0,#0
  61. bx LR
  62. ASM_PFX(ArmGetFiqState):
  63. mrs R0,CPSR
  64. tst R0,#0x40 @Check if FIQ is enabled.
  65. moveq R0,#1
  66. movne R0,#0
  67. bx LR
  68. ASM_PFX(ArmSetDomainAccessControl):
  69. mcr p15,0,r0,c3,c0,0
  70. bx lr
  71. ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
  72. stmfd sp!, {r4-r12, lr} @ save all the banked registers
  73. mov r3, sp @ copy the stack pointer into a non-banked register
  74. mrs r2, cpsr @ read the cpsr
  75. bic r2, r2, r0 @ clear mask in the cpsr
  76. and r1, r1, r0 @ clear bits outside the mask in the input
  77. orr r2, r2, r1 @ set field
  78. msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
  79. isb
  80. mov sp, r3 @ restore stack pointer
  81. ldmfd sp!, {r4-r12, lr} @ restore registers
  82. bx lr @ return (hopefully thumb-safe!)
  83. ASM_PFX(CPSRRead):
  84. mrs r0, cpsr
  85. bx lr
  86. ASM_PFX(ArmReadCpacr):
  87. mrc p15, 0, r0, c1, c0, 2
  88. bx lr
  89. ASM_PFX(ArmWriteCpacr):
  90. mcr p15, 0, r0, c1, c0, 2
  91. isb
  92. bx lr
  93. ASM_PFX(ArmWriteAuxCr):
  94. mcr p15, 0, r0, c1, c0, 1
  95. bx lr
  96. ASM_PFX(ArmReadAuxCr):
  97. mrc p15, 0, r0, c1, c0, 1
  98. bx lr
  99. ASM_PFX(ArmSetTTBR0):
  100. mcr p15,0,r0,c2,c0,0
  101. isb
  102. bx lr
  103. ASM_PFX(ArmGetTTBR0BaseAddress):
  104. mrc p15,0,r0,c2,c0,0
  105. LoadConstantToReg(0xFFFFC000, r1)
  106. and r0, r0, r1
  107. isb
  108. bx lr
  109. //
  110. //VOID
  111. //ArmUpdateTranslationTableEntry (
  112. // IN VOID *TranslationTableEntry // R0
  113. // IN VOID *MVA // R1
  114. // );
  115. ASM_PFX(ArmUpdateTranslationTableEntry):
  116. mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
  117. dsb
  118. mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
  119. mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
  120. dsb
  121. isb
  122. bx lr
  123. ASM_PFX(ArmInvalidateTlb):
  124. mov r0,#0
  125. mcr p15,0,r0,c8,c7,0
  126. mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
  127. dsb
  128. isb
  129. bx lr
  130. ASM_PFX(ArmReadScr):
  131. mrc p15, 0, r0, c1, c1, 0
  132. bx lr
  133. ASM_PFX(ArmWriteScr):
  134. mcr p15, 0, r0, c1, c1, 0
  135. bx lr
  136. ASM_PFX(ArmReadHVBar):
  137. mrc p15, 4, r0, c12, c0, 0
  138. bx lr
  139. ASM_PFX(ArmWriteHVBar):
  140. mcr p15, 4, r0, c12, c0, 0
  141. bx lr
  142. ASM_PFX(ArmReadMVBar):
  143. mrc p15, 0, r0, c12, c0, 1
  144. bx lr
  145. ASM_PFX(ArmWriteMVBar):
  146. mcr p15, 0, r0, c12, c0, 1
  147. bx lr
  148. ASM_PFX(ArmCallWFE):
  149. wfe
  150. bx lr
  151. ASM_PFX(ArmCallSEV):
  152. sev
  153. bx lr
  154. ASM_PFX(ArmReadSctlr):
  155. mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
  156. bx lr
  157. ASM_PFX(ArmReadCpuActlr):
  158. mrc p15, 0, r0, c1, c0, 1
  159. bx lr
  160. ASM_PFX(ArmWriteCpuActlr):
  161. mcr p15, 0, r0, c1, c0, 1
  162. dsb
  163. isb
  164. bx lr
  165. ASM_FUNCTION_REMOVE_IF_UNREFERENCED