Exception.c 7.7 KB

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  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. Copyright (c) 2014, ARM Limited. All rights reserved.<BR>
  4. This program and the accompanying materials
  5. are licensed and made available under the terms and conditions of the BSD License
  6. which accompanies this distribution. The full text of the license may be found at
  7. http://opensource.org/licenses/bsd-license.php
  8. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10. **/
  11. #include "CpuDxe.h"
  12. //FIXME: Will not compile on non-ARMv7 builds
  13. #include <Chipset/ArmV7.h>
  14. VOID
  15. ExceptionHandlersStart (
  16. VOID
  17. );
  18. VOID
  19. ExceptionHandlersEnd (
  20. VOID
  21. );
  22. VOID
  23. CommonExceptionEntry (
  24. VOID
  25. );
  26. VOID
  27. AsmCommonExceptionEntry (
  28. VOID
  29. );
  30. EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1];
  31. EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1];
  32. /**
  33. This function registers and enables the handler specified by InterruptHandler for a processor
  34. interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
  35. handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
  36. The installed handler is called once for each processor interrupt or exception.
  37. @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
  38. are enabled and FALSE if interrupts are disabled.
  39. @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
  40. when a processor interrupt occurs. If this parameter is NULL, then the handler
  41. will be uninstalled.
  42. @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
  43. @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
  44. previously installed.
  45. @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
  46. previously installed.
  47. @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
  48. **/
  49. EFI_STATUS
  50. RegisterInterruptHandler (
  51. IN EFI_EXCEPTION_TYPE InterruptType,
  52. IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
  53. )
  54. {
  55. if (InterruptType > MAX_ARM_EXCEPTION) {
  56. return EFI_UNSUPPORTED;
  57. }
  58. if ((InterruptHandler != NULL) && (gExceptionHandlers[InterruptType] != NULL)) {
  59. return EFI_ALREADY_STARTED;
  60. }
  61. gExceptionHandlers[InterruptType] = InterruptHandler;
  62. return EFI_SUCCESS;
  63. }
  64. VOID
  65. EFIAPI
  66. CommonCExceptionHandler (
  67. IN EFI_EXCEPTION_TYPE ExceptionType,
  68. IN OUT EFI_SYSTEM_CONTEXT SystemContext
  69. )
  70. {
  71. if (ExceptionType <= MAX_ARM_EXCEPTION) {
  72. if (gExceptionHandlers[ExceptionType]) {
  73. gExceptionHandlers[ExceptionType] (ExceptionType, SystemContext);
  74. return;
  75. }
  76. } else {
  77. DEBUG ((EFI_D_ERROR, "Unknown exception type %d from %08x\n", ExceptionType, SystemContext.SystemContextArm->PC));
  78. ASSERT (FALSE);
  79. }
  80. if (ExceptionType == EXCEPT_ARM_SOFTWARE_INTERRUPT) {
  81. //
  82. // ARM JTAG debuggers some times use this vector, so it is not an error to get one
  83. //
  84. return;
  85. }
  86. DefaultExceptionHandler (ExceptionType, SystemContext);
  87. }
  88. EFI_STATUS
  89. InitializeExceptions (
  90. IN EFI_CPU_ARCH_PROTOCOL *Cpu
  91. )
  92. {
  93. EFI_STATUS Status;
  94. UINTN Offset;
  95. UINTN Length;
  96. UINTN Index;
  97. BOOLEAN IrqEnabled;
  98. BOOLEAN FiqEnabled;
  99. EFI_PHYSICAL_ADDRESS Base;
  100. UINT32 *VectorBase;
  101. Status = EFI_SUCCESS;
  102. ZeroMem (gExceptionHandlers,sizeof(*gExceptionHandlers));
  103. //
  104. // Disable interrupts
  105. //
  106. Cpu->GetInterruptState (Cpu, &IrqEnabled);
  107. Cpu->DisableInterrupt (Cpu);
  108. //
  109. // EFI does not use the FIQ, but a debugger might so we must disable
  110. // as we take over the exception vectors.
  111. //
  112. FiqEnabled = ArmGetFiqState ();
  113. ArmDisableFiq ();
  114. if (FeaturePcdGet(PcdRelocateVectorTable) == TRUE) {
  115. //
  116. // Copy an implementation of the ARM exception vectors to PcdCpuVectorBaseAddress.
  117. //
  118. Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;
  119. // Check if the exception vector is in the low address
  120. if (PcdGet32 (PcdCpuVectorBaseAddress) == 0x0) {
  121. // Set SCTLR.V to 0 to enable VBAR to be used
  122. ArmSetLowVectors ();
  123. } else {
  124. ArmSetHighVectors ();
  125. }
  126. //
  127. // Reserve space for the exception handlers
  128. //
  129. Base = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdCpuVectorBaseAddress);
  130. VectorBase = (UINT32 *)(UINTN)Base;
  131. Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, EFI_SIZE_TO_PAGES (Length), &Base);
  132. // If the request was for memory that's not in the memory map (which is often the case for 0x00000000
  133. // on embedded systems, for example, we don't want to hang up. So we'll check here for a status of
  134. // EFI_NOT_FOUND, and continue in that case.
  135. if (EFI_ERROR(Status) && (Status != EFI_NOT_FOUND)) {
  136. ASSERT_EFI_ERROR (Status);
  137. }
  138. if (FeaturePcdGet(PcdDebuggerExceptionSupport) == TRUE) {
  139. // Save existing vector table, in case debugger is already hooked in
  140. CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (gDebuggerExceptionHandlers));
  141. }
  142. // Copy our assembly code into the page that contains the exception vectors.
  143. CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);
  144. //
  145. // Patch in the common Assembly exception handler
  146. //
  147. Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;
  148. *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry;
  149. //
  150. // Initialize the C entry points for interrupts
  151. //
  152. for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {
  153. if (!FeaturePcdGet(PcdDebuggerExceptionSupport) ||
  154. (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)(UINTN)0xEAFFFFFE)) {
  155. // Exception handler contains branch to vector location (jmp $) so no handler
  156. // NOTE: This code assumes vectors are ARM and not Thumb code
  157. Status = RegisterInterruptHandler (Index, NULL);
  158. ASSERT_EFI_ERROR (Status);
  159. } else {
  160. // If the debugger has already hooked put its vector back
  161. VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];
  162. }
  163. }
  164. // Flush Caches since we updated executable stuff
  165. InvalidateInstructionCacheRange ((VOID *)PcdGet32(PcdCpuVectorBaseAddress), Length);
  166. //Note: On ARM processor with the Security Extension, the Vector Table can be located anywhere in the memory.
  167. // The Vector Base Address Register defines the location
  168. ArmWriteVBar (PcdGet32(PcdCpuVectorBaseAddress));
  169. } else {
  170. // The Vector table must be 32-byte aligned
  171. if (((UINT32)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) != 0) {
  172. ASSERT (0);
  173. return EFI_INVALID_PARAMETER;
  174. }
  175. // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
  176. ArmWriteVBar ((UINT32)ExceptionHandlersStart);
  177. }
  178. if (FiqEnabled) {
  179. ArmEnableFiq ();
  180. }
  181. if (IrqEnabled) {
  182. //
  183. // Restore interrupt state
  184. //
  185. Status = Cpu->EnableInterrupt (Cpu);
  186. }
  187. return Status;
  188. }