CpuDxe.c 8.6 KB

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  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. Copyright (c) 2011, ARM Limited. All rights reserved.
  4. This program and the accompanying materials
  5. are licensed and made available under the terms and conditions of the BSD License
  6. which accompanies this distribution. The full text of the license may be found at
  7. http://opensource.org/licenses/bsd-license.php
  8. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10. **/
  11. #include "CpuDxe.h"
  12. #include <Guid/IdleLoopEvent.h>
  13. BOOLEAN mInterruptState = FALSE;
  14. /**
  15. This function flushes the range of addresses from Start to Start+Length
  16. from the processor's data cache. If Start is not aligned to a cache line
  17. boundary, then the bytes before Start to the preceding cache line boundary
  18. are also flushed. If Start+Length is not aligned to a cache line boundary,
  19. then the bytes past Start+Length to the end of the next cache line boundary
  20. are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
  21. supported. If the data cache is fully coherent with all DMA operations, then
  22. this function can just return EFI_SUCCESS. If the processor does not support
  23. flushing a range of the data cache, then the entire data cache can be flushed.
  24. @param This The EFI_CPU_ARCH_PROTOCOL instance.
  25. @param Start The beginning physical address to flush from the processor's data
  26. cache.
  27. @param Length The number of bytes to flush from the processor's data cache. This
  28. function may flush more bytes than Length specifies depending upon
  29. the granularity of the flush operation that the processor supports.
  30. @param FlushType Specifies the type of flush operation to perform.
  31. @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from
  32. the processor's data cache.
  33. @retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified
  34. by FlushType.
  35. @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed
  36. from the processor's data cache.
  37. **/
  38. EFI_STATUS
  39. EFIAPI
  40. CpuFlushCpuDataCache (
  41. IN EFI_CPU_ARCH_PROTOCOL *This,
  42. IN EFI_PHYSICAL_ADDRESS Start,
  43. IN UINT64 Length,
  44. IN EFI_CPU_FLUSH_TYPE FlushType
  45. )
  46. {
  47. switch (FlushType) {
  48. case EfiCpuFlushTypeWriteBack:
  49. WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
  50. break;
  51. case EfiCpuFlushTypeInvalidate:
  52. InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
  53. break;
  54. case EfiCpuFlushTypeWriteBackInvalidate:
  55. WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
  56. break;
  57. default:
  58. return EFI_INVALID_PARAMETER;
  59. }
  60. return EFI_SUCCESS;
  61. }
  62. /**
  63. This function enables interrupt processing by the processor.
  64. @param This The EFI_CPU_ARCH_PROTOCOL instance.
  65. @retval EFI_SUCCESS Interrupts are enabled on the processor.
  66. @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
  67. **/
  68. EFI_STATUS
  69. EFIAPI
  70. CpuEnableInterrupt (
  71. IN EFI_CPU_ARCH_PROTOCOL *This
  72. )
  73. {
  74. ArmEnableInterrupts ();
  75. mInterruptState = TRUE;
  76. return EFI_SUCCESS;
  77. }
  78. /**
  79. This function disables interrupt processing by the processor.
  80. @param This The EFI_CPU_ARCH_PROTOCOL instance.
  81. @retval EFI_SUCCESS Interrupts are disabled on the processor.
  82. @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
  83. **/
  84. EFI_STATUS
  85. EFIAPI
  86. CpuDisableInterrupt (
  87. IN EFI_CPU_ARCH_PROTOCOL *This
  88. )
  89. {
  90. ArmDisableInterrupts ();
  91. mInterruptState = FALSE;
  92. return EFI_SUCCESS;
  93. }
  94. /**
  95. This function retrieves the processor's current interrupt state a returns it in
  96. State. If interrupts are currently enabled, then TRUE is returned. If interrupts
  97. are currently disabled, then FALSE is returned.
  98. @param This The EFI_CPU_ARCH_PROTOCOL instance.
  99. @param State A pointer to the processor's current interrupt state. Set to TRUE if
  100. interrupts are enabled and FALSE if interrupts are disabled.
  101. @retval EFI_SUCCESS The processor's current interrupt state was returned in State.
  102. @retval EFI_INVALID_PARAMETER State is NULL.
  103. **/
  104. EFI_STATUS
  105. EFIAPI
  106. CpuGetInterruptState (
  107. IN EFI_CPU_ARCH_PROTOCOL *This,
  108. OUT BOOLEAN *State
  109. )
  110. {
  111. if (State == NULL) {
  112. return EFI_INVALID_PARAMETER;
  113. }
  114. *State = mInterruptState;
  115. return EFI_SUCCESS;
  116. }
  117. /**
  118. This function generates an INIT on the processor. If this function succeeds, then the
  119. processor will be reset, and control will not be returned to the caller. If InitType is
  120. not supported by this processor, or the processor cannot programmatically generate an
  121. INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
  122. occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
  123. @param This The EFI_CPU_ARCH_PROTOCOL instance.
  124. @param InitType The type of processor INIT to perform.
  125. @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.
  126. @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported
  127. by this processor.
  128. @retval EFI_DEVICE_ERROR The processor INIT failed.
  129. **/
  130. EFI_STATUS
  131. EFIAPI
  132. CpuInit (
  133. IN EFI_CPU_ARCH_PROTOCOL *This,
  134. IN EFI_CPU_INIT_TYPE InitType
  135. )
  136. {
  137. return EFI_UNSUPPORTED;
  138. }
  139. EFI_STATUS
  140. EFIAPI
  141. CpuRegisterInterruptHandler (
  142. IN EFI_CPU_ARCH_PROTOCOL *This,
  143. IN EFI_EXCEPTION_TYPE InterruptType,
  144. IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
  145. )
  146. {
  147. return RegisterInterruptHandler (InterruptType, InterruptHandler);
  148. }
  149. EFI_STATUS
  150. EFIAPI
  151. CpuGetTimerValue (
  152. IN EFI_CPU_ARCH_PROTOCOL *This,
  153. IN UINT32 TimerIndex,
  154. OUT UINT64 *TimerValue,
  155. OUT UINT64 *TimerPeriod OPTIONAL
  156. )
  157. {
  158. return EFI_UNSUPPORTED;
  159. }
  160. /**
  161. Callback function for idle events.
  162. @param Event Event whose notification function is being invoked.
  163. @param Context The pointer to the notification function's context,
  164. which is implementation-dependent.
  165. **/
  166. VOID
  167. EFIAPI
  168. IdleLoopEventCallback (
  169. IN EFI_EVENT Event,
  170. IN VOID *Context
  171. )
  172. {
  173. CpuSleep ();
  174. }
  175. //
  176. // Globals used to initialize the protocol
  177. //
  178. EFI_HANDLE mCpuHandle = NULL;
  179. EFI_CPU_ARCH_PROTOCOL mCpu = {
  180. CpuFlushCpuDataCache,
  181. CpuEnableInterrupt,
  182. CpuDisableInterrupt,
  183. CpuGetInterruptState,
  184. CpuInit,
  185. CpuRegisterInterruptHandler,
  186. CpuGetTimerValue,
  187. CpuSetMemoryAttributes,
  188. 0, // NumberOfTimers
  189. 4, // DmaBufferAlignment
  190. };
  191. EFI_STATUS
  192. CpuDxeInitialize (
  193. IN EFI_HANDLE ImageHandle,
  194. IN EFI_SYSTEM_TABLE *SystemTable
  195. )
  196. {
  197. EFI_STATUS Status;
  198. EFI_EVENT IdleLoopEvent;
  199. InitializeExceptions (&mCpu);
  200. Status = gBS->InstallMultipleProtocolInterfaces (
  201. &mCpuHandle,
  202. &gEfiCpuArchProtocolGuid, &mCpu,
  203. &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,
  204. NULL
  205. );
  206. //
  207. // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
  208. // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
  209. // after the protocol is installed
  210. //
  211. SyncCacheConfig (&mCpu);
  212. // If the platform is a MPCore system then install the Configuration Table describing the
  213. // secondary core states
  214. if (ArmIsMpCore()) {
  215. PublishArmProcessorTable();
  216. }
  217. //
  218. // Setup a callback for idle events
  219. //
  220. Status = gBS->CreateEventEx (
  221. EVT_NOTIFY_SIGNAL,
  222. TPL_NOTIFY,
  223. IdleLoopEventCallback,
  224. NULL,
  225. &gIdleLoopEventGuid,
  226. &IdleLoopEvent
  227. );
  228. ASSERT_EFI_ERROR (Status);
  229. return Status;
  230. }