ArmLibSupport.asm 4.6 KB

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  1. //------------------------------------------------------------------------------
  2. //
  3. // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  4. // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
  5. //
  6. // This program and the accompanying materials
  7. // are licensed and made available under the terms and conditions of the BSD License
  8. // which accompanies this distribution. The full text of the license may be found at
  9. // http://opensource.org/licenses/bsd-license.php
  10. //
  11. // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12. // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13. //
  14. //------------------------------------------------------------------------------
  15. #include <AsmMacroIoLib.h>
  16. INCLUDE AsmMacroIoLib.inc
  17. #ifdef ARM_CPU_ARMv6
  18. // No memory barriers for ARMv6
  19. #define isb
  20. #define dsb
  21. #endif
  22. EXPORT ArmReadMidr
  23. EXPORT ArmCacheInfo
  24. EXPORT ArmGetInterruptState
  25. EXPORT ArmGetFiqState
  26. EXPORT ArmGetTTBR0BaseAddress
  27. EXPORT ArmSetTTBR0
  28. EXPORT ArmSetDomainAccessControl
  29. EXPORT CPSRMaskInsert
  30. EXPORT CPSRRead
  31. EXPORT ArmReadCpacr
  32. EXPORT ArmWriteCpacr
  33. EXPORT ArmWriteAuxCr
  34. EXPORT ArmReadAuxCr
  35. EXPORT ArmInvalidateTlb
  36. EXPORT ArmUpdateTranslationTableEntry
  37. EXPORT ArmReadScr
  38. EXPORT ArmWriteScr
  39. EXPORT ArmReadMVBar
  40. EXPORT ArmWriteMVBar
  41. EXPORT ArmReadHVBar
  42. EXPORT ArmWriteHVBar
  43. EXPORT ArmCallWFE
  44. EXPORT ArmCallSEV
  45. EXPORT ArmReadSctlr
  46. EXPORT ArmReadCpuActlr
  47. EXPORT ArmWriteCpuActlr
  48. AREA ArmLibSupport, CODE, READONLY
  49. ArmReadMidr
  50. mrc p15,0,R0,c0,c0,0
  51. bx LR
  52. ArmCacheInfo
  53. mrc p15,0,R0,c0,c0,1
  54. bx LR
  55. ArmGetInterruptState
  56. mrs R0,CPSR
  57. tst R0,#0x80 // Check if IRQ is enabled.
  58. moveq R0,#1
  59. movne R0,#0
  60. bx LR
  61. ArmGetFiqState
  62. mrs R0,CPSR
  63. tst R0,#0x40 // Check if FIQ is enabled.
  64. moveq R0,#1
  65. movne R0,#0
  66. bx LR
  67. ArmSetDomainAccessControl
  68. mcr p15,0,r0,c3,c0,0
  69. bx lr
  70. CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert
  71. stmfd sp!, {r4-r12, lr} // save all the banked registers
  72. mov r3, sp // copy the stack pointer into a non-banked register
  73. mrs r2, cpsr // read the cpsr
  74. bic r2, r2, r0 // clear mask in the cpsr
  75. and r1, r1, r0 // clear bits outside the mask in the input
  76. orr r2, r2, r1 // set field
  77. msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)
  78. isb
  79. mov sp, r3 // restore stack pointer
  80. ldmfd sp!, {r4-r12, lr} // restore registers
  81. bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)
  82. CPSRRead
  83. mrs r0, cpsr
  84. bx lr
  85. ArmReadCpacr
  86. mrc p15, 0, r0, c1, c0, 2
  87. bx lr
  88. ArmWriteCpacr
  89. mcr p15, 0, r0, c1, c0, 2
  90. isb
  91. bx lr
  92. ArmWriteAuxCr
  93. mcr p15, 0, r0, c1, c0, 1
  94. bx lr
  95. ArmReadAuxCr
  96. mrc p15, 0, r0, c1, c0, 1
  97. bx lr
  98. ArmSetTTBR0
  99. mcr p15,0,r0,c2,c0,0
  100. isb
  101. bx lr
  102. ArmGetTTBR0BaseAddress
  103. mrc p15,0,r0,c2,c0,0
  104. LoadConstantToReg(0xFFFFC000, r1)
  105. and r0, r0, r1
  106. isb
  107. bx lr
  108. //
  109. //VOID
  110. //ArmUpdateTranslationTableEntry (
  111. // IN VOID *TranslationTableEntry // R0
  112. // IN VOID *MVA // R1
  113. // );
  114. ArmUpdateTranslationTableEntry
  115. mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA
  116. dsb
  117. mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA
  118. mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
  119. dsb
  120. isb
  121. bx lr
  122. ArmInvalidateTlb
  123. mov r0,#0
  124. mcr p15,0,r0,c8,c7,0
  125. mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
  126. dsb
  127. isb
  128. bx lr
  129. ArmReadScr
  130. mrc p15, 0, r0, c1, c1, 0
  131. bx lr
  132. ArmWriteScr
  133. mcr p15, 0, r0, c1, c1, 0
  134. bx lr
  135. ArmReadHVBar
  136. mrc p15, 4, r0, c12, c0, 0
  137. bx lr
  138. ArmWriteHVBar
  139. mcr p15, 4, r0, c12, c0, 0
  140. bx lr
  141. ArmReadMVBar
  142. mrc p15, 0, r0, c12, c0, 1
  143. bx lr
  144. ArmWriteMVBar
  145. mcr p15, 0, r0, c12, c0, 1
  146. bx lr
  147. ArmCallWFE
  148. wfe
  149. bx lr
  150. ArmCallSEV
  151. sev
  152. bx lr
  153. ArmReadSctlr
  154. mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)
  155. bx lr
  156. ArmReadCpuActlr
  157. mrc p15, 0, r0, c1, c0, 1
  158. bx lr
  159. ArmWriteCpuActlr
  160. mcr p15, 0, r0, c1, c0, 1
  161. dsb
  162. isb
  163. bx lr
  164. END