Arm11Support.asm 4.4 KB

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  1. //------------------------------------------------------------------------------
  2. //
  3. // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  4. //
  5. // This program and the accompanying materials
  6. // are licensed and made available under the terms and conditions of the BSD License
  7. // which accompanies this distribution. The full text of the license may be found at
  8. // http://opensource.org/licenses/bsd-license.php
  9. //
  10. // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12. //
  13. //------------------------------------------------------------------------------
  14. EXPORT ArmCleanInvalidateDataCache
  15. EXPORT ArmCleanDataCache
  16. EXPORT ArmInvalidateDataCache
  17. EXPORT ArmInvalidateInstructionCache
  18. EXPORT ArmInvalidateDataCacheEntryByMVA
  19. EXPORT ArmCleanDataCacheEntryByMVA
  20. EXPORT ArmCleanInvalidateDataCacheEntryByMVA
  21. EXPORT ArmEnableMmu
  22. EXPORT ArmDisableMmu
  23. EXPORT ArmMmuEnabled
  24. EXPORT ArmEnableDataCache
  25. EXPORT ArmDisableDataCache
  26. EXPORT ArmEnableInstructionCache
  27. EXPORT ArmDisableInstructionCache
  28. EXPORT ArmEnableBranchPrediction
  29. EXPORT ArmDisableBranchPrediction
  30. EXPORT ArmDataMemoryBarrier
  31. EXPORT ArmDataSyncronizationBarrier
  32. EXPORT ArmInstructionSynchronizationBarrier
  33. DC_ON EQU ( 0x1:SHL:2 )
  34. IC_ON EQU ( 0x1:SHL:12 )
  35. XP_ON EQU ( 0x1:SHL:23 )
  36. AREA ArmCacheLib, CODE, READONLY
  37. PRESERVE8
  38. ArmInvalidateDataCacheEntryByMVA
  39. mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
  40. bx lr
  41. ArmCleanDataCacheEntryByMVA
  42. mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
  43. bx lr
  44. ArmCleanInvalidateDataCacheEntryByMVA
  45. mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
  46. bx lr
  47. ArmCleanDataCache
  48. mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
  49. bx lr
  50. ArmCleanInvalidateDataCache
  51. mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
  52. bx lr
  53. ArmInvalidateDataCache
  54. mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
  55. bx lr
  56. ArmInvalidateInstructionCache
  57. mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
  58. mov R0,#0
  59. mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
  60. bx lr
  61. ArmEnableMmu
  62. mrc p15,0,R0,c1,c0,0
  63. orr R0,R0,#1
  64. mcr p15,0,R0,c1,c0,0
  65. bx LR
  66. ArmMmuEnabled
  67. mrc p15,0,R0,c1,c0,0
  68. and R0,R0,#1
  69. bx LR
  70. ArmDisableMmu
  71. mrc p15,0,R0,c1,c0,0
  72. bic R0,R0,#1
  73. mcr p15,0,R0,c1,c0,0
  74. mov R0,#0
  75. mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
  76. mov R0,#0
  77. mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
  78. bx LR
  79. ArmEnableDataCache
  80. LDR R1,=DC_ON
  81. MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
  82. ORR R0,R0,R1 ;Set C bit
  83. MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
  84. BX LR
  85. ArmDisableDataCache
  86. LDR R1,=DC_ON
  87. MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
  88. BIC R0,R0,R1 ;Clear C bit
  89. MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
  90. BX LR
  91. ArmEnableInstructionCache
  92. LDR R1,=IC_ON
  93. MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
  94. ORR R0,R0,R1 ;Set I bit
  95. MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
  96. BX LR
  97. ArmDisableInstructionCache
  98. LDR R1,=IC_ON
  99. MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
  100. BIC R0,R0,R1 ;Clear I bit.
  101. MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
  102. BX LR
  103. ArmEnableBranchPrediction
  104. mrc p15, 0, r0, c1, c0, 0
  105. orr r0, r0, #0x00000800
  106. mcr p15, 0, r0, c1, c0, 0
  107. bx LR
  108. ArmDisableBranchPrediction
  109. mrc p15, 0, r0, c1, c0, 0
  110. bic r0, r0, #0x00000800
  111. mcr p15, 0, r0, c1, c0, 0
  112. bx LR
  113. ASM_PFX(ArmDataMemoryBarrier):
  114. mov R0, #0
  115. mcr P15, #0, R0, C7, C10, #5
  116. bx LR
  117. ASM_PFX(ArmDataSyncronizationBarrier):
  118. mov R0, #0
  119. mcr P15, #0, R0, C7, C10, #4
  120. bx LR
  121. ASM_PFX(ArmInstructionSynchronizationBarrier):
  122. MOV R0, #0
  123. MCR P15, #0, R0, C7, C5, #4
  124. bx LR
  125. END