Arm11Support.S 7.9 KB

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  1. #------------------------------------------------------------------------------
  2. #
  3. # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  4. # Copyright (c) 2011, ARM Limited. All rights reserved.
  5. #
  6. # This program and the accompanying materials
  7. # are licensed and made available under the terms and conditions of the BSD License
  8. # which accompanies this distribution. The full text of the license may be found at
  9. # http://opensource.org/licenses/bsd-license.php
  10. #
  11. # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12. # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13. #
  14. #------------------------------------------------------------------------------
  15. #include <AsmMacroIoLib.h>
  16. .text
  17. .align 2
  18. GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
  19. GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
  20. GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
  21. GCC_ASM_EXPORT(ArmCleanDataCache)
  22. GCC_ASM_EXPORT(ArmInvalidateDataCache)
  23. GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
  24. GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
  25. GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
  26. GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
  27. GCC_ASM_EXPORT(ArmEnableMmu)
  28. GCC_ASM_EXPORT(ArmDisableMmu)
  29. GCC_ASM_EXPORT(ArmMmuEnabled)
  30. GCC_ASM_EXPORT(ArmEnableDataCache)
  31. GCC_ASM_EXPORT(ArmDisableDataCache)
  32. GCC_ASM_EXPORT(ArmEnableInstructionCache)
  33. GCC_ASM_EXPORT(ArmDisableInstructionCache)
  34. GCC_ASM_EXPORT(ArmEnableBranchPrediction)
  35. GCC_ASM_EXPORT(ArmDisableBranchPrediction)
  36. GCC_ASM_EXPORT(ArmDataMemoryBarrier)
  37. GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
  38. GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
  39. GCC_ASM_EXPORT(ArmSetLowVectors)
  40. GCC_ASM_EXPORT(ArmSetHighVectors)
  41. GCC_ASM_EXPORT(ArmIsMpCore)
  42. GCC_ASM_EXPORT(ArmCallWFI)
  43. GCC_ASM_EXPORT(ArmReadMpidr)
  44. GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
  45. GCC_ASM_EXPORT(ArmEnableFiq)
  46. GCC_ASM_EXPORT(ArmDisableFiq)
  47. GCC_ASM_EXPORT(ArmEnableInterrupts)
  48. GCC_ASM_EXPORT(ArmDisableInterrupts)
  49. GCC_ASM_EXPORT (ArmEnableVFP)
  50. Arm11PartNumberMask: .word 0xFFF0
  51. Arm11PartNumber: .word 0xB020
  52. .set DC_ON, (0x1<<2)
  53. .set IC_ON, (0x1<<12)
  54. .set XP_ON, (0x1<<23)
  55. .set CTRL_M_BIT, (1 << 0)
  56. .set CTRL_C_BIT, (1 << 2)
  57. .set CTRL_I_BIT, (1 << 12)
  58. ASM_PFX(ArmDisableCachesAndMmu):
  59. mrc p15, 0, r0, c1, c0, 0 @ Get control register
  60. bic r0, r0, #CTRL_M_BIT @ Disable MMU
  61. bic r0, r0, #CTRL_C_BIT @ Disable D Cache
  62. bic r0, r0, #CTRL_I_BIT @ Disable I Cache
  63. mcr p15, 0, r0, c1, c0, 0 @ Write control register
  64. bx LR
  65. ASM_PFX(ArmInvalidateInstructionAndDataTlb):
  66. mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
  67. bx lr
  68. ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  69. mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
  70. bx lr
  71. ASM_PFX(ArmCleanDataCacheEntryByMVA):
  72. mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
  73. bx lr
  74. ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  75. mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
  76. bx lr
  77. ASM_PFX(ArmCleanDataCache):
  78. mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
  79. bx lr
  80. ASM_PFX(ArmCleanInvalidateDataCache):
  81. mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
  82. bx lr
  83. ASM_PFX(ArmInvalidateDataCache):
  84. mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
  85. bx lr
  86. ASM_PFX(ArmInvalidateInstructionCache):
  87. mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
  88. mov R0,#0
  89. mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
  90. bx lr
  91. ASM_PFX(ArmEnableMmu):
  92. mrc p15,0,R0,c1,c0,0
  93. orr R0,R0,#1
  94. mcr p15,0,R0,c1,c0,0
  95. bx LR
  96. ASM_PFX(ArmMmuEnabled):
  97. mrc p15,0,R0,c1,c0,0
  98. and R0,R0,#1
  99. bx LR
  100. ASM_PFX(ArmDisableMmu):
  101. mrc p15,0,R0,c1,c0,0
  102. bic R0,R0,#1
  103. mcr p15,0,R0,c1,c0,0
  104. mov R0,#0
  105. mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
  106. mov R0,#0
  107. mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
  108. bx LR
  109. ASM_PFX(ArmEnableDataCache):
  110. LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
  111. mrc p15,0,R0,c1,c0,0 @Read control register configuration data
  112. orr R0,R0,R1 @Set C bit
  113. mcr p15,0,r0,c1,c0,0 @Write control register configuration data
  114. bx LR
  115. ASM_PFX(ArmDisableDataCache):
  116. LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
  117. mrc p15,0,R0,c1,c0,0 @Read control register configuration data
  118. bic R0,R0,R1 @Clear C bit
  119. mcr p15,0,r0,c1,c0,0 @Write control register configuration data
  120. bx LR
  121. ASM_PFX(ArmEnableInstructionCache):
  122. ldr R1,=IC_ON
  123. mrc p15,0,R0,c1,c0,0 @Read control register configuration data
  124. orr R0,R0,R1 @Set I bit
  125. mcr p15,0,r0,c1,c0,0 @Write control register configuration data
  126. bx LR
  127. ASM_PFX(ArmDisableInstructionCache):
  128. ldr R1,=IC_ON
  129. mrc p15,0,R0,c1,c0,0 @Read control register configuration data
  130. bic R0,R0,R1 @Clear I bit.
  131. mcr p15,0,r0,c1,c0,0 @Write control register configuration data
  132. bx LR
  133. ASM_PFX(ArmEnableBranchPrediction):
  134. mrc p15, 0, r0, c1, c0, 0
  135. orr r0, r0, #0x00000800
  136. mcr p15, 0, r0, c1, c0, 0
  137. bx LR
  138. ASM_PFX(ArmDisableBranchPrediction):
  139. mrc p15, 0, r0, c1, c0, 0
  140. bic r0, r0, #0x00000800
  141. mcr p15, 0, r0, c1, c0, 0
  142. bx LR
  143. ASM_PFX(ArmDataMemoryBarrier):
  144. mov R0, #0
  145. mcr P15, #0, R0, C7, C10, #5
  146. bx LR
  147. ASM_PFX(ArmDataSyncronizationBarrier):
  148. mov R0, #0
  149. mcr P15, #0, R0, C7, C10, #4
  150. bx LR
  151. ASM_PFX(ArmInstructionSynchronizationBarrier):
  152. mov R0, #0
  153. mcr P15, #0, R0, C7, C5, #4
  154. bx LR
  155. ASM_PFX(ArmSetLowVectors):
  156. mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
  157. bic r0, r0, #0x00002000 @ clear V bit
  158. mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
  159. bx LR
  160. ASM_PFX(ArmSetHighVectors):
  161. mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
  162. orr r0, r0, #0x00002000 @ clear V bit
  163. mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
  164. bx LR
  165. ASM_PFX(ArmIsMpCore):
  166. push { r1 }
  167. mrc p15, 0, r0, c0, c0, 0
  168. # Extract Part Number to check it is an ARM11MP core (0xB02)
  169. LoadConstantToReg (Arm11PartNumberMask, r1)
  170. and r0, r0, r1
  171. LoadConstantToReg (Arm11PartNumber, r1)
  172. cmp r0, r1
  173. movne r0, #0
  174. pop { r1 }
  175. bx lr
  176. ASM_PFX(ArmCallWFI):
  177. wfi
  178. bx lr
  179. ASM_PFX(ArmReadMpidr):
  180. mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
  181. bx lr
  182. ASM_PFX(ArmEnableFiq):
  183. mrs R0,CPSR
  184. bic R0,R0,#0x40 @Enable FIQ interrupts
  185. msr CPSR_c,R0
  186. bx LR
  187. ASM_PFX(ArmDisableFiq):
  188. mrs R0,CPSR
  189. orr R1,R0,#0x40 @Disable FIQ interrupts
  190. msr CPSR_c,R1
  191. tst R0,#0x80
  192. moveq R0,#1
  193. movne R0,#0
  194. bx LR
  195. ASM_PFX(ArmEnableInterrupts):
  196. mrs R0,CPSR
  197. bic R0,R0,#0x80 @Enable IRQ interrupts
  198. msr CPSR_c,R0
  199. bx LR
  200. ASM_PFX(ArmDisableInterrupts):
  201. mrs R0,CPSR
  202. orr R1,R0,#0x80 @Disable IRQ interrupts
  203. msr CPSR_c,R1
  204. tst R0,#0x80
  205. moveq R0,#1
  206. movne R0,#0
  207. bx LR
  208. ASM_PFX(ArmEnableVFP):
  209. # Read CPACR (Coprocessor Access Control Register)
  210. mrc p15, 0, r0, c1, c0, 2
  211. # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
  212. orr r0, r0, #0x00f00000
  213. # Write back CPACR (Coprocessor Access Control Register)
  214. mcr p15, 0, r0, c1, c0, 2
  215. # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
  216. mov r0, #0x40000000
  217. #TODO: Fixme - need compilation flag
  218. #fmxr FPEXC, r0
  219. bx lr
  220. ASM_FUNCTION_REMOVE_IF_UNREFERENCED