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@@ -341,7 +341,7 @@ The following options need to be configured:
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CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
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Physical address from the view of DDR controllers. It is the
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- same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
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+ same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
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it could be different for ARM SoCs.
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- MIPS CPU options:
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@@ -352,7 +352,7 @@ The following options need to be configured:
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be swapped if a flash programmer is used.
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- ARM options:
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- CONFIG_SYS_EXCEPTION_VECTORS_HIGH
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+ CFG_SYS_EXCEPTION_VECTORS_HIGH
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Select high exception vectors of the ARM core, e.g., do not
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clear the V bit of the c1 register of CP15.
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@@ -415,7 +415,7 @@ The following options need to be configured:
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the defaults discussed just above.
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- Cache Configuration for ARM:
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- CONFIG_SYS_PL310_BASE - Physical base address of PL310
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+ CFG_SYS_PL310_BASE - Physical base address of PL310
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controller register space
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- Serial Ports:
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@@ -485,7 +485,7 @@ The following options need to be configured:
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- GPIO Support:
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CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
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- The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
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+ The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of
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chip-ngpio pairs that tell the PCA953X driver the number of
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pins supported by a particular chip.
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@@ -927,21 +927,21 @@ The following options need to be configured:
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CONFIG_SYS_I2C_DIRECT_BUS
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define this, if you don't use i2c muxes on your hardware.
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- if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
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+ if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
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omit this define.
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- CONFIG_SYS_I2C_MAX_HOPS
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+ CFG_SYS_I2C_MAX_HOPS
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define how many muxes are maximal consecutively connected
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on one i2c bus. If you not use i2c muxes, omit this
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define.
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- CONFIG_SYS_I2C_BUSES
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+ CFG_SYS_I2C_BUSES
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hold a list of buses you want to use, only used if
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CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
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- a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
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+ a board with CFG_SYS_I2C_MAX_HOPS = 1 and
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CFG_SYS_NUM_I2C_BUSES = 9:
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- CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
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+ CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
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{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
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{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
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{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
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@@ -1044,7 +1044,7 @@ The following options need to be configured:
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active. To switch to a different bus, use the 'i2c dev' command.
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Note that bus numbering is zero-based.
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- CONFIG_SYS_I2C_NOPROBES
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+ CFG_SYS_I2C_NOPROBES
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This option specifies a list of I2C devices that will be skipped
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when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS
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@@ -1053,16 +1053,16 @@ The following options need to be configured:
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e.g.
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#undef CONFIG_I2C_MULTI_BUS
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- #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
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+ #define CFG_SYS_I2C_NOPROBES {0x50,0x68}
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will skip addresses 0x50 and 0x68 on a board with one I2C bus
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#define CONFIG_I2C_MULTI_BUS
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- #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
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+ #define CFG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
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will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
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- CONFIG_SYS_RTC_BUS_NUM
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+ CFG_SYS_RTC_BUS_NUM
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If defined, then this indicates the I2C bus number for the RTC.
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If not defined, then U-Boot assumes that RTC is on I2C bus 0.
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@@ -1120,19 +1120,19 @@ The following options need to be configured:
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configuration if the INIT_B line goes low (which
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indicated a CRC error).
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- CONFIG_SYS_FPGA_WAIT_INIT
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+ CFG_SYS_FPGA_WAIT_INIT
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Maximum time to wait for the INIT_B line to de-assert
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after PROB_B has been de-asserted during a Virtex II
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FPGA configuration sequence. The default time is 500
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ms.
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- CONFIG_SYS_FPGA_WAIT_BUSY
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+ CFG_SYS_FPGA_WAIT_BUSY
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Maximum time to wait for BUSY to de-assert during
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Virtex II FPGA configuration. The default is 5 ms.
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- CONFIG_SYS_FPGA_WAIT_CONFIG
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+ CFG_SYS_FPGA_WAIT_CONFIG
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Time to wait after FPGA configuration. The default is
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200 ms.
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@@ -1429,12 +1429,12 @@ Configuration Settings:
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- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
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prompt for user input.
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-- CONFIG_SYS_BAUDRATE_TABLE:
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+- CFG_SYS_BAUDRATE_TABLE:
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List of legal baudrate settings for this board.
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-- CONFIG_SYS_MEM_RESERVE_SECURE
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+- CFG_SYS_MEM_RESERVE_SECURE
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Only implemented for ARMv8 for now.
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- If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
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+ If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
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is substracted from total RAM and won't be reported to OS.
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This memory can be used as secure memory. A variable
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gd->arch.secure_ram is used to track the location. In systems
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@@ -1444,7 +1444,7 @@ Configuration Settings:
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- CFG_SYS_SDRAM_BASE:
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Physical start address of SDRAM. _Must_ be 0 here.
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-- CONFIG_SYS_FLASH_BASE:
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+- CFG_SYS_FLASH_BASE:
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Physical start address of Flash memory.
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- CONFIG_SYS_MALLOC_LEN:
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@@ -1468,16 +1468,16 @@ Configuration Settings:
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boards which do not use the full malloc in SPL (which is
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enabled with CONFIG_SYS_SPL_MALLOC).
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-- CONFIG_SYS_BOOTMAPSZ:
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+- CFG_SYS_BOOTMAPSZ:
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Maximum size of memory mapped by the startup code of
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the Linux kernel; all data that must be processed by
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the Linux kernel (bd_info, boot arguments, FDT blob if
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used) must be put below this limit, unless "bootm_low"
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environment variable is defined and non-zero. In such case
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all data for the Linux kernel must be between "bootm_low"
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- and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment
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+ and "bootm_low" + CFG_SYS_BOOTMAPSZ. The environment
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variable "bootm_mapsize" will override the value of
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- CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
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+ CFG_SYS_BOOTMAPSZ. If CFG_SYS_BOOTMAPSZ is undefined,
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then the value in "bootm_size" will be used instead.
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- CONFIG_SYS_BOOT_GET_CMDLINE:
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@@ -1638,11 +1638,11 @@ Low Level (hardware related) configuration options:
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Default (power-on reset) physical address of CCSR on Freescale
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PowerPC SOCs.
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-- CONFIG_SYS_CCSRBAR:
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+- CFG_SYS_CCSRBAR:
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Virtual address of CCSR. On a 32-bit build, this is typically
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the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
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-- CONFIG_SYS_CCSRBAR_PHYS:
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+- CFG_SYS_CCSRBAR_PHYS:
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Physical address of CCSR. CCSR can be relocated to a new
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physical address, if desired. In this case, this macro should
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be set to that address. Otherwise, it should be set to the
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@@ -1650,17 +1650,17 @@ Low Level (hardware related) configuration options:
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is typically relocated on 36-bit builds. It is recommended
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that this macro be defined via the _HIGH and _LOW macros:
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- #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
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- * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
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+ #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH
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+ * 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
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-- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
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- Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically
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+- CFG_SYS_CCSRBAR_PHYS_HIGH:
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+ Bits 33-36 of CFG_SYS_CCSRBAR_PHYS. This value is typically
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either 0 (32-bit build) or 0xF (36-bit build). This macro is
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used in assembly code, so it must not contain typecasts or
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integer size suffixes (e.g. "ULL").
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-- CONFIG_SYS_CCSRBAR_PHYS_LOW:
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- Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is
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+- CFG_SYS_CCSRBAR_PHYS_LOW:
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+ Lower 32-bits of CFG_SYS_CCSRBAR_PHYS. This macro is
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used in assembly code, so it must not contain typecasts or
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integer size suffixes (e.g. "ULL").
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@@ -1668,7 +1668,7 @@ Low Level (hardware related) configuration options:
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DO NOT CHANGE unless you know exactly what you're
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doing! (11-4) [MPC8xx systems only]
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-- CONFIG_SYS_INIT_RAM_ADDR:
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+- CFG_SYS_INIT_RAM_ADDR:
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Start address of memory area that can be used for
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initial data and stack; please note that this must be
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@@ -2737,7 +2737,7 @@ locked as (mis-) used as memory, etc.
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cause you grief during the initial boot! It is frequently not
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used.
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- CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
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+ CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
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with your processor/board/system design. The default value
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you will find in any recent u-boot distribution in
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walnut.h should work for you. I'd set it to a value larger
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