spl_boot.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. */
  5. #include <common.h>
  6. #include <config.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <asm/global_data.h>
  10. #include <asm/cache.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/clk.h>
  13. #include <asm/arch/dmc.h>
  14. #include <asm/arch/periph.h>
  15. #include <asm/arch/pinmux.h>
  16. #include <asm/arch/power.h>
  17. #include <asm/arch/spl.h>
  18. #include <asm/arch/spi.h>
  19. #include "common_setup.h"
  20. #include "clock_init.h"
  21. #ifdef CONFIG_ARCH_EXYNOS5
  22. #define SECURE_BL1_ONLY
  23. /* Secure FW size configuration */
  24. #ifdef SECURE_BL1_ONLY
  25. #define SEC_FW_SIZE (8 << 10) /* 8KB */
  26. #else
  27. #define SEC_FW_SIZE 0
  28. #endif
  29. /* Configuration of BL1, BL2, ENV Blocks on mmc */
  30. #define RES_BLOCK_SIZE (512)
  31. #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
  32. #define BL2_SIZE (512UL << 10UL) /* 512 KB */
  33. #define BL1_OFFSET (RES_BLOCK_SIZE + SEC_FW_SIZE)
  34. #define BL2_OFFSET (BL1_OFFSET + BL1_SIZE)
  35. /* U-Boot copy size from boot Media to DRAM.*/
  36. #define BL2_START_OFFSET (BL2_OFFSET/512)
  37. #define BL2_SIZE_BLOC_COUNT (BL2_SIZE/512)
  38. #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
  39. #define SPI_FLASH_UBOOT_POS (SEC_FW_SIZE + BL1_SIZE)
  40. #elif defined(CONFIG_ARCH_EXYNOS4)
  41. #define COPY_BL2_SIZE 0x80000
  42. #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
  43. #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
  44. #endif
  45. DECLARE_GLOBAL_DATA_PTR;
  46. /* Index into irom ptr table */
  47. enum index {
  48. MMC_INDEX,
  49. EMMC44_INDEX,
  50. EMMC44_END_INDEX,
  51. SPI_INDEX,
  52. USB_INDEX,
  53. };
  54. /* IROM Function Pointers Table */
  55. u32 irom_ptr_table[] = {
  56. [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
  57. [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
  58. [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
  59. -EMMC4.4 end boot operation */
  60. [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
  61. [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
  62. };
  63. void *get_irom_func(int index)
  64. {
  65. return (void *)*(u32 *)irom_ptr_table[index];
  66. }
  67. #ifdef CONFIG_USB_BOOTING
  68. /*
  69. * Set/clear program flow prediction and return the previous state.
  70. */
  71. static int config_branch_prediction(int set_cr_z)
  72. {
  73. unsigned int cr;
  74. /* System Control Register: 11th bit Z Branch prediction enable */
  75. cr = get_cr();
  76. set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
  77. return cr & CR_Z;
  78. }
  79. #endif
  80. #ifdef CONFIG_SPI_BOOTING
  81. static void spi_rx_tx(struct exynos_spi *regs, int todo,
  82. void *dinp, void const *doutp, int i)
  83. {
  84. uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
  85. int rx_lvl, tx_lvl;
  86. uint out_bytes, in_bytes;
  87. out_bytes = todo;
  88. in_bytes = todo;
  89. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  90. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  91. writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  92. while (in_bytes) {
  93. uint32_t spi_sts;
  94. int temp;
  95. spi_sts = readl(&regs->spi_sts);
  96. rx_lvl = ((spi_sts >> 15) & 0x7f);
  97. tx_lvl = ((spi_sts >> 6) & 0x7f);
  98. while (tx_lvl < 32 && out_bytes) {
  99. temp = 0xffffffff;
  100. writel(temp, &regs->tx_data);
  101. out_bytes -= 4;
  102. tx_lvl += 4;
  103. }
  104. while (rx_lvl >= 4 && in_bytes) {
  105. temp = readl(&regs->rx_data);
  106. if (rxp)
  107. *rxp++ = temp;
  108. in_bytes -= 4;
  109. rx_lvl -= 4;
  110. }
  111. }
  112. }
  113. /*
  114. * Copy uboot from spi flash to RAM
  115. *
  116. * @parma uboot_size size of u-boot to copy
  117. * @param uboot_addr address in u-boot to copy
  118. */
  119. static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
  120. {
  121. int upto, todo;
  122. int i, timeout = 100;
  123. struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE;
  124. set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
  125. /* set the spi1 GPIO */
  126. exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
  127. /* set pktcnt and enable it */
  128. writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  129. /* set FB_CLK_SEL */
  130. writel(SPI_FB_DELAY_180, &regs->fb_clk);
  131. /* set CH_WIDTH and BUS_WIDTH as word */
  132. setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  133. SPI_MODE_BUS_WIDTH_WORD);
  134. clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
  135. /* clear rx and tx channel if set priveously */
  136. clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  137. setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
  138. SPI_RX_BYTE_SWAP |
  139. SPI_RX_HWORD_SWAP);
  140. /* do a soft reset */
  141. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  142. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  143. /* now set rx and tx channel ON */
  144. setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
  145. clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
  146. /* Send read instruction (0x3h) followed by a 24 bit addr */
  147. writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
  148. /* waiting for TX done */
  149. while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
  150. if (!timeout) {
  151. debug("SPI TIMEOUT\n");
  152. break;
  153. }
  154. timeout--;
  155. }
  156. for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
  157. todo = min(uboot_size - upto, (unsigned int)(1 << 15));
  158. spi_rx_tx(regs, todo, (void *)(uboot_addr),
  159. (void *)(SPI_FLASH_UBOOT_POS), i);
  160. }
  161. setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
  162. /*
  163. * Let put controller mode to BYTE as
  164. * SPI driver does not support WORD mode yet
  165. */
  166. clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  167. SPI_MODE_BUS_WIDTH_WORD);
  168. writel(0, &regs->swap_cfg);
  169. /*
  170. * Flush spi tx, rx fifos and reset the SPI controller
  171. * and clear rx/tx channel
  172. */
  173. clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
  174. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  175. clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
  176. }
  177. #endif
  178. /*
  179. * Copy U-Boot from mmc to RAM:
  180. * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
  181. * Pointer to API (Data transfer from mmc to ram)
  182. */
  183. void copy_uboot_to_ram(void)
  184. {
  185. unsigned int bootmode = BOOT_MODE_OM;
  186. u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
  187. u32 offset = 0, size = 0;
  188. #ifdef CONFIG_SPI_BOOTING
  189. struct spl_machine_param *param = spl_get_machine_params();
  190. #endif
  191. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  192. u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
  193. void (*end_bootop_from_emmc)(void);
  194. #endif
  195. #ifdef CONFIG_USB_BOOTING
  196. int is_cr_z_set;
  197. unsigned int sec_boot_check;
  198. /*
  199. * Note that older hardware (before Exynos5800) does not expect any
  200. * arguments, but it does not hurt to pass them, so a common function
  201. * prototype is used.
  202. */
  203. u32 (*usb_copy)(u32 num_of_block, u32 *dst);
  204. /* Read iRAM location to check for secondary USB boot mode */
  205. sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
  206. if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
  207. bootmode = BOOT_MODE_USB;
  208. #endif
  209. if (bootmode == BOOT_MODE_OM)
  210. bootmode = get_boot_mode();
  211. switch (bootmode) {
  212. #ifdef CONFIG_SPI_BOOTING
  213. case BOOT_MODE_SERIAL:
  214. /* Customised function to copy u-boot from SF */
  215. exynos_spi_copy(param->uboot_size, CONFIG_TEXT_BASE);
  216. break;
  217. #endif
  218. case BOOT_MODE_SD:
  219. offset = BL2_START_OFFSET;
  220. size = BL2_SIZE_BLOC_COUNT;
  221. copy_bl2 = get_irom_func(MMC_INDEX);
  222. break;
  223. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  224. case BOOT_MODE_EMMC:
  225. /* Set the FSYS1 clock divisor value for EMMC boot */
  226. emmc_boot_clk_div_set();
  227. copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
  228. end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
  229. copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_TEXT_BASE);
  230. end_bootop_from_emmc();
  231. break;
  232. #endif
  233. #ifdef CONFIG_USB_BOOTING
  234. case BOOT_MODE_USB:
  235. /*
  236. * iROM needs program flow prediction to be disabled
  237. * before copy from USB device to RAM
  238. */
  239. is_cr_z_set = config_branch_prediction(0);
  240. usb_copy = get_irom_func(USB_INDEX);
  241. usb_copy(0, (u32 *)CONFIG_TEXT_BASE);
  242. config_branch_prediction(is_cr_z_set);
  243. break;
  244. #endif
  245. default:
  246. break;
  247. }
  248. if (copy_bl2)
  249. copy_bl2(offset, size, CONFIG_TEXT_BASE);
  250. }
  251. void memzero(void *s, size_t n)
  252. {
  253. char *ptr = s;
  254. size_t i;
  255. for (i = 0; i < n; i++)
  256. *ptr++ = '\0';
  257. }
  258. /**
  259. * Set up the U-Boot global_data pointer
  260. *
  261. * This sets the address of the global data, and sets up basic values.
  262. *
  263. * @param gdp Value to give to gd
  264. */
  265. static void setup_global_data(gd_t *gdp)
  266. {
  267. set_gd(gdp);
  268. memzero((void *)gd, sizeof(gd_t));
  269. gd->flags |= GD_FLG_RELOC;
  270. gd->baudrate = CONFIG_BAUDRATE;
  271. gd->have_console = 1;
  272. }
  273. void board_init_f(unsigned long bootflag)
  274. {
  275. __aligned(8) gd_t local_gd;
  276. __attribute__((noreturn)) void (*uboot)(void);
  277. setup_global_data(&local_gd);
  278. if (do_lowlevel_init())
  279. power_exit_wakeup();
  280. copy_uboot_to_ram();
  281. /* Jump to U-Boot image */
  282. uboot = (void *)CONFIG_TEXT_BASE;
  283. (*uboot)();
  284. /* Never returns Here */
  285. }
  286. /* Place Holders */
  287. void board_init_r(gd_t *id, ulong dest_addr)
  288. {
  289. /* Function attribute is no-return */
  290. /* This Function never executes */
  291. while (1)
  292. ;
  293. }