README.lsch3 17 KB

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  1. #
  2. # Copyright 2014-2015 Freescale Semiconductor
  3. #
  4. # SPDX-License-Identifier: GPL-2.0+
  5. #
  6. Freescale LayerScape with Chassis Generation 3
  7. This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
  8. for example LS2080A.
  9. DDR Layout
  10. ============
  11. Entire DDR region splits into two regions.
  12. - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
  13. - Region 2 is at 0x80_8000_0000 to the top of total memory,
  14. for example 16GB, 0x83_ffff_ffff.
  15. All DDR memory is marked as cache-enabled.
  16. When MC and Debug server is enabled, they carve 512MB away from the high
  17. end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
  18. with MC and Debug server enabled. Linux only sees 15.5GB.
  19. The reserved 512MB layout looks like
  20. +---------------+ <-- top/end of memory
  21. | 256MB | debug server
  22. +---------------+
  23. | 256MB | MC
  24. +---------------+
  25. | ... |
  26. MC requires the memory to be aligned with 512MB, so even debug server is
  27. not enabled, 512MB is reserved, not 256MB.
  28. Flash Layout
  29. ============
  30. (1) A typical layout of various images (including Linux and other firmware images)
  31. is shown below considering a 32MB NOR flash device present on most
  32. pre-silicon platforms (simulator and emulator):
  33. -------------------------
  34. | FIT Image |
  35. | (linux + DTB + RFS) |
  36. ------------------------- ----> 0x0120_0000
  37. | Debug Server FW |
  38. ------------------------- ----> 0x00C0_0000
  39. | AIOP FW |
  40. ------------------------- ----> 0x0070_0000
  41. | MC FW |
  42. ------------------------- ----> 0x006C_0000
  43. | MC DPL Blob |
  44. ------------------------- ----> 0x0020_0000
  45. | BootLoader + Env|
  46. ------------------------- ----> 0x0000_1000
  47. | PBI |
  48. ------------------------- ----> 0x0000_0080
  49. | RCW |
  50. ------------------------- ----> 0x0000_0000
  51. 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
  52. (2) A typical layout of various images (including Linux and other firmware images)
  53. is shown below considering a 128MB NOR flash device present on QDS and RDB
  54. boards:
  55. ----------------------------------------- ----> 0x5_8800_0000 ---
  56. | .. Unused .. (7M) | |
  57. ----------------------------------------- ----> 0x5_8790_0000 |
  58. | FIT Image (linux + DTB + RFS) (40M) | |
  59. ----------------------------------------- ----> 0x5_8510_0000 |
  60. | PHY firmware (2M) | |
  61. ----------------------------------------- ----> 0x5_84F0_0000 | 64K
  62. | Debug Server FW (2M) | | Alt
  63. ----------------------------------------- ----> 0x5_84D0_0000 | Bank
  64. | AIOP FW (4M) | |
  65. ----------------------------------------- ----> 0x5_8490_0000 (vbank4)
  66. | MC DPC Blob (1M) | |
  67. ----------------------------------------- ----> 0x5_8480_0000 |
  68. | MC DPL Blob (1M) | |
  69. ----------------------------------------- ----> 0x5_8470_0000 |
  70. | MC FW (4M) | |
  71. ----------------------------------------- ----> 0x5_8430_0000 |
  72. | BootLoader Environment (1M) | |
  73. ----------------------------------------- ----> 0x5_8420_0000 |
  74. | BootLoader (1M) | |
  75. ----------------------------------------- ----> 0x5_8410_0000 |
  76. | RCW and PBI (1M) | |
  77. ----------------------------------------- ----> 0x5_8400_0000 ---
  78. | .. Unused .. (7M) | |
  79. ----------------------------------------- ----> 0x5_8390_0000 |
  80. | FIT Image (linux + DTB + RFS) (40M) | |
  81. ----------------------------------------- ----> 0x5_8110_0000 |
  82. | PHY firmware (2M) | |
  83. ----------------------------------------- ----> 0x5_80F0_0000 | 64K
  84. | Debug Server FW (2M) | | Bank
  85. ----------------------------------------- ----> 0x5_80D0_0000 |
  86. | AIOP FW (4M) | |
  87. ----------------------------------------- ----> 0x5_8090_0000 (vbank0)
  88. | MC DPC Blob (1M) | |
  89. ----------------------------------------- ----> 0x5_8080_0000 |
  90. | MC DPL Blob (1M) | |
  91. ----------------------------------------- ----> 0x5_8070_0000 |
  92. | MC FW (4M) | |
  93. ----------------------------------------- ----> 0x5_8030_0000 |
  94. | BootLoader Environment (1M) | |
  95. ----------------------------------------- ----> 0x5_8020_0000 |
  96. | BootLoader (1M) | |
  97. ----------------------------------------- ----> 0x5_8010_0000 |
  98. | RCW and PBI (1M) | |
  99. ----------------------------------------- ----> 0x5_8000_0000 ---
  100. 128-MB NOR flash layout for QDS and RDB boards
  101. Environment Variables
  102. =====================
  103. mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
  104. the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
  105. mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value
  106. CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
  107. mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
  108. from the location where it is stored(NOR, NAND, SD, SATA, USB)during
  109. u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
  110. will be null and MC will not be booted and DPL will not be applied
  111. during U-boot booting.However the MC, DPC and DPL can be applied from
  112. console independently.
  113. The variable needs to be set from the console once and then on
  114. rebooting the parameters set in the variable will automatically be
  115. executed. The commmand is demostrated taking an example of mc boot
  116. using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash:
  117. cp.b 0xa0000000 0x580300000 $filesize
  118. cp.b 0x80000000 0x580800000 $filesize
  119. cp.b 0x90000000 0x580700000 $filesize
  120. setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000'
  121. If only linux is to be booted then the mcinitcmd environment should be set as
  122. setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
  123. Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where
  124. MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000
  125. and 0x580700000 are addresses in NOR where these are copied. It is to be
  126. noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
  127. can be replaced with the addresses of DDR to
  128. which these will be copied in case of these binaries being stored in other
  129. devices like SATA, USB, NAND, SD etc.
  130. Booting from NAND
  131. -------------------
  132. Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
  133. The difference between NAND boot RCW image and NOR boot image is the PBI
  134. command sequence. Below is one example for PBI commands for LS2085AQDS which
  135. uses NAND device with 2KB/page, block size 128KB.
  136. 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
  137. 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
  138. The above two commands set bootloc register to 0x00000000_1800a000 where
  139. the u-boot code will be running in OCRAM.
  140. 3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
  141. BLOCK_SIZE=0x00014000
  142. This command copies u-boot image from NAND device into OCRAM. The values need
  143. to adjust accordingly.
  144. SRC should match the cfg_rcw_src, the reset config pins. It depends
  145. on the NAND device. See reference manual for cfg_rcw_src.
  146. SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In
  147. the example above, 128KB. For easy maintenance, we put it at
  148. the beginning of next block from RCW.
  149. DEST_ADDR is fixed at 0x1800a000, matching bootloc set above.
  150. BLOCK_SIZE is the size to be copied by PBI.
  151. RCW image should be written to the beginning of NAND device. Example of using
  152. u-boot command
  153. nand write <rcw image in memory> 0 <size of rcw image>
  154. To form the NAND image, build u-boot with NAND config, for example,
  155. ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
  156. The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
  157. nand write <u-boot image in memory> 200000 <size of u-boot image>
  158. With these two images in NAND device, the board can boot from NAND.
  159. Another example for LS2085ARDB boards,
  160. 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
  161. 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
  162. 3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
  163. BLOCK_SIZE=0x00014000
  164. nand write <rcw image in memory> 0 <size of rcw image>
  165. nand write <u-boot image in memory> 80000 <size of u-boot image>
  166. Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
  167. to match board NAND device with 4KB/page, block size 512KB.
  168. Note, LS2088A and LS1088A don't support booting from NAND.
  169. Booting from SD/eMMC
  170. -------------------
  171. Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin.
  172. The difference between SD boot RCW image and QSPI-NOR boot image is the
  173. PBI command sequence. Below is one example for PBI commands for RDB
  174. and QDS which uses SD device with block size 512. Block location can be
  175. calculated by dividing offset with block size.
  176. 1) Block Copy: SRC=0x0040, SRC_ADDR=0x00100000, DEST_ADDR=0x1800a000,
  177. BLOCK_SIZE=0x00016000
  178. This command copies u-boot image from SD device into OCRAM. The values
  179. need to adjust accordingly for SD/eMMC
  180. SRC should match the cfg_rcw_src, the reset config pins.
  181. The value for source(SRC) can be 0x0040 or 0x0041
  182. depending upon SD or eMMC.
  183. SRC_ADDR is the offset of u-boot-with-spl.bin image in SD device.
  184. In the example above, 1MB. This is same as QSPI-NOR.
  185. DEST_ADDR is configured at 0x1800a000, matching bootloc set above.
  186. BLOCK_SIZE is the size to be copied by PBI.
  187. 2) CCSR 4-byte write to 0x01e00404, data=0x00000000
  188. 3) CCSR 4-byte write to 0x01e00400, data=0x1800a000
  189. The above two commands set bootloc register to 0x00000000_1800a000 where
  190. the u-boot code will be running in OCRAM.
  191. RCW image should be written at 8th block of device(SD/eMMC). Example of
  192. using u-boot command
  193. mmc erase 0x8 0x10
  194. mmc write <rcw image in memory> 0x8 <size of rcw in block count typical value=10>
  195. To form the SD-Boot image, build u-boot with SD config, for example,
  196. ls1088ardb_sdcard_qspi_defconfig. The image needed is u-boot-with-spl.bin.
  197. The u-boot image should be written to match SRC_ADDR, in above example
  198. offset 0x100000 in other work it means block location 0x800
  199. mmc erase 0x800 0x1800
  200. mmc write <u-boot image in memory> 0x800 <size of u-boot image in block count>
  201. With these two images in SD/eMMC device, the board can boot from SD/eMMC.
  202. MMU Translation Tables
  203. ======================
  204. (1) Early MMU Tables:
  205. Level 0 Level 1 Level 2
  206. ------------------ ------------------ ------------------
  207. | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
  208. ------------------ ------------------ ------------------
  209. | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
  210. ------------------ | ------------------ ------------------
  211. | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
  212. ------------------ | ------------------ ------------------
  213. | | 0x00_c000_0000 | | 0x00_0060_0000 |
  214. | ------------------ ------------------
  215. | | 0x01_0000_0000 | | 0x00_0080_0000 |
  216. | ------------------ ------------------
  217. | ... ...
  218. | ------------------
  219. | | 0x05_8000_0000 | --|
  220. | ------------------ |
  221. | | 0x05_c000_0000 | |
  222. | ------------------ |
  223. | ... |
  224. | ------------------ | ------------------
  225. |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 |
  226. ------------------ ------------------
  227. | 0x80_4000_0000 | | 0x00_3020_0000 |
  228. ------------------ ------------------
  229. | 0x80_8000_0000 | | 0x00_3040_0000 |
  230. ------------------ ------------------
  231. | 0x80_c000_0000 | | 0x00_3060_0000 |
  232. ------------------ ------------------
  233. | 0x81_0000_0000 | | 0x00_3080_0000 |
  234. ------------------ ------------------
  235. ... ...
  236. (2) Final MMU Tables:
  237. Level 0 Level 1 Level 2
  238. ------------------ ------------------ ------------------
  239. | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
  240. ------------------ ------------------ ------------------
  241. | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
  242. ------------------ | ------------------ ------------------
  243. | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
  244. ------------------ | ------------------ ------------------
  245. | | 0x00_c000_0000 | | 0x00_0060_0000 |
  246. | ------------------ ------------------
  247. | | 0x01_0000_0000 | | 0x00_0080_0000 |
  248. | ------------------ ------------------
  249. | ... ...
  250. | ------------------
  251. | | 0x08_0000_0000 | --|
  252. | ------------------ |
  253. | | 0x08_4000_0000 | |
  254. | ------------------ |
  255. | ... |
  256. | ------------------ | ------------------
  257. |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 |
  258. ------------------ ------------------
  259. | 0x80_4000_0000 | | 0x08_0020_0000 |
  260. ------------------ ------------------
  261. | 0x80_8000_0000 | | 0x08_0040_0000 |
  262. ------------------ ------------------
  263. | 0x80_c000_0000 | | 0x08_0060_0000 |
  264. ------------------ ------------------
  265. | 0x81_0000_0000 | | 0x08_0080_0000 |
  266. ------------------ ------------------
  267. ... ...
  268. DPAA2 commands to manage Management Complex (MC)
  269. ------------------------------------------------
  270. DPAA2 commands has been introduced to manage Management Complex
  271. (MC). These commands are used to start mc, aiop and apply DPL
  272. from u-boot command prompt.
  273. Please note Management complex Firmware(MC), DPL and DPC are no
  274. more deployed during u-boot boot-sequence.
  275. Commands:
  276. a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
  277. b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
  278. c) fsl_mc start aiop <FW_addr> - Start AIOP
  279. How to use commands :-
  280. 1. Command sequence for u-boot ethernet:
  281. a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
  282. b) DPMAC net-devices are now available for use
  283. Example-
  284. Assumption: MC firmware, DPL and DPC dtb is already programmed
  285. on NOR flash.
  286. => fsl_mc start mc 580300000 580800000
  287. => setenv ethact DPMAC1@xgmii
  288. => ping $serverip
  289. 2. Command sequence for Linux boot:
  290. a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
  291. b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
  292. c) No DPMAC net-devices are available for use in u-boot
  293. d) boot Linux
  294. Example-
  295. Assumption: MC firmware, DPL and DPC dtb is already programmed
  296. on NOR flash.
  297. => fsl_mc start mc 580300000 580800000
  298. => setenv ethact DPMAC1@xgmii
  299. => tftp a0000000 kernel.itb
  300. => fsl_mc apply dpl 580700000
  301. => bootm a0000000
  302. 3. Command sequence for AIOP boot:
  303. a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
  304. b) fsl_mc start aiop <FW_addr> - Start AIOP
  305. c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
  306. d) No DPMAC net-devices are availabe for use in u-boot
  307. Please note actual AIOP start will happen during DPL parsing of
  308. Management complex
  309. Example-
  310. Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
  311. programmed on NOR flash.
  312. => fsl_mc start mc 580300000 580800000
  313. => fsl_mc start aiop 0x580900000
  314. => setenv ethact DPMAC1@xgmii
  315. => fsl_mc apply dpl 580700000
  316. Errata A009635
  317. ---------------
  318. If the core runs at higher than x3 speed of the platform, there is
  319. possiblity about sev instruction to getting missed by other cores.
  320. This is because of SoC Run Control block may not able to sample
  321. the EVENTI(Sev) signals.
  322. Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
  323. wake up A57 cores
  324. Errata workaround uses Env variable "a009635_interval_val". It uses decimal
  325. value.
  326. - Default value of env variable is platform clock (MHz)
  327. - User can modify default value by updating the env variable
  328. setenv a009635_interval_val 600; saveenv;
  329. It configure platform clock as 600 MHz
  330. - Env variable as 0 signifies no workaround