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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * armboot - Startup Code for ARM926EJS CPU-core
  4. *
  5. * Copyright (c) 2003 Texas Instruments
  6. *
  7. * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  8. *
  9. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  10. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  11. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  12. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  13. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  14. * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
  15. */
  16. #include <asm-offsets.h>
  17. #include <config.h>
  18. #include <common.h>
  19. #include <linux/linkage.h>
  20. /*
  21. *************************************************************************
  22. *
  23. * Startup Code (reset vector)
  24. *
  25. * do important init only if we don't start from memory!
  26. * setup Memory and board specific bits prior to relocation.
  27. * relocate armboot to ram
  28. * setup stack
  29. *
  30. *************************************************************************
  31. */
  32. .globl reset
  33. .globl save_boot_params_ret
  34. .type save_boot_params_ret,%function
  35. reset:
  36. /* Allow the board to save important registers */
  37. b save_boot_params
  38. save_boot_params_ret:
  39. /*
  40. * set the cpu to SVC32 mode
  41. */
  42. mrs r0,cpsr
  43. bic r0,r0,#0x1f
  44. orr r0,r0,#0xd3
  45. msr cpsr,r0
  46. /*
  47. * we do sys-critical inits only at reboot,
  48. * not when booting from ram!
  49. */
  50. #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
  51. bl cpu_init_crit
  52. #endif
  53. bl _main
  54. /*------------------------------------------------------------------------------*/
  55. .globl c_runtime_cpu_setup
  56. c_runtime_cpu_setup:
  57. bx lr
  58. /*
  59. *************************************************************************
  60. *
  61. * CPU_init_critical registers
  62. *
  63. * setup important registers
  64. * setup memory timing
  65. *
  66. *************************************************************************
  67. */
  68. #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
  69. cpu_init_crit:
  70. /*
  71. * flush D cache before disabling it
  72. */
  73. mov r0, #0
  74. flush_dcache:
  75. mrc p15, 0, r15, c7, c10, 3
  76. bne flush_dcache
  77. mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
  78. mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
  79. /*
  80. * disable MMU and D cache
  81. * enable I cache if SYS_ICACHE_OFF is not defined
  82. */
  83. mrc p15, 0, r0, c1, c0, 0
  84. bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
  85. bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
  86. #ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
  87. orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
  88. #else
  89. bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
  90. #endif
  91. orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
  92. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  93. orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
  94. #endif
  95. mcr p15, 0, r0, c1, c0, 0
  96. #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
  97. /*
  98. * Go setup Memory and board specific bits prior to relocation.
  99. */
  100. mov r4, lr /* perserve link reg across call */
  101. bl lowlevel_init /* go setup pll,mux,memory */
  102. mov lr, r4 /* restore link */
  103. #endif
  104. mov pc, lr /* back to my caller */
  105. #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
  106. /*************************************************************************
  107. *
  108. * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
  109. * __attribute__((weak));
  110. *
  111. * Stack pointer is not yet initialized at this moment
  112. * Don't save anything to stack even if compiled with -O0
  113. *
  114. *************************************************************************/
  115. WEAK(save_boot_params)
  116. b save_boot_params_ret /* back to my caller */
  117. ENDPROC(save_boot_params)