soc.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. *
  7. * Header file for the Marvell's Feroceon CPU core.
  8. */
  9. #ifndef _MVEBU_SOC_H
  10. #define _MVEBU_SOC_H
  11. #ifndef __ASSEMBLY__
  12. #include <linux/bitops.h>
  13. #endif
  14. #define SOC_MV78230_ID 0x7823
  15. #define SOC_MV78260_ID 0x7826
  16. #define SOC_MV78460_ID 0x7846
  17. #define SOC_88F6720_ID 0x6720
  18. #define SOC_88F6810_ID 0x6810
  19. #define SOC_88F6820_ID 0x6820
  20. #define SOC_88F6828_ID 0x6828
  21. #define SOC_98DX3236_ID 0xf410
  22. #define SOC_98DX3336_ID 0xf400
  23. #define SOC_98DX4251_ID 0xfc00
  24. /* A375 revisions */
  25. #define MV_88F67XX_A0_ID 0x3
  26. /* A38x revisions */
  27. #define MV_88F68XX_Z1_ID 0x0
  28. #define MV_88F68XX_A0_ID 0x4
  29. #define MV_88F68XX_B0_ID 0xa
  30. /* SOC specific definations */
  31. #define INTREG_BASE 0xd0000000
  32. #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
  33. #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700)
  34. /*
  35. * The SPL U-Boot version still runs with the default
  36. * address for the internal registers, configured by
  37. * the BootROM. Only the main U-Boot version uses the
  38. * new internal register base address, that also is
  39. * required for the Linux kernel.
  40. */
  41. #define SOC_REGS_PHY_BASE 0xd0000000
  42. #elif defined(CONFIG_ARMADA_8K)
  43. #define SOC_REGS_PHY_BASE 0xf0000000
  44. #else
  45. #define SOC_REGS_PHY_BASE 0xf1000000
  46. #endif
  47. #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
  48. #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
  49. #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
  50. #define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
  51. #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
  52. #define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100))
  53. #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
  54. #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
  55. #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
  56. #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
  57. #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
  58. #define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700))
  59. #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
  60. #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
  61. #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
  62. #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
  63. #define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000))
  64. #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000))
  65. #define MVEBU_REG_PCIE0_BASE (MVEBU_REGISTER(0x80000))
  66. #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
  67. #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
  68. #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
  69. #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
  70. #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
  71. #ifdef CONFIG_ARMADA_MSYS
  72. #define MVEBU_DFX_BASE (MBUS_DFX_BASE)
  73. #else
  74. #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
  75. #endif
  76. #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
  77. #define MBUS_ERR_PROP_EN (1 << 8)
  78. #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
  79. #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
  80. #define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08)
  81. #define NAND_EN BIT(0)
  82. #define NAND_ARBITER_EN BIT(27)
  83. #define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c)
  84. #define GE0_PUP_EN BIT(0)
  85. #define GE1_PUP_EN BIT(1)
  86. #define LCD_PUP_EN BIT(2)
  87. #define NAND_PUP_EN BIT(4)
  88. #define SPI_PUP_EN BIT(5)
  89. #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
  90. #ifdef CONFIG_ARMADA_MSYS
  91. #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
  92. #define NAND_ECC_DIVCKL_RATIO_OFFS 6
  93. #define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
  94. #else
  95. #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
  96. #endif
  97. #ifdef CONFIG_ARMADA_MSYS
  98. #define NAND_ECC_DIVCKL_RATIO_OFFS 6
  99. #define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
  100. #else
  101. #define NAND_ECC_DIVCKL_RATIO_OFFS 8
  102. #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
  103. #endif
  104. #define SDRAM_MAX_CS 4
  105. #define SDRAM_ADDR_MASK 0xFF000000
  106. /* MVEBU CPU memory windows */
  107. #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
  108. #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
  109. #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
  110. #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
  111. /* BootROM error register (also includes some status infos) */
  112. #define BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
  113. #define BOOTROM_ERR_MODE_OFFS 28
  114. #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
  115. #define BOOTROM_ERR_MODE_UART 0x6
  116. #define BOOTROM_ERR_CODE_OFFS 0
  117. #define BOOTROM_ERR_CODE_MASK (0xf << BOOTROM_ERR_CODE_OFFS)
  118. #if defined(CONFIG_ARMADA_375)
  119. /* SAR values for Armada 375 */
  120. #define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200))
  121. #define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204))
  122. #define SAR_CPU_FREQ_OFFS 17
  123. #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
  124. #define BOOT_DEV_SEL_OFFS 3
  125. #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
  126. #define BOOT_FROM_UART 0x30
  127. #define BOOT_FROM_SPI 0x38
  128. #define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
  129. 200000000 : 166000000)
  130. #elif defined(CONFIG_ARMADA_38X)
  131. /* SAR values for Armada 38x */
  132. #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
  133. #define SAR_CPU_FREQ_OFFS 10
  134. #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
  135. #define SAR_BOOT_DEVICE_OFFS 4
  136. #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
  137. #define BOOT_DEV_SEL_OFFS 4
  138. #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
  139. #define BOOT_FROM_NAND 0x0A
  140. #define BOOT_FROM_SATA 0x22
  141. #define BOOT_FROM_UART 0x28
  142. #define BOOT_FROM_SATA_ALT 0x2A
  143. #define BOOT_FROM_UART_ALT 0x3f
  144. #define BOOT_FROM_SPI 0x32
  145. #define BOOT_FROM_MMC 0x30
  146. #define BOOT_FROM_MMC_ALT 0x31
  147. #define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
  148. 200000000 : 250000000)
  149. #elif defined(CONFIG_ARMADA_MSYS)
  150. /* SAR values for MSYS */
  151. #define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
  152. #define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
  153. #define SAR_CPU_FREQ_OFFS 18
  154. #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
  155. #define SAR_BOOT_DEVICE_OFFS 11
  156. #define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
  157. #define BOOT_DEV_SEL_OFFS 11
  158. #define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
  159. #define BOOT_FROM_NAND 0x1
  160. #define BOOT_FROM_UART 0x2
  161. #define BOOT_FROM_SPI 0x3
  162. #define CFG_SYS_TCLK 200000000 /* 200MHz */
  163. #elif defined(CONFIG_ARMADA_XP)
  164. /* SAR values for Armada XP */
  165. #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
  166. #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
  167. #define SAR_CPU_FREQ_OFFS 21
  168. #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
  169. #define SAR_FFC_FREQ_OFFS 24
  170. #define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS)
  171. #define SAR2_CPU_FREQ_OFFS 20
  172. #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
  173. #define SAR_BOOT_DEVICE_OFFS 5
  174. #define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
  175. #define BOOT_DEV_SEL_OFFS 5
  176. #define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS)
  177. #define BOOT_FROM_UART 0x2
  178. #define BOOT_FROM_SPI 0x3
  179. #define CFG_SYS_TCLK 250000000 /* 250MHz */
  180. #endif
  181. #endif /* _MVEBU_SOC_H */