lowlevel.S 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. #include <config.h>
  3. #include <linux/linkage.h>
  4. #include <asm/system.h>
  5. #include <asm/pl310.h>
  6. ENTRY(arch_very_early_init)
  7. #ifdef CONFIG_ARMADA_38X
  8. /*
  9. * Only with disabled MMU its possible to switch the base
  10. * register address on Armada 38x. Without this the SDRAM
  11. * located at >= 0x4000.0000 is also not accessible, as its
  12. * still locked to cache.
  13. *
  14. * So to fully release / unlock this area from cache, we need
  15. * to first flush all caches, then disable the MMU and
  16. * disable the L2 cache.
  17. */
  18. /* Invalidate L1 I/D */
  19. mov r0, #0 @ set up for MCR
  20. mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
  21. mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
  22. mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
  23. mcr p15, 0, r0, c7, c10, 4 @ DSB
  24. mcr p15, 0, r0, c7, c5, 4 @ ISB
  25. /* Disable MMU */
  26. mrc p15, 0, r0, c1, c0, 0
  27. bic r0, #CR_M
  28. mcr p15, 0, r0, c1, c0, 0
  29. /*
  30. * Disable L2 cache
  31. *
  32. * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
  33. * but CFG_SYS_PL310_BASE is already calculated from base
  34. * address SOC_REGS_PHY_BASE.
  35. */
  36. ldr r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
  37. ldr r0, [r1, #L2X0_CTRL_OFF]
  38. bic r0, #L2X0_CTRL_EN
  39. str r0, [r1, #L2X0_CTRL_OFF]
  40. #endif
  41. /* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */
  42. ldr r0, =SOC_REGS_PHY_BASE
  43. ldr r1, =INTREG_BASE_ADDR_REG
  44. str r0, [r1]
  45. add r0, r0, #0xC000
  46. mcr p15, 4, r0, c15, c0
  47. bx lr
  48. ENDPROC(arch_very_early_init)