misc_gen5.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <asm/global_data.h>
  9. #include <asm/io.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <fdtdec.h>
  13. #include <linux/bitops.h>
  14. #include <linux/libfdt.h>
  15. #include <altera.h>
  16. #include <miiphy.h>
  17. #include <netdev.h>
  18. #include <watchdog.h>
  19. #include <asm/arch/misc.h>
  20. #include <asm/arch/reset_manager.h>
  21. #include <asm/arch/scan_manager.h>
  22. #include <asm/arch/sdram.h>
  23. #include <asm/arch/system_manager.h>
  24. #include <asm/arch/nic301.h>
  25. #include <asm/arch/scu.h>
  26. #include <asm/pl310.h>
  27. #include <dt-bindings/reset/altr,rst-mgr.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. static struct pl310_regs *const pl310 =
  30. (struct pl310_regs *)CFG_SYS_PL310_BASE;
  31. static struct nic301_registers *nic301_regs =
  32. (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  33. static struct scu_registers *scu_regs =
  34. (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  35. /*
  36. * FPGA programming support for SoC FPGA Cyclone V
  37. */
  38. static Altera_desc altera_fpga[] = {
  39. {
  40. /* Family */
  41. Altera_SoCFPGA,
  42. /* Interface type */
  43. fast_passive_parallel,
  44. /* No limitation as additional data will be ignored */
  45. -1,
  46. /* No device function table */
  47. NULL,
  48. /* Base interface address specified in driver */
  49. NULL,
  50. /* No cookie implementation */
  51. 0
  52. },
  53. };
  54. static const struct {
  55. const u16 pn;
  56. const char *name;
  57. const char *var;
  58. } socfpga_fpga_model[] = {
  59. /* Cyclone V E */
  60. { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
  61. { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
  62. { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
  63. { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
  64. { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
  65. /* Cyclone V GX/GT */
  66. { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
  67. { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
  68. { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
  69. { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
  70. { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
  71. /* Cyclone V SE/SX/ST */
  72. { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
  73. { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
  74. { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
  75. { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
  76. /* Arria V */
  77. { 0x2d03, "Arria V, D5", "av_d5" },
  78. /* Arria V ST/SX */
  79. { 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" },
  80. };
  81. static int socfpga_fpga_id(const bool print_id)
  82. {
  83. const u32 altera_mi = 0x6e;
  84. const u32 id = scan_mgr_get_fpga_id();
  85. const u32 lsb = id & 0x00000001;
  86. const u32 mi = (id >> 1) & 0x000007ff;
  87. const u32 pn = (id >> 12) & 0x0000ffff;
  88. const u32 version = (id >> 28) & 0x0000000f;
  89. int i;
  90. if ((mi != altera_mi) || (lsb != 1)) {
  91. printf("FPGA: Not Altera chip ID\n");
  92. return -EINVAL;
  93. }
  94. for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
  95. if (pn == socfpga_fpga_model[i].pn)
  96. break;
  97. if (i == ARRAY_SIZE(socfpga_fpga_model)) {
  98. printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id);
  99. return -EINVAL;
  100. }
  101. if (print_id)
  102. printf("FPGA: Altera %s, version 0x%01x\n",
  103. socfpga_fpga_model[i].name, version);
  104. return i;
  105. }
  106. /*
  107. * Print CPU information
  108. */
  109. #if defined(CONFIG_DISPLAY_CPUINFO)
  110. int print_cpuinfo(void)
  111. {
  112. const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
  113. SYSMGR_GEN5_BOOTINFO);
  114. const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
  115. puts("CPU: Altera SoCFPGA Platform\n");
  116. socfpga_fpga_id(1);
  117. printf("BOOT: %s\n", bsel_str[bsel].name);
  118. return 0;
  119. }
  120. #endif
  121. #ifdef CONFIG_ARCH_MISC_INIT
  122. int arch_misc_init(void)
  123. {
  124. const u32 bsel = readl(socfpga_get_sysmgr_addr() +
  125. SYSMGR_GEN5_BOOTINFO) & 0x7;
  126. const int fpga_id = socfpga_fpga_id(0);
  127. env_set("bootmode", bsel_str[bsel].mode);
  128. if (fpga_id >= 0)
  129. env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
  130. return 0;
  131. }
  132. #endif
  133. /*
  134. * Convert all NIC-301 AMBA slaves from secure to non-secure
  135. */
  136. static void socfpga_nic301_slave_ns(void)
  137. {
  138. writel(0x1, &nic301_regs->lwhps2fpgaregs);
  139. writel(0x1, &nic301_regs->hps2fpgaregs);
  140. writel(0x1, &nic301_regs->acp);
  141. writel(0x1, &nic301_regs->rom);
  142. writel(0x1, &nic301_regs->ocram);
  143. writel(0x1, &nic301_regs->sdrdata);
  144. }
  145. void socfpga_sdram_remap_zero(void)
  146. {
  147. u32 remap;
  148. socfpga_nic301_slave_ns();
  149. /*
  150. * Private components security:
  151. * U-Boot : configure private timer, global timer and cpu component
  152. * access as non secure for kernel stage (as required by Linux)
  153. */
  154. setbits_le32(&scu_regs->sacr, 0xfff);
  155. /* Configure the L2 controller to make SDRAM start at 0 */
  156. remap = 0x1; /* remap.mpuzero */
  157. /* Keep fpga bridge enabled when running from FPGA onchip RAM */
  158. if (socfpga_is_booting_from_fpga())
  159. remap |= 0x8; /* remap.hps2fpga */
  160. writel(remap, &nic301_regs->remap);
  161. writel(0x1, &pl310->pl310_addr_filter_start);
  162. }
  163. static u32 iswgrp_handoff[8];
  164. int arch_early_init_r(void)
  165. {
  166. int i;
  167. /*
  168. * Write magic value into magic register to unlock support for
  169. * issuing warm reset. The ancient kernel code expects this
  170. * value to be written into the register by the bootloader, so
  171. * to support that old code, we write it here instead of in the
  172. * reset_cpu() function just before resetting the CPU.
  173. */
  174. writel(0xae9efebc,
  175. socfpga_get_sysmgr_addr() + SYSMGR_GEN5_WARMRAMGRP_EN);
  176. for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
  177. iswgrp_handoff[i] = readl(socfpga_get_sysmgr_addr() +
  178. SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
  179. socfpga_bridges_reset(1);
  180. socfpga_sdram_remap_zero();
  181. /* Add device descriptor to FPGA device table */
  182. socfpga_fpga_add(&altera_fpga[0]);
  183. return 0;
  184. }
  185. #ifndef CONFIG_SPL_BUILD
  186. static struct socfpga_sdr_ctrl *sdr_ctrl =
  187. (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  188. void do_bridge_reset(int enable, unsigned int mask)
  189. {
  190. int i;
  191. if (enable) {
  192. socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
  193. !(mask & BIT(1)),
  194. !(mask & BIT(2)));
  195. for (i = 0; i < 2; i++) { /* Reload SW setting cache */
  196. iswgrp_handoff[i] =
  197. readl(socfpga_get_sysmgr_addr() +
  198. SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
  199. }
  200. writel(iswgrp_handoff[2],
  201. socfpga_get_sysmgr_addr() +
  202. SYSMGR_GEN5_FPGAINFGRP_MODULE);
  203. writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
  204. writel(iswgrp_handoff[0],
  205. socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
  206. writel(iswgrp_handoff[1], &nic301_regs->remap);
  207. writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
  208. writel(iswgrp_handoff[0],
  209. socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
  210. } else {
  211. writel(0, socfpga_get_sysmgr_addr() +
  212. SYSMGR_GEN5_FPGAINFGRP_MODULE);
  213. writel(0, &sdr_ctrl->fpgaport_rst);
  214. writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
  215. writel(1, &nic301_regs->remap);
  216. }
  217. }
  218. #endif