spl.c 3.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <cpu_func.h>
  8. #include <debug_uart.h>
  9. #include <env.h>
  10. #include <hang.h>
  11. #include <image.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <semihosting.h>
  15. #include <spl.h>
  16. #include <asm/cache.h>
  17. #include <asm/global_data.h>
  18. #include <asm/io.h>
  19. #include <fsl_ifc.h>
  20. #include <i2c.h>
  21. #include <fsl_csu.h>
  22. #include <asm/arch/fdt.h>
  23. #include <asm/arch/ppa.h>
  24. #include <asm/arch/soc.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. u32 spl_boot_device(void)
  27. {
  28. if (semihosting_enabled())
  29. return BOOT_DEVICE_SMH;
  30. #ifdef CONFIG_SPL_MMC
  31. return BOOT_DEVICE_MMC1;
  32. #endif
  33. #ifdef CONFIG_SPL_NAND_SUPPORT
  34. return BOOT_DEVICE_NAND;
  35. #endif
  36. #ifdef CONFIG_QSPI_BOOT
  37. return BOOT_DEVICE_NOR;
  38. #endif
  39. return 0;
  40. }
  41. #ifdef CONFIG_SPL_BUILD
  42. void spl_board_init(void)
  43. {
  44. #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
  45. /*
  46. * In case of Secure Boot, the IBR configures the SMMU
  47. * to allow only Secure transactions.
  48. * SMMU must be reset in bypass mode.
  49. * Set the ClientPD bit and Clear the USFCFG Bit
  50. */
  51. u32 val;
  52. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  53. out_le32(SMMU_SCR0, val);
  54. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  55. out_le32(SMMU_NSCR0, val);
  56. #endif
  57. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  58. enable_layerscape_ns_access();
  59. #endif
  60. #ifdef CONFIG_SPL_FSL_LS_PPA
  61. ppa_init();
  62. #endif
  63. }
  64. void tzpc_init(void)
  65. {
  66. /*
  67. * Mark the whole OCRAM as non-secure, otherwise DMA devices cannot
  68. * access it. This is for example necessary for MMC boot.
  69. */
  70. #ifdef TZPCR0SIZE_BASE
  71. out_le32(TZPCR0SIZE_BASE, 0);
  72. #endif
  73. }
  74. void board_init_f(ulong dummy)
  75. {
  76. int ret;
  77. icache_enable();
  78. tzpc_init();
  79. /* Clear global data */
  80. memset((void *)gd, 0, sizeof(gd_t));
  81. if (IS_ENABLED(CONFIG_DEBUG_UART))
  82. debug_uart_init();
  83. board_early_init_f();
  84. ret = spl_early_init();
  85. if (ret) {
  86. debug("spl_early_init() failed: %d\n", ret);
  87. hang();
  88. }
  89. timer_init();
  90. #ifdef CONFIG_ARCH_LS2080A
  91. env_init();
  92. #endif
  93. get_clocks();
  94. preloader_console_init();
  95. spl_set_bd();
  96. #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
  97. #ifdef CONFIG_SPL_I2C
  98. i2c_init_all();
  99. #endif
  100. #endif
  101. #if defined(CONFIG_VID) && (defined(CONFIG_ARCH_LS1088A) || \
  102. defined(CONFIG_ARCH_LX2160A) || \
  103. defined(CONFIG_ARCH_LX2162A))
  104. init_func_vid();
  105. #endif
  106. dram_init();
  107. #ifdef CONFIG_SPL_FSL_LS_PPA
  108. #ifndef CFG_SYS_MEM_RESERVE_SECURE
  109. #error Need secure RAM for PPA
  110. #endif
  111. /*
  112. * Secure memory location is determined in dram_init_banksize().
  113. * gd->ram_size is deducted by the size of secure ram.
  114. */
  115. dram_init_banksize();
  116. /*
  117. * After dram_init_bank_size(), we know U-Boot only uses the first
  118. * memory bank regardless how big the memory is.
  119. */
  120. gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
  121. /*
  122. * If PPA is loaded, U-Boot will resume running at EL2.
  123. * Cache and MMU will be enabled. Need a place for TLB.
  124. * U-Boot will be relocated to the end of available memory
  125. * in first bank. At this point, we cannot know how much
  126. * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK
  127. * to avoid overlapping. As soon as the RAM version U-Boot sets
  128. * up new MMU, this space is no longer needed.
  129. */
  130. gd->ram_top -= SPL_TLB_SETBACK;
  131. gd->arch.tlb_size = PGTABLE_SIZE;
  132. gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
  133. gd->arch.tlb_allocated = gd->arch.tlb_addr;
  134. #endif /* CONFIG_SPL_FSL_LS_PPA */
  135. #if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
  136. qspi_ahb_init();
  137. #endif
  138. }
  139. #ifdef CONFIG_SPL_OS_BOOT
  140. /*
  141. * Return
  142. * 0 if booting into OS is selected
  143. * 1 if booting into U-Boot is selected
  144. */
  145. int spl_start_uboot(void)
  146. {
  147. env_init();
  148. if (env_get_yesno("boot_os") != 0)
  149. return 0;
  150. return 1;
  151. }
  152. #endif /* CONFIG_SPL_OS_BOOT */
  153. #endif /* CONFIG_SPL_BUILD */