spl_a10.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2021 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <hang.h>
  8. #include <init.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <asm/pl310.h>
  12. #include <asm/u-boot.h>
  13. #include <asm/utils.h>
  14. #include <image.h>
  15. #include <asm/arch/reset_manager.h>
  16. #include <spl.h>
  17. #include <asm/arch/system_manager.h>
  18. #include <asm/arch/freeze_controller.h>
  19. #include <asm/arch/clock_manager.h>
  20. #include <asm/arch/scan_manager.h>
  21. #include <asm/arch/sdram.h>
  22. #include <asm/arch/scu.h>
  23. #include <asm/arch/misc.h>
  24. #include <asm/arch/nic301.h>
  25. #include <asm/sections.h>
  26. #include <fdtdec.h>
  27. #include <watchdog.h>
  28. #include <asm/arch/pinmux.h>
  29. #include <asm/arch/fpga_manager.h>
  30. #include <mmc.h>
  31. #include <memalign.h>
  32. #include <linux/delay.h>
  33. #define FPGA_BUFSIZ 16 * 1024
  34. #define FSBL_IMAGE_IS_VALID 0x49535756
  35. #define FSBL_IMAGE_IS_INVALID 0x0
  36. #define BOOTROM_CONFIGURES_IO_PINMUX 0x3
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
  39. #define BOOTROM_SHARED_MEM_ADDR (CFG_SYS_INIT_RAM_ADDR + \
  40. SOCFPGA_PHYS_OCRAM_SIZE - \
  41. BOOTROM_SHARED_MEM_SIZE)
  42. #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
  43. static u32 rst_mgr_status __section(".data");
  44. /*
  45. * Bootrom will clear the status register in reset manager and stores the
  46. * reset status value in shared memory. Bootrom stores shared data at last
  47. * 2KB of onchip RAM.
  48. * This function save reset status provided by BootROM to rst_mgr_status.
  49. * More information about reset status register value can be found in reset
  50. * manager register description.
  51. * When running in debugger without Bootrom, r0 to r3 are random values.
  52. * So, skip save the value when r0 is not BootROM shared data address.
  53. *
  54. * r0 - Contains the pointer to the shared memory block. The shared
  55. * memory block is located in the top 2 KB of on-chip RAM.
  56. * r1 - contains the length of the shared memory.
  57. * r2 - unused and set to 0x0.
  58. * r3 - points to the version block.
  59. */
  60. void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
  61. unsigned long r3)
  62. {
  63. if (r0 == BOOTROM_SHARED_MEM_ADDR)
  64. rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
  65. save_boot_params_ret();
  66. }
  67. u32 spl_boot_device(void)
  68. {
  69. const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
  70. switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  71. case 0x1: /* FPGA (HPS2FPGA Bridge) */
  72. return BOOT_DEVICE_RAM;
  73. case 0x2: /* NAND Flash (1.8V) */
  74. case 0x3: /* NAND Flash (3.0V) */
  75. socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  76. return BOOT_DEVICE_NAND;
  77. case 0x4: /* SD/MMC External Transceiver (1.8V) */
  78. case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
  79. socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  80. socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  81. return BOOT_DEVICE_MMC1;
  82. case 0x6: /* QSPI Flash (1.8V) */
  83. case 0x7: /* QSPI Flash (3.0V) */
  84. socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  85. return BOOT_DEVICE_SPI;
  86. default:
  87. printf("Invalid boot device (bsel=%08x)!\n", bsel);
  88. hang();
  89. }
  90. }
  91. #ifdef CONFIG_SPL_MMC
  92. u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
  93. {
  94. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  95. return MMCSD_MODE_FS;
  96. #else
  97. return MMCSD_MODE_RAW;
  98. #endif
  99. }
  100. #endif
  101. void spl_board_init(void)
  102. {
  103. int ret;
  104. ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
  105. /* enable console uart printing */
  106. preloader_console_init();
  107. schedule();
  108. arch_early_init_r();
  109. /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
  110. if (is_fpgamgr_user_mode()) {
  111. ret = config_pins(gd->fdt_blob, "shared");
  112. if (ret)
  113. return;
  114. ret = config_pins(gd->fdt_blob, "fpga");
  115. if (ret)
  116. return;
  117. } else if (!is_fpgamgr_early_user_mode()) {
  118. /* Program IOSSM(early IO release) or full FPGA */
  119. fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  120. /* Skipping double program for combined RBF */
  121. if (!is_fpgamgr_user_mode()) {
  122. /*
  123. * Expect FPGA entered early user mode, so
  124. * the flag is set to re-program IOSSM
  125. */
  126. force_periph_program(true);
  127. /* Re-program IOSSM to stabilize IO system */
  128. fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  129. force_periph_program(false);
  130. }
  131. }
  132. /* If the IOSSM/full FPGA is already loaded, start DDR */
  133. if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) {
  134. if (!is_regular_boot_valid()) {
  135. /*
  136. * Ensure all signals in stable state before triggering
  137. * warm reset. This value is recommended from stress
  138. * test.
  139. */
  140. mdelay(10);
  141. #if IS_ENABLED(CONFIG_CADENCE_QSPI)
  142. /*
  143. * Trigger software reset to QSPI flash.
  144. * On some boards, the QSPI flash reset may not be
  145. * connected to the HPS warm reset.
  146. */
  147. qspi_flash_software_reset();
  148. #endif
  149. ret = readl(socfpga_get_rstmgr_addr() +
  150. RSTMGR_A10_SYSWARMMASK);
  151. /*
  152. * Masking s2f & FPGA manager module reset from warm
  153. * reset
  154. */
  155. writel(ret & (~(ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK |
  156. ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK)),
  157. socfpga_get_rstmgr_addr() +
  158. RSTMGR_A10_SYSWARMMASK);
  159. /*
  160. * BootROM will configure both IO and pin mux after a
  161. * warm reset
  162. */
  163. ret = readl(socfpga_get_sysmgr_addr() +
  164. SYSMGR_A10_ROMCODE_CTRL);
  165. writel(ret | BOOTROM_CONFIGURES_IO_PINMUX,
  166. socfpga_get_sysmgr_addr() +
  167. SYSMGR_A10_ROMCODE_CTRL);
  168. /*
  169. * Up to here, image is considered valid and should be
  170. * set as valid before warm reset is triggered
  171. */
  172. writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
  173. SYSMGR_A10_ROMCODE_INITSWSTATE);
  174. /*
  175. * Set this flag to scratch register, so that a proper
  176. * boot progress before / after warm reset can be
  177. * tracked by FSBL
  178. */
  179. set_regular_boot(true);
  180. schedule();
  181. reset_cpu();
  182. }
  183. /*
  184. * Reset this flag to scratch register, so that a proper
  185. * boot progress before / after warm reset can be
  186. * tracked by FSBL
  187. */
  188. set_regular_boot(false);
  189. ret = readl(socfpga_get_rstmgr_addr() +
  190. RSTMGR_A10_SYSWARMMASK);
  191. /*
  192. * Unmasking s2f & FPGA manager module reset from warm
  193. * reset
  194. */
  195. writel(ret | ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK |
  196. ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK,
  197. socfpga_get_rstmgr_addr() + RSTMGR_A10_SYSWARMMASK);
  198. /*
  199. * Up to here, MPFE hang workaround is considered done and
  200. * should be reset as invalid until FSBL successfully loading
  201. * SSBL, and prepare jumping to SSBL, then only setting as
  202. * valid
  203. */
  204. writel(FSBL_IMAGE_IS_INVALID, socfpga_get_sysmgr_addr() +
  205. SYSMGR_A10_ROMCODE_INITSWSTATE);
  206. ddr_calibration_sequence();
  207. }
  208. if (!is_fpgamgr_user_mode())
  209. fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  210. }
  211. void board_init_f(ulong dummy)
  212. {
  213. if (spl_early_init())
  214. hang();
  215. socfpga_get_managers_addr();
  216. dcache_disable();
  217. socfpga_init_security_policies();
  218. socfpga_sdram_remap_zero();
  219. socfpga_pl310_clear();
  220. /* Assert reset to all except L4WD0 and L4TIMER0 */
  221. socfpga_per_reset_all();
  222. socfpga_watchdog_disable();
  223. /* Configure the clock based on handoff */
  224. cm_basic_init(gd->fdt_blob);
  225. #ifdef CONFIG_HW_WATCHDOG
  226. /* release osc1 watchdog timer 0 from reset */
  227. socfpga_reset_deassert_osc1wd0();
  228. /* reconfigure and enable the watchdog */
  229. hw_watchdog_init();
  230. schedule();
  231. #endif /* CONFIG_HW_WATCHDOG */
  232. config_dedicated_pins(gd->fdt_blob);
  233. schedule();
  234. }
  235. /* board specific function prior loading SSBL / U-Boot proper */
  236. void spl_board_prepare_for_boot(void)
  237. {
  238. writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
  239. SYSMGR_A10_ROMCODE_INITSWSTATE);
  240. }