cpu.c 9.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Josef Baumgartner <josef.baumgartner@telex.de>
  5. *
  6. * MCF5282 additionals
  7. * (C) Copyright 2005
  8. * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
  9. *
  10. * MCF5275 additions
  11. * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  12. *
  13. * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  14. */
  15. #include <common.h>
  16. #include <init.h>
  17. #include <net.h>
  18. #include <vsprintf.h>
  19. #include <watchdog.h>
  20. #include <command.h>
  21. #include <asm/global_data.h>
  22. #include <asm/immap.h>
  23. #include <asm/io.h>
  24. #include <netdev.h>
  25. #include <linux/delay.h>
  26. #include "cpu.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #ifdef CONFIG_M5208
  29. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  30. {
  31. rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  32. udelay(1000);
  33. out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  34. /* we don't return! */
  35. return 0;
  36. };
  37. #if defined(CONFIG_DISPLAY_CPUINFO)
  38. int print_cpuinfo(void)
  39. {
  40. char buf1[32], buf2[32];
  41. printf("CPU: Freescale Coldfire MCF5208\n"
  42. " CPU CLK %s MHz BUS CLK %s MHz\n",
  43. strmhz(buf1, gd->cpu_clk),
  44. strmhz(buf2, gd->bus_clk));
  45. return 0;
  46. };
  47. #endif /* CONFIG_DISPLAY_CPUINFO */
  48. #if defined(CONFIG_WATCHDOG)
  49. /* Called by macro WATCHDOG_RESET */
  50. void watchdog_reset(void)
  51. {
  52. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  53. out_be16(&wdt->sr, 0x5555);
  54. out_be16(&wdt->sr, 0xaaaa);
  55. }
  56. int watchdog_disable(void)
  57. {
  58. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  59. /* reset watchdog counter */
  60. out_be16(&wdt->sr, 0x5555);
  61. out_be16(&wdt->sr, 0xaaaa);
  62. /* disable watchdog timer */
  63. out_be16(&wdt->cr, 0);
  64. puts("WATCHDOG:disabled\n");
  65. return (0);
  66. }
  67. int watchdog_init(void)
  68. {
  69. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  70. /* disable watchdog */
  71. out_be16(&wdt->cr, 0);
  72. /* set timeout and enable watchdog */
  73. out_be16(&wdt->mr,
  74. (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  75. /* reset watchdog counter */
  76. out_be16(&wdt->sr, 0x5555);
  77. out_be16(&wdt->sr, 0xaaaa);
  78. puts("WATCHDOG:enabled\n");
  79. return (0);
  80. }
  81. #endif /* #ifdef CONFIG_WATCHDOG */
  82. #endif /* #ifdef CONFIG_M5208 */
  83. #ifdef CONFIG_M5271
  84. #if defined(CONFIG_DISPLAY_CPUINFO)
  85. /*
  86. * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
  87. * determine which one we are running on, based on the Chip Identification
  88. * Register (CIR).
  89. */
  90. int print_cpuinfo(void)
  91. {
  92. char buf[32];
  93. unsigned short cir; /* Chip Identification Register */
  94. unsigned short pin; /* Part identification number */
  95. unsigned char prn; /* Part revision number */
  96. char *cpu_model;
  97. cir = mbar_readShort(MCF_CCM_CIR);
  98. pin = cir >> MCF_CCM_CIR_PIN_LEN;
  99. prn = cir & MCF_CCM_CIR_PRN_MASK;
  100. switch (pin) {
  101. case MCF_CCM_CIR_PIN_MCF5270:
  102. cpu_model = "5270";
  103. break;
  104. case MCF_CCM_CIR_PIN_MCF5271:
  105. cpu_model = "5271";
  106. break;
  107. default:
  108. cpu_model = NULL;
  109. break;
  110. }
  111. if (cpu_model)
  112. printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
  113. cpu_model, prn, strmhz(buf, CFG_SYS_CLK));
  114. else
  115. printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
  116. " (PIN: 0x%x) rev. %hu, at %s MHz\n",
  117. pin, prn, strmhz(buf, CFG_SYS_CLK));
  118. return 0;
  119. }
  120. #endif /* CONFIG_DISPLAY_CPUINFO */
  121. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  122. {
  123. /* Call the board specific reset actions first. */
  124. if(board_reset) {
  125. board_reset();
  126. }
  127. mbar_writeByte(MCF_RCM_RCR,
  128. MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
  129. return 0;
  130. };
  131. #if defined(CONFIG_WATCHDOG)
  132. void watchdog_reset(void)
  133. {
  134. mbar_writeShort(MCF_WTM_WSR, 0x5555);
  135. mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
  136. }
  137. int watchdog_disable(void)
  138. {
  139. mbar_writeShort(MCF_WTM_WCR, 0);
  140. return (0);
  141. }
  142. int watchdog_init(void)
  143. {
  144. mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
  145. return (0);
  146. }
  147. #endif /* #ifdef CONFIG_WATCHDOG */
  148. #endif
  149. #ifdef CONFIG_M5272
  150. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  151. {
  152. wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  153. out_be16(&wdp->wdog_wrrr, 0);
  154. udelay(1000);
  155. /* enable watchdog, set timeout to 0 and wait */
  156. out_be16(&wdp->wdog_wrrr, 1);
  157. while (1) ;
  158. /* we don't return! */
  159. return 0;
  160. };
  161. #if defined(CONFIG_DISPLAY_CPUINFO)
  162. int print_cpuinfo(void)
  163. {
  164. sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
  165. uchar msk;
  166. char *suf;
  167. puts("CPU: ");
  168. msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
  169. switch (msk) {
  170. case 0x2:
  171. suf = "1K75N";
  172. break;
  173. case 0x4:
  174. suf = "3K75N";
  175. break;
  176. default:
  177. suf = NULL;
  178. printf("Freescale MCF5272 (Mask:%01x)\n", msk);
  179. break;
  180. }
  181. if (suf)
  182. printf("Freescale MCF5272 %s\n", suf);
  183. return 0;
  184. };
  185. #endif /* CONFIG_DISPLAY_CPUINFO */
  186. #if defined(CONFIG_WATCHDOG)
  187. /* Called by macro WATCHDOG_RESET */
  188. void watchdog_reset(void)
  189. {
  190. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  191. out_be16(&wdt->wdog_wcr, 0);
  192. }
  193. int watchdog_disable(void)
  194. {
  195. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  196. /* reset watchdog counter */
  197. out_be16(&wdt->wdog_wcr, 0);
  198. /* disable watchdog interrupt */
  199. out_be16(&wdt->wdog_wirr, 0);
  200. /* disable watchdog timer */
  201. out_be16(&wdt->wdog_wrrr, 0);
  202. puts("WATCHDOG:disabled\n");
  203. return (0);
  204. }
  205. int watchdog_init(void)
  206. {
  207. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  208. /* disable watchdog interrupt */
  209. out_be16(&wdt->wdog_wirr, 0);
  210. /* set timeout and enable watchdog */
  211. out_be16(&wdt->wdog_wrrr,
  212. (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  213. /* reset watchdog counter */
  214. out_be16(&wdt->wdog_wcr, 0);
  215. puts("WATCHDOG:enabled\n");
  216. return (0);
  217. }
  218. #endif /* #ifdef CONFIG_WATCHDOG */
  219. #endif /* #ifdef CONFIG_M5272 */
  220. #ifdef CONFIG_M5275
  221. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  222. {
  223. rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  224. udelay(1000);
  225. out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  226. /* we don't return! */
  227. return 0;
  228. };
  229. #if defined(CONFIG_DISPLAY_CPUINFO)
  230. int print_cpuinfo(void)
  231. {
  232. char buf[32];
  233. printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
  234. strmhz(buf, CFG_SYS_CLK));
  235. return 0;
  236. };
  237. #endif /* CONFIG_DISPLAY_CPUINFO */
  238. #if defined(CONFIG_WATCHDOG)
  239. /* Called by macro WATCHDOG_RESET */
  240. void watchdog_reset(void)
  241. {
  242. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  243. out_be16(&wdt->wsr, 0x5555);
  244. out_be16(&wdt->wsr, 0xaaaa);
  245. }
  246. int watchdog_disable(void)
  247. {
  248. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  249. /* reset watchdog counter */
  250. out_be16(&wdt->wsr, 0x5555);
  251. out_be16(&wdt->wsr, 0xaaaa);
  252. /* disable watchdog timer */
  253. out_be16(&wdt->wcr, 0);
  254. puts("WATCHDOG:disabled\n");
  255. return (0);
  256. }
  257. int watchdog_init(void)
  258. {
  259. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  260. /* disable watchdog */
  261. out_be16(&wdt->wcr, 0);
  262. /* set timeout and enable watchdog */
  263. out_be16(&wdt->wmr,
  264. (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  265. /* reset watchdog counter */
  266. out_be16(&wdt->wsr, 0x5555);
  267. out_be16(&wdt->wsr, 0xaaaa);
  268. puts("WATCHDOG:enabled\n");
  269. return (0);
  270. }
  271. #endif /* #ifdef CONFIG_WATCHDOG */
  272. #endif /* #ifdef CONFIG_M5275 */
  273. #ifdef CONFIG_M5282
  274. #if defined(CONFIG_DISPLAY_CPUINFO)
  275. int print_cpuinfo(void)
  276. {
  277. unsigned char resetsource = MCFRESET_RSR;
  278. printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
  279. MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
  280. printf("Reset:%s%s%s%s%s%s%s\n",
  281. (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
  282. (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
  283. (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
  284. (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
  285. (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
  286. (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
  287. (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
  288. return 0;
  289. }
  290. #endif /* CONFIG_DISPLAY_CPUINFO */
  291. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  292. {
  293. MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
  294. return 0;
  295. };
  296. #endif
  297. #ifdef CONFIG_M5249
  298. #if defined(CONFIG_DISPLAY_CPUINFO)
  299. int print_cpuinfo(void)
  300. {
  301. char buf[32];
  302. printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
  303. strmhz(buf, CFG_SYS_CLK));
  304. return 0;
  305. }
  306. #endif /* CONFIG_DISPLAY_CPUINFO */
  307. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  308. {
  309. /* enable watchdog, set timeout to 0 and wait */
  310. mbar_writeByte(MCFSIM_SYPCR, 0xc0);
  311. while (1) ;
  312. /* we don't return! */
  313. return 0;
  314. };
  315. #endif
  316. #ifdef CONFIG_M5253
  317. #if defined(CONFIG_DISPLAY_CPUINFO)
  318. int print_cpuinfo(void)
  319. {
  320. char buf[32];
  321. unsigned char resetsource = mbar_readLong(SIM_RSR);
  322. printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
  323. strmhz(buf, CFG_SYS_CLK));
  324. if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
  325. printf("Reset:%s%s\n",
  326. (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
  327. : "",
  328. (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
  329. "");
  330. }
  331. return 0;
  332. }
  333. #endif /* CONFIG_DISPLAY_CPUINFO */
  334. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  335. {
  336. /* enable watchdog, set timeout to 0 and wait */
  337. mbar_writeByte(SIM_SYPCR, 0xc0);
  338. while (1) ;
  339. /* we don't return! */
  340. return 0;
  341. };
  342. #endif
  343. #if defined(CONFIG_MCFFEC)
  344. /* Default initializations for MCFFEC controllers. To override,
  345. * create a board-specific function called:
  346. * int board_eth_init(struct bd_info *bis)
  347. */
  348. int cpu_eth_init(struct bd_info *bis)
  349. {
  350. return mcffec_initialize(bis);
  351. }
  352. #endif