config.h 8.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016-2018, 2020 NXP
  4. * Copyright 2015, Freescale Semiconductor
  5. */
  6. #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
  7. #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
  8. #include <linux/kconfig.h>
  9. #include <fsl_ddrc_version.h>
  10. #ifndef __ASSEMBLY__
  11. #include <linux/bitops.h>
  12. #endif
  13. #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
  14. /*
  15. * Reserve secure memory
  16. * To be aligned with MMU block size
  17. */
  18. #define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
  19. #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
  20. #ifdef CONFIG_ARCH_LS2080A
  21. #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
  22. #define SRDS_MAX_LANES 8
  23. #define CFG_SYS_PAGE_SIZE 0x10000
  24. #ifndef L1_CACHE_BYTES
  25. #define L1_CACHE_SHIFT 6
  26. #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
  27. #endif
  28. #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
  29. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
  30. #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
  31. /* DDR */
  32. #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  33. #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
  34. /* Generic Interrupt Controller Definitions */
  35. #define GICD_BASE 0x06000000
  36. #define GICR_BASE 0x06100000
  37. /* SMMU Defintions */
  38. #define SMMU_BASE 0x05000000 /* GR0 Base */
  39. /* Cache Coherent Interconnect */
  40. #define CCI_MN_BASE 0x04000000
  41. #define CCI_MN_RNF_NODEID_LIST 0x180
  42. #define CCI_MN_DVM_DOMAIN_CTL 0x200
  43. #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
  44. #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
  45. #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
  46. #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
  47. #define CCN_HN_F_SAM_NODEID_MASK 0x7f
  48. #define CCN_HN_F_SAM_NODEID_DDR0 0x4
  49. #define CCN_HN_F_SAM_NODEID_DDR1 0xe
  50. #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
  51. #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
  52. #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
  53. #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
  54. #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
  55. #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
  56. #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
  57. #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
  58. #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
  59. #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
  60. /* TZ Protection Controller Definitions */
  61. #define TZPC_BASE 0x02200000
  62. #define TZPCR0SIZE_BASE (TZPC_BASE)
  63. #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
  64. #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
  65. #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
  66. #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
  67. #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
  68. #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
  69. #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
  70. #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
  71. #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
  72. #define DCSR_CGACRE5 0x700070914ULL
  73. #define EPU_EPCMPR5 0x700060914ULL
  74. #define EPU_EPCCR5 0x700060814ULL
  75. #define EPU_EPSMCR5 0x700060228ULL
  76. #define EPU_EPECR5 0x700060314ULL
  77. #define EPU_EPCTR5 0x700060a14ULL
  78. #define EPU_EPGCR 0x700060000ULL
  79. #elif defined(CONFIG_ARCH_LS1088A)
  80. #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
  81. #define CFG_SYS_PAGE_SIZE 0x10000
  82. #define SRDS_MAX_LANES 4
  83. #define SRDS_BITS_PER_LANE 4
  84. /* TZ Protection Controller Definitions */
  85. #define TZPC_BASE 0x02200000
  86. #define TZPCR0SIZE_BASE (TZPC_BASE)
  87. #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
  88. #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
  89. #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
  90. #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
  91. #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
  92. #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
  93. #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
  94. #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
  95. #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
  96. /* Generic Interrupt Controller Definitions */
  97. #define GICD_BASE 0x06000000
  98. #define GICR_BASE 0x06100000
  99. /* SMMU Defintions */
  100. #define SMMU_BASE 0x05000000 /* GR0 Base */
  101. /* DDR */
  102. #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  103. #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
  104. /* DCFG - GUR */
  105. #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
  106. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
  107. #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
  108. /* LX2160A/LX2162A Soc Support */
  109. #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
  110. #define TZPC_BASE 0x02200000
  111. #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
  112. #define SRDS_MAX_LANES 8
  113. #ifndef L1_CACHE_BYTES
  114. #define L1_CACHE_SHIFT 6
  115. #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
  116. #endif
  117. #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
  118. #define CFG_SYS_PAGE_SIZE 0x10000
  119. #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
  120. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
  121. #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
  122. /* DDR */
  123. #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  124. #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
  125. /* Generic Interrupt Controller Definitions */
  126. #define GICD_BASE 0x06000000
  127. #define GICR_BASE 0x06200000
  128. /* SMMU Definitions */
  129. #define SMMU_BASE 0x05000000 /* GR0 Base */
  130. /* DCFG - GUR */
  131. #elif defined(CONFIG_ARCH_LS1028A)
  132. #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
  133. #define CONFIG_FSL_TZASC_400
  134. /* TZ Protection Controller Definitions */
  135. #define TZPC_BASE 0x02200000
  136. #define TZPCR0SIZE_BASE (TZPC_BASE)
  137. #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
  138. #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
  139. #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
  140. #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
  141. #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
  142. #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
  143. #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
  144. #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
  145. #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
  146. #define SRDS_MAX_LANES 4
  147. #define SRDS_BITS_PER_LANE 4
  148. #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
  149. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
  150. #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
  151. /* Generic Interrupt Controller Definitions */
  152. #define GICD_BASE 0x06000000
  153. #define GICR_BASE 0x06040000
  154. /* SMMU Definitions */
  155. #define SMMU_BASE 0x05000000 /* GR0 Base */
  156. /* DDR */
  157. #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  158. #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
  159. /* SEC */
  160. /* DCFG - GUR */
  161. #elif defined(CONFIG_FSL_LSCH2)
  162. #define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
  163. #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
  164. #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
  165. #define DCSR_DCFG_SBEESR2 0x20140534
  166. #define DCSR_DCFG_MBEESR2 0x20140544
  167. /* SoC related */
  168. #ifdef CONFIG_ARCH_LS1043A
  169. #define CFG_SYS_NUM_FMAN 1
  170. #define CFG_SYS_NUM_FM1_DTSEC 7
  171. #define CFG_SYS_NUM_FM1_10GEC 1
  172. #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  173. #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
  174. #define QE_MURAM_SIZE 0x6000UL
  175. #define MAX_QE_RISC 1
  176. #define QE_NUM_OF_SNUM 28
  177. /* SMMU Defintions */
  178. #define SMMU_BASE 0x09000000
  179. /* Generic Interrupt Controller Definitions */
  180. #define GICD_BASE 0x01401000
  181. #define GICC_BASE 0x01402000
  182. #define GICH_BASE 0x01404000
  183. #define GICV_BASE 0x01406000
  184. #define GICD_SIZE 0x1000
  185. #define GICC_SIZE 0x2000
  186. #define GICH_SIZE 0x2000
  187. #define GICV_SIZE 0x2000
  188. #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
  189. #define GICD_BASE_64K 0x01410000
  190. #define GICC_BASE_64K 0x01420000
  191. #define GICH_BASE_64K 0x01440000
  192. #define GICV_BASE_64K 0x01460000
  193. #define GICD_SIZE_64K 0x10000
  194. #define GICC_SIZE_64K 0x20000
  195. #define GICH_SIZE_64K 0x20000
  196. #define GICV_SIZE_64K 0x20000
  197. #endif
  198. #define DCFG_CCSR_SVR 0x1ee00a4
  199. #define REV1_0 0x10
  200. #define REV1_1 0x11
  201. #define GIC_ADDR_BIT 31
  202. #define SCFG_GIC400_ALIGN 0x1570188
  203. #elif defined(CONFIG_ARCH_LS1012A)
  204. #define GICD_BASE 0x01401000
  205. #define GICC_BASE 0x01402000
  206. #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  207. #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
  208. #elif defined(CONFIG_ARCH_LS1046A)
  209. #define CFG_SYS_NUM_FMAN 1
  210. #define CFG_SYS_NUM_FM1_DTSEC 8
  211. #define CFG_SYS_NUM_FM1_10GEC 2
  212. #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  213. #define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
  214. /* SMMU Defintions */
  215. #define SMMU_BASE 0x09000000
  216. /* Generic Interrupt Controller Definitions */
  217. #define GICD_BASE 0x01410000
  218. #define GICC_BASE 0x01420000
  219. #else
  220. #error SoC not defined
  221. #endif
  222. #endif
  223. #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */